sys/dev/atm/hfa/fore_slave.h

   1 /*
   2  *
   3  * ===================================
   4  * HARP  |  Host ATM Research Platform
   5  * ===================================
   6  *
   7  *
   8  * This Host ATM Research Platform ("HARP") file (the "Software") is
   9  * made available by Network Computing Services, Inc. ("NetworkCS")
  10  * "AS IS".  NetworkCS does not provide maintenance, improvements or
  11  * support of any kind.
  12  *
  13  * NETWORKCS MAKES NO WARRANTIES OR REPRESENTATIONS, EXPRESS OR IMPLIED,
  14  * INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF MERCHANTABILITY
  15  * AND FITNESS FOR A PARTICULAR PURPOSE, AS TO ANY ELEMENT OF THE
  16  * SOFTWARE OR ANY SUPPORT PROVIDED IN CONNECTION WITH THIS SOFTWARE.
  17  * In no event shall NetworkCS be responsible for any damages, including
  18  * but not limited to consequential damages, arising from or relating to
  19  * any use of the Software or related support.
  20  *
  21  * Copyright 1994-1998 Network Computing Services, Inc.
  22  *
  23  * Copies of this Software may be made, however, the above copyright
  24  * notice must be reproduced on all copies.
  25  *
  26  *      @(#) $FreeBSD: src/sys/dev/hfa/fore_slave.h,v 1.2 1999/08/28 00:41:52 peter Exp $
  27  *      @(#) $DragonFly: src/sys/dev/atm/hfa/fore_slave.h,v 1.2 2003/06/17 04:28:27 dillon Exp $
  28  *
  29  */
  30
  31 /*
  32  * FORE Systems 200-Series Adapter Support
  33  * ---------------------------------------
  34  *
  35  * Slave Interface definitions
  36  *
  37  */
  38
  39 #ifndef _FORE_SLAVE_H
  40 #define _FORE_SLAVE_H
  41
  42 /*
  43  * This file contains the (mostly hardware) definitions for each of the
  44  * supported 200-series slave interfaces.
  45  */
  46
  47
  48 /*
  49  * Structure defining the supported FORE 200-series interfaces
  50  */
  51 struct fore_device {
  52         char            *fd_name;       /* Device name (from PROM) */
  53         Atm_device      fd_devtyp;      /* Device type */
  54 };
  55 typedef struct fore_device      Fore_device;
  56
  57
  58
  59 /*
  60  * Common definitions
  61  * ------------------
  62  */
  63 #define MON960_BASE     0x400           /* Address offset of Mon960 */
  64 #define AALI_BASE       0x4d40          /* Address offset of Aali */
  65
  66 typedef volatile unsigned int   Fore_reg;       /* Slave control register */
  67 typedef volatile unsigned char  Fore_mem;       /* Slave memory */
  68
  69
  70 /*
  71  * SBA-200E SBus Slave Interface
  72  * -----------------------------
  73  */
  74
  75 #define SBA200E_PROM_NAME       "FORE,sba-200e"
  76
  77 /*
  78  * SBA-200E Host Control Register (HCR)
  79  */
  80 #define SBA200E_READ_BITS       0x1ff   /* Valid read data bits */
  81 #define SBA200E_WRITE_BITS      0x01f   /* Valid write data bits */
  82 #define SBA200E_STICKY_BITS     0x013   /* Sticky data bits */
  83
  84 /* Read access */
  85 #define SBA200E_SBUS_INTR_RD    0x100   /* State of SBus interrupt */
  86 #define SBA200E_TEST_MODE       0x080   /* Device is in test-mode  */
  87 #define SBA200E_IFIFO_FULL      0x040   /* Input FIFO almost full (when 0) */
  88 #define SBA200E_ESP_HOLD_RD     0x020   /* State of ESP bus hold */
  89 #define SBA200E_SBUS_ENA_RD     0x010   /* State of SBus interrupt enable */
  90 #define SBA200E_OFIFO_FULL      0x008   /* Output FIFO almost full */
  91 #define SBA200E_SELFTEST_FAIL   0x004   /* i960 self-test failed (when 0) */
  92 #define SBA200E_HOLD_LOCK_RD    0x002   /* State of i960 hold lock signal */
  93 #define SBA200E_RESET_RD        0x001   /* State of board reset signal */
  94
  95 /* Write access - bit set (clear) */
  96 #define SBA200E_SBUS_ENA        0x010   /* Enable (disable) SBus interrupts */
  97 #define SBA200E_CLR_SBUS_INTR   0x008   /* Clear SBus interrupt */
  98 #define SBA200E_I960_INTR       0x004   /* Issue interrupt to i960 */
  99 #define SBA200E_HOLD_LOCK       0x002   /* Set (clear) i960 hold lock signal */
 100 #define SBA200E_RESET           0x001   /* Set (clear) board reset signal */
 101
 102 #define SBA200E_HCR_INIT(hcr,bits) \
 103                         ((hcr) = (SBA200E_WRITE_BITS & (bits)))
 104 #define SBA200E_HCR_SET(hcr,bits) \
 105                         ((hcr) = (((hcr) & SBA200E_STICKY_BITS) | (bits)))
 106 #define SBA200E_HCR_CLR(hcr,bits) \
 107                         ((hcr) = ((hcr) & (SBA200E_STICKY_BITS ^ (bits))))
 108
 109
 110
 111 /*
 112  * SBA-200 SBus Slave Interface
 113  * ----------------------------
 114  */
 115
 116 #define SBA200_PROM_NAME        "FORE,sba-200"
 117
 118 /*
 119  * SBA-200 Board Control Register (BCR)
 120  */
 121 /* Write access - bit set */
 122 #define SBA200_CLR_SBUS_INTR    0x04    /* Clear SBus interrupt */
 123 #define SBA200_RESET            0x01    /* Assert board reset signal */
 124
 125 /* Write access - bit clear */
 126 #define SBA200_RESET_CLR        0x00    /* Clear board reset signal */
 127
 128
 129
 130 /*
 131  * PCA-200E PCI Bus Slave Interface
 132  * --------------------------------
 133  */
 134
 135 /*
 136  * PCI Identifiers
 137  */
 138 #define FORE_VENDOR_ID          0x1127
 139 #define FORE_PCA200E_ID         0x0300
 140
 141 /*
 142  * PCA-200E PCI Configuration Space
 143  */
 144 #define PCA200E_PCI_MEMBASE     0x10    /* Memory base address */
 145 #define PCA200E_PCI_MCTL        0x40    /* Master control */
 146
 147 /*
 148  * PCA-200E Address Space
 149  */
 150 #define PCA200E_RAM_SIZE        0x100000
 151 #define PCA200E_HCR_OFFSET      0x100000
 152 #define PCA200E_IMASK_OFFSET    0x100004
 153 #define PCA200E_PSR_OFFSET      0x100008
 154 #define PCA200E_MMAP_SIZE       0x10000c
 155
 156 /*
 157  * PCA-200E Master Control
 158  */
 159 #define PCA200E_MCTL_SWAP       0x4000  /* Convert Slave endianess */
 160
 161 /*
 162  * PCA-200E Host Control Register (HCR)
 163  */
 164 #define PCA200E_READ_BITS       0x0ff   /* Valid read data bits */
 165 #define PCA200E_WRITE_BITS      0x01f   /* Valid write data bits */
 166 #define PCA200E_STICKY_BITS     0x000   /* Sticky data bits */
 167
 168 /* Read access */
 169 #define PCA200E_TEST_MODE       0x080   /* Device is in test-mode */
 170 #define PCA200E_IFIFO_FULL      0x040   /* Input FIFO almost full */
 171 #define PCA200E_ESP_HOLD_RD     0x020   /* State of ESP hold bus */
 172 #define PCA200E_OFIFO_FULL      0x010   /* Output FIFO almost full */
 173 #define PCA200E_HOLD_ACK        0x008   /* State of Hold Ack */
 174 #define PCA200E_SELFTEST_FAIL   0x004   /* i960 self-test failed */
 175 #define PCA200E_HOLD_LOCK_RD    0x002   /* State of i960 hold lock signal */
 176 #define PCA200E_RESET_BD        0x001   /* State of board reset signal */
 177
 178 /* Write access */
 179 #define PCA200E_CLR_HBUS_INT    0x010   /* Clear host bus interrupt */
 180 #define PCA200E_I960_INTRA      0x008   /* Set slave interrupt A */
 181 #define PCA200E_I960_INTRB      0x004   /* Set slave interrupt B */
 182 #define PCA200E_HOLD_LOCK       0x002   /* Set (clear) i960 hold lock signal */
 183 #define PCA200E_RESET           0x001   /* Set (clear) board reset signal */
 184
 185 #define PCA200E_HCR_INIT(hcr,bits) \
 186                         ((hcr) = (PCA200E_WRITE_BITS & (bits)))
 187 #define PCA200E_HCR_SET(hcr,bits) \
 188                         ((hcr) = (bits))
 189 #define PCA200E_HCR_CLR(hcr,bits) \
 190                         ((hcr) = 0)
 191
 192 #endif  /* _FORE_SLAVE_H */