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HAMMER 60I/Many: Mirroring
[dragonfly.git] / sys / dev / agp / agp_nvidia.c
blob1b849db3ff8f0277deb3e768ad05f16b9fcfbb91
1 /*-
2 * Copyright (c) 2003 Matthew N. Dodd <winter@jurai.net>
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
7 * are met:
8 * 1. Redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer.
10 * 2. Redistributions in binary form must reproduce the above copyright
11 * notice, this list of conditions and the following disclaimer in the
12 * documentation and/or other materials provided with the distribution.
13 *
14 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
15 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
16 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
17 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
18 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
19 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
20 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
21 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
22 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
23 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
24 * SUCH DAMAGE.
25 *
26 * $FreeBSD: src/sys/dev/agp/agp_nvidia.c,v 1.13 2007/11/12 21:51:37 jhb Exp $
27 * $DragonFly: src/sys/dev/agp/agp_nvidia.c,v 1.7 2008/01/07 01:34:58 corecode Exp $
28 */
29
30 /*
31 * Written using information gleaned from the
32 * NVIDIA nForce/nForce2 AGPGART Linux Kernel Patch.
33 */
34
35 #include "opt_bus.h"
36
37 #include <sys/param.h>
38 #include <sys/systm.h>
39 #include <sys/malloc.h>
40 #include <sys/kernel.h>
41 #include <sys/bus.h>
42 #include <sys/lock.h>
43 #include <sys/rman.h>
44
45 #include <bus/pci/pcivar.h>
46 #include <bus/pci/pcireg.h>
47 #include "agppriv.h"
48 #include "agpreg.h"
49
50 #include <vm/vm.h>
51 #include <vm/vm_object.h>
52 #include <vm/pmap.h>
53
54 #define NVIDIA_VENDORID 0x10de
55 #define NVIDIA_DEVICEID_NFORCE 0x01a4
56 #define NVIDIA_DEVICEID_NFORCE2 0x01e0
57
58 struct agp_nvidia_softc {
59 struct agp_softc agp;
60 u_int32_t initial_aperture; /* aperture size at startup */
61 struct agp_gatt * gatt;
62
63 device_t dev; /* AGP Controller */
64 device_t mc1_dev; /* Memory Controller */
65 device_t mc2_dev; /* Memory Controller */
66 device_t bdev; /* Bridge */
67
68 u_int32_t wbc_mask;
69 int num_dirs;
70 int num_active_entries;
71 off_t pg_offset;
72 };
73
74 static const char *agp_nvidia_match(device_t dev);
75 static int agp_nvidia_probe(device_t);
76 static int agp_nvidia_attach(device_t);
77 static int agp_nvidia_detach(device_t);
78 static u_int32_t agp_nvidia_get_aperture(device_t);
79 static int agp_nvidia_set_aperture(device_t, u_int32_t);
80 static int agp_nvidia_bind_page(device_t, int, vm_offset_t);
81 static int agp_nvidia_unbind_page(device_t, int);
82
83 static int nvidia_init_iorr(u_int32_t, u_int32_t);
84
85 static const char *
86 agp_nvidia_match (device_t dev)
87 {
88 if (pci_get_class(dev) != PCIC_BRIDGE ||
89 pci_get_subclass(dev) != PCIS_BRIDGE_HOST ||
90 pci_get_vendor(dev) != NVIDIA_VENDORID)
91 return (NULL);
92
93 switch (pci_get_device(dev)) {
94 case NVIDIA_DEVICEID_NFORCE:
95 return ("NVIDIA nForce AGP Controller");
96 case NVIDIA_DEVICEID_NFORCE2:
97 return ("NVIDIA nForce2 AGP Controller");
98 }
99 return (NULL);
100 }
101
102 static int
103 agp_nvidia_probe (device_t dev)
104 {
105 const char *desc;
106
107 if (resource_disabled("agp", device_get_unit(dev)))
108 return (ENXIO);
109 desc = agp_nvidia_match(dev);
110 if (desc) {
111 device_verbose(dev);
112 device_set_desc(dev, desc);
113 return (BUS_PROBE_DEFAULT);
114 }
115 return (ENXIO);
116 }
117
118 static int
119 agp_nvidia_attach (device_t dev)
120 {
121 struct agp_nvidia_softc *sc = device_get_softc(dev);
122 struct agp_gatt *gatt;
123 u_int32_t apbase;
124 u_int32_t aplimit;
125 u_int32_t temp;
126 int size;
127 int i;
128 int error;
129
130 switch (pci_get_device(dev)) {
131 case NVIDIA_DEVICEID_NFORCE:
132 sc->wbc_mask = 0x00010000;
133 break;
134 case NVIDIA_DEVICEID_NFORCE2:
135 sc->wbc_mask = 0x80000000;
136 break;
137 default:
138 device_printf(dev, "Bad chip id\n");
139 return (ENODEV);
140 }
141
142 /* AGP Controller */
143 sc->dev = dev;
144
145 /* Memory Controller 1 */
146 sc->mc1_dev = pci_find_bsf(pci_get_bus(dev), 0, 1);
147 if (sc->mc1_dev == NULL) {
148 device_printf(dev,
149 "Unable to find NVIDIA Memory Controller 1.\n");
150 return (ENODEV);
151 }
152
153 /* Memory Controller 2 */
154 sc->mc2_dev = pci_find_bsf(pci_get_bus(dev), 0, 2);
155 if (sc->mc2_dev == NULL) {
156 device_printf(dev,
157 "Unable to find NVIDIA Memory Controller 2.\n");
158 return (ENODEV);
159 }
160
161 /* AGP Host to PCI Bridge */
162 sc->bdev = pci_find_bsf(pci_get_bus(dev), 30, 0);
163 if (sc->bdev == NULL) {
164 device_printf(dev,
165 "Unable to find NVIDIA AGP Host to PCI Bridge.\n");
166 return (ENODEV);
167 }
168
169 error = agp_generic_attach(dev);
170 if (error)
171 return (error);
172
173 sc->initial_aperture = AGP_GET_APERTURE(dev);
174 if (sc->initial_aperture == 0) {
175 device_printf(dev, "bad initial aperture size, disabling\n");
176 return ENXIO;
177 }
178
179 for (;;) {
180 gatt = agp_alloc_gatt(dev);
181 if (gatt)
182 break;
183 /*
184 * Probably contigmalloc failure. Try reducing the
185 * aperture so that the gatt size reduces.
186 */
187 if (AGP_SET_APERTURE(dev, AGP_GET_APERTURE(dev) / 2))
188 goto fail;
189 }
190 sc->gatt = gatt;
191
192 apbase = rman_get_start(sc->agp.as_aperture);
193 aplimit = apbase + AGP_GET_APERTURE(dev) - 1;
194 pci_write_config(sc->mc2_dev, AGP_NVIDIA_2_APBASE, apbase, 4);
195 pci_write_config(sc->mc2_dev, AGP_NVIDIA_2_APLIMIT, aplimit, 4);
196 pci_write_config(sc->bdev, AGP_NVIDIA_3_APBASE, apbase, 4);
197 pci_write_config(sc->bdev, AGP_NVIDIA_3_APLIMIT, aplimit, 4);
198
199 error = nvidia_init_iorr(apbase, AGP_GET_APERTURE(dev));
200 if (error) {
201 device_printf(dev, "Failed to setup IORRs\n");
202 goto fail;
203 }
204
205 /* directory size is 64k */
206 size = AGP_GET_APERTURE(dev) / 1024 / 1024;
207 sc->num_dirs = size / 64;
208 sc->num_active_entries = (size == 32) ? 16384 : ((size * 1024) / 4);
209 sc->pg_offset = 0;
210 if (sc->num_dirs == 0) {
211 sc->num_dirs = 1;
212 sc->num_active_entries /= (64 / size);
213 sc->pg_offset = (apbase & (64 * 1024 * 1024 - 1) &
214 ~(AGP_GET_APERTURE(dev) - 1)) / PAGE_SIZE;
215 }
216
217 /* (G)ATT Base Address */
218 for (i = 0; i < 8; i++) {
219 pci_write_config(sc->mc2_dev, AGP_NVIDIA_2_ATTBASE(i),
220 (sc->gatt->ag_physical +
221 (i % sc->num_dirs) * 64 * 1024) | 1, 4);
222 }
223
224 /* GTLB Control */
225 temp = pci_read_config(sc->mc2_dev, AGP_NVIDIA_2_GARTCTRL, 4);
226 pci_write_config(sc->mc2_dev, AGP_NVIDIA_2_GARTCTRL, temp | 0x11, 4);
227
228 /* GART Control */
229 temp = pci_read_config(sc->dev, AGP_NVIDIA_0_APSIZE, 4);
230 pci_write_config(sc->dev, AGP_NVIDIA_0_APSIZE, temp | 0x100, 4);
231
232 return (0);
233 fail:
234 agp_generic_detach(dev);
235 return (ENOMEM);
236 }
237
238 static int
239 agp_nvidia_detach (device_t dev)
240 {
241 struct agp_nvidia_softc *sc = device_get_softc(dev);
242 u_int32_t temp;
243
244 agp_free_cdev(dev);
245
246 /* GART Control */
247 temp = pci_read_config(sc->dev, AGP_NVIDIA_0_APSIZE, 4);
248 pci_write_config(sc->dev, AGP_NVIDIA_0_APSIZE, temp & ~(0x100), 4);
249
250 /* GTLB Control */
251 temp = pci_read_config(sc->mc2_dev, AGP_NVIDIA_2_GARTCTRL, 4);
252 pci_write_config(sc->mc2_dev, AGP_NVIDIA_2_GARTCTRL, temp & ~(0x11), 4);
253
254 /* Put the aperture back the way it started. */
255 AGP_SET_APERTURE(dev, sc->initial_aperture);
256
257 /* restore iorr for previous aperture size */
258 nvidia_init_iorr(rman_get_start(sc->agp.as_aperture),
259 sc->initial_aperture);
260
261 agp_free_gatt(sc->gatt);
262 agp_free_res(dev);
263
264 return (0);
265 }
266
267 static u_int32_t
268 agp_nvidia_get_aperture(device_t dev)
269 {
270 switch (pci_read_config(dev, AGP_NVIDIA_0_APSIZE, 1) & 0x0f) {
271 case 0: return (512 * 1024 * 1024); break;
272 case 8: return (256 * 1024 * 1024); break;
273 case 12: return (128 * 1024 * 1024); break;
274 case 14: return (64 * 1024 * 1024); break;
275 case 15: return (32 * 1024 * 1024); break;
276 default:
277 device_printf(dev, "Invalid aperture setting 0x%x",
278 pci_read_config(dev, AGP_NVIDIA_0_APSIZE, 1));
279 return 0;
280 }
281 }
282
283 static int
284 agp_nvidia_set_aperture(device_t dev, u_int32_t aperture)
285 {
286 u_int8_t val;
287 u_int8_t key;
288
289 switch (aperture) {
290 case (512 * 1024 * 1024): key = 0; break;
291 case (256 * 1024 * 1024): key = 8; break;
292 case (128 * 1024 * 1024): key = 12; break;
293 case (64 * 1024 * 1024): key = 14; break;
294 case (32 * 1024 * 1024): key = 15; break;
295 default:
296 device_printf(dev, "Invalid aperture size (%dMb)\n",
297 aperture / 1024 / 1024);
298 return (EINVAL);
299 }
300 val = pci_read_config(dev, AGP_NVIDIA_0_APSIZE, 1);
301 pci_write_config(dev, AGP_NVIDIA_0_APSIZE, ((val & ~0x0f) | key), 1);
302
303 return (0);
304 }
305
306 static int
307 agp_nvidia_bind_page(device_t dev, int offset, vm_offset_t physical)
308 {
309 struct agp_nvidia_softc *sc = device_get_softc(dev);
310 u_int32_t index;
311
312 if (offset < 0 || offset >= (sc->gatt->ag_entries << AGP_PAGE_SHIFT))
313 return (EINVAL);
314
315 index = (sc->pg_offset + offset) >> AGP_PAGE_SHIFT;
316 sc->gatt->ag_virtual[index] = physical | 1;
317
318 return (0);
319 }
320
321 static int
322 agp_nvidia_unbind_page(device_t dev, int offset)
323 {
324 struct agp_nvidia_softc *sc = device_get_softc(dev);
325 u_int32_t index;
326
327 if (offset < 0 || offset >= (sc->gatt->ag_entries << AGP_PAGE_SHIFT))
328 return (EINVAL);
329
330 index = (sc->pg_offset + offset) >> AGP_PAGE_SHIFT;
331 sc->gatt->ag_virtual[index] = 0;
332
333 return (0);
334 }
335
336 static int
337 agp_nvidia_flush_tlb (device_t dev, int offset)
338 {
339 struct agp_nvidia_softc *sc;
340 u_int32_t wbc_reg, temp;
341 volatile u_int32_t *ag_virtual;
342 int i;
343
344 sc = (struct agp_nvidia_softc *)device_get_softc(dev);
345
346 if (sc->wbc_mask) {
347 wbc_reg = pci_read_config(sc->mc1_dev, AGP_NVIDIA_1_WBC, 4);
348 wbc_reg |= sc->wbc_mask;
349 pci_write_config(sc->mc1_dev, AGP_NVIDIA_1_WBC, wbc_reg, 4);
350
351 /* Wait no more than 3 seconds. */
352 for (i = 0; i < 3000; i++) {
353 wbc_reg = pci_read_config(sc->mc1_dev,
354 AGP_NVIDIA_1_WBC, 4);
355 if ((sc->wbc_mask & wbc_reg) == 0)
356 break;
357 else
358 DELAY(1000);
359 }
360 if (i == 3000)
361 device_printf(dev,
362 "TLB flush took more than 3 seconds.\n");
363 }
364
365 ag_virtual = (volatile u_int32_t *)sc->gatt->ag_virtual;
366
367 /* Flush TLB entries. */
368 for(i = 0; i < 32 + 1; i++)
369 temp = ag_virtual[i * PAGE_SIZE / sizeof(u_int32_t)];
370 for(i = 0; i < 32 + 1; i++)
371 temp = ag_virtual[i * PAGE_SIZE / sizeof(u_int32_t)];
372
373 return (0);
374 }
375
376 #define SYSCFG 0xC0010010
377 #define IORR_BASE0 0xC0010016
378 #define IORR_MASK0 0xC0010017
379 #define AMD_K7_NUM_IORR 2
380
381 static int
382 nvidia_init_iorr(u_int32_t addr, u_int32_t size)
383 {
384 quad_t base, mask, sys;
385 u_int32_t iorr_addr, free_iorr_addr;
386
387 /* Find the iorr that is already used for the addr */
388 /* If not found, determine the uppermost available iorr */
389 free_iorr_addr = AMD_K7_NUM_IORR;
390 for(iorr_addr = 0; iorr_addr < AMD_K7_NUM_IORR; iorr_addr++) {
391 base = rdmsr(IORR_BASE0 + 2 * iorr_addr);
392 mask = rdmsr(IORR_MASK0 + 2 * iorr_addr);
393
394 if ((base & 0xfffff000ULL) == (addr & 0xfffff000))
395 break;
396
397 if ((mask & 0x00000800ULL) == 0)
398 free_iorr_addr = iorr_addr;
399 }
400
401 if (iorr_addr >= AMD_K7_NUM_IORR) {
402 iorr_addr = free_iorr_addr;
403 if (iorr_addr >= AMD_K7_NUM_IORR)
404 return (EINVAL);
405 }
406
407 base = (addr & ~0xfff) | 0x18;
408 mask = (0xfULL << 32) | ((~(size - 1)) & 0xfffff000) | 0x800;
409 wrmsr(IORR_BASE0 + 2 * iorr_addr, base);
410 wrmsr(IORR_MASK0 + 2 * iorr_addr, mask);
411
412 sys = rdmsr(SYSCFG);
413 sys |= 0x00100000ULL;
414 wrmsr(SYSCFG, sys);
415
416 return (0);
417 }
418
419 static device_method_t agp_nvidia_methods[] = {
420 /* Device interface */
421 DEVMETHOD(device_probe, agp_nvidia_probe),
422 DEVMETHOD(device_attach, agp_nvidia_attach),
423 DEVMETHOD(device_detach, agp_nvidia_detach),
424 DEVMETHOD(device_shutdown, bus_generic_shutdown),
425 DEVMETHOD(device_suspend, bus_generic_suspend),
426 DEVMETHOD(device_resume, bus_generic_resume),
427
428 /* AGP interface */
429 DEVMETHOD(agp_get_aperture, agp_nvidia_get_aperture),
430 DEVMETHOD(agp_set_aperture, agp_nvidia_set_aperture),
431 DEVMETHOD(agp_bind_page, agp_nvidia_bind_page),
432 DEVMETHOD(agp_unbind_page, agp_nvidia_unbind_page),
433 DEVMETHOD(agp_flush_tlb, agp_nvidia_flush_tlb),
434
435 DEVMETHOD(agp_enable, agp_generic_enable),
436 DEVMETHOD(agp_alloc_memory, agp_generic_alloc_memory),
437 DEVMETHOD(agp_free_memory, agp_generic_free_memory),
438 DEVMETHOD(agp_bind_memory, agp_generic_bind_memory),
439 DEVMETHOD(agp_unbind_memory, agp_generic_unbind_memory),
440
441 { 0, 0 }
442 };
443
444 static driver_t agp_nvidia_driver = {
445 "agp",
446 agp_nvidia_methods,
447 sizeof(struct agp_nvidia_softc),
448 };
449
450 static devclass_t agp_devclass;
451
452 DRIVER_MODULE(agp_nvidia, pci, agp_nvidia_driver, agp_devclass, 0, 0);
453 MODULE_DEPEND(agp_nvidia, agp, 1, 1, 1);
454 MODULE_DEPEND(agp_nvidia, pci, 1, 1, 1);
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