sys/cpu/i386/include/specialreg.h

   1 /*-
   2  * Copyright (c) 1991 The Regents of the University of California.
   3  * All rights reserved.
   4  *
   5  * Redistribution and use in source and binary forms, with or without
   6  * modification, are permitted provided that the following conditions
   7  * are met:
   8  * 1. Redistributions of source code must retain the above copyright
   9  *    notice, this list of conditions and the following disclaimer.
  10  * 2. Redistributions in binary form must reproduce the above copyright
  11  *    notice, this list of conditions and the following disclaimer in the
  12  *    documentation and/or other materials provided with the distribution.
  13  * 3. All advertising materials mentioning features or use of this software
  14  *    must display the following acknowledgement:
  15  *      This product includes software developed by the University of
  16  *      California, Berkeley and its contributors.
  17  * 4. Neither the name of the University nor the names of its contributors
  18  *    may be used to endorse or promote products derived from this software
  19  *    without specific prior written permission.
  20  *
  21  * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND
  22  * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
  23  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
  24  * ARE DISCLAIMED.  IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE
  25  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
  26  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
  27  * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
  28  * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
  29  * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
  30  * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
  31  * SUCH DAMAGE.
  32  *
  33  *      from: @(#)specialreg.h  7.1 (Berkeley) 5/9/91
  34  * $FreeBSD: src/sys/i386/include/specialreg.h,v 1.19.2.3 2003/01/22 17:24:28 jhb Exp $
  35  * $DragonFly: src/sys/cpu/i386/include/specialreg.h,v 1.9 2007/10/02 13:16:42 hasso Exp $
  36  */
  37
  38 #ifndef _CPU_SPECIALREG_H_
  39 #define _CPU_SPECIALREG_H_
  40
  41 /*
  42  * Bits in 386 special registers:
  43  */
  44 #define CR0_PE  0x00000001      /* Protected mode Enable */
  45 #define CR0_MP  0x00000002      /* "Math" Present (NPX or NPX emulator) */
  46 #define CR0_EM  0x00000004      /* EMulate non-NPX coproc. (trap ESC only) */
  47 #define CR0_TS  0x00000008      /* Task Switched (if MP, trap ESC and WAIT) */
  48 #ifdef notused
  49 #define CR0_ET  0x00000010      /* Extension Type (387 (if set) vs 287) */
  50 #endif
  51 #define CR0_PG  0x80000000      /* PaGing enable */
  52
  53 /*
  54  * Bits in 486 special registers:
  55  */
  56 #define CR0_NE  0x00000020      /* Numeric Error enable (EX16 vs IRQ13) */
  57 #define CR0_WP  0x00010000      /* Write Protect (honor page protect in
  58                                                            all modes) */
  59 #define CR0_AM  0x00040000      /* Alignment Mask (set to enable AC flag) */
  60 #define CR0_NW  0x20000000      /* Not Write-through */
  61 #define CR0_CD  0x40000000      /* Cache Disable */
  62
  63 /*
  64  * Bits in PPro special registers
  65  */
  66 #define CR4_VME 0x00000001      /* Virtual 8086 mode extensions */
  67 #define CR4_PVI 0x00000002      /* Protected-mode virtual interrupts */
  68 #define CR4_TSD 0x00000004      /* Time stamp disable */
  69 #define CR4_DE  0x00000008      /* Debugging extensions */
  70 #define CR4_PSE 0x00000010      /* Page size extensions */
  71 #define CR4_PAE 0x00000020      /* Physical address extension */
  72 #define CR4_MCE 0x00000040      /* Machine check enable */
  73 #define CR4_PGE 0x00000080      /* Page global enable */
  74 #define CR4_PCE 0x00000100      /* Performance monitoring counter enable */
  75 #define CR4_FXSR 0x00000200     /* Fast FPU save/restore used by OS */
  76 #define CR4_XMM 0x00000400      /* enable SIMD/MMX2 to use except 16 */
  77
  78 /*
  79  * CPUID instruction features register
  80  */
  81 #define CPUID_FPU       0x00000001
  82 #define CPUID_VME       0x00000002
  83 #define CPUID_DE        0x00000004
  84 #define CPUID_PSE       0x00000008
  85 #define CPUID_TSC       0x00000010
  86 #define CPUID_MSR       0x00000020
  87 #define CPUID_PAE       0x00000040
  88 #define CPUID_MCE       0x00000080
  89 #define CPUID_CX8       0x00000100
  90 #define CPUID_APIC      0x00000200
  91 #define CPUID_B10       0x00000400
  92 #define CPUID_SEP       0x00000800
  93 #define CPUID_MTRR      0x00001000
  94 #define CPUID_PGE       0x00002000
  95 #define CPUID_MCA       0x00004000
  96 #define CPUID_CMOV      0x00008000
  97 #define CPUID_PAT       0x00010000
  98 #define CPUID_PSE36     0x00020000
  99 #define CPUID_PSN       0x00040000
 100 #define CPUID_CLFSH     0x00080000
 101 #define CPUID_B20       0x00100000
 102 #define CPUID_DS        0x00200000
 103 #define CPUID_ACPI      0x00400000
 104 #define CPUID_MMX       0x00800000
 105 #define CPUID_FXSR      0x01000000
 106 #define CPUID_SSE       0x02000000
 107 #define CPUID_XMM       0x02000000
 108 #define CPUID_SSE2      0x04000000
 109 #define CPUID_SS        0x08000000
 110 #define CPUID_HTT       0x10000000
 111 #define CPUID_TM        0x20000000
 112 #define CPUID_B30       0x40000000
 113 #define CPUID_PBE       0x80000000
 114
 115 #define CPUID2_SSE3     0x00000001
 116 #define CPUID2_MON      0x00000008
 117 #define CPUID2_DS_CPL   0x00000010
 118 #define CPUID2_VMX      0x00000020
 119 #define CPUID2_EST      0x00000080
 120 #define CPUID2_TM2      0x00000100
 121 #define CPUID2_SSSE3    0x00000200
 122 #define CPUID2_CNTXID   0x00000400
 123 #define CPUID2_CX16     0x00002000
 124
 125 /*
 126  * CPUID instruction 1 ebx info
 127  */
 128 #define CPUID_BRAND_INDEX       0x000000ff
 129 #define CPUID_CLFUSH_SIZE       0x0000ff00
 130 #define CPUID_HTT_CORES         0x00ff0000
 131 #define CPUID_LOCAL_APIC_ID     0xff000000
 132
 133 /*
 134  * Model-specific registers for the i386 family
 135  */
 136 #define MSR_P5_MC_ADDR          0x000
 137 #define MSR_P5_MC_TYPE          0x001
 138 #define MSR_TSC                 0x010
 139 #define MSR_APICBASE            0x01b
 140 #define MSR_EBL_CR_POWERON      0x02a
 141 #define MSR_BIOS_UPDT_TRIG      0x079
 142 #define MSR_BIOS_SIGN           0x08b
 143 #define MSR_PERFCTR0            0x0c1
 144 #define MSR_PERFCTR1            0x0c2
 145 #define MSR_IA32_EXT_CONFIG     0x0ee   /* Undocumented. Core Solo/Duo only */
 146 #define MSR_MTRRcap             0x0fe
 147 #define MSR_MCG_CAP             0x179
 148 #define MSR_MCG_STATUS          0x17a
 149 #define MSR_MCG_CTL             0x17b
 150 #define MSR_EVNTSEL0            0x186
 151 #define MSR_EVNTSEL1            0x187
 152 #define MSR_DEBUGCTLMSR         0x1d9
 153 #define MSR_LASTBRANCHFROMIP    0x1db
 154 #define MSR_LASTBRANCHTOIP      0x1dc
 155 #define MSR_LASTINTFROMIP       0x1dd
 156 #define MSR_LASTINTTOIP         0x1de
 157 #define MSR_ROB_CR_BKUPTMPDR6   0x1e0
 158 #define MSR_MTRRVarBase         0x200
 159 #define MSR_MTRR64kBase         0x250
 160 #define MSR_MTRR16kBase         0x258
 161 #define MSR_MTRR4kBase          0x268
 162 #define MSR_MTRRdefType         0x2ff
 163 #define MSR_MC0_CTL             0x400
 164 #define MSR_MC0_STATUS          0x401
 165 #define MSR_MC0_ADDR            0x402
 166 #define MSR_MC0_MISC            0x403
 167 #define MSR_MC1_CTL             0x404
 168 #define MSR_MC1_STATUS          0x405
 169 #define MSR_MC1_ADDR            0x406
 170 #define MSR_MC1_MISC            0x407
 171 #define MSR_MC2_CTL             0x408
 172 #define MSR_MC2_STATUS          0x409
 173 #define MSR_MC2_ADDR            0x40a
 174 #define MSR_MC2_MISC            0x40b
 175 #define MSR_MC4_CTL             0x40c
 176 #define MSR_MC4_STATUS          0x40d
 177 #define MSR_MC4_ADDR            0x40e
 178 #define MSR_MC4_MISC            0x40f
 179 #define MSR_MC3_CTL             0x410
 180 #define MSR_MC3_STATUS          0x411
 181 #define MSR_MC3_ADDR            0x412
 182 #define MSR_MC3_MISC            0x413
 183 #define MSR_THERM_CONTROL       0x19a
 184 #define MSR_THERM_INTERRUPT     0x19b
 185 #define MSR_THERM_STATUS        0x19c
 186
 187
 188 /*
 189  * Constants related to MTRRs
 190  */
 191 #define MTRR_N64K               8       /* numbers of fixed-size entries */
 192 #define MTRR_N16K               16
 193 #define MTRR_N4K                64
 194
 195 /*
 196  * Cyrix configuration registers, accessible as IO ports.
 197  */
 198 #define CCR0                    0xc0    /* Configuration control register 0 */
 199 #define CCR0_NC0                0x01    /* First 64K of each 1M memory region is
 200                                                                    non-cacheable */
 201 #define CCR0_NC1                0x02    /* 640K-1M region is non-cacheable */
 202 #define CCR0_A20M               0x04    /* Enables A20M# input pin */
 203 #define CCR0_KEN                0x08    /* Enables KEN# input pin */
 204 #define CCR0_FLUSH              0x10    /* Enables FLUSH# input pin */
 205 #define CCR0_BARB               0x20    /* Flushes internal cache when entering hold
 206                                                                    state */
 207 #define CCR0_CO                 0x40    /* Cache org: 1=direct mapped, 0=2x set
 208                                                                    assoc */
 209 #define CCR0_SUSPEND    0x80    /* Enables SUSP# and SUSPA# pins */
 210
 211 #define CCR1                    0xc1    /* Configuration control register 1 */
 212 #define CCR1_RPL                0x01    /* Enables RPLSET and RPLVAL# pins */
 213 #define CCR1_SMI                0x02    /* Enables SMM pins */
 214 #define CCR1_SMAC               0x04    /* System management memory access */
 215 #define CCR1_MMAC               0x08    /* Main memory access */
 216 #define CCR1_NO_LOCK    0x10    /* Negate LOCK# */
 217 #define CCR1_SM3                0x80    /* SMM address space address region 3 */
 218
 219 #define CCR2                    0xc2
 220 #define CCR2_WB                 0x02    /* Enables WB cache interface pins */
 221 #define CCR2_SADS               0x02    /* Slow ADS */
 222 #define CCR2_LOCK_NW    0x04    /* LOCK NW Bit */
 223 #define CCR2_SUSP_HLT   0x08    /* Suspend on HALT */
 224 #define CCR2_WT1                0x10    /* WT region 1 */
 225 #define CCR2_WPR1               0x10    /* Write-protect region 1 */
 226 #define CCR2_BARB               0x20    /* Flushes write-back cache when entering
 227                                                                    hold state. */
 228 #define CCR2_BWRT               0x40    /* Enables burst write cycles */
 229 #define CCR2_USE_SUSP   0x80    /* Enables suspend pins */
 230
 231 #define CCR3                    0xc3
 232 #define CCR3_SMILOCK    0x01    /* SMM register lock */
 233 #define CCR3_NMI                0x02    /* Enables NMI during SMM */
 234 #define CCR3_LINBRST    0x04    /* Linear address burst cycles */
 235 #define CCR3_SMMMODE    0x08    /* SMM Mode */
 236 #define CCR3_MAPEN0             0x10    /* Enables Map0 */
 237 #define CCR3_MAPEN1             0x20    /* Enables Map1 */
 238 #define CCR3_MAPEN2             0x40    /* Enables Map2 */
 239 #define CCR3_MAPEN3             0x80    /* Enables Map3 */
 240
 241 #define CCR4                    0xe8
 242 #define CCR4_IOMASK             0x07
 243 #define CCR4_MEM                0x08    /* Enables momory bypassing */
 244 #define CCR4_DTE                0x10    /* Enables directory table entry cache */
 245 #define CCR4_FASTFPE    0x20    /* Fast FPU exception */
 246 #define CCR4_CPUID              0x80    /* Enables CPUID instruction */
 247
 248 #define CCR5                    0xe9
 249 #define CCR5_WT_ALLOC   0x01    /* Write-through allocate */
 250 #define CCR5_SLOP               0x02    /* LOOP instruction slowed down */
 251 #define CCR5_LBR1               0x10    /* Local bus region 1 */
 252 #define CCR5_ARREN              0x20    /* Enables ARR region */
 253
 254 #define CCR6                    0xea
 255
 256 #define CCR7                    0xeb
 257
 258 /* Performance Control Register (5x86 only). */
 259 #define PCR0                    0x20
 260 #define PCR0_RSTK               0x01    /* Enables return stack */
 261 #define PCR0_BTB                0x02    /* Enables branch target buffer */
 262 #define PCR0_LOOP               0x04    /* Enables loop */
 263 #define PCR0_AIS                0x08    /* Enables all instrcutions stalled to
 264                                                                    serialize pipe. */
 265 #define PCR0_MLR                0x10    /* Enables reordering of misaligned loads */
 266 #define PCR0_BTBRT              0x40    /* Enables BTB test register. */
 267 #define PCR0_LSSER              0x80    /* Disable reorder */
 268
 269 /* Device Identification Registers */
 270 #define DIR0                    0xfe
 271 #define DIR1                    0xff
 272
 273 /*
 274  * The following four 3-byte registers control the non-cacheable regions.
 275  * These registers must be written as three separate bytes.
 276  *
 277  * NCRx+0: A31-A24 of starting address
 278  * NCRx+1: A23-A16 of starting address
 279  * NCRx+2: A15-A12 of starting address | NCR_SIZE_xx.
 280  *
 281  * The non-cacheable region's starting address must be aligned to the
 282  * size indicated by the NCR_SIZE_xx field.
 283  */
 284 #define NCR1    0xc4
 285 #define NCR2    0xc7
 286 #define NCR3    0xca
 287 #define NCR4    0xcd
 288
 289 #define NCR_SIZE_0K     0
 290 #define NCR_SIZE_4K     1
 291 #define NCR_SIZE_8K     2
 292 #define NCR_SIZE_16K    3
 293 #define NCR_SIZE_32K    4
 294 #define NCR_SIZE_64K    5
 295 #define NCR_SIZE_128K   6
 296 #define NCR_SIZE_256K   7
 297 #define NCR_SIZE_512K   8
 298 #define NCR_SIZE_1M     9
 299 #define NCR_SIZE_2M     10
 300 #define NCR_SIZE_4M     11
 301 #define NCR_SIZE_8M     12
 302 #define NCR_SIZE_16M    13
 303 #define NCR_SIZE_32M    14
 304 #define NCR_SIZE_4G     15
 305
 306 /*
 307  * The address region registers are used to specify the location and
 308  * size for the eight address regions.
 309  *
 310  * ARRx + 0: A31-A24 of start address
 311  * ARRx + 1: A23-A16 of start address
 312  * ARRx + 2: A15-A12 of start address | ARR_SIZE_xx
 313  */
 314 #define ARR0    0xc4
 315 #define ARR1    0xc7
 316 #define ARR2    0xca
 317 #define ARR3    0xcd
 318 #define ARR4    0xd0
 319 #define ARR5    0xd3
 320 #define ARR6    0xd6
 321 #define ARR7    0xd9
 322
 323 #define ARR_SIZE_0K             0
 324 #define ARR_SIZE_4K             1
 325 #define ARR_SIZE_8K             2
 326 #define ARR_SIZE_16K    3
 327 #define ARR_SIZE_32K    4
 328 #define ARR_SIZE_64K    5
 329 #define ARR_SIZE_128K   6
 330 #define ARR_SIZE_256K   7
 331 #define ARR_SIZE_512K   8
 332 #define ARR_SIZE_1M             9
 333 #define ARR_SIZE_2M             10
 334 #define ARR_SIZE_4M             11
 335 #define ARR_SIZE_8M             12
 336 #define ARR_SIZE_16M    13
 337 #define ARR_SIZE_32M    14
 338 #define ARR_SIZE_4G             15
 339
 340 /*
 341  * The region control registers specify the attributes associated with
 342  * the ARRx addres regions.
 343  */
 344 #define RCR0    0xdc
 345 #define RCR1    0xdd
 346 #define RCR2    0xde
 347 #define RCR3    0xdf
 348 #define RCR4    0xe0
 349 #define RCR5    0xe1
 350 #define RCR6    0xe2
 351 #define RCR7    0xe3
 352
 353 #define RCR_RCD 0x01    /* Disables caching for ARRx (x = 0-6). */
 354 #define RCR_RCE 0x01    /* Enables caching for ARR7. */
 355 #define RCR_WWO 0x02    /* Weak write ordering. */
 356 #define RCR_WL  0x04    /* Weak locking. */
 357 #define RCR_WG  0x08    /* Write gathering. */
 358 #define RCR_WT  0x10    /* Write-through. */
 359 #define RCR_NLB 0x20    /* LBA# pin is not asserted. */
 360
 361 /* AMD Write Allocate Top-Of-Memory and Control Register */
 362 #define AMD_WT_ALLOC_TME        0x40000 /* top-of-memory enable */
 363 #define AMD_WT_ALLOC_PRE        0x20000 /* programmable range enable */
 364 #define AMD_WT_ALLOC_FRE        0x10000 /* fixed (A0000-FFFFF) range enable */
 365
 366 #ifndef LOCORE
 367
 368 #ifndef _SYS_TYPES_H_
 369 #include <sys/types.h>
 370 #endif
 371 #ifndef _CPU_CPUFUNC_H_
 372 #include <cpu/cpufunc.h>
 373 #endif
 374
 375 static __inline u_char
 376 read_cyrix_reg(u_char reg)
 377 {
 378         outb(0x22, reg);
 379         return inb(0x23);
 380 }
 381
 382 static __inline void
 383 write_cyrix_reg(u_char reg, u_char data)
 384 {
 385         outb(0x22, reg);
 386         outb(0x23, data);
 387 }
 388 #endif
 389
 390 #endif /* !_CPU_SPECIALREG_H_ */