| blob | 67bd776179098546c8112a07569b0d97779981e4 |
1 /* Optimize by combining instructions for GNU compiler.
2 Copyright (C) 1987, 1988, 1992, 1993, 1994, 1995, 1996, 1997, 1998,
3 1999, 2000, 2001, 2002, 2003, 2004, 2005, 2006, 2007, 2008, 2009, 2010,
4 2011, 2012 Free Software Foundation, Inc.
6 This file is part of GCC.
8 GCC is free software; you can redistribute it and/or modify it under
9 the terms of the GNU General Public License as published by the Free
10 Software Foundation; either version 3, or (at your option) any later
11 version.
13 GCC is distributed in the hope that it will be useful, but WITHOUT ANY
14 WARRANTY; without even the implied warranty of MERCHANTABILITY or
15 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
16 for more details.
18 You should have received a copy of the GNU General Public License
19 along with GCC; see the file COPYING3. If not see
20 <http://www.gnu.org/licenses/>. */
22 /* This module is essentially the "combiner" phase of the U. of Arizona
23 Portable Optimizer, but redone to work on our list-structured
24 representation for RTL instead of their string representation.
26 The LOG_LINKS of each insn identify the most recent assignment
27 to each REG used in the insn. It is a list of previous insns,
28 each of which contains a SET for a REG that is used in this insn
29 and not used or set in between. LOG_LINKs never cross basic blocks.
30 They were set up by the preceding pass (lifetime analysis).
32 We try to combine each pair of insns joined by a logical link.
33 We also try to combine triples of insns A, B and C when
34 C has a link back to B and B has a link back to A.
36 LOG_LINKS does not have links for use of the CC0. They don't
37 need to, because the insn that sets the CC0 is always immediately
38 before the insn that tests it. So we always regard a branch
39 insn as having a logical link to the preceding insn. The same is true
40 for an insn explicitly using CC0.
42 We check (with use_crosses_set_p) to avoid combining in such a way
43 as to move a computation to a place where its value would be different.
45 Combination is done by mathematically substituting the previous
46 insn(s) values for the regs they set into the expressions in
47 the later insns that refer to these regs. If the result is a valid insn
48 for our target machine, according to the machine description,
49 we install it, delete the earlier insns, and update the data flow
50 information (LOG_LINKS and REG_NOTES) for what we did.
52 There are a few exceptions where the dataflow information isn't
53 completely updated (however this is only a local issue since it is
54 regenerated before the next pass that uses it):
56 - reg_live_length is not updated
57 - reg_n_refs is not adjusted in the rare case when a register is
58 no longer required in a computation
59 - there are extremely rare cases (see distribute_notes) when a
60 REG_DEAD note is lost
61 - a LOG_LINKS entry that refers to an insn with multiple SETs may be
62 removed because there is no way to know which register it was
63 linking
65 To simplify substitution, we combine only when the earlier insn(s)
66 consist of only a single assignment. To simplify updating afterward,
67 we never combine when a subroutine call appears in the middle.
69 Since we do not represent assignments to CC0 explicitly except when that
70 is all an insn does, there is no LOG_LINKS entry in an insn that uses
71 the condition code for the insn that set the condition code.
72 Fortunately, these two insns must be consecutive.
73 Therefore, every JUMP_INSN is taken to have an implicit logical link
74 to the preceding insn. This is not quite right, since non-jumps can
75 also use the condition code; but in practice such insns would not
76 combine anyway. */
91 /* Include expr.h after insn-config.h so we get HAVE_conditional_move. */
100 /* Include output.h for dump_file. */
109 /* Number of attempts to combine instructions in this function. */
113 /* Number of attempts that got as far as substitution in this function. */
117 /* Number of instructions combined with added SETs in this function. */
121 /* Number of instructions combined in this function. */
125 /* Totals over entire compilation. */
129 /* combine_instructions may try to replace the right hand side of the
130 second instruction with the value of an associated REG_EQUAL note
131 before throwing it at try_combine. That is problematic when there
132 is a REG_DEAD note for a register used in the old right hand side
133 and can cause distribute_notes to do wrong things. This is the
134 second instruction if it has been so modified, null otherwise. */
138 /* When I2MOD is nonnull, this is a copy of the old right hand side. */
142 /* When I2MOD is nonnull, this is a copy of the new right hand side. */
145 \f
147 /* Record last point of death of (hard or pseudo) register n. */
148 rtx last_death;
150 /* Record last point of modification of (hard or pseudo) register n. */
151 rtx last_set;
153 /* The next group of fields allows the recording of the last value assigned
154 to (hard or pseudo) register n. We use this information to see if an
155 operation being processed is redundant given a prior operation performed
156 on the register. For example, an `and' with a constant is redundant if
157 all the zero bits are already known to be turned off.
159 We use an approach similar to that used by cse, but change it in the
160 following ways:
162 (1) We do not want to reinitialize at each label.
163 (2) It is useful, but not critical, to know the actual value assigned
164 to a register. Often just its form is helpful.
166 Therefore, we maintain the following fields:
168 last_set_value the last value assigned
169 last_set_label records the value of label_tick when the
170 register was assigned
171 last_set_table_tick records the value of label_tick when a
172 value using the register is assigned
173 last_set_invalid set to nonzero when it is not valid
174 to use the value of this register in some
175 register's value
177 To understand the usage of these tables, it is important to understand
178 the distinction between the value in last_set_value being valid and
179 the register being validly contained in some other expression in the
180 table.
182 (The next two parameters are out of date).
184 reg_stat[i].last_set_value is valid if it is nonzero, and either
185 reg_n_sets[i] is 1 or reg_stat[i].last_set_label == label_tick.
187 Register I may validly appear in any expression returned for the value
188 of another register if reg_n_sets[i] is 1. It may also appear in the
189 value for register J if reg_stat[j].last_set_invalid is zero, or
190 reg_stat[i].last_set_label < reg_stat[j].last_set_label.
192 If an expression is found in the table containing a register which may
193 not validly appear in an expression, the register is replaced by
194 something that won't match, (clobber (const_int 0)). */
196 /* Record last value assigned to (hard or pseudo) register n. */
198 rtx last_set_value;
200 /* Record the value of label_tick when an expression involving register n
201 is placed in last_set_value. */
205 /* Record the value of label_tick when the value for register n is placed in
206 last_set_value. */
210 /* These fields are maintained in parallel with last_set_value and are
211 used to store the mode in which the register was last set, the bits
212 that were known to be zero when it was last set, and the number of
213 sign bits copies it was known to have when it was last set. */
219 /* Set nonzero if references to register n in expressions should not be
220 used. last_set_invalid is set nonzero when this register is being
221 assigned to and last_set_table_tick == label_tick. */
225 /* Some registers that are set more than once and used in more than one
226 basic block are nevertheless always set in similar ways. For example,
227 a QImode register may be loaded from memory in two places on a machine
228 where byte loads zero extend.
230 We record in the following fields if a register has some leading bits
231 that are always equal to the sign bit, and what we know about the
232 nonzero bits of a register, specifically which bits are known to be
233 zero.
235 If an entry is zero, it means that we don't know anything special. */
241 /* Record the value of the label_tick when the last truncation
242 happened. The field truncated_to_mode is only valid if
243 truncation_label == label_tick. */
247 /* Record the last truncation seen for this register. If truncation
248 is not a nop to this mode we might be able to save an explicit
249 truncation if we know that value already contains a truncated
250 value. */
260 /* Record the luid of the last insn that invalidated memory
261 (anything that writes memory, and subroutine calls, but not pushes). */
265 /* Record the luid of the last CALL_INSN
266 so we can tell whether a potential combination crosses any calls. */
270 /* When `subst' is called, this is the insn that is being modified
271 (by combining in a previous insn). The PATTERN of this insn
272 is still the old pattern partially modified and it should not be
273 looked at, but this may be used to examine the successors of the insn
274 to judge whether a simplification is valid. */
278 /* This is the lowest LUID that `subst' is currently dealing with.
279 get_last_value will not return a value if the register was set at or
280 after this LUID. If not for this mechanism, we could get confused if
281 I2 or I1 in try_combine were an insn that used the old value of a register
282 to obtain a new value. In that case, we might erroneously get the
283 new value of the register when we wanted the old one. */
287 /* This contains any hard registers that are used in newpat; reg_dead_at_p
288 must consider all these registers to be always live. */
292 /* This is an insn to which a LOG_LINKS entry has been added. If this
293 insn is the earlier than I2 or I3, combine should rescan starting at
294 that location. */
298 /* Basic block in which we are performing combines. */
302 \f
303 /* Length of the currently allocated uid_insn_cost array. */
307 /* The following array records the insn_rtx_cost for every insn
308 in the instruction stream. */
312 /* The following array records the LOG_LINKS for every insn in the
313 instruction stream as struct insn_link pointers. */
316 rtx insn;
318 };
322 #define INSN_COST(INSN) (uid_insn_cost[INSN_UID (INSN)])
323 #define LOG_LINKS(INSN) (uid_log_links[INSN_UID (INSN)])
325 #define FOR_EACH_LOG_LINK(L, INSN) \
326 for ((L) = LOG_LINKS (INSN); (L); (L) = (L)->next)
328 /* Links for LOG_LINKS are allocated from this obstack. */
332 /* Allocate a link. */
336 {
343 }
345 /* Incremented for each basic block. */
349 /* Reset to label_tick for each extended basic block in scanning order. */
353 /* Mode used to compute significance in reg_stat[].nonzero_bits. It is the
354 largest integer mode that can fit in HOST_BITS_PER_WIDE_INT. */
358 /* Nonzero when reg_stat[].nonzero_bits and reg_stat[].sign_bit_copies can
359 be safely used. It is zero while computing them and after combine has
360 completed. This former test prevents propagating values based on
361 previously set values, which can be incorrect if a variable is modified
362 in a loop. */
366 \f
367 /* Record one modification to rtl structure
368 to be undone by storing old_contents into *where. */
372 struct undo
373 {
378 };
380 /* Record a bunch of changes to be undone, up to MAX_UNDO of them.
381 num_undo says how many are currently recorded.
383 other_insn is nonzero if we have modified some other insn in the process
384 of working on subst_insn. It must be verified too. */
386 struct undobuf
387 {
390 rtx other_insn;
391 };
395 /* Number of times the pseudo being substituted for
396 was found and replaced. */
477 \f
479 /* It is not safe to use ordinary gen_lowpart in combine.
480 See comments in gen_lowpart_for_combine. */
481 #undef RTL_HOOKS_GEN_LOWPART
482 #define RTL_HOOKS_GEN_LOWPART gen_lowpart_for_combine
484 /* Our implementation of gen_lowpart never emits a new pseudo. */
485 #undef RTL_HOOKS_GEN_LOWPART_NO_EMIT
486 #define RTL_HOOKS_GEN_LOWPART_NO_EMIT gen_lowpart_for_combine
488 #undef RTL_HOOKS_REG_NONZERO_REG_BITS
489 #define RTL_HOOKS_REG_NONZERO_REG_BITS reg_nonzero_bits_for_combine
491 #undef RTL_HOOKS_REG_NUM_SIGN_BIT_COPIES
492 #define RTL_HOOKS_REG_NUM_SIGN_BIT_COPIES reg_num_sign_bit_copies_for_combine
494 #undef RTL_HOOKS_REG_TRUNCATED_TO_MODE
495 #define RTL_HOOKS_REG_TRUNCATED_TO_MODE reg_truncated_to_mode
499 \f
500 /* Try to split PATTERN found in INSN. This returns NULL_RTX if
501 PATTERN can not be split. Otherwise, it returns an insn sequence.
502 This is a wrapper around split_insns which ensures that the
503 reg_stat vector is made larger if the splitter creates a new
504 register. */
506 static rtx
508 {
509 rtx ret;
517 }
519 /* This is used by find_single_use to locate an rtx in LOC that
520 contains exactly one use of DEST, which is typically either a REG
521 or CC0. It returns a pointer to the innermost rtx expression
522 containing DEST. Appearances of DEST that are being used to
523 totally replace it are not counted. */
527 {
536 {
547 /* If the destination is anything other than CC0, PC, a REG or a SUBREG
548 of a REG that occupies all of the REG, the insn uses DEST if
549 it is mentioned in the destination or the source. Otherwise, we
550 need just check the source. */
570 }
572 /* If it wasn't one of the common cases above, check each expression and
573 vector of this code. Look for a unique usage of DEST. */
577 {
579 {
584 else
590 /* Duplicate usage. */
592 }
594 {
598 {
604 else
611 }
612 }
613 }
616 }
619 /* See if DEST, produced in INSN, is used only a single time in the
620 sequel. If so, return a pointer to the innermost rtx expression in which
621 it is used.
623 If PLOC is nonzero, *PLOC is set to the insn containing the single use.
625 If DEST is cc0_rtx, we look only at the next insn. In that case, we don't
626 care about REG_DEAD notes or LOG_LINKS.
628 Otherwise, we find the single use by finding an insn that has a
629 LOG_LINKS pointing at INSN and has a REG_DEAD note for DEST. If DEST is
630 only referenced once in that insn, we know that it must be the first
631 and last insn referencing DEST. */
635 {
636 basic_block bb;
637 rtx next;
641 #ifdef HAVE_cc0
643 {
653 }
654 #endif
664 {
670 {
675 }
676 }
679 }
680 \f
681 /* Substitute NEWVAL, an rtx expression, into INTO, a place in some
682 insn. The substitution can be undone by undo_all. If INTO is already
683 set to NEWVAL, do not record this change. Because computing NEWVAL might
684 also call SUBST, we have to compute it before we put anything into
685 the undo table. */
687 static void
689 {
696 /* We'd like to catch as many invalid transformations here as
697 possible. Unfortunately, there are way too many mode changes
698 that are perfectly valid, so we'd waste too much effort for
699 little gain doing the checks here. Focus on catching invalid
700 transformations involving integer constants. */
703 {
704 /* Sanity check that we're replacing oldval with a CONST_INT
705 that is a valid sign-extension for the original mode. */
709 /* Replacing the operand of a SUBREG or a ZERO_EXTEND with a
710 CONST_INT is not valid, because after the replacement, the
711 original mode would be gone. Unfortunately, we can't tell
712 when do_SUBST is called to replace the operand thereof, so we
713 perform this test on oldval instead, checking whether an
714 invalid replacement took place before we got here. */
719 }
723 else
732 }
734 #define SUBST(INTO, NEWVAL) do_SUBST(&(INTO), (NEWVAL))
736 /* Similar to SUBST, but NEWVAL is an int expression. Note that substitution
737 for the value of a HOST_WIDE_INT value (including CONST_INT) is
738 not safe. */
740 static void
742 {
751 else
760 }
762 #define SUBST_INT(INTO, NEWVAL) do_SUBST_INT(&(INTO), (NEWVAL))
764 /* Similar to SUBST, but just substitute the mode. This is used when
765 changing the mode of a pseudo-register, so that any other
766 references to the entry in the regno_reg_rtx array will change as
767 well. */
769 static void
771 {
780 else
789 }
791 #define SUBST_MODE(INTO, NEWVAL) do_SUBST_MODE(&(INTO), (NEWVAL))
793 #ifndef HAVE_cc0
794 /* Similar to SUBST, but NEWVAL is a LOG_LINKS expression. */
796 static void
798 {
807 else
816 }
818 #define SUBST_LINK(oldval, newval) do_SUBST_LINK (&oldval, newval)
819 #endif
820 \f
821 /* Subroutine of try_combine. Determine whether the replacement patterns
822 NEWPAT, NEWI2PAT and NEWOTHERPAT are cheaper according to insn_rtx_cost
823 than the original sequence I0, I1, I2, I3 and undobuf.other_insn. Note
824 that I0, I1 and/or NEWI2PAT may be NULL_RTX. Similarly, NEWOTHERPAT and
825 undobuf.other_insn may also both be NULL_RTX. Return false if the cost
826 of all the instructions can be estimated and the replacements are more
827 expensive than the original sequence. */
829 static bool
832 {
837 /* Lookup the original insn_rtx_costs. */
842 {
845 {
849 }
850 else
851 {
855 }
856 }
857 else
858 {
861 }
863 /* Calculate the replacement insn_rtx_costs. */
866 {
870 }
871 else
872 {
875 }
878 {
884 {
887 }
888 else
890 }
892 /* Disallow this combination if both new_cost and old_cost are greater than
893 zero, and new_cost is greater than old cost. */
895 {
897 {
899 {
906 }
908 {
914 }
915 else
916 {
922 }
925 {
928 }
929 else
931 }
934 }
936 /* Update the uid_insn_cost array with the replacement costs. */
940 {
944 }
947 }
950 /* Delete any insns that copy a register to itself. */
952 static void
954 {
956 basic_block bb;
959 {
961 {
964 {
969 }
970 }
971 }
972 }
974 \f
975 /* Fill in log links field for all insns. */
977 static void
979 {
980 basic_block bb;
986 /* Pass through each block from the end, recording the uses of each
987 register and establishing log links when def is encountered.
988 Note that we do not clear next_use array in order to save time,
989 so we have to test whether the use is in the same basic block as def.
991 There are a few cases below when we do not consider the definition or
992 usage -- these are taken from original flow.c did. Don't ask me why it is
993 done this way; I don't know and if it works, I don't want to know. */
996 {
998 {
1002 /* Log links are created only once. */
1006 {
1009 rtx use_insn;
1014 /* Do not consider if it is pre/post modification in MEM. */
1018 /* Do not make the log link for frame pointer. */
1021 #if !HARD_FRAME_POINTER_IS_FRAME_POINTER
1024 #endif
1025 #if FRAME_POINTER_REGNUM != ARG_POINTER_REGNUM
1027 #endif
1028 )
1033 {
1034 /* flow.c claimed:
1036 We don't build a LOG_LINK for hard registers contained
1037 in ASM_OPERANDs. If these registers get replaced,
1038 we might wind up changing the semantics of the insn,
1039 even if reload can make what appear to be valid
1040 assignments later. */
1043 {
1044 /* Don't add duplicate links between instructions. */
1053 }
1054 }
1056 }
1059 {
1063 /* Do not consider the usage of the stack pointer
1064 by function call. */
1069 }
1070 }
1071 }
1074 }
1076 /* Walk the LOG_LINKS of insn B to see if we find a reference to A. Return
1077 true if we found a LOG_LINK that proves that A feeds B. This only works
1078 if there are no instructions between A and B which could have a link
1079 depending on A, since in that case we would not record a link for B.
1080 We also check the implicit dependency created by a cc0 setter/user
1081 pair. */
1083 static bool
1085 {
1090 #ifdef HAVE_cc0
1093 #endif
1095 }
1096 \f
1097 /* Main entry point for combiner. F is the first insn of the function.
1098 NREGS is the first unused pseudo-reg number.
1100 Return nonzero if the combiner has turned an indirect jump
1101 instruction into a direct jump. */
1102 static int
1104 {
1106 #ifdef HAVE_cc0
1107 rtx prev;
1108 #endif
1110 rtx first;
1111 basic_block last_bb;
1131 /* Allocate array for insn info. */
1139 /* Don't use reg_stat[].nonzero_bits when computing it. This can cause
1140 problems when, for example, we have j <<= 1 in a loop. */
1145 /* Scan all SETs and see if we can deduce anything about what
1146 bits are known to be zero for some registers and how many copies
1147 of the sign bit are known to exist for those registers.
1149 Also set any known values so that we can use it while searching
1150 for what bits are known to be set. */
1153 /* Allow the entry block and the first block to fall into the same EBB.
1154 Conceptually the incoming promotions are assigned to the entry block. */
1159 {
1164 label_tick++;
1172 {
1173 #ifdef AUTO_INC_DEC
1174 rtx links;
1175 #endif
1181 insn);
1184 #ifdef AUTO_INC_DEC
1188 insn);
1189 #endif
1191 /* Record the current insn_rtx_cost of this instruction. */
1194 optimize_this_for_speed_p);
1198 }
1199 }
1203 /* Now scan all the insns in forward order. */
1210 {
1216 label_tick++;
1226 {
1229 {
1239 /* See if we know about function return values before this
1240 insn based upon SUBREG flags. */
1243 /* See if we can find hardregs and subreg of pseudos in
1244 narrower modes. This could help turning TRUNCATEs
1245 into SUBREGs. */
1248 /* Try this insn with each insn it links back to. */
1256 /* Try each sequence of three linked insns ending with this one. */
1259 {
1262 /* If the linked insn has been replaced by a note, then there
1263 is no point in pursuing this chain any further. */
1272 }
1274 #ifdef HAVE_cc0
1275 /* Try to combine a jump insn that uses CC0
1276 with a preceding insn that sets CC0, and maybe with its
1277 logical predecessor as well.
1278 This is how we make decrement-and-branch insns.
1279 We need this special code because data flow connections
1280 via CC0 do not get entered in LOG_LINKS. */
1286 {
1297 }
1299 /* Do the same for an insn that explicitly references CC0. */
1306 {
1317 }
1319 /* Finally, see if any of the insns that this insn links to
1320 explicitly references CC0. If so, try this insn, that insn,
1321 and its predecessor if it sets CC0. */
1333 #endif
1335 /* Try combining an insn with two different insns whose results it
1336 uses. */
1346 /* Try four-instruction combinations. */
1348 {
1352 /* If the linked insn has been replaced by a note, then there
1353 is no point in pursuing this chain any further. */
1358 {
1362 /* I0 -> I1 -> I2 -> I3. */
1369 /* I0, I1 -> I2, I2 -> I3. */
1377 }
1380 {
1384 /* I0 -> I2; I1, I2 -> I3. */
1391 /* I0 -> I1; I1, I2 -> I3. */
1398 }
1399 }
1401 /* Try this insn with each REG_EQUAL note it links back to. */
1403 {
1409 /* Avoid using a register that may already been marked
1410 dead by an earlier instruction. */
1415 {
1416 /* Temporarily replace the set's source with the
1417 contents of the REG_EQUAL note. The insn will
1418 be deleted or recognized by try_combine. */
1426 last_combined_insn);
1431 }
1432 }
1437 retry:
1438 ;
1439 }
1440 }
1441 }
1448 /* Clean up. */
1454 {
1457 {
1460 }
1462 }
1472 /* Make recognizer allow volatile MEMs again. */
1476 }
1478 /* Wipe the last_xxx fields of reg_stat in preparation for another pass. */
1480 static void
1482 {
1488 }
1489 \f
1490 /* Set up any promoted values for incoming argument registers. */
1492 static void
1494 {
1495 tree arg;
1500 {
1505 /* Only continue if the incoming argument is in a register. */
1509 /* Determine, if possible, whether all call sites of the current
1510 function lie within the current compilation unit. (This does
1511 take into account the exporting of a function via taking its
1512 address, and so forth.) */
1515 /* The mode and signedness of the argument before any promotions happen
1516 (equal to the mode of the pseudo holding it at that stage). */
1520 /* The mode and signedness of the argument after any source language and
1521 TARGET_PROMOTE_PROTOTYPES-driven promotions. */
1525 /* The mode and signedness of the argument as it is actually passed,
1526 after any TARGET_PROMOTE_FUNCTION_ARGS-driven ABI promotions. */
1530 /* The mode of the register in which the argument is being passed. */
1533 /* Eliminate sign extensions in the callee when:
1534 (a) A mode promotion has occurred; */
1537 /* (b) The mode of the register is the same as the mode of
1538 the argument as it is passed; */
1541 /* (c) There's no language level extension; */
1543 ;
1544 /* (c.1) All callers are from the current compilation unit. If that's
1545 the case we don't have to rely on an ABI, we only have to know
1546 what we're generating right now, and we know that we will do the
1547 mode1 to mode2 promotion with the given sign. */
1550 /* (c.2) The combination of the two promotions is useful. This is
1551 true when the signs match, or if the first promotion is unsigned.
1552 In the later case, (sign_extend (zero_extend x)) is the same as
1553 (zero_extend (zero_extend x)), so make sure to force UNS3 true. */
1559 /* Record that the value was promoted from mode1 to mode3,
1560 so that any sign extension at the head of the current
1561 function may be eliminated. */
1565 }
1566 }
1568 /* Called via note_stores. If X is a pseudo that is narrower than
1569 HOST_BITS_PER_WIDE_INT and is being set, record what bits are known zero.
1571 If we are setting only a portion of X and we can't figure out what
1572 portion, assume all bits will be used since we don't know what will
1573 be happening.
1575 Similarly, set how many bits of X are known to be copies of the sign bit
1576 at all locations in the function. This is the smallest number implied
1577 by any set of X. */
1579 static void
1581 {
1587 /* If this register is undefined at the start of the file, we can't
1588 say what its contents were. */
1589 && ! REGNO_REG_SET_P
1592 {
1596 {
1600 }
1602 /* If this register is being initialized using itself, and the
1603 register is uninitialized in this basic block, and there are
1604 no LOG_LINKS which set the register, then part of the
1605 register is uninitialized. In that case we can't assume
1606 anything about the number of nonzero bits.
1608 ??? We could do better if we checked this in
1609 reg_{nonzero_bits,num_sign_bit_copies}_for_combine. Then we
1610 could avoid making assumptions about the insn which initially
1611 sets the register, while still using the information in other
1612 insns. We would have to be careful to check every insn
1613 involved in the combination. */
1619 {
1626 {
1630 }
1631 }
1633 /* If this is a complex assignment, see if we can convert it into a
1634 simple assignment. */
1637 /* If this is a simple assignment, or we have a paradoxical SUBREG,
1638 set what we know about X. */
1643 {
1646 #ifdef SHORT_IMMEDIATES_SIGN_EXTEND
1647 /* If X is narrower than a word and SRC is a non-negative
1648 constant that would appear negative in the mode of X,
1649 sign-extend it for use in reg_stat[].nonzero_bits because some
1650 machines (maybe most) will actually do the sign-extension
1651 and this is the conservative approach.
1653 ??? For 2.5, try to tighten up the MD files in this regard
1654 instead of this kludge. */
1661 #endif
1663 /* Don't call nonzero_bits if it cannot change anything. */
1670 }
1671 else
1672 {
1675 }
1676 }
1677 }
1678 \f
1679 /* See if INSN can be combined into I3. PRED, PRED2, SUCC and SUCC2 are
1680 optionally insns that were previously combined into I3 or that will be
1681 combined into the merger of INSN and I3. The order is PRED, PRED2,
1682 INSN, SUCC, SUCC2, I3.
1684 Return 0 if the combination is not allowed for any reason.
1686 If the combination is allowed, *PDEST will be set to the single
1687 destination of INSN and *PSRC to the single source, and this function
1688 will return 1. */
1690 static int
1694 {
1698 rtx p;
1699 #ifdef AUTO_INC_DEC
1700 rtx link;
1701 #endif
1706 {
1708 {
1713 }
1718 }
1722 /* Can combine only if previous insn is a SET of a REG, a SUBREG or CC0.
1723 or a PARALLEL consisting of such a SET and CLOBBERs.
1725 If INSN has CLOBBER parallel parts, ignore them for our processing.
1726 By definition, these happen during the execution of the insn. When it
1727 is merged with another insn, all bets are off. If they are, in fact,
1728 needed and aren't also supplied in I3, they may be added by
1729 recog_for_combine. Otherwise, it won't match.
1731 We can also ignore a SET whose SET_DEST is mentioned in a REG_UNUSED
1732 note.
1734 Get the source and destination of INSN. If more than one, can't
1735 combine. */
1741 {
1743 {
1747 {
1748 /* This is important to combine floating point insns
1749 for the SH4 port. */
1751 /* Combining an isolated USE doesn't make sense.
1752 We depend here on combinable_i3pat to reject them. */
1753 /* The code below this loop only verifies that the inputs of
1754 the SET in INSN do not change. We call reg_set_between_p
1755 to verify that the REG in the USE does not change between
1756 I3 and INSN.
1757 If the USE in INSN was for a pseudo register, the matching
1758 insn pattern will likely match any register; combining this
1759 with any other USE would only be safe if we knew that the
1760 used registers have identical values, or if there was
1761 something to tell them apart, e.g. different modes. For
1762 now, we forgo such complicated tests and simply disallow
1763 combining of USES of pseudo registers with any other USE. */
1766 {
1771 do
1772 {
1782 }
1784 }
1787 /* We can ignore CLOBBERs. */
1792 /* Ignore SETs whose result isn't used but not those that
1793 have side-effects. */
1799 /* If we have already found a SET, this is a second one and
1800 so we cannot combine with this insn. */
1808 /* Anything else means we can't combine. */
1810 }
1811 }
1814 /* If SET_SRC is an ASM_OPERANDS we can't throw away these CLOBBERs,
1815 so don't do anything with it. */
1818 }
1819 else
1825 /* The simplification in expand_field_assignment may call back to
1826 get_last_value, so set safe guard here. */
1832 /* Don't eliminate a store in the stack pointer. */
1834 /* Don't combine with an insn that sets a register to itself if it has
1835 a REG_EQUAL note. This may be part of a LIBCALL sequence. */
1837 /* Can't merge an ASM_OPERANDS. */
1839 /* Can't merge a function call. */
1841 /* Don't eliminate a function call argument. */
1847 /* Don't substitute into an incremented register. */
1851 /* Don't substitute into a non-local goto, this confuses CFG. */
1853 /* Make sure that DEST is not used after SUCC but before I3. */
1854 || (!all_adjacent
1855 && ((succ2
1859 /* Make sure that the value that is to be substituted for the register
1860 does not use any registers whose values alter in between. However,
1861 If the insns are adjacent, a use can't cross a set even though we
1862 think it might (this can happen for a sequence of insns each setting
1863 the same destination; last_set of that register might point to
1864 a NOTE). If INSN has a REG_EQUIV note, the register is always
1865 equivalent to the memory so the substitution is valid even if there
1866 are intervening stores. Also, don't move a volatile asm or
1867 UNSPEC_VOLATILE across any other insns. */
1868 || (! all_adjacent
1874 /* Don't combine across a CALL_INSN, because that would possibly
1875 change whether the life span of some REGs crosses calls or not,
1876 and it is a pain to update that information.
1877 Exception: if source is a constant, moving it later can't hurt.
1878 Accept that as a special case. */
1882 /* DEST must either be a REG or CC0. */
1884 {
1885 /* If register alignment is being enforced for multi-word items in all
1886 cases except for parameters, it is possible to have a register copy
1887 insn referencing a hard register that is not allowed to contain the
1888 mode being copied and which would not be valid as an operand of most
1889 insns. Eliminate this problem by not combining with such an insn.
1891 Also, on some machines we don't want to extend the life of a hard
1892 register. */
1897 /* Don't extend the life of a hard register unless it is
1898 user variable (if we have few registers) or it can't
1899 fit into the desired register (meaning something special
1900 is going on).
1901 Also avoid substituting a return register into I3, because
1902 reload can't handle a conflict with constraints of other
1903 inputs. */
1907 }
1915 {
1916 /* Don't substitute for a register intended as a clobberable
1917 operand. */
1922 /* If the clobber represents an earlyclobber operand, we must not
1923 substitute an expression containing the clobbered register.
1924 As we do not analyze the constraint strings here, we have to
1925 make the conservative assumption. However, if the register is
1926 a fixed hard reg, the clobber cannot represent any operand;
1927 we leave it up to the machine description to either accept or
1928 reject use-and-clobber patterns. */
1934 }
1936 /* If INSN contains anything volatile, or is an `asm' (whether volatile
1937 or not), reject, unless nothing volatile comes between it and I3 */
1940 {
1941 /* Make sure neither succ nor succ2 contains a volatile reference. */
1946 /* We'll check insns between INSN and I3 below. */
1947 }
1949 /* If INSN is an asm, and DEST is a hard register, reject, since it has
1950 to be an explicit register variable, and was chosen for a reason. */
1956 /* If INSN contains volatile references (specifically volatile MEMs),
1957 we cannot combine across any other volatile references.
1958 Even if INSN doesn't contain volatile references, any intervening
1959 volatile insn might affect machine state. */
1962 ? volatile_refs_p
1969 /* If INSN contains an autoincrement or autodecrement, make sure that
1970 register is not used between there and I3, and not already used in
1971 I3 either. Neither must it be used in PRED or SUCC, if they exist.
1972 Also insist that I3 not be a jump; if it were one
1973 and the incremented register were spilled, we would lose. */
1975 #ifdef AUTO_INC_DEC
1990 #endif
1992 #ifdef HAVE_cc0
1993 /* Don't combine an insn that follows a CC0-setting insn.
1994 An insn that uses CC0 must not be separated from the one that sets it.
1995 We do, however, allow I2 to follow a CC0-setting insn if that insn
1996 is passed as I1; in that case it will be deleted also.
1997 We also allow combining in this case if all the insns are adjacent
1998 because that would leave the two CC0 insns adjacent as well.
1999 It would be more logical to test whether CC0 occurs inside I1 or I2,
2000 but that would be much slower, and this ought to be equivalent. */
2006 #endif
2008 /* If we get here, we have passed all the tests and the combination is
2009 to be allowed. */
2015 }
2016 \f
2017 /* LOC is the location within I3 that contains its pattern or the component
2018 of a PARALLEL of the pattern. We validate that it is valid for combining.
2020 One problem is if I3 modifies its output, as opposed to replacing it
2021 entirely, we can't allow the output to contain I2DEST, I1DEST or I0DEST as
2022 doing so would produce an insn that is not equivalent to the original insns.
2024 Consider:
2026 (set (reg:DI 101) (reg:DI 100))
2027 (set (subreg:SI (reg:DI 101) 0) <foo>)
2029 This is NOT equivalent to:
2031 (parallel [(set (subreg:SI (reg:DI 100) 0) <foo>)
2032 (set (reg:DI 101) (reg:DI 100))])
2034 Not only does this modify 100 (in which case it might still be valid
2035 if 100 were dead in I2), it sets 101 to the ORIGINAL value of 100.
2037 We can also run into a problem if I2 sets a register that I1
2038 uses and I1 gets directly substituted into I3 (not via I2). In that
2039 case, we would be getting the wrong value of I2DEST into I3, so we
2040 must reject the combination. This case occurs when I2 and I1 both
2041 feed into I3, rather than when I1 feeds into I2, which feeds into I3.
2042 If I1_NOT_IN_SRC is nonzero, it means that finding I1 in the source
2043 of a SET must prevent combination from occurring. The same situation
2044 can occur for I0, in which case I0_NOT_IN_SRC is set.
2046 Before doing the above check, we first try to expand a field assignment
2047 into a set of logical operations.
2049 If PI3_DEST_KILLED is nonzero, it is a pointer to a location in which
2050 we place a register that is both set and used within I3. If more than one
2051 such register is detected, we fail.
2053 Return 1 if the combination is valid, zero otherwise. */
2055 static int
2058 {
2062 {
2067 rtx subdest;
2074 /* Check for the case where I3 modifies its output, as discussed
2075 above. We don't want to prevent pseudos from being combined
2076 into the address of a MEM, so only prevent the combination if
2077 i1 or i2 set the same MEM. */
2087 /* This is the same test done in can_combine_p except we can't test
2088 all_adjacent; we don't have to, since this instruction will stay
2089 in place, thus we are not considering increasing the lifetime of
2090 INNER_DEST.
2092 Also, if this insn sets a function argument, combining it with
2093 something that might need a spill could clobber a previous
2094 function argument; the all_adjacent test in can_combine_p also
2095 checks this; here, we do a more specific test for this case. */
2105 /* If DEST is used in I3, it is being killed in this insn, so
2106 record that for later. We have to consider paradoxical
2107 subregs here, since they kill the whole register, but we
2108 ignore partial subregs, STRICT_LOW_PART, etc.
2109 Never add REG_DEAD notes for the FRAME_POINTER_REGNUM or the
2110 STACK_POINTER_REGNUM, since these are always considered to be
2111 live. Similarly for ARG_POINTER_REGNUM if it is fixed. */
2121 #if !HARD_FRAME_POINTER_IS_FRAME_POINTER
2123 #endif
2124 #if ARG_POINTER_REGNUM != FRAME_POINTER_REGNUM
2127 #endif
2129 {
2134 }
2135 }
2138 {
2145 }
2148 }
2149 \f
2150 /* Return 1 if X is an arithmetic expression that contains a multiplication
2151 and division. We don't count multiplications by powers of two here. */
2153 static int
2155 {
2157 {
2173 }
2174 }
2175 \f
2176 /* Determine whether INSN can be used in a combination. Return nonzero if
2177 not. This is used in try_combine to detect early some cases where we
2178 can't perform combinations. */
2180 static int
2182 {
2183 rtx set;
2186 /* If this isn't really an insn, we can't do anything.
2187 This can occur when flow deletes an insn that it has merged into an
2188 auto-increment address. */
2192 /* Never combine loads and stores involving hard regs that are likely
2193 to be spilled. The register allocator can usually handle such
2194 reg-reg moves by tying. If we allow the combiner to make
2195 substitutions of likely-spilled regs, reload might die.
2196 As an exception, we allow combinations involving fixed regs; these are
2197 not available to the register allocator so there's no risk involved. */
2218 }
2220 struct likely_spilled_retval_info
2221 {
2224 };
2226 /* Called via note_stores by likely_spilled_retval_p. Remove from info->mask
2227 hard registers that are known to be written to / clobbered in full. */
2228 static void
2230 {
2247 else
2250 }
2252 /* Return nonzero iff part of the return value is live during INSN, and
2253 it is likely spilled. This can happen when more than one insn is needed
2254 to copy the return value, e.g. when we consider to combine into the
2255 second copy insn for a complex value. */
2257 static int
2259 {
2263 /* We assume here that no machine mode needs more than
2264 32 hard registers when the value overlaps with a register
2265 for which TARGET_FUNCTION_VALUE_REGNO_P is true. */
2280 /* Disregard parts of the return value that are set later. */
2289 /* Check if any of the (probably) live return value registers is
2290 likely spilled. */
2291 nregs --;
2292 do
2293 {
2299 }
2301 /* Adjust INSN after we made a change to its destination.
2303 Changing the destination can invalidate notes that say something about
2304 the results of the insn and a LOG_LINK pointing to the insn. */
2306 static void
2308 {
2309 /* For notes, be conservative and simply remove them. */
2312 /* The new insn will have a destination that was previously the destination
2313 of an insn just above it. Call distribute_links to make a LOG_LINK from
2314 the next use of that destination. */
2318 }
2320 /* Return TRUE if combine can reuse reg X in mode MODE.
2321 ADDED_SETS is nonzero if the original set is still required. */
2322 static bool
2324 {
2331 /* Allow hard registers if the new mode is legal, and occupies no more
2332 registers than the old mode. */
2338 /* Or a pseudo that is only used once. */
2341 }
2344 /* Check whether X, the destination of a set, refers to part of
2345 the register specified by REG. */
2347 static bool
2349 {
2350 /* Check that reg is an integer mode register. */
2361 }
2363 #ifdef AUTO_INC_DEC
2364 /* Replace auto-increment addressing modes with explicit operations to access
2365 the same addresses without modifying the corresponding registers. */
2367 static rtx
2369 {
2376 {
2387 /* SCRATCH must be shared because they represent distinct values. */
2418 mem_mode);
2422 }
2424 /* Copy the various flags, fields, and other information. We assume
2425 that all fields need copying, and then clear the fields that should
2426 not be copied. That is the sensible default behavior, and forces
2427 us to explicitly document why we are *not* copying a flag. */
2430 /* We do not copy the USED flag, which is used as a mark bit during
2431 walks over the RTL. */
2434 /* We do not copy FRAME_RELATED for INSNs. */
2443 {
2449 }
2452 }
2453 #endif
2455 /* Auxiliary data structure for propagate_for_debug_stmt. */
2457 struct rtx_subst_pair
2458 {
2459 rtx to;
2461 };
2463 /* DATA points to an rtx_subst_pair. Return the value that should be
2464 substituted. */
2466 static rtx
2468 {
2474 {
2476 #ifdef AUTO_INC_DEC
2478 #else
2480 #endif
2483 }
2485 }
2487 /* Replace all the occurrences of DEST with SRC in DEBUG_INSNs between INSN
2488 and LAST, not including INSN, but including LAST. Also stop at the end
2489 of THIS_BASIC_BLOCK. */
2491 static void
2493 {
2503 {
2507 {
2514 }
2515 }
2516 }
2518 /* Delete the unconditional jump INSN and adjust the CFG correspondingly.
2519 Note that the INSN should be deleted *after* removing dead edges, so
2520 that the kept edge is the fallthrough edge for a (set (pc) (pc))
2521 but not for a (set (pc) (label_ref FOO)). */
2523 static void
2525 {
2533 {
2534 rtx insn;
2538 /* Remove barriers from the footer if there are any. */
2541 {
2544 else
2548 }
2551 }
2552 }
2554 /* Try to combine the insns I0, I1 and I2 into I3.
2555 Here I0, I1 and I2 appear earlier than I3.
2556 I0 and I1 can be zero; then we combine just I2 into I3, or I1 and I2 into
2557 I3.
2559 If we are combining more than two insns and the resulting insn is not
2560 recognized, try splitting it into two insns. If that happens, I2 and I3
2561 are retained and I1/I0 are pseudo-deleted by turning them into a NOTE.
2562 Otherwise, I0, I1 and I2 are pseudo-deleted.
2564 Return 0 if the combination does not work. Then nothing is changed.
2565 If we did the combination, return the insn at which combine should
2566 resume scanning.
2568 Set NEW_DIRECT_JUMP_P to a nonzero value if try_combine creates a
2569 new direct jump instruction.
2571 LAST_COMBINED_INSN is either I3, or some insn after I3 that has
2572 been I3 passed to an earlier try_combine within the same basic
2573 block. */
2575 static rtx
2577 rtx last_combined_insn)
2578 {
2579 /* New patterns for I3 and I2, respectively. */
2583 /* Indicates need to preserve SET in I0, I1 or I2 in I3 if it is not
2584 dead. */
2586 /* Total number of SETs to put into I3. */
2588 /* Nonzero if I2's or I1's body now appears in I3. */
2590 /* INSN_CODEs for new I3, new I2, and user of condition code. */
2592 /* Contains I3 if the destination of I3 is used in its source, which means
2593 that the old life of I3 is being killed. If that usage is placed into
2594 I2 and not in I3, a REG_DEAD note must be made. */
2596 /* SET_DEST and SET_SRC of I2, I1 and I0. */
2598 /* Copy of SET_SRC of I1 and I0, if needed. */
2600 /* Set if I2DEST was reused as a scratch register. */
2602 /* The PATTERNs of I0, I1, and I2, or a copy of them in certain cases. */
2604 /* Indicates if I2DEST or I1DEST is in I2SRC or I1_SRC. */
2609 /* Notes that must be added to REG_NOTES in I3 and I2. */
2611 /* Notes that we substituted I3 into I2 instead of the normal case. */
2613 /* Notes that I1, I2 or I3 is a MULT operation. */
2619 rtx temp;
2622 rtx new_other_notes;
2625 /* Only try four-insn combinations when there's high likelihood of
2626 success. Look for simple insns, such as loads of constants or
2627 binary operations involving a constant. */
2629 {
2638 {
2641 rtx src;
2646 {
2649 }
2651 ngood++;
2654 nshift++;
2655 }
2658 }
2660 /* Exit early if one of the insns involved can't be used for
2661 combinations. */
2669 combine_attempts++;
2672 /* Reset the hard register usage information. */
2676 {
2683 else
2686 }
2688 /* If multiple insns feed into one of I2 or I3, they can be in any
2689 order. To simplify the code below, reorder them in sequence. */
2699 /* First check for one important special case that the code below will
2700 not handle. Namely, the case where I1 is zero, I2 is a PARALLEL
2701 and I3 is a SET whose SET_SRC is a SET_DEST in I2. In that case,
2702 we may be able to replace that destination with the destination of I3.
2703 This occurs in the common code where we compute both a quotient and
2704 remainder into a structure, in which case we want to do the computation
2705 directly into the structure to avoid register-register copies.
2707 Note that this case handles both multiple sets in I2 and also cases
2708 where I2 has a number of CLOBBERs inside the PARALLEL.
2710 We make very conservative checks below and only try to handle the
2711 most common cases of this. For example, we only handle the case
2712 where I2 and I3 are adjacent to avoid making difficult register
2713 usage tests. */
2721 /* If the dest of I3 is a ZERO_EXTRACT or STRICT_LOW_PART, the code
2722 below would need to check what is inside (and reg_overlap_mentioned_p
2723 doesn't support those codes anyway). Don't allow those destinations;
2724 the resulting insn isn't likely to be recognized anyway. */
2730 {
2733 /* Make sure that the destination of I3,
2734 which we are going to substitute into one output of I2,
2735 is not used within another output of I2. We must avoid making this:
2736 (parallel [(set (mem (reg 69)) ...)
2737 (set (reg 69) ...)])
2738 which is not well-defined as to order of actions.
2739 (Besides, reload can't handle output reloads for this.)
2741 The problem can also happen if the dest of I3 is a memory ref,
2742 if another dest in I2 is an indirect memory ref. */
2754 {
2755 combine_merges++;
2765 /* Replace the dest in I2 with our dest and make the resulting
2766 insn the new pattern for I3. Then skip to where we validate
2767 the pattern. Everything was set up above. */
2772 }
2773 }
2775 /* If I2 is setting a pseudo to a constant and I3 is setting some
2776 sub-part of it to another constant, merge them by making a new
2777 constant. */
2786 {
2792 {
2795 {
2801 }
2802 }
2803 else
2804 {
2809 }
2812 {
2813 /* If this is the low part, we're done. */
2815 ;
2816 /* Handle the case where inner is twice the size of outer. */
2820 /* Otherwise give up for now. */
2821 else
2823 }
2828 {
2842 combine_merges++;
2849 /* Replace the source in I2 with the new constant and make the
2850 resulting insn the new pattern for I3. Then skip to where we
2851 validate the pattern. Everything was set up above. */
2857 /* The dest of I3 has been replaced with the dest of I2. */
2860 }
2861 }
2863 #ifndef HAVE_cc0
2864 /* If we have no I1 and I2 looks like:
2865 (parallel [(set (reg:CC X) (compare:CC OP (const_int 0)))
2866 (set Y OP)])
2867 make up a dummy I1 that is
2868 (set Y OP)
2869 and change I2 to be
2870 (set (reg:CC X) (compare:CC Y (const_int 0)))
2872 (We can ignore any trailing CLOBBERs.)
2874 This undoes a previous combination and allows us to match a branch-and-
2875 decrement insn. */
2888 {
2894 {
2895 /* We make I1 with the same INSN_UID as I2. This gives it
2896 the same DF_INSN_LUID for value tracking. Our fake I1 will
2897 never appear in the insn stream so giving it the same INSN_UID
2898 as I2 will not cause a problem. */
2908 }
2909 }
2910 #endif
2912 /* Verify that I2 and I1 are valid for combining. */
2918 {
2921 }
2923 /* Record whether I2DEST is used in I2SRC and similarly for the other
2924 cases. Knowing this will help in register status updating below. */
2935 /* For the earlier insns, determine which of the subsequent ones they
2936 feed. */
2943 /* Ensure that I3's pattern can be the destination of combines. */
2949 {
2952 }
2954 /* See if any of the insns is a MULT operation. Unless one is, we will
2955 reject a combination that is, since it must be slower. Be conservative
2956 here. */
2964 /* If I3 has an inc, then give up if I1 or I2 uses the reg that is inc'd.
2965 We used to do this EXCEPT in one case: I3 has a post-inc in an
2966 output operand. However, that exception can give rise to insns like
2967 mov r3,(r3)+
2968 which is a famous insn on the PDP-11 where the value of r3 used as the
2969 source was model-dependent. Avoid this sort of thing. */
2971 #if 0
2977 /* It's not the exception. */
2978 #endif
2979 #ifdef AUTO_INC_DEC
2980 {
2981 rtx link;
2987 {
2990 }
2991 }
2992 #endif
2994 /* See if the SETs in I1 or I2 need to be kept around in the merged
2995 instruction: whenever the value set there is still needed past I3.
2996 For the SETs in I2, this is easy: we see if I2DEST dies or is set in I3.
2998 For the SET in I1, we have two cases: If I1 and I2 independently
2999 feed into I3, the set in I1 needs to be kept around if I1DEST dies
3000 or is set in I3. Otherwise (if I1 feeds I2 which feeds I3), the set
3001 in I1 needs to be kept around unless I1DEST dies or is set in either
3002 I2 or I3. The same consideration applies to I0. */
3009 else
3016 else
3019 /* We are about to copy insns for the case where they need to be kept
3020 around. Check that they can be copied in the merged instruction. */
3026 {
3029 }
3031 /* If the set in I2 needs to be kept around, we must make a copy of
3032 PATTERN (I2), so that when we substitute I1SRC for I1DEST in
3033 PATTERN (I2), we are only substituting for the original I1DEST, not into
3034 an already-substituted copy. This also prevents making self-referential
3035 rtx. If I2 is a PARALLEL, we just need the piece that assigns I2SRC to
3036 I2DEST. */
3039 {
3042 else
3044 }
3047 {
3050 else
3052 }
3055 {
3058 else
3060 }
3062 combine_merges++;
3064 /* Substitute in the latest insn for the regs set by the earlier ones. */
3070 #ifndef HAVE_cc0
3071 /* Many machines that don't use CC0 have insns that can both perform an
3072 arithmetic operation and set the condition code. These operations will
3073 be represented as a PARALLEL with the first element of the vector
3074 being a COMPARE of an arithmetic operation with the constant zero.
3075 The second element of the vector will set some pseudo to the result
3076 of the same arithmetic operation. If we simplify the COMPARE, we won't
3077 match such a pattern and so will generate an extra insn. Here we test
3078 for this case, where both the comparison and the operation result are
3079 needed, and make the PARALLEL by just replacing I2DEST in I3SRC with
3080 I2SRC. Later we will make the PARALLEL that contains I2. */
3086 {
3087 rtx newpat_dest;
3100 {
3104 #ifdef CANONICALIZE_COMPARISON
3106 #endif
3107 }
3109 /* Do the rest only if op1 is const0_rtx, which may be the
3110 result of simplification. */
3112 {
3113 /* If a single use of the CC is found, prepare to modify it
3114 when SELECT_CC_MODE returns a new CC-class mode, or when
3115 the above simplify_compare_const() returned a new comparison
3116 operator. undobuf.other_insn is assigned the CC use insn
3117 when modifying it. */
3119 {
3120 #ifdef SELECT_CC_MODE
3121 enum machine_mode new_mode
3126 {
3131 else
3132 {
3135 }
3136 }
3137 #endif
3138 /* Cases for modifying the CC-using comparison. */
3140 /* ??? Do we need to verify the zero rtx? */
3142 {
3143 /* Replace cc_use_loc with entire new RTX. */
3148 }
3150 {
3151 /* Just replace the CC reg with a new mode. */
3154 }
3155 }
3157 /* Now we modify the current newpat:
3158 First, SET_DEST(newpat) is updated if the CC mode has been
3159 altered. For targets without SELECT_CC_MODE, this should be
3160 optimized away. */
3163 /* This is always done to propagate i2src into newpat. */
3166 /* Create new version of i2pat if needed; the below PARALLEL
3167 creation needs this to work correctly. */
3171 }
3172 }
3173 #endif
3176 {
3177 /* It is possible that the source of I2 or I1 may be performing
3178 an unneeded operation, such as a ZERO_EXTEND of something
3179 that is known to have the high part zero. Handle that case
3180 by letting subst look at the inner insns.
3182 Another way to do this would be to have a function that tries
3183 to simplify a single insn instead of merging two or more
3184 insns. We don't do this because of the potential of infinite
3185 loops and because of the potential extra memory required.
3186 However, doing it the way we are is a bit of a kludge and
3187 doesn't catch all cases.
3189 But only do this if -fexpensive-optimizations since it slows
3190 things down and doesn't usually win.
3192 This is not done in the COMPARE case above because the
3193 unmodified I2PAT is used in the PARALLEL and so a pattern
3194 with a modified I2SRC would not match. */
3197 {
3198 /* Pass pc_rtx so no substitutions are done, just
3199 simplifications. */
3201 {
3204 }
3208 }
3213 /* If I1 feeds into I2 and I1DEST is in I1SRC, we need to make a unique
3214 copy of I2SRC each time we substitute it, in order to avoid creating
3215 self-referential RTL when we will be substituting I1SRC for I1DEST
3216 later. Likewise if I0 feeds into I2, either directly or indirectly
3217 through I1, and I0DEST is in I0SRC. */
3224 /* Record whether I2's body now appears within I3's body. */
3226 }
3228 /* If we already got a failure, don't try to do more. Otherwise, try to
3229 substitute I1 if we have it. */
3232 {
3233 /* Check that an autoincrement side-effect on I1 has not been lost.
3234 This happens if I1DEST is mentioned in I2 and dies there, and
3235 has disappeared from the new pattern. */
3237 && i1_feeds_i2_n
3240 /* Before we can do this substitution, we must redo the test done
3241 above (see detailed comments there) that ensures I1DEST isn't
3242 mentioned in any SETs in NEWPAT that are field assignments. */
3245 {
3248 }
3253 /* If the following substitution will modify I1SRC, make a copy of it
3254 for the case where it is substituted for I1DEST in I2PAT later. */
3258 /* If I0 feeds into I1 and I0DEST is in I0SRC, we need to make a unique
3259 copy of I1SRC each time we substitute it, in order to avoid creating
3260 self-referential RTL when we will be substituting I0SRC for I0DEST
3261 later. */
3266 /* Record whether I1's body now appears within I3's body. */
3268 }
3270 /* Likewise for I0 if we have it. */
3273 {
3280 {
3283 }
3285 /* If the following substitution will modify I0SRC, make a copy of it
3286 for the case where it is substituted for I0DEST in I1PAT later. */
3289 /* And a copy for I0DEST in I2PAT substitution. */
3298 }
3300 /* Fail if an autoincrement side-effect has been duplicated. Be careful
3301 to count all the ways that I2SRC and I1SRC can be used. */
3312 /* Fail if we tried to make a new register. */
3314 /* Fail if we couldn't do something and have a CLOBBER. */
3316 /* Fail if this new pattern is a MULT and we didn't have one before
3317 at the outer level. */
3320 {
3323 }
3325 /* If the actions of the earlier insns must be kept
3326 in addition to substituting them into the latest one,
3327 we must make a new PARALLEL for the latest insn
3328 to hold additional the SETs. */
3331 {
3333 combine_extras++;
3336 {
3342 }
3343 else
3344 {
3349 }
3355 {
3361 }
3363 {
3372 }
3373 }
3375 validate_replacement:
3377 /* Note which hard regs this insn has as inputs. */
3380 /* If recog_for_combine fails, it strips existing clobbers. If we'll
3381 consider splitting this pattern, we might need these clobbers. */
3384 {
3390 }
3392 /* Is the result of combination a valid instruction? */
3395 /* If the result isn't valid, see if it is a PARALLEL of two SETs where
3396 the second SET's destination is a register that is unused and isn't
3397 marked as an instruction that might trap in an EH region. In that case,
3398 we just need the first SET. This can occur when simplifying a divmod
3399 insn. We *must* test for this case here because the code below that
3400 splits two independent SETs doesn't handle this case correctly when it
3401 updates the register status.
3403 It's pointless doing this if we originally had two sets, one from
3404 i3, and one from i2. Combining then splitting the parallel results
3405 in the original i2 again plus an invalid insn (which we delete).
3406 The net effect is only to move instructions around, which makes
3407 debug info less accurate.
3409 Also check the case where the first SET's destination is unused.
3410 That would not cause incorrect code, but does cause an unneeded
3411 insn to remain. */
3420 {
3430 {
3433 }
3442 {
3448 }
3449 }
3451 /* If we were combining three insns and the result is a simple SET
3452 with no ASM_OPERANDS that wasn't recognized, try to split it into two
3453 insns. There are two ways to do this. It can be split using a
3454 machine-specific method (like when you have an addition of a large
3455 constant) or by combine in the function find_split_point. */
3459 {
3462 /* See if the MD file can split NEWPAT. If it can't, see if letting it
3463 use I2DEST as a scratch register will help. In the latter case,
3464 convert I2DEST to the mode of the source of NEWPAT if we can. */
3468 /* We can only use I2DEST as a scratch reg if it doesn't overlap any
3469 inputs of NEWPAT. */
3471 /* ??? If I2DEST is not safe, and I1DEST exists, then it would be
3472 possible to try that as a scratch reg. This would require adding
3473 more code to make it work though. */
3476 {
3479 /* First try to split using the original register as a
3480 scratch register. */
3484 i2dest)));
3487 /* If that didn't work, try changing the mode of I2DEST if
3488 we can. */
3493 {
3495 rtx ni2dest;
3499 else
3500 {
3503 }
3505 parallel = (gen_rtx_PARALLEL
3509 ni2dest))));
3514 {
3522 }
3523 }
3526 }
3528 /* If recog_for_combine has discarded clobbers, try to use them
3529 again for the split. */
3531 {
3534 }
3537 {
3542 }
3546 {
3556 /* If I2 or I3 has multiple SETs, we won't know how to track
3557 register status, so don't use these insns. If I2's destination
3558 is used between I2 and I3, we also can't use these insns. */
3568 /* It is possible that both insns now set the destination of I3.
3569 If so, we must show an extra use of it. */
3572 {
3590 }
3591 }
3593 /* If we can split it and use I2DEST, go ahead and see if that
3594 helps things be recognized. Verify that none of the registers
3595 are set between I2 and I3. */
3598 #ifdef HAVE_cc0
3600 #endif
3601 /* We need I2DEST in the proper mode. If it is a hard register
3602 or the only use of a pseudo, we can change its mode.
3603 Make sure we don't change a hard register to have a mode that
3604 isn't valid for it, or change the number of registers. */
3611 /* We can't overwrite I2DEST if its value is still used by
3612 NEWPAT. */
3614 {
3623 /* *SPLIT may be part of I2SRC, so make sure we have the
3624 original expression around for later debug processing.
3625 We should not need I2SRC any more in other cases. */
3628 else
3631 /* Get NEWDEST as a register in the proper mode. We have already
3632 validated that we can do this. */
3634 {
3637 else
3638 {
3641 }
3642 }
3644 /* If *SPLIT is a (mult FOO (const_int pow2)), convert it to
3645 an ASHIFT. This can occur if it was inside a PLUS and hence
3646 appeared to be a memory address. This is a kludge. */
3651 {
3654 /* Update split_code because we may not have a multiply
3655 anymore. */
3657 }
3659 #ifdef INSN_SCHEDULING
3660 /* If *SPLIT is a paradoxical SUBREG, when we split it, it should
3661 be written as a ZERO_EXTEND. */
3663 {
3664 #ifdef LOAD_EXTEND_OP
3665 /* Or as a SIGN_EXTEND if LOAD_EXTEND_OP says that that's
3666 what it really is. */
3671 else
3672 #endif
3675 }
3676 #endif
3678 /* Attempt to split binary operators using arithmetic identities. */
3682 {
3689 /* Split "X = Y op Y" as "Z = Y; X = Z op Z". */
3691 {
3696 }
3697 /* Split "((P op Q) op R) op S" where op is PLUS or MULT. */
3704 {
3710 /* Split both "((X op Y) op X) op Y" and
3711 "((X op Y) op Y) op X" as "T op T" where T is
3712 "X op Y". */
3715 {
3721 }
3722 /* Split "((X op X) op Y) op Y)" as "T op T" where
3723 T is "X op Y". */
3725 {
3731 }
3732 }
3733 }
3736 {
3739 }
3743 /* recog_for_combine might have added CLOBBERs to newi2pat.
3744 Make sure NEWPAT does not depend on the clobbered regs. */
3748 {
3751 {
3754 }
3755 }
3757 /* If the split point was a MULT and we didn't have one before,
3758 don't use one now. */
3761 }
3762 }
3764 /* Check for a case where we loaded from memory in a narrow mode and
3765 then sign extended it, but we need both registers. In that case,
3766 we have a PARALLEL with both loads from the same memory location.
3767 We can split this into a load from memory followed by a register-register
3768 copy. This saves at least one insn, more if register allocation can
3769 eliminate the copy.
3771 We cannot do this if the destination of the first assignment is a
3772 condition code register or cc0. We eliminate this case by making sure
3773 the SET_DEST and SET_SRC have the same mode.
3775 We cannot do this if the destination of the second assignment is
3776 a register that we have already assumed is zero-extended. Similarly
3777 for a SUBREG of such a register. */
3816 {
3817 rtx ni2dest;
3831 }
3833 /* Similarly, check for a case where we have a PARALLEL of two independent
3834 SETs but we started with three insns. In this case, we can do the sets
3835 as two separate insns. This case occurs when some SET allows two
3836 other insns to combine, but the destination of that SET is still live. */
3853 {
3854 /* Normally, it doesn't matter which of the two is done first,
3855 but the one that references cc0 can't be the second, and
3856 one which uses any regs/memory set in between i2 and i3 can't
3857 be first. */
3860 #ifdef HAVE_cc0
3862 #endif
3863 )
3864 {
3867 }
3870 #ifdef HAVE_cc0
3872 #endif
3873 )
3874 {
3877 }
3878 else
3879 {
3882 }
3887 {
3888 /* recog_for_combine might have added CLOBBERs to newi2pat.
3889 Make sure NEWPAT does not depend on the clobbered regs. */
3891 {
3894 {
3897 {
3900 }
3901 }
3902 }
3905 }
3906 }
3908 /* If it still isn't recognized, fail and change things back the way they
3909 were. */
3911 /* Is the result a reasonable ASM_OPERANDS? */
3913 {
3916 }
3918 /* If we had to change another insn, make sure it is valid also. */
3920 {
3928 {
3931 }
3932 }
3934 #ifdef HAVE_cc0
3935 /* If I2 is the CC0 setter and I3 is the CC0 user then check whether
3936 they are adjacent to each other or not. */
3937 {
3941 {
3944 }
3945 }
3946 #endif
3948 /* Only allow this combination if insn_rtx_costs reports that the
3949 replacement instructions are cheaper than the originals. */
3951 {
3954 }
3957 {
3962 {
3967 /* Temporarily revert mode back. */
3971 {
3972 /* If we used i2dest as a scratch register with a
3973 different mode, substitute it for the original
3974 i2src while its original mode is temporarily
3975 restored, and then clear i2scratch so that we don't
3976 do it again later. */
3979 /* Put back the new mode. */
3981 }
3982 else
3983 {
3988 {
3991 }
3992 else
3993 {
4000 }
4002 /* We're dealing with a reg that changed mode but not
4003 meaning, so we want to turn it into a subreg for
4004 the new mode. However, because of REG sharing and
4005 because its mode had already changed, we have to do
4006 it in two steps. First, replace any debug uses of
4007 reg, with its original mode temporarily restored,
4008 with this copy we have created; then, replace the
4009 copy with the SUBREG of the original shared reg,
4010 once again changed to the new mode. */
4015 }
4016 }
4017 }
4019 /* If we will be able to accept this, we have made a
4020 change to the destination of I3. This requires us to
4021 do a few adjustments. */
4024 {
4027 }
4029 /* We now know that we can do this combination. Merge the insns and
4030 update the status of registers and LOG_LINKS. */
4033 {
4038 /* If any of the notes in OTHER_INSN were REG_UNUSED, ensure that they
4039 are still valid. Then add any non-duplicate notes added by
4040 recog_for_combine. */
4042 {
4048 }
4052 NULL_RTX);
4053 }
4056 {
4057 rtx insn;
4059 rtx ni2dest;
4061 /* I3 now uses what used to be its destination and which is now
4062 I2's destination. This requires us to do a few adjustments. */
4066 /* We need a LOG_LINK from I3 to I2. But we used to have one,
4067 so we still will.
4069 However, some later insn might be using I2's dest and have
4070 a LOG_LINK pointing at I3. We must remove this link.
4071 The simplest way to remove the link is to point it at I1,
4072 which we know will be a NOTE. */
4074 /* newi2pat is usually a SET here; however, recog_for_combine might
4075 have added some clobbers. */
4078 else
4085 {
4087 {
4093 }
4094 }
4095 }
4097 {
4102 /* Compute which registers we expect to eliminate. newi2pat may be setting
4103 either i3dest or i2dest, so we must check it. Also, i1dest may be the
4104 same as i3dest, in which case newi2pat may be setting i1dest. */
4107 || !i2dest_killed
4111 || !i1dest_killed
4115 || !i0dest_killed
4118 /* Get the old REG_NOTES and LOG_LINKS from all our insns and
4119 clear them. */
4127 /* Ensure that we do not have something that should not be shared but
4128 occurs multiple times in the new insns. Check this by first
4129 resetting all the `used' flags and then copying anything is shared. */
4153 {
4160 {
4161 /* I2SRC must still be meaningful at this point. Some splitting
4162 operations can invalidate I2SRC, but those operations do not
4163 apply to calls. */
4166 }
4174 }
4179 /* We had one special case above where I2 had more than one set and
4180 we replaced a destination of one of those sets with the destination
4181 of I3. In that case, we have to update LOG_LINKS of insns later
4182 in this basic block. Note that this (expensive) case is rare.
4184 Also, in this case, we must pretend that all REG_NOTEs for I2
4185 actually came from I3, so that REG_UNUSED notes from I2 will be
4186 properly handled. */
4189 {
4207 {
4212 }
4213 else
4216 }
4224 {
4229 }
4230 else
4231 {
4235 }
4238 {
4244 }
4247 {
4253 }
4255 /* Get death notes for everything that is now used in either I3 or
4256 I2 and used to die in a previous insn. If we built two new
4257 patterns, move from I1 to I2 then I2 to I3 so that we get the
4258 proper movement on registers that I2 modifies. */
4264 else
4270 /* Distribute all the LOG_LINKS and REG_NOTES from I1, I2, and I3. */
4287 /* Distribute any notes added to I2 or I3 by recog_for_combine. We
4288 know these are REG_UNUSED and want them to go to the desired insn,
4289 so we always pass it as i3. */
4293 NULL_RTX);
4297 NULL_RTX);
4299 /* If I3DEST was used in I3SRC, it really died in I3. We may need to
4300 put a REG_DEAD note for it somewhere. If NEWI2PAT exists and sets
4301 I3DEST, the death must be somewhere before I2, not I3. If we passed I3
4302 in that case, it might delete I2. Similarly for I2 and I1.
4303 Show an additional death due to the REG_DEAD note we make here. If
4304 we discard it in distribute_notes, we will decrement it again. */
4307 {
4310 NULL_RTX),
4312 else
4314 NULL_RTX),
4317 }
4320 {
4325 else
4328 }
4331 {
4336 else
4339 }
4342 {
4347 else
4350 }
4358 {
4362 /* The insn that used to set this register doesn't exist, and
4363 this life of the register may not exist either. See if one of
4364 I3's links points to an insn that sets I2DEST. If it does,
4365 that is now the last known value for I2DEST. If we don't update
4366 this and I2 set the register to a value that depended on its old
4367 contents, we will get confused. If this insn is used, thing
4368 will be set correctly in combine_instructions. */
4376 /* If the reg formerly set in I2 died only once and that was in I3,
4377 zero its use count so it won't make `reload' do any work. */
4382 }
4385 {
4398 }
4401 {
4414 }
4416 /* Update reg_stat[].nonzero_bits et al for any changes that may have
4417 been made to this insn. The order of
4418 set_nonzero_bits_and_sign_copies() is important. Because newi2pat
4419 can affect nonzero_bits of newpat */
4423 }
4426 {
4428 {
4431 }
4433 }
4436 {
4438 {
4441 }
4443 }
4446 {
4448 {
4451 }
4453 }
4456 {
4458 {
4461 }
4463 }
4466 {
4468 {
4471 }
4473 }
4475 /* Set new_direct_jump_p if a new return or simple jump instruction
4476 has been created. Adjust the CFG accordingly. */
4479 {
4483 }
4488 {
4491 }
4493 /* A noop might also need cleaning up of CFG, if it comes from the
4494 simplification of a jump. */
4499 {
4502 }
4509 {
4512 }
4514 combine_successes++;
4521 else
4523 }
4524 \f
4525 /* Undo all the modifications recorded in undobuf. */
4527 static void
4529 {
4533 {
4536 {
4551 }
4555 }
4558 }
4560 /* We've committed to accepting the changes we made. Move all
4561 of the undos to the free list. */
4563 static void
4565 {
4569 {
4573 }
4575 }
4576 \f
4577 /* Find the innermost point within the rtx at LOC, possibly LOC itself,
4578 where we have an arithmetic expression and return that point. LOC will
4579 be inside INSN.
4581 try_combine will call this function to see if an insn can be split into
4582 two insns. */
4586 {
4595 /* First special-case some codes. */
4597 {
4599 #ifdef INSN_SCHEDULING
4600 /* If we are making a paradoxical SUBREG invalid, it becomes a split
4601 point. */
4604 #endif
4608 #ifdef HAVE_lo_sum
4609 /* If we have (mem (const ..)) or (mem (symbol_ref ...)), split it
4610 using LO_SUM and HIGH. */
4613 {
4614 enum machine_mode address_mode
4622 }
4623 #endif
4625 /* If we have a PLUS whose second operand is a constant and the
4626 address is not valid, perhaps will can split it up using
4627 the machine-specific way to split large constants. We use
4628 the first pseudo-reg (one of the virtual regs) as a placeholder;
4629 it will not remain in the result. */
4634 {
4638 subst_insn);
4640 /* This should have produced two insns, each of which sets our
4641 placeholder. If the source of the second is a valid address,
4642 we can make put both sources together and make a split point
4643 in the middle. */
4656 && memory_address_addr_space_p
4659 {
4663 /* Replace the placeholder in SRC2 with SRC1. If we can
4664 find where in SRC2 it was placed, that can become our
4665 split point and we can replace this address with SRC2.
4666 Just try two obvious places. */
4677 {
4680 }
4681 }
4683 /* If that didn't work, perhaps the first operand is complex and
4684 needs to be computed separately, so make a split point there.
4685 This will occur on machines that just support REG + CONST
4686 and have a constant moved through some previous computation. */
4692 }
4694 /* If we have a PLUS whose first operand is complex, try computing it
4695 separately by making a split there. */
4706 #ifdef HAVE_cc0
4707 /* If SET_DEST is CC0 and SET_SRC is not an operand, a COMPARE, or a
4708 ZERO_EXTRACT, the most likely reason why this doesn't match is that
4709 we need to put the operand into a register. So split at that
4710 point. */
4719 #endif
4721 /* See if we can split SET_SRC as it stands. */
4726 /* See if we can split SET_DEST as it stands. */
4731 /* See if this is a bitfield assignment with everything constant. If
4732 so, this is an IOR of an AND, so split it into that. */
4742 {
4748 unsigned HOST_WIDE_INT mask
4750 rtx or_mask;
4759 else
4760 {
4766 or_mask));
4767 }
4774 }
4776 /* Otherwise, see if this is an operation that we can split into two.
4777 If so, try to split that. */
4781 {
4783 /* If we are AND'ing with a large constant that is only a single
4784 bit and the result is only being used in a context where we
4785 need to know if it is zero or nonzero, replace it with a bit
4786 extraction. This will avoid the large constant, which might
4787 have taken more than one insn to make. If the constant were
4788 not a valid argument to the AND but took only one insn to make,
4789 this is no worse, but if it took more than one insn, it will
4790 be better. */
4800 {
4805 {
4808 }
4809 }
4813 /* If STORE_FLAG_VALUE is -1, this is (NE X 0) and only one bit of X
4814 is known to be on, this can be converted into a NEG of a shift. */
4820 {
4832 }
4838 /* We can't optimize if either mode is a partial integer
4839 mode as we don't know how many bits are significant
4840 in those modes. */
4854 {
4862 }
4867 }
4871 {
4874 /* For unsigned, we have a choice of a shift followed by an
4875 AND or two shifts. Use two shifts for field sizes where the
4876 constant might be too large. We assume here that we can
4877 always at least get 8-bit constants in an AND insn, which is
4878 true for every current RISC. */
4881 {
4884 gen_rtx_LSHIFTRT
4893 }
4894 else
4895 {
4897 gen_rtx_fmt_ee
4908 }
4909 }
4911 /* See if this is a simple operation with a constant as the second
4912 operand. It might be that this constant is out of range and hence
4913 could be used as a split point. */
4921 /* Finally, see if this is a simple operation with its first operand
4922 not in a register. The operation might require this operand in a
4923 register, so return it as a split point. We can always do this
4924 because if the first operand were another operation, we would have
4925 already found it as a split point. */
4934 /* We write NOR as (and (not A) (not B)), but if we don't have a NOR,
4935 it is better to write this as (not (ior A B)) so we can split it.
4936 Similarly for IOR. */
4938 {
4946 }
4948 /* Many RISC machines have a large set of logical insns. If the
4949 second operand is a NOT, put it first so we will try to split the
4950 other operand first. */
4952 {
4956 }
4961 /* Canonicalization can produce (minus A (mult B C)), where C is a
4962 constant. It may be better to try splitting (plus (mult B -C) A)
4963 instead if this isn't a multiply by a power of two. */
4967 {
4976 }
4978 /* Split at a multiply-accumulate instruction. However if this is
4979 the SET_SRC, we likely do not have such an instruction and it's
4980 worthless to try this split. */
4986 }
4988 /* Otherwise, select our actions depending on our rtx class. */
4990 {
4996 /* ... fall through ... */
5004 /* ... fall through ... */
5006 /* Some machines have (and (shift ...) ...) insns. If X is not
5007 an AND, but XEXP (X, 0) is, use it as our split point. */
5017 /* Otherwise, we don't have a split point. */
5019 }
5020 }
5021 \f
5022 /* Throughout X, replace FROM with TO, and return the result.
5023 The result is TO if X is FROM;
5024 otherwise the result is X, but its contents may have been modified.
5025 If they were modified, a record was made in undobuf so that
5026 undo_all will (among other things) return X to its original state.
5028 If the number of changes necessary is too much to record to undo,
5029 the excess changes are not made, so the result is invalid.
5030 The changes already made can still be undone.
5031 undobuf.num_undo is incremented for such changes, so by testing that
5032 the caller can tell whether the result is valid.
5034 `n_occurrences' is incremented each time FROM is replaced.
5036 IN_DEST is nonzero if we are processing the SET_DEST of a SET.
5038 IN_COND is nonzero if we are at the top level of a condition.
5040 UNIQUE_COPY is nonzero if each substitution must be unique. We do this
5041 by copying if `n_occurrences' is nonzero. */
5043 static rtx
5045 {
5050 rtx new_rtx;
5052 /* Two expressions are equal if they are identical copies of a shared
5053 RTX or if they are both registers with the same register number
5054 and mode. */
5056 #define COMBINE_RTX_EQUAL_P(X,Y) \
5057 ((X) == (Y) \
5058 || (REG_P (X) && REG_P (Y) \
5059 && REGNO (X) == REGNO (Y) && GET_MODE (X) == GET_MODE (Y)))
5062 {
5063 n_occurrences++;
5065 }
5067 /* If X and FROM are the same register but different modes, they
5068 will not have been seen as equal above. However, the log links code
5069 will make a LOG_LINKS entry for that case. If we do nothing, we
5070 will try to rerecognize our original insn and, when it succeeds,
5071 we will delete the feeding insn, which is incorrect.
5073 So force this insn not to match in this (rare) case. */
5078 /* If this is an object, we are done unless it is a MEM or LO_SUM, both
5079 of which may contain things that can be combined. */
5083 /* It is possible to have a subexpression appear twice in the insn.
5084 Suppose that FROM is a register that appears within TO.
5085 Then, after that subexpression has been scanned once by `subst',
5086 the second time it is scanned, TO may be found. If we were
5087 to scan TO here, we would find FROM within it and create a
5088 self-referent rtl structure which is completely wrong. */
5092 /* Parallel asm_operands need special attention because all of the
5093 inputs are shared across the arms. Furthermore, unsharing the
5094 rtl results in recognition failures. Failure to handle this case
5095 specially can result in circular rtl.
5097 Solve this by doing a normal pass across the first entry of the
5098 parallel, and only processing the SET_DESTs of the subsequent
5099 entries. Ug. */
5104 {
5107 /* If this substitution failed, this whole thing fails. */
5115 {
5121 {
5124 /* If this substitution failed, this whole thing fails. */
5130 }
5131 }
5132 }
5133 else
5134 {
5138 /* We don't need to process a SET_DEST that is a register, CC0,
5139 or PC, so set up to skip this common case. All other cases
5140 where we want to suppress replacing something inside a
5141 SET_SRC are handled via the IN_DEST operand. */
5148 /* Get the mode of operand 0 in case X is now a SIGN_EXTEND of a
5149 constant. */
5154 {
5156 {
5159 {
5161 {
5164 n_occurrences++;
5165 }
5166 else
5167 {
5169 unique_copy);
5171 /* If this substitution failed, this whole thing
5172 fails. */
5176 }
5179 }
5180 }
5182 {
5183 /* If this is a register being set, ignore it. */
5190 ;
5193 {
5194 /* In general, don't install a subreg involving two
5195 modes not tieable. It can worsen register
5196 allocation, and can even make invalid reload
5197 insns, since the reg inside may need to be copied
5198 from in the outside mode, and that may be invalid
5199 if it is an fp reg copied in integer mode.
5201 We allow two exceptions to this: It is valid if
5202 it is inside another SUBREG and the mode of that
5203 SUBREG and the mode of the inside of TO is
5204 tieable and it is valid if X is a SET that copies
5205 FROM to CC0. */
5213 #ifdef HAVE_cc0
5215 #endif
5216 )
5219 #ifdef CANNOT_CHANGE_MODE_CLASS
5227 #endif
5230 n_occurrences++;
5231 }
5232 else
5233 /* If we are in a SET_DEST, suppress most cases unless we
5234 have gone inside a MEM, in which case we want to
5235 simplify the address. We assume here that things that
5236 are actually part of the destination have their inner
5237 parts in the first expression. This is true for SUBREG,
5238 STRICT_LOW_PART, and ZERO_EXTRACT, which are the only
5239 things aside from REG and MEM that should appear in a
5240 SET_DEST. */
5242 (((in_dest
5248 unique_copy);
5250 /* If we found that we will have to reject this combination,
5251 indicate that by returning the CLOBBER ourselves, rather than
5252 an expression containing it. This will speed things up as
5253 well as prevent accidents where two CLOBBERs are considered
5254 to be equal, thus producing an incorrect simplification. */
5262 {
5270 }
5273 {
5277 }
5278 else
5280 }
5281 }
5282 }
5284 /* Check if we are loading something from the constant pool via float
5285 extension; in this case we would undo compress_float_constant
5286 optimization and degenerate constant load to an immediate value. */
5290 {
5294 }
5296 /* Try to simplify X. If the simplification changed the code, it is likely
5297 that further simplification will help, so loop, but limit the number
5298 of repetitions that will be performed. */
5301 {
5302 /* If X is sufficiently simple, don't bother trying to do anything
5303 with it. */
5312 /* We no longer know the original mode of operand 0 since we
5313 have changed the form of X) */
5315 }
5318 }
5319 \f
5320 /* Simplify X, a piece of RTL. We just operate on the expression at the
5321 outer level; call `subst' to simplify recursively. Return the new
5322 expression.
5324 OP0_MODE is the original mode of XEXP (x, 0). IN_DEST is nonzero
5325 if we are inside a SET_DEST. IN_COND is nonzero if we are at the top level
5326 of a condition. */
5328 static rtx
5331 {
5334 rtx temp;
5337 /* If this is a commutative operation, put a constant last and a complex
5338 expression first. We don't need to do this for comparisons here. */
5341 {
5345 }
5347 /* If this is a simple operation applied to an IF_THEN_ELSE, try
5348 applying it to the arms of the IF_THEN_ELSE. This often simplifies
5349 things. Check for cases where both arms are testing the same
5350 condition.
5352 Don't do anything if all operands are very simple. */
5365 {
5370 /* If everything is a comparison, what we have is highly unlikely
5371 to be simpler, so don't use it. */
5374 {
5381 /* Simplify the alternative arms; this may collapse the true and
5382 false arms to store-flag values. Be careful to use copy_rtx
5383 here since true_rtx or false_rtx might share RTL with x as a
5384 result of the if_then_else_cond call above. */
5388 /* If true_rtx and false_rtx are not general_operands, an if_then_else
5389 is unlikely to be simpler. */
5392 {
5395 /* Restarting if we generate a store-flag expression will cause
5396 us to loop. Just drop through in this case. */
5398 /* If the result values are STORE_FLAG_VALUE and zero, we can
5399 just make the comparison operation. */
5410 /* Likewise, we can make the negate of a comparison operation
5411 if the result values are - STORE_FLAG_VALUE and zero. */
5419 mode);
5430 mode);
5431 else
5434 mode,
5435 VOIDmode,
5436 cond,
5437 cop1),
5442 }
5443 }
5444 }
5446 /* Try to fold this expression in case we have constants that weren't
5447 present before. */
5450 {
5458 {
5461 {
5465 }
5468 }
5481 }
5484 {
5489 }
5491 /* First see if we can apply the inverse distributive law. */
5494 {
5498 }
5500 /* If CODE is an associative operation not otherwise handled, see if we
5501 can associate some operands. This can win if they are constants or
5502 if they are logically related (i.e. (a & b) & a). */
5508 {
5510 {
5514 rtx inner;
5516 /* Make sure we pass the constant operand if any as the second
5517 one if this is a commutative operation. */
5519 {
5523 }
5529 /* For commutative operations, try the other pair if that one
5530 didn't simplify. */
5532 {
5537 }
5541 }
5542 }
5544 /* A little bit of algebraic simplification here. */
5546 {
5548 /* Ensure that our address has any ASHIFTs converted to MULT in case
5549 address-recognizing predicates are called later. */
5558 /* See if this can be moved to simplify_subreg. */
5561 /* Don't call gen_lowpart if the inner mode
5562 is VOIDmode and we cannot simplify it, as SUBREG without
5563 inner mode is invalid. */
5570 {
5571 rtx temp;
5576 }
5578 /* Don't change the mode of the MEM if that would change the meaning
5579 of the address. */
5585 /* Note that we cannot do any narrowing for non-constants since
5586 we might have been counting on using the fact that some bits were
5587 zero. We now do this in the SET. */
5594 /* For C equal to the width of MODE minus 1, (neg (ashiftrt X C)) can be
5595 replaced by (lshiftrt X C). This will convert
5596 (neg (sign_extract X 1 Y)) to (zero_extract X 1 Y). */
5604 /* If X has only a single bit that might be nonzero, say, bit I, convert
5605 (neg X) to (ashiftrt (ashift X C-I) C-I) where C is the bitsize of
5606 MODE minus 1. This will convert (neg (zero_extract X 1 Y)) to
5607 (sign_extract X 1 Y). But only do this if TEMP isn't a register
5608 or a SUBREG of one since we'd be making the expression more
5609 complex if it was just a register. */
5615 {
5616 rtx temp1 = simplify_shift_const
5622 /* If all we did was surround TEMP with the two shifts, we
5623 haven't improved anything, so don't use it. Otherwise,
5624 we are better off with TEMP1. */
5629 }
5633 /* We can't handle truncation to a partial integer mode here
5634 because we don't know the real bitsize of the partial
5635 integer mode. */
5644 /* We can truncate a constant value and return it. */
5648 /* Similarly to what we do in simplify-rtx.c, a truncate of a register
5649 whose value is a comparison can be replaced with a subreg if
5650 STORE_FLAG_VALUE permits. */
5659 /* (const (const X)) can become (const X). Do it this way rather than
5660 returning the inner CONST since CONST can be shared with a
5661 REG_EQUAL note. */
5666 #ifdef HAVE_lo_sum
5668 /* Convert (lo_sum (high FOO) FOO) to FOO. This is necessary so we
5669 can add in an offset. find_split_point will split this address up
5670 again if it doesn't match. */
5675 #endif
5678 /* (plus (xor (and <foo> (const_int pow2 - 1)) <c>) <-c>)
5679 when c is (const_int (pow2 + 1) / 2) is a sign extension of a
5680 bit-field and can be replaced by either a sign_extend or a
5681 sign_extract. The `and' may be a zero_extend and the two
5682 <c>, -<c> constants may be reversed. */
5697 return simplify_shift_const
5704 /* If only the low-order bit of X is possibly nonzero, (plus x -1)
5705 can become (ashiftrt (ashift (xor x 1) C) C) where C is
5706 the bitsize of the mode - 1. This allows simplification of
5707 "a = (b & 8) == 0;" */
5719 /* If we are adding two things that have no bits in common, convert
5720 the addition into an IOR. This will often be further simplified,
5721 for example in cases like ((a & 1) + (a & 2)), which can
5722 become a & 3. */
5727 {
5728 /* Try to simplify the expression further. */
5732 /* If we could, great. If not, do not go ahead with the IOR
5733 replacement, since PLUS appears in many special purpose
5734 address arithmetic instructions. */
5742 }
5746 /* (minus <foo> (and <foo> (const_int -pow2))) becomes
5747 (and <foo> (const_int pow2-1)) */
5757 /* If we have (mult (plus A B) C), apply the distributive law and then
5758 the inverse distributive law to see if things simplify. This
5759 occurs mostly in addresses, often when unrolling loops. */
5762 {
5766 }
5768 /* Try simplify a*(b/c) as (a*b)/c. */
5771 {
5777 }
5781 /* If this is a divide by a power of two, treat it as a shift if
5782 its first operand is a shift. */
5800 /* If the first operand is a condition code, we can't do anything
5801 with it. */
5805 {
5813 /* Simplify our comparison, if possible. */
5816 /* If STORE_FLAG_VALUE is 1, we can convert (ne x 0) to simply X
5817 if only the low-order bit is possibly nonzero in X (such as when
5818 X is a ZERO_EXTRACT of one bit). Similarly, we can convert EQ to
5819 (xor X 1) or (minus 1 X); we use the former. Finally, if X is
5820 known to be either 0 or -1, NE becomes a NEG and EQ becomes
5821 (plus X 1).
5823 Remove any ZERO_EXTRACT we made when thinking this was a
5824 comparison. It may now be simpler to use, e.g., an AND. If a
5825 ZERO_EXTRACT is indeed appropriate, it will be placed back by
5826 the call to make_compound_operation in the SET case.
5828 Don't apply these optimizations if the caller would
5829 prefer a comparison rather than a value.
5830 E.g., for the condition in an IF_THEN_ELSE most targets need
5831 an explicit comparison. */
5834 ;
5850 {
5854 mode);
5855 }
5862 {
5866 const1_rtx);
5867 }
5875 {
5878 }
5880 /* If STORE_FLAG_VALUE is -1, we have cases similar to
5881 those above. */
5883 ;
5898 {
5902 mode);
5903 }
5911 {
5915 mode);
5916 }
5918 /* If X is 0/1, (eq X 0) is X-1. */
5924 {
5927 }
5929 /* If STORE_FLAG_VALUE says to just test the sign bit and X has just
5930 one bit that might be nonzero, we can convert (ne x 0) to
5931 (ashift x c) where C puts the bit in the sign bit. Remove any
5932 AND with STORE_FLAG_VALUE when we are done, since we are only
5933 going to test the sign bit. */
5940 {
5946 else
5948 }
5950 /* If the code changed, return a whole new comparison. */
5954 /* Otherwise, keep this operation, but maybe change its operands.
5955 This also converts (ne (compare FOO BAR) 0) to (ne FOO BAR). */
5958 }
5968 /* If we are processing SET_DEST, we are done. */
5986 /* If this is a shift by a constant amount, simplify it. */
6002 }
6005 }
6006 \f
6007 /* Simplify X, an IF_THEN_ELSE expression. Return the new expression. */
6009 static rtx
6011 {
6018 rtx temp;
6021 rtx reversed;
6023 /* Simplify storing of the truth value. */
6028 /* Also when the truth value has to be reversed. */
6034 /* Sometimes we can simplify the arm of an IF_THEN_ELSE if a register used
6035 in it is being compared against certain values. Get the true and false
6036 comparisons and see if that says anything about the value of each arm. */
6042 {
6043 HOST_WIDE_INT nzb;
6049 /* If FALSE_CODE is EQ, swap the codes and arms. */
6052 {
6055 }
6057 /* If we are comparing against zero and the expression being tested has
6058 only a single bit that might be nonzero, that is its value when it is
6059 not equal to zero. Similarly if it is known to be -1 or 0. */
6063 {
6066 }
6070 {
6073 }
6075 /* Now simplify an arm if we know the value of the register in the
6076 branch and it is used in the arm. Be careful due to the potential
6077 of locally-shared RTL. */
6094 }
6096 /* If we have (if_then_else FOO (pc) (label_ref BAR)) and FOO can be
6097 reversed, do so to avoid needing two sets of patterns for
6098 subtract-and-branch insns. Similarly if we have a constant in the true
6099 arm, the false arm is the same as the first operand of the comparison, or
6100 the false arm is more complicated than the true arm. */
6113 {
6122 /* It is possible that the conditional has been simplified out. */
6125 }
6127 /* If the two arms are identical, we don't need the comparison. */
6132 /* Convert a == b ? b : a to "a". */
6144 /* Look for cases where we have (abs x) or (neg (abs X)). */
6147 && comparison_p
6154 {
6160 return
6163 mode);
6166 }
6168 /* Look for MIN or MAX. */
6171 && comparison_p
6176 {
6191 }
6193 /* If we have (if_then_else COND (OP Z C1) Z) and OP is an identity when its
6194 second operand is zero, this can be done as (OP Z (mult COND C2)) where
6195 C2 = C1 * STORE_FLAG_VALUE. Similarly if OP has an outer ZERO_EXTEND or
6196 SIGN_EXTEND as long as Z is already extended (so we don't destroy it).
6197 We can do this kind of thing in some cases when STORE_FLAG_VALUE is
6198 neither 1 or -1, but it isn't worth checking for. */
6201 && comparison_p
6204 {
6220 /* If an identity-zero op is commutative, check whether there
6221 would be a match if we swapped the operands. */
6241 {
6245 }
6257 {
6261 }
6277 {
6281 }
6293 {
6297 }
6300 {
6306 const_true_rtx));
6314 }
6315 }
6317 /* If we have (if_then_else (ne A 0) C1 0) and either A is known to be 0 or
6318 1 and C1 is a single bit or A is known to be 0 or -1 and C1 is the
6319 negation of a single bit, we can convert this operation to a shift. We
6320 can actually do this more generally, but it doesn't seem worth it. */
6329 return
6333 /* (IF_THEN_ELSE (NE REG 0) (0) (8)) is REG for nonzero_bits (REG) == 8. */
6343 }
6344 \f
6345 /* Simplify X, a SET expression. Return the new expression. */
6347 static rtx
6349 {
6352 enum machine_mode mode
6354 rtx other_insn;
6357 /* (set (pc) (return)) gets written as (return). */
6361 /* Now that we know for sure which bits of SRC we are using, see if we can
6362 simplify the expression for the object knowing that we only need the
6363 low-order bits. */
6366 {
6369 }
6371 /* If we are setting CC0 or if the source is a COMPARE, look for the use of
6372 the comparison result and try to simplify it unless we already have used
6373 undobuf.other_insn. */
6381 {
6390 {
6393 {
6396 }
6397 }
6398 else
6406 {
6410 }
6411 else
6412 {
6417 /* Attempt to simplify CC user. */
6419 {
6423 }
6425 /* Convert X into a no-op move. */
6429 }
6431 /* Simplify our comparison, if possible. */
6434 #ifdef SELECT_CC_MODE
6435 /* If this machine has CC modes other than CCmode, check to see if we
6436 need to use a different CC mode here. */
6445 else
6448 #ifndef HAVE_cc0
6449 /* If the mode changed, we have to change SET_DEST, the mode in the
6450 compare, and the mode in the place SET_DEST is used. If SET_DEST is
6451 a hard register, just build new versions with the proper mode. If it
6452 is a pseudo, we lose unless it is only time we set the pseudo, in
6453 which case we can safely change its mode. */
6455 {
6457 {
6459 rtx new_dest;
6463 else
6464 {
6467 }
6474 }
6475 }
6479 /* If the code changed, we have to build a new comparison in
6480 undobuf.other_insn. */
6482 {
6491 /* If the only change we made was to change an EQ into an NE or
6492 vice versa, OP0 has only one bit that might be nonzero, and OP1
6493 is zero, check if changing the user of the condition code will
6494 produce a valid insn. If it won't, we can keep the original code
6495 in that insn by surrounding our operation with an XOR. */
6502 {
6507 {
6513 }
6514 }
6515 }
6520 /* Otherwise, if we didn't previously have a COMPARE in the
6521 correct mode, we need one. */
6523 {
6526 }
6528 {
6531 }
6532 /* Otherwise, update the COMPARE if needed. */
6534 {
6537 }
6538 }
6539 else
6540 {
6541 /* Get SET_SRC in a form where we have placed back any
6542 compound expressions. Then do the checks below. */
6545 }
6547 /* If we have (set x (subreg:m1 (op:m2 ...) 0)) with OP being some operation,
6548 and X being a REG or (subreg (reg)), we may be able to convert this to
6549 (set (subreg:m2 x) (op)).
6551 We can always do this if M1 is narrower than M2 because that means that
6552 we only care about the low bits of the result.
6554 However, on machines without WORD_REGISTER_OPERATIONS defined, we cannot
6555 perform a narrower operation than requested since the high-order bits will
6556 be undefined. On machine where it is defined, this transformation is safe
6557 as long as M1 and M2 have the same number of words. */
6565 #ifndef WORD_REGISTER_OPERATIONS
6568 #endif
6569 #ifdef CANNOT_CHANGE_MODE_CLASS
6574 #endif
6578 {
6581 dest));
6585 }
6587 #ifdef HAVE_cc0
6588 /* If we have (set (cc0) (subreg ...)), we try to remove the subreg
6589 in SRC. */
6595 {
6599 /* Here we make sure that we don't have a sign bit on. */
6602 {
6605 }
6606 }
6607 #endif
6609 #ifdef LOAD_EXTEND_OP
6610 /* If we have (set FOO (subreg:M (mem:N BAR) 0)) with M wider than N, this
6611 would require a paradoxical subreg. Replace the subreg with a
6612 zero_extend to avoid the reload that would otherwise be required. */
6620 {
6626 }
6627 #endif
6629 /* If we don't have a conditional move, SET_SRC is an IF_THEN_ELSE, and we
6630 are comparing an item known to be 0 or -1 against 0, use a logical
6631 operation instead. Check for one of the arms being an IOR of the other
6632 arm with some value. We compute three terms to be IOR'ed together. In
6633 practice, at most two will be nonzero. Then we do the IOR's. */
6641 #ifdef HAVE_conditional_move
6643 #endif
6648 {
6674 false_rtx);
6680 term3));
6683 }
6685 /* If either SRC or DEST is a CLOBBER of (const_int 0), make this
6686 whole thing fail. */
6691 else
6692 /* Convert this into a field assignment operation, if possible. */
6694 }
6695 \f
6696 /* Simplify, X, and AND, IOR, or XOR operation, and return the simplified
6697 result. */
6699 static rtx
6701 {
6707 {
6709 /* We can call simplify_and_const_int only if we don't lose
6710 any (sign) bits when converting INTVAL (op1) to
6711 "unsigned HOST_WIDE_INT". */
6715 {
6722 }
6724 /* If we have any of (and (ior A B) C) or (and (xor A B) C),
6725 apply the distributive law and then the inverse distributive
6726 law to see if things simplify. */
6728 {
6732 }
6734 {
6738 }
6742 /* If we have (ior (and A B) C), apply the distributive law and then
6743 the inverse distributive law to see if things simplify. */
6746 {
6750 }
6753 {
6757 }
6762 }
6765 }
6766 \f
6767 /* We consider ZERO_EXTRACT, SIGN_EXTRACT, and SIGN_EXTEND as "compound
6768 operations" because they can be replaced with two more basic operations.
6769 ZERO_EXTEND is also considered "compound" because it can be replaced with
6770 an AND operation, which is simpler, though only one operation.
6772 The function expand_compound_operation is called with an rtx expression
6773 and will convert it to the appropriate shifts and AND operations,
6774 simplifying at each stage.
6776 The function make_compound_operation is called to convert an expression
6777 consisting of shifts and ANDs into the equivalent compound expression.
6778 It is the inverse of this function, loosely speaking. */
6780 static rtx
6782 {
6786 rtx tem;
6789 {
6793 /* We can't necessarily use a const_int for a multiword mode;
6794 it depends on implicitly extending the value.
6795 Since we don't know the right way to extend it,
6796 we can't tell whether the implicit way is right.
6798 Even for a mode that is no wider than a const_int,
6799 we can't win, because we need to sign extend one of its bits through
6800 the rest of it, and we don't know which bit. */
6804 /* Return if (subreg:MODE FROM 0) is not a safe replacement for
6805 (zero_extend:MODE FROM) or (sign_extend:MODE FROM). It is for any MEM
6806 because (SUBREG (MEM...)) is guaranteed to cause the MEM to be
6807 reloaded. If not for that, MEM's would very rarely be safe.
6809 Reject MODEs bigger than a word, because we might not be able
6810 to reference a two-register group starting with an arbitrary register
6811 (and currently gen_lowpart might crash for a SUBREG). */
6816 /* Reject MODEs that aren't scalar integers because turning vector
6817 or complex modes into shifts causes problems. */
6823 /* If the inner object has VOIDmode (the only way this can happen
6824 is if it is an ASM_OPERANDS), we can't do anything since we don't
6825 know how much masking to do. */
6834 /* ... fall through ... */
6837 /* If the operand is a CLOBBER, just return it. */
6846 /* Reject MODEs that aren't scalar integers because turning vector
6847 or complex modes into shifts causes problems. */
6855 /* This should stay within the object being extracted, fail otherwise. */
6866 }
6867 /* Convert sign extension to zero extension, if we know that the high
6868 bit is not set, as this is easier to optimize. It will be converted
6869 back to cheaper alternative in make_extraction. */
6877 {
6881 /* Make sure this is a profitable operation. */
6888 else
6890 }
6892 /* We can optimize some special cases of ZERO_EXTEND. */
6894 {
6895 /* (zero_extend:DI (truncate:SI foo:DI)) is just foo:DI if we
6896 know that the last value didn't have any inappropriate bits
6897 set. */
6905 /* Likewise for (zero_extend:DI (subreg:SI foo:DI 0)). */
6914 /* (zero_extend:DI (truncate:SI foo:DI)) is just foo:DI when foo
6915 is a comparison and STORE_FLAG_VALUE permits. This is like
6916 the first case, but it works even when GET_MODE (x) is larger
6917 than HOST_WIDE_INT. */
6926 /* Likewise for (zero_extend:DI (subreg:SI foo:DI 0)). */
6936 }
6938 /* If we reach here, we want to return a pair of shifts. The inner
6939 shift is a left shift of BITSIZE - POS - LEN bits. The outer
6940 shift is a right shift of BITSIZE - LEN bits. It is arithmetic or
6941 logical depending on the value of UNSIGNEDP.
6943 If this was a ZERO_EXTEND or ZERO_EXTRACT, this pair of shifts will be
6944 converted into an AND of a shift.
6946 We must check for the case where the left shift would have a negative
6947 count. This can happen in a case like (x >> 31) & 255 on machines
6948 that can't shift by a constant. On those machines, we would first
6949 combine the shift with the AND to produce a variable-position
6950 extraction. Then the constant of 31 would be substituted in
6951 to produce such a position. */
6955 {
6964 }
6971 else
6972 /* Any other cases we can't handle. */
6975 /* If we couldn't do this for some reason, return the original
6976 expression. */
6981 }
6982 \f
6983 /* X is a SET which contains an assignment of one object into
6984 a part of another (such as a bit-field assignment, STRICT_LOW_PART,
6985 or certain SUBREGS). If possible, convert it into a series of
6986 logical operations.
6988 We half-heartedly support variable positions, but do not at all
6989 support variable lengths. */
6991 static const_rtx
6993 {
6994 rtx inner;
7000 /* Loop until we find something we can't simplify. */
7002 {
7005 {
7009 }
7012 {
7017 /* A constant position should stay within the width of INNER. */
7023 {
7031 /* If position is ADJUST - X, new position is X. */
7033 else
7038 pos);
7039 }
7040 }
7042 /* A SUBREG between two modes that occupy the same numbers of words
7043 can be done by moving the SUBREG to the source. */
7045 /* We need SUBREGs to compute nonzero_bits properly. */
7046 && nonzero_sign_valid
7051 {
7053 gen_lowpart
7057 }
7058 else
7066 /* Don't attempt bitwise arithmetic on non scalar integer modes. */
7068 {
7071 /* Don't do anything for vector or complex integral types. */
7075 /* Try to find an integral mode to pun with. */
7082 }
7084 /* Compute a mask of LEN bits, if we can do this on the host machine. */
7088 /* Now compute the equivalent expression. Make a copy of INNER
7089 for the SET_DEST in case it is a MEM into which we will substitute;
7090 we don't want shared RTL in that case. */
7095 compute_mode,
7097 compute_mode),
7098 inner);
7103 mask),
7104 pos);
7109 }
7112 }
7113 \f
7114 /* Return an RTX for a reference to LEN bits of INNER. If POS_RTX is nonzero,
7115 it is an RTX that represents a variable starting position; otherwise,
7116 POS is the (constant) starting bit position (counted from the LSB).
7118 UNSIGNEDP is nonzero for an unsigned reference and zero for a
7119 signed reference.
7121 IN_DEST is nonzero if this is a reference in the destination of a
7122 SET. This is used when a ZERO_ or SIGN_EXTRACT isn't needed. If nonzero,
7123 a STRICT_LOW_PART will be used, if zero, ZERO_EXTEND or SIGN_EXTEND will
7124 be used.
7126 IN_COMPARE is nonzero if we are in a COMPARE. This means that a
7127 ZERO_EXTRACT should be built even for bits starting at bit 0.
7129 MODE is the desired mode of the result (if IN_DEST == 0).
7131 The result is an RTX for the extraction or NULL_RTX if the target
7132 can't handle it. */
7134 static rtx
7138 {
7139 /* This mode describes the size of the storage area
7140 to fetch the overall value from. Within that, we
7141 ignore the POS lowest bits, etc. */
7151 HOST_WIDE_INT orig_pos;
7154 {
7155 /* If going from (subreg:SI (mem:QI ...)) to (mem:QI ...),
7156 consider just the QI as the memory to extract from.
7157 The subreg adds or removes high bits; its mode is
7158 irrelevant to the meaning of this extraction,
7159 since POS and LEN count from the lsb. */
7163 }
7168 {
7169 /* We're extracting the least significant bits of an rtx
7170 (ashift X (const_int C)), where LEN > C. Extract the
7171 least significant (LEN - C) bits of X, giving an rtx
7172 whose mode is MODE, then shift it left C times. */
7178 }
7185 /* See if this can be done without an extraction. We never can if the
7186 width of the field is not the same as that of some integer mode. For
7187 registers, we can only avoid the extraction if the position is at the
7188 low-order bit and this is either not in the destination or we have the
7189 appropriate STRICT_LOW_PART operation available.
7191 For MEM, we can avoid an extract if the field starts on an appropriate
7192 boundary and we can change the mode of the memory reference. */
7201 && (! in_dest
7205 && (pos
7208 /* We can't do this if we are widening INNER_MODE (it
7209 may not be aligned, for one thing). */
7214 {
7215 /* If INNER is a MEM, make a new MEM that encompasses just the desired
7216 field. If the original and current mode are the same, we need not
7217 adjust the offset. Otherwise, we do if bytes big endian.
7219 If INNER is not a MEM, get a piece consisting of just the field
7220 of interest (in this case POS % BITS_PER_WORD must be 0). */
7223 {
7224 HOST_WIDE_INT offset;
7226 /* POS counts from lsb, but make OFFSET count in memory order. */
7229 else
7233 }
7235 {
7237 {
7238 /* We can't call gen_lowpart in a DEST since we
7239 always want a SUBREG (see below) and it would sometimes
7240 return a new hard register. */
7242 {
7257 /* Avoid creating invalid subregs, for example when
7258 simplifying (x>>32)&255. */
7263 }
7264 else
7266 }
7267 else
7269 }
7270 else
7272 len >= HOST_BITS_PER_WIDE_INT
7277 /* If this extraction is going into the destination of a SET,
7278 make a STRICT_LOW_PART unless we made a MEM. */
7294 /* If we know that no extraneous bits are set, and that the high
7295 bit is not set, convert the extraction to the cheaper of
7296 sign and zero extension, that are equivalent in these cases. */
7302 {
7306 /* Prefer ZERO_EXTENSION, since it gives more information to
7307 backends. */
7312 }
7314 /* Otherwise, sign- or zero-extend unless we already are in the
7315 proper mode. */
7319 }
7321 /* Unless this is a COMPARE or we have a funny memory reference,
7322 don't do anything with zero-extending field extracts starting at
7323 the low-order bit since they are simple AND operations. */
7328 /* Unless INNER is not MEM, reject this if we would be spanning bytes or
7329 if the position is not a constant and the length is not 1. In all
7330 other cases, we would only be going outside our object in cases when
7331 an original shift would have been undefined. */
7337 /* Get the mode to use should INNER not be a MEM, the mode for the position,
7338 and the mode for the result. */
7340 {
7344 }
7348 {
7352 }
7356 {
7360 }
7362 /* Never narrow an object, since that might not be safe. */
7372 /* If this is not from memory, the desired mode is the preferred mode
7373 for an extraction pattern's first input operand, or word_mode if there
7374 is none. */
7377 else
7378 {
7379 /* Be careful not to go beyond the extracted object and maintain the
7380 natural alignment of the memory. */
7384 {
7387 }
7389 /* If we have to change the mode of memory and cannot, the desired mode
7390 is EXTRACTION_MODE. */
7396 }
7401 {
7402 /* POS is passed as if BITS_BIG_ENDIAN == 0, so we need to convert it to
7403 BITS_BIG_ENDIAN style. If position is constant, compute new
7404 position. Otherwise, build subtraction.
7405 Note that POS is relative to the mode of the original argument.
7406 If it's a MEM we need to recompute POS relative to that.
7407 However, if we're extracting from (or inserting into) a register,
7408 we want to recompute POS relative to wanted_inner_mode. */
7415 else
7416 pos_rtx
7418 /* POS may be less than 0 now, but we check for that below.
7419 Note that it can only be less than 0 if !MEM_P (inner). */
7420 }
7422 /* If INNER has a wider mode, and this is a constant extraction, try to
7423 make it smaller and adjust the byte to point to the byte containing
7424 the value. */
7427 && ! pos_rtx
7432 {
7435 /* The computations below will be correct if the machine is big
7436 endian in both bits and bytes or little endian in bits and bytes.
7437 If it is mixed, we must adjust. */
7439 /* If bytes are big endian and we had a paradoxical SUBREG, we must
7440 adjust OFFSET to compensate. */
7445 /* We can now move to the desired byte. */
7456 }
7458 /* If INNER is not memory, get it into the proper mode. If we are changing
7459 its mode, POS must be a constant and smaller than the size of the new
7460 mode. */
7462 {
7463 /* On the LHS, don't create paradoxical subregs implicitely truncating
7464 the register unless TRULY_NOOP_TRUNCATION. */
7467 wanted_inner_mode))
7479 pos_rtx
7485 }
7487 /* Adjust mode of POS_RTX, if needed. If we want a wider mode, we
7488 have to zero extend. Otherwise, we can just use a SUBREG. */
7491 {
7494 /* If we know that no extraneous bits are set, and that the high
7495 bit is not set, convert extraction to cheaper one - either
7496 SIGN_EXTENSION or ZERO_EXTENSION, that are equivalent in these
7497 cases. */
7505 {
7508 /* Prefer ZERO_EXTENSION, since it gives more information to
7509 backends. */
7513 }
7515 }
7520 /* Make POS_RTX unless we already have it and it is correct. If we don't
7521 have a POS_RTX but we do have an ORIG_POS_RTX, the latter must
7522 be a CONST_INT. */
7529 /* Make the required operation. See if we can use existing rtx. */
7536 }
7537 \f
7538 /* See if X contains an ASHIFT of COUNT or more bits that can be commuted
7539 with any other operations in X. Return X without that shift if so. */
7541 static rtx
7543 {
7546 rtx tem;
7549 {
7551 /* This is the shift itself. If it is wide enough, we will return
7552 either the value being shifted if the shift count is equal to
7553 COUNT or a shift for the difference. */
7567 /* If we can safely shift this constant and we find the inner shift,
7568 make a new operation. */
7580 }
7583 }
7584 \f
7585 /* Look at the expression rooted at X. Look for expressions
7586 equivalent to ZERO_EXTRACT, SIGN_EXTRACT, ZERO_EXTEND, SIGN_EXTEND.
7587 Form these expressions.
7589 Return the new rtx, usually just X.
7591 Also, for machines like the VAX that don't have logical shift insns,
7592 try to convert logical to arithmetic shift operations in cases where
7593 they are equivalent. This undoes the canonicalizations to logical
7594 shifts done elsewhere.
7596 We try, as much as possible, to re-use rtl expressions to save memory.
7598 IN_CODE says what kind of expression we are processing. Normally, it is
7599 SET. In a memory address (inside a MEM, PLUS or minus, the latter two
7600 being kludges), it is MEM. When processing the arguments of a comparison
7601 or a COMPARE against zero, it is COMPARE. */
7603 static rtx
7605 {
7613 rtx tem;
7616 /* Select the code to be used in recursive calls. Once we are inside an
7617 address, we stay there. If we have a comparison, set to COMPARE,
7618 but once inside, go back to our default of SET. */
7627 /* Process depending on the code of this operation. If NEW is set
7628 nonzero, it will be returned. */
7631 {
7633 /* Convert shifts by constants into multiplications if inside
7634 an address. */
7639 {
7645 {
7648 }
7651 }
7661 {
7665 }
7668 {
7672 mode));
7674 }
7675 else
7676 {
7680 }
7691 {
7695 }
7698 {
7702 mode));
7704 }
7705 else
7706 {
7710 }
7714 /* If the second operand is not a constant, we can't do anything
7715 with it. */
7719 /* If the constant is a power of two minus one and the first operand
7720 is a logical right shift, make an extraction. */
7723 {
7727 }
7729 /* Same as previous, but for (subreg (lshiftrt ...)) in first op. */
7734 {
7736 next_code);
7740 }
7741 /* Same as previous, but for (xor/ior (lshiftrt...) (lshiftrt...)). */
7747 {
7748 /* Apply the distributive law, and then try to make extractions. */
7755 }
7757 /* If we are have (and (rotate X C) M) and C is larger than the number
7758 of bits in M, this is an extraction. */
7764 {
7770 }
7772 /* On machines without logical shifts, if the operand of the AND is
7773 a logical shift and our mask turns off all the propagated sign
7774 bits, we can replace the logical shift with an arithmetic shift. */
7782 {
7789 make_compound_operation
7792 }
7794 /* If the constant is one less than a power of two, this might be
7795 representable by an extraction even if no shift is present.
7796 If it doesn't end up being a ZERO_EXTEND, we will ignore it unless
7797 we are in a COMPARE. */
7801 next_code),
7804 /* If we are in a comparison and this is an AND with a power of two,
7805 convert this into the appropriate bit extract. */
7810 next_code),
7816 /* If the sign bit is known to be zero, replace this with an
7817 arithmetic shift. */
7822 {
7825 next_code),
7828 }
7830 /* ... fall through ... */
7836 /* If we have (ashiftrt (ashift foo C1) C2) with C2 >= C1,
7837 this is a SIGN_EXTRACT. */
7844 {
7851 }
7853 /* See if we have operations between an ASHIFTRT and an ASHIFT.
7854 If so, try to merge the shifts into a SIGN_EXTEND. We could
7855 also do this for some cases of SIGN_EXTRACT, but it doesn't
7856 seem worth the effort; the case checked for occurs on Alpha. */
7872 /* Call ourselves recursively on the inner expression. If we are
7873 narrowing the object and it has a different RTL code from
7874 what it originally did, do this SUBREG as a force_to_mode. */
7875 {
7880 simplified
7888 {
7889 rtx newer
7892 /* If we have something other than a SUBREG, we might have
7893 done an expansion, so rerun ourselves. */
7897 /* force_to_mode can expand compounds. If it just re-expanded the
7898 compound, use gen_lowpart to convert to the desired mode. */
7900 /* Likewise if it re-expanded the compound only partially.
7901 This happens for SUBREG of ZERO_EXTRACT if they extract
7902 the same number of bits. */
7911 }
7915 }
7920 }
7923 {
7926 }
7928 /* Now recursively process each operand of this operation. We need to
7929 handle ZERO_EXTEND specially so that we don't lose track of the
7930 inner mode. */
7932 {
7940 }
7945 {
7948 }
7951 {
7954 }
7956 maybe_swap:
7957 /* If this is a commutative operation, the changes to the operands
7958 may have made it noncanonical. */
7961 {
7965 }
7968 }
7969 \f
7970 /* Given M see if it is a value that would select a field of bits
7971 within an item, but not the entire word. Return -1 if not.
7972 Otherwise, return the starting position of the field, where 0 is the
7973 low-order bit.
7975 *PLEN is set to the length of the field. */
7977 static int
7979 {
7980 /* Get the bit number of the first 1 bit from the right, -1 if none. */
7985 /* Now shift off the low-order zero bits and see if we have a
7986 power of two minus 1. */
7994 }
7995 \f
7996 /* If X refers to a register that equals REG in value, replace these
7997 references with REG. */
7998 static rtx
8000 {
8008 {
8044 {
8048 else
8050 }
8052 /* fall through */
8059 {
8062 {
8064 {
8067 }
8069 }
8070 }
8072 {
8075 {
8078 {
8080 {
8083 }
8085 }
8086 }
8087 }
8090 }
8093 }
8095 /* Return X converted to MODE. If the value is already truncated to
8096 MODE we can just return a subreg even though in the general case we
8097 would need an explicit truncation. */
8099 static rtx
8101 {
8106 {
8107 /* Bit-cast X into an integer mode. */
8112 }
8115 }
8117 /* See if X can be simplified knowing that we will only refer to it in
8118 MODE and will only refer to those bits that are nonzero in MASK.
8119 If other bits are being computed or if masking operations are done
8120 that select a superset of the bits in MASK, they can sometimes be
8121 ignored.
8123 Return a possibly simplified expression, but always convert X to
8124 MODE. If X is a CONST_INT, AND the CONST_INT with MASK.
8126 If JUST_SELECT is nonzero, don't optimize by noticing that bits in MASK
8127 are all off in X. This is used when X will be complemented, by either
8128 NOT, NEG, or XOR. */
8130 static rtx
8133 {
8140 /* If this is a CALL or ASM_OPERANDS, don't do anything. Some of the
8141 code below will do the wrong thing since the mode of such an
8142 expression is VOIDmode.
8144 Also do nothing if X is a CLOBBER; this can happen if X was
8145 the return value from a call to gen_lowpart. */
8149 /* We want to perform the operation is its present mode unless we know
8150 that the operation is valid in MODE, in which case we do the operation
8151 in MODE. */
8156 /* It is not valid to do a right-shift in a narrower mode
8157 than the one it came in with. */
8162 /* Truncate MASK to fit OP_MODE. */
8166 /* When we have an arithmetic operation, or a shift whose count we
8167 do not know, we need to assume that all bits up to the highest-order
8168 bit in MASK will be needed. This is how we form such a mask. */
8171 else
8175 /* Determine what bits of X are guaranteed to be (non)zero. */
8178 /* If none of the bits in X are needed, return a zero. */
8182 /* If X is a CONST_INT, return a new one. Do this here since the
8183 test below will fail. */
8185 {
8188 else
8189 {
8192 }
8193 }
8195 /* If X is narrower than MODE and we want all the bits in X's mode, just
8196 get X in the proper mode. */
8201 /* We can ignore the effect of a SUBREG if it narrows the mode or
8202 if the constant masks to zero all the bits the mode doesn't have. */
8212 /* The arithmetic simplifications here only work for scalar integer modes. */
8217 {
8219 /* If X is a (clobber (const_int)), return it since we know we are
8220 generating something that won't match. */
8233 /* Similarly for a truncate. */
8237 /* If this is an AND with a constant, convert it into an AND
8238 whose constant is the AND of that constant with MASK. If it
8239 remains an AND of MASK, delete it since it is redundant. */
8242 {
8246 /* If X is still an AND, see if it is an AND with a mask that
8247 is just some low-order bits. If so, and it is MASK, we don't
8248 need it. */
8255 /* If it remains an AND, try making another AND with the bits
8256 in the mode mask that aren't in MASK turned on. If the
8257 constant in the AND is wide enough, this might make a
8258 cheaper constant. */
8263 {
8264 unsigned HOST_WIDE_INT cval
8268 rtx y;
8270 /* If MODE is narrower than HOST_WIDE_INT and CVAL is a negative
8271 number, sign extend it. */
8281 }
8284 }
8289 /* In (and (plus FOO C1) M), if M is a mask that just turns off
8290 low-order bits (as in an alignment operation) and FOO is already
8291 aligned to that boundary, mask C1 to that boundary as well.
8292 This may eliminate that PLUS and, later, the AND. */
8294 {
8298 /* If MODE is narrower than HOST_WIDE_INT and mask is a negative
8299 number, sign extend it. */
8312 }
8314 /* ... fall through ... */
8317 /* For PLUS, MINUS and MULT, we need any bits less significant than the
8318 most significant bit in MASK since carries from those bits will
8319 affect the bits we are interested in. */
8324 /* If X is (minus C Y) where C's least set bit is larger than any bit
8325 in the mask, then we may replace with (neg Y). */
8330 {
8334 }
8336 /* Similarly, if C contains every bit in the fuller_mask, then we may
8337 replace with (not Y). */
8340 {
8344 }
8351 /* If X is (ior (lshiftrt FOO C1) C2), try to commute the IOR and
8352 LSHIFTRT so we end up with an (and (lshiftrt (ior ...) ...) ...)
8353 operation which may be a bitfield extraction. Ensure that the
8354 constant we form is not wider than the mode of X. */
8366 {
8374 }
8376 binop:
8377 /* For most binary operations, just propagate into the operation and
8378 change the mode if we have an operation of that mode. */
8383 /* If we ended up truncating both operands, truncate the result of the
8384 operation instead. */
8387 {
8390 }
8400 /* For left shifts, do the same, but just for the first operand.
8401 However, we cannot do anything with shifts where we cannot
8402 guarantee that the counts are smaller than the size of the mode
8403 because such a count will have a different meaning in a
8404 wider mode. */
8414 /* If the shift count is a constant and we can do arithmetic in
8415 the mode of the shift, refine which bits we need. Otherwise, use the
8416 conservative form of the mask. */
8422 else
8434 /* Here we can only do something if the shift count is a constant,
8435 this shift constant is valid for the host, and we can do arithmetic
8436 in OP_MODE. */
8442 {
8446 /* Select the mask of the bits we need for the shift operand. */
8449 /* We can only change the mode of the shift if we can do arithmetic
8450 in the mode of the shift and INNER_MASK is no wider than the
8451 width of X's mode. */
8459 }
8461 /* If we have (and (lshiftrt FOO C1) C2) where the combination of the
8462 shift and AND produces only copies of the sign bit (C2 is one less
8463 than a power of two), we can do this with just a shift. */
8467 /* The shift puts one of the sign bit copies in the least significant
8468 bit. */
8473 /* Number of bits left after the shift must be more than the mask
8474 needs. */
8477 /* Must be more sign bit copies than the mask needs. */
8487 /* If we are just looking for the sign bit, we don't need this shift at
8488 all, even if it has a variable count. */
8492 /* If this is a shift by a constant, get a mask that contains those bits
8493 that are not copies of the sign bit. We then have two cases: If
8494 MASK only includes those bits, this can be a logical shift, which may
8495 allow simplifications. If MASK is a single-bit field not within
8496 those bits, we are requesting a copy of the sign bit and hence can
8497 shift the sign bit to the appropriate location. */
8501 {
8504 /* If the considered data is wider than HOST_WIDE_INT, we can't
8505 represent a mask for all its bits in a single scalar.
8506 But we only care about the lower bits, so calculate these. */
8509 {
8512 /* GET_MODE_PRECISION (GET_MODE (x)) - INTVAL (XEXP (x, 1))
8513 is the number of bits a full-width mask would have set.
8514 We need only shift if these are fewer than nonzero can
8515 hold. If not, we must keep all bits set in nonzero. */
8520 + HOST_BITS_PER_WIDE_INT
8522 }
8523 else
8524 {
8527 }
8530 {
8535 }
8538 {
8539 x = simplify_shift_const
8545 }
8546 }
8548 /* If MASK is 1, convert this to an LSHIFTRT. This can be done
8549 even if the shift count isn't a constant. */
8554 shiftrt:
8556 /* If this is a zero- or sign-extension operation that just affects bits
8557 we don't care about, remove it. Be sure the call above returned
8558 something that is still a shift. */
8568 next_select);
8574 /* If the shift count is constant and we can do computations
8575 in the mode of X, compute where the bits we care about are.
8576 Otherwise, we can't do anything. Don't change the mode of
8577 the shift or propagate MODE into the shift, though. */
8580 {
8588 }
8592 /* If we just want the low-order bit, the NEG isn't needed since it
8593 won't change the low-order bit. */
8597 /* We need any bits less significant than the most significant bit in
8598 MASK since carries from those bits will affect the bits we are
8599 interested in. */
8604 /* (not FOO) is (xor FOO CONST), so if FOO is an LSHIFTRT, we can do the
8605 same as the XOR case above. Ensure that the constant we form is not
8606 wider than the mode of X. */
8614 {
8623 }
8625 /* (and (not FOO) CONST) is (not (or FOO (not CONST))), so we must
8626 use the full mask inside the NOT. */
8629 unop:
8632 next_select));
8638 /* (and (ne FOO 0) CONST) can be (and FOO CONST) if CONST is included
8639 in STORE_FLAG_VALUE and FOO has a single bit that might be nonzero,
8640 which is equal to STORE_FLAG_VALUE. */
8652 /* We have no way of knowing if the IF_THEN_ELSE can itself be
8653 written in a narrower mode. We play it safe and do not do so. */
8667 }
8669 /* Ensure we return a value of the proper mode. */
8671 }
8672 \f
8673 /* Return nonzero if X is an expression that has one of two values depending on
8674 whether some other value is zero or nonzero. In that case, we return the
8675 value that is being tested, *PTRUE is set to the value if the rtx being
8676 returned has a nonzero value, and *PFALSE is set to the other alternative.
8678 If we return zero, we set *PTRUE and *PFALSE to X. */
8680 static rtx
8682 {
8688 /* If we are comparing a value against zero, we are done. */
8691 {
8695 }
8697 /* If this is a unary operation whose operand has one of two values, apply
8698 our opcode to compute those values. */
8701 {
8706 }
8708 /* If this is a COMPARE, do nothing, since the IF_THEN_ELSE we would
8709 make can't possibly match and would suppress other optimizations. */
8711 ;
8713 /* If this is a binary operation, see if either side has only one of two
8714 values. If either one does or if both do and they are conditional on
8715 the same value, compute the new true and false values. */
8717 {
8723 {
8724 /* If if_then_else_cond returned zero, then true/false are the
8725 same rtl. We must copy one of them to prevent invalid rtl
8726 sharing. */
8733 {
8738 }
8739 else
8740 {
8743 }
8746 }
8748 /* See if we have PLUS, IOR, XOR, MINUS or UMAX, where one of the
8749 operands is zero when the other is nonzero, and vice-versa,
8750 and STORE_FLAG_VALUE is 1 or -1. */
8756 {
8773 {
8780 const_true_rtx);
8782 }
8783 }
8785 /* Similarly for MULT, AND and UMIN, except that for these the result
8786 is always zero. */
8790 {
8804 {
8807 }
8808 }
8809 }
8812 {
8813 /* If we have IF_THEN_ELSE already, extract the condition and
8814 canonicalize it if it is NE or EQ. */
8820 {
8823 }
8824 else
8826 }
8828 /* If X is a SUBREG, we can narrow both the true and false values
8829 if the inner expression, if there is a condition. */
8833 {
8839 {
8843 }
8844 }
8846 /* If X is a constant, this isn't special and will cause confusions
8847 if we treat it as such. Likewise if it is equivalent to a constant. */
8850 ;
8852 /* If we're in BImode, canonicalize on 0 and STORE_FLAG_VALUE, as that
8853 will be least confusing to the rest of the compiler. */
8855 {
8858 }
8860 /* If X is known to be either 0 or -1, those are the true and
8861 false values when testing X. */
8865 {
8868 }
8870 /* Likewise for 0 or a single bit. */
8873 {
8876 }
8878 /* Otherwise fail; show no condition with true and false values the same. */
8881 }
8882 \f
8883 /* Return the value of expression X given the fact that condition COND
8884 is known to be true when applied to REG as its first operand and VAL
8885 as its second. X is known to not be shared and so can be modified in
8886 place.
8888 We only handle the simplest cases, and specifically those cases that
8889 arise with IF_THEN_ELSE expressions. */
8891 static rtx
8893 {
8895 rtx temp;
8902 /* If either operand of the condition is a floating point value,
8903 then we have to avoid collapsing an EQ comparison. */
8913 /* If X is (abs REG) and we know something about REG's relationship
8914 with zero, we may be able to simplify this. */
8918 {
8927 }
8929 /* The only other cases we handle are MIN, MAX, and comparisons if the
8930 operands are the same as REG and VAL. */
8933 {
8938 {
8940 {
8948 else
8950 }
8953 {
8956 /* Do not reverse the condition when it is NE or EQ.
8957 This is because we cannot conclude anything about
8958 the value of 'SMAX (x, y)' when x is not equal to y,
8959 but we can when x equals y. */
8965 {
8976 }
8977 }
8978 }
8979 }
8981 {
8986 {
8987 /* We must simplify subreg here, before we lose track of the
8988 original inner_mode. */
8993 else
8995 }
8998 }
8999 /* We don't have to handle SIGN_EXTEND here, because even in the
9000 case of replacing something with a modeless CONST_INT, a
9001 CONST_INT is already (supposed to be) a valid sign extension for
9002 its narrower mode, which implies it's already properly
9003 sign-extended for the wider mode. Now, for ZERO_EXTEND, the
9004 story is different. */
9006 {
9011 {
9012 /* We must simplify the zero_extend here, before we lose
9013 track of the original inner_mode. */
9018 else
9020 }
9023 }
9027 {
9034 }
9037 }
9038 \f
9039 /* See if X and Y are equal for the purposes of seeing if we can rewrite an
9040 assignment as a field assignment. */
9042 static int
9044 {
9051 /* Check for a paradoxical SUBREG of a MEM compared with the MEM.
9052 Note that all SUBREGs of MEM are paradoxical; otherwise they
9053 would have been rewritten. */
9066 /* We used to see if get_last_value of X and Y were the same but that's
9067 not correct. In one direction, we'll cause the assignment to have
9068 the wrong destination and in the case, we'll import a register into this
9069 insn that might have already have been dead. So fail if none of the
9070 above cases are true. */
9072 }
9073 \f
9074 /* See if X, a SET operation, can be rewritten as a bit-field assignment.
9075 Return that assignment if so.
9077 We only handle the most common cases. */
9079 static rtx
9081 {
9084 rtx assign;
9086 HOST_WIDE_INT c1;
9087 HOST_WIDE_INT pos;
9089 rtx other;
9092 /* If SRC was (and (not (ashift (const_int 1) POS)) DEST), this is
9093 a clear of a one-bit field. We will have changed it to
9094 (and (rotate (const_int -2) POS) DEST), so check for that. Also check
9095 for a SUBREG. */
9101 {
9107 }
9117 {
9124 }
9126 /* If SRC is (ior (ashift (const_int 1) POS) DEST), this is a set of a
9127 one-bit field. */
9131 {
9137 }
9139 /* If DEST is already a field assignment, i.e. ZERO_EXTRACT, and the
9140 SRC is an AND with all bits of that field set, then we can discard
9141 the AND. */
9146 {
9153 else
9156 /* Complete overlap. We can remove the source AND. */
9160 /* Partial overlap. We can reduce the source AND. */
9162 {
9167 }
9168 }
9170 /* The other case we handle is assignments into a constant-position
9171 field. They look like (ior/xor (and DEST C1) OTHER). If C1 represents
9172 a mask that has all one bits except for a group of zero bits and
9173 OTHER is known to have zeros where C1 has ones, this is such an
9174 assignment. Compute the position and length from C1. Shift OTHER
9175 to the appropriate position, force it to the required mode, and
9176 make the extraction. Check for the AND in both operands. */
9192 else
9205 /* The mode to use for the source is the mode of the assignment, or of
9206 what is inside a possible STRICT_LOW_PART. */
9210 /* Shift OTHER right POS places and make it the source, restricting it
9211 to the proper length and mode. */
9216 dest);
9223 /* If SRC is masked by an AND that does not make a difference in
9224 the value being stored, strip it. */
9235 }
9236 \f
9237 /* See if X is of the form (+ (* a c) (* b c)) and convert to (* (+ a b) c)
9238 if so. */
9240 static rtx
9242 {
9246 rtx tem;
9248 /* Distributivity is not true for floating point as it can change the
9249 value. So we don't do it unless -funsafe-math-optimizations. */
9254 /* The outer operation can only be one of the following: */
9262 /* If either operand is a primitive we can't do anything, so get out
9263 fast. */
9273 /* See if the inner and outer operations distribute. */
9275 {
9280 /* These all distribute except over PLUS. */
9291 /* This is also a multiply, so it distributes over everything. */
9295 /* Non-paradoxical SUBREGs distributes over all operations,
9296 provided the inner modes and byte offsets are the same, this
9297 is an extraction of a low-order part, we don't convert an fp
9298 operation to int or vice versa, this is not a vector mode,
9299 and we would not be converting a single-word operation into a
9300 multi-word operation. The latter test is not required, but
9301 it prevents generating unneeded multi-word operations. Some
9302 of the previous tests are redundant given the latter test,
9303 but are retained because they are required for correctness.
9305 We produce the result slightly differently in this case. */
9315 /* Result might need to be truncated. Don't change mode if
9316 explicit truncation is needed. */
9327 }
9329 /* Set LHS and RHS to the inner operands (A and B in the example
9330 above) and set OTHER to the common operand (C in the example).
9331 There is only one way to do this unless the inner operation is
9332 commutative. */
9344 else
9347 /* Form the new inner operation, seeing if it simplifies first. */
9350 /* There is one exception to the general way of distributing:
9351 (a | c) ^ (b | c) -> (a ^ b) & ~c */
9353 {
9356 }
9358 /* We may be able to continuing distributing the result, so call
9359 ourselves recursively on the inner operation before forming the
9360 outer operation, which we return. */
9363 }
9365 /* See if X is of the form (* (+ A B) C), and if so convert to
9366 (+ (* A C) (* B C)) and try to simplify.
9368 Most of the time, this results in no change. However, if some of
9369 the operands are the same or inverses of each other, simplifications
9370 will result.
9372 For example, (and (ior A B) (not B)) can occur as the result of
9373 expanding a bit field assignment. When we apply the distributive
9374 law to this, we get (ior (and (A (not B))) (and (B (not B)))),
9375 which then simplifies to (and (A (not B))).
9377 Note that no checks happen on the validity of applying the inverse
9378 distributive law. This is pointless since we can do it in the
9379 few places where this routine is called.
9381 N is the index of the term that is decomposed (the arithmetic operation,
9382 i.e. (+ A B) in the first example above). !N is the index of the term that
9383 is distributed, i.e. of C in the first example above. */
9384 static rtx
9386 {
9391 /* Distributivity is not true for floating point as it can change the
9392 value. So we don't do it unless -funsafe-math-optimizations. */
9409 /* Special case (and (xor B C) (not A)), which is equivalent to
9410 (xor (ior A B) (ior A C)) */
9412 {
9415 }
9418 {
9419 /* Distribute the second term. */
9422 }
9423 else
9424 {
9425 /* Distribute the first term. */
9428 }
9438 }
9439 \f
9440 /* Simplify a logical `and' of VAROP with the constant CONSTOP, to be done
9441 in MODE. Return an equivalent form, if different from (and VAROP
9442 (const_int CONSTOP)). Otherwise, return NULL_RTX. */
9444 static rtx
9447 {
9450 rtx orig_varop;
9458 /* Simplify VAROP knowing that we will be only looking at some of the
9459 bits in it.
9461 Note by passing in CONSTOP, we guarantee that the bits not set in
9462 CONSTOP are not significant and will never be examined. We must
9463 ensure that is the case by explicitly masking out those bits
9464 before returning. */
9467 /* If VAROP is a CLOBBER, we will fail so return it. */
9471 /* If VAROP is a CONST_INT, then we need to apply the mask in CONSTOP
9472 to VAROP and return the new constant. */
9476 /* See what bits may be nonzero in VAROP. Unlike the general case of
9477 a call to nonzero_bits, here we don't care about bits outside
9478 MODE. */
9482 /* Turn off all bits in the constant that are known to already be zero.
9483 Thus, if the AND isn't needed at all, we will have CONSTOP == NONZERO_BITS
9484 which is tested below. */
9488 /* If we don't have any bits left, return zero. */
9492 /* If VAROP is a NEG of something known to be zero or 1 and CONSTOP is
9493 a power of two, we can replace this with an ASHIFT. */
9498 /* If VAROP is an IOR or XOR, apply the AND to both branches of the IOR
9499 or XOR, then try to apply the distributive law. This may eliminate
9500 operations if either branch can be simplified because of the AND.
9501 It may also make some cases more complex, but those cases probably
9502 won't match a pattern either with or without this. */
9505 return
9506 gen_lowpart
9508 apply_distributive_law
9513 constop),
9517 constop))));
9519 /* If VAROP is PLUS, and the constant is a mask of low bits, distribute
9520 the AND and see if one of the operands simplifies to zero. If so, we
9521 may eliminate it. */
9525 {
9534 }
9536 /* Make a SUBREG if necessary. If we can't make it, fail. */
9541 /* If we are only masking insignificant bits, return VAROP. */
9548 /* Otherwise, return an AND. */
9550 }
9553 /* We have X, a logical `and' of VAROP with the constant CONSTOP, to be done
9554 in MODE.
9556 Return an equivalent form, if different from X. Otherwise, return X. If
9557 X is zero, we are to always construct the equivalent form. */
9559 static rtx
9562 {
9573 }
9574 \f
9575 /* Given a REG, X, compute which bits in X can be nonzero.
9576 We don't care about bits outside of those defined in MODE.
9578 For most X this is simply GET_MODE_MASK (GET_MODE (MODE)), but if X is
9579 a shift, AND, or zero_extract, we can do better. */
9581 static rtx
9583 const_rtx known_x ATTRIBUTE_UNUSED,
9587 {
9588 rtx tem;
9591 /* If X is a register whose nonzero bits value is current, use it.
9592 Otherwise, if X is a register whose value we can find, use that
9593 value. Otherwise, use the previously-computed global nonzero bits
9594 for this register. */
9607 && !REGNO_REG_SET_P
9609 {
9612 }
9617 {
9618 #ifdef SHORT_IMMEDIATES_SIGN_EXTEND
9619 /* If X is narrower than MODE and TEM is a non-negative
9620 constant that would appear negative in the mode of X,
9621 sign-extend it for use in reg_nonzero_bits because some
9622 machines (maybe most) will actually do the sign-extension
9623 and this is the conservative approach.
9625 ??? For 2.5, try to tighten up the MD files in this regard
9626 instead of this kludge. */
9633 #endif
9635 }
9637 {
9641 /* We don't know anything about the upper bits. */
9644 }
9647 }
9649 /* Return the number of bits at the high-order end of X that are known to
9650 be equal to the sign bit. X will be used in mode MODE; if MODE is
9651 VOIDmode, X will be used in its own mode. The returned value will always
9652 be between 1 and the number of bits in MODE. */
9654 static rtx
9656 const_rtx known_x ATTRIBUTE_UNUSED,
9657 enum machine_mode known_mode
9658 ATTRIBUTE_UNUSED,
9661 {
9662 rtx tem;
9674 && !REGNO_REG_SET_P
9676 {
9679 }
9690 }
9691 \f
9692 /* Return the number of "extended" bits there are in X, when interpreted
9693 as a quantity in MODE whose signedness is indicated by UNSIGNEDP. For
9694 unsigned quantities, this is the number of high-order zero bits.
9695 For signed quantities, this is the number of copies of the sign bit
9696 minus 1. In both case, this function returns the number of "spare"
9697 bits. For example, if two quantities for which this function returns
9698 at least 1 are added, the addition is known not to overflow.
9700 This function will always return 0 unless called during combine, which
9701 implies that it must be called from a define_split. */
9703 unsigned int
9705 {
9715 }
9716 \f
9717 /* This function is called from `simplify_shift_const' to merge two
9718 outer operations. Specifically, we have already found that we need
9719 to perform operation *POP0 with constant *PCONST0 at the outermost
9720 position. We would now like to also perform OP1 with constant CONST1
9721 (with *POP0 being done last).
9723 Return 1 if we can do the operation and update *POP0 and *PCONST0 with
9724 the resulting operation. *PCOMP_P is set to 1 if we would need to
9725 complement the innermost operand, otherwise it is unchanged.
9727 MODE is the mode in which the operation will be done. No bits outside
9728 the width of this mode matter. It is assumed that the width of this mode
9729 is smaller than or equal to HOST_BITS_PER_WIDE_INT.
9731 If *POP0 or OP1 are UNKNOWN, it means no operation is required. Only NEG, PLUS,
9732 IOR, XOR, and AND are supported. We may set *POP0 to SET if the proper
9733 result is simply *PCONST0.
9735 If the resulting operation cannot be expressed as one operation, we
9736 return 0 and do not change *POP0, *PCONST0, and *PCOMP_P. */
9738 static int
9739 merge_outer_ops (enum rtx_code *pop0, HOST_WIDE_INT *pconst0, enum rtx_code op1, HOST_WIDE_INT const1, enum machine_mode mode, int *pcomp_p)
9740 {
9747 /* If OP0 is an AND, clear unimportant bits in CONST1. */
9751 /* If OP0 or OP1 is UNKNOWN, this is easy. Similarly if they are the same or
9752 if OP0 is SET. */
9761 {
9763 {
9781 }
9782 }
9784 /* Otherwise, if either is a PLUS or NEG, we can't do anything. */
9788 /* If the two constants aren't the same, we can't do anything. The
9789 remaining six cases can all be done. */
9793 else
9795 {
9798 /* (a & b) | b == b */
9801 /* (a ^ b) | b == a | b */
9802 {;}
9807 /* (a & b) ^ b == (~a) & b */
9810 /* (a | b) ^ b == a & ~b */
9816 /* (a | b) & b == b */
9819 /* (a ^ b) & b) == (~a) & b */
9824 }
9826 /* Check for NO-OP cases. */
9839 /* ??? Slightly redundant with the above mask, but not entirely.
9840 Moving this above means we'd have to sign-extend the mode mask
9841 for the final test. */
9846 }
9847 \f
9848 /* A helper to simplify_shift_const_1 to determine the mode we can perform
9849 the shift in. The original shift operation CODE is performed on OP in
9850 ORIG_MODE. Return the wider mode MODE if we can perform the operation
9851 in that mode. Return ORIG_MODE otherwise. We can also assume that the
9852 result of the shift is subject to operation OUTER_CODE with operand
9853 OUTER_CONST. */
9855 static enum machine_mode
9859 {
9864 /* In general we can't perform in wider mode for right shift and rotate. */
9866 {
9868 /* We can still widen if the bits brought in from the left are identical
9869 to the sign bit of ORIG_MODE. */
9877 /* Similarly here but with zero bits. */
9882 /* We can also widen if the bits brought in will be masked off. This
9883 operation is performed in ORIG_MODE. */
9885 {
9891 }
9892 /* fall through */
9902 }
9903 }
9905 /* Simplify a shift of VAROP by ORIG_COUNT bits. CODE says what kind
9906 of shift. The result of the shift is RESULT_MODE. Return NULL_RTX
9907 if we cannot simplify it. Otherwise, return a simplified value.
9909 The shift is normally computed in the widest mode we find in VAROP, as
9910 long as it isn't a different number of words than RESULT_MODE. Exceptions
9911 are ASHIFTRT and ROTATE, which are always done in their original mode. */
9913 static rtx
9916 {
9922 unsigned int mode_words
9924 /* We form (outer_op (code varop count) (outer_const)). */
9930 /* Make sure and truncate the "natural" shift on the way in. We don't
9931 want to do this inside the loop as it makes it more difficult to
9932 combine shifts. */
9936 /* If we were given an invalid count, don't do anything except exactly
9937 what was requested. */
9944 /* Unless one of the branches of the `if' in this loop does a `continue',
9945 we will `break' the loop after the `if'. */
9948 {
9949 /* If we have an operand of (clobber (const_int 0)), fail. */
9953 /* Convert ROTATERT to ROTATE. */
9955 {
9960 else
9962 }
9967 /* Handle cases where the count is greater than the size of the mode
9968 minus 1. For ASHIFT, use the size minus one as the count (this can
9969 occur when simplifying (lshiftrt (ashiftrt ..))). For rotates,
9970 take the count modulo the size. For other shifts, the result is
9971 zero.
9973 Since these shifts are being produced by the compiler by combining
9974 multiple operations, each of which are defined, we know what the
9975 result is supposed to be. */
9978 {
9983 else
9984 {
9985 /* We can't simply return zero because there may be an
9986 outer op. */
9990 }
9991 }
9993 /* If we discovered we had to complement VAROP, leave. Making a NOT
9994 here would cause an infinite loop. */
9998 /* An arithmetic right shift of a quantity known to be -1 or 0
9999 is a no-op. */
10003 {
10006 }
10008 /* If we are doing an arithmetic right shift and discarding all but
10009 the sign bit copies, this is equivalent to doing a shift by the
10010 bitsize minus one. Convert it into that shift because it will often
10011 allow other simplifications. */
10018 /* We simplify the tests below and elsewhere by converting
10019 ASHIFTRT to LSHIFTRT if we know the sign bit is clear.
10020 `make_compound_operation' will convert it to an ASHIFTRT for
10021 those machines (such as VAX) that don't have an LSHIFTRT. */
10038 {
10045 {
10048 }
10052 /* If we have (xshiftrt (mem ...) C) and C is MODE_WIDTH
10053 minus the width of a smaller mode, we can do this with a
10054 SIGN_EXTEND or ZERO_EXTEND from the narrower memory location. */
10060 {
10069 }
10073 /* If VAROP is a SUBREG, strip it as long as the inner operand has
10074 the same number of words as what we've seen so far. Then store
10075 the widest mode in MODE. */
10081 == mode_words
10084 {
10089 }
10093 /* Some machines use MULT instead of ASHIFT because MULT
10094 is cheaper. But it is still better on those machines to
10095 merge two shifts into one. */
10098 {
10099 varop
10105 }
10109 /* Similar, for when divides are cheaper. */
10112 {
10113 varop
10119 }
10123 /* If we are extracting just the sign bit of an arithmetic
10124 right shift, that shift is not needed. However, the sign
10125 bit of a wider mode may be different from what would be
10126 interpreted as the sign bit in a narrower mode, so, if
10127 the result is narrower, don't discard the shift. */
10132 {
10135 }
10137 /* ... fall through ... */
10142 /* Here we have two nested shifts. The result is usually the
10143 AND of a new shift with a mask. We compute the result below. */
10150 {
10154 rtx mask_rtx;
10156 /* We have one common special case. We can't do any merging if
10157 the inner code is an ASHIFTRT of a smaller mode. However, if
10158 we have (ashift:M1 (subreg:M1 (ashiftrt:M2 FOO C1) 0) C2)
10159 with C2 == GET_MODE_BITSIZE (M1) - GET_MODE_BITSIZE (M2),
10160 we can convert it to
10161 (ashiftrt:M1 (ashift:M1 (and:M1 (subreg:M1 FOO 0) C3) C2) C1).
10162 This simplifies certain SIGN_EXTEND operations. */
10166 {
10167 /* C3 has the low-order C1 bits zero. */
10179 }
10181 /* If this was (ashiftrt (ashift foo C1) C2) and FOO has more
10182 than C1 high-order bits equal to the sign bit, we can convert
10183 this to either an ASHIFT or an ASHIFTRT depending on the
10184 two counts.
10186 We cannot do this if VAROP's mode is not SHIFT_MODE. */
10192 {
10196 {
10199 }
10202 }
10204 /* There are some cases we can't do. If CODE is ASHIFTRT,
10205 we can only do this if FIRST_CODE is also ASHIFTRT.
10207 We can't do the case when CODE is ROTATE and FIRST_CODE is
10208 ASHIFTRT.
10210 If the mode of this shift is not the mode of the outer shift,
10211 we can't do this if either shift is a right shift or ROTATE.
10213 Finally, we can't do any of these if the mode is too wide
10214 unless the codes are the same.
10216 Handle the case where the shift codes are the same
10217 first. */
10220 {
10229 }
10240 /* To compute the mask to apply after the shift, shift the
10241 nonzero bits of the inner shift the same way the
10242 outer shift will. */
10246 mask_rtx
10250 /* Give up if we can't compute an outer operation to use. */
10258 /* If the shifts are in the same direction, we add the
10259 counts. Otherwise, we subtract them. */
10263 else
10266 /* If COUNT is positive, the new shift is usually CODE,
10267 except for the two exceptions below, in which case it is
10268 FIRST_CODE. If the count is negative, FIRST_CODE should
10269 always be used */
10279 }
10281 /* If we have (A << B << C) for any shift, we can convert this to
10282 (A << C << B). This wins if A is a constant. Only try this if
10283 B is not a constant. */
10288 {
10295 }
10302 /* Make this fit the case below. */
10309 /* If we have (xshiftrt (ior (plus X (const_int -1)) X) C)
10310 with C the size of VAROP - 1 and the shift is logical if
10311 STORE_FLAG_VALUE is 1 and arithmetic if STORE_FLAG_VALUE is -1,
10312 we have an (le X 0) operation. If we have an arithmetic shift
10313 and STORE_FLAG_VALUE is 1 or we have a logical shift with
10314 STORE_FLAG_VALUE of -1, we have a (neg (le X 0)) operation. */
10322 {
10325 const0_rtx);
10331 }
10333 /* If we have (shift (logical)), move the logical to the outside
10334 to allow it to possibly combine with another logical and the
10335 shift to combine with another shift. This also canonicalizes to
10336 what a ZERO_EXTRACT looks like. Also, some machines have
10337 (and (shift)) insns. */
10340 /* We can't do this if we have (ashiftrt (xor)) and the
10341 constant has its sign bit set in shift_mode. */
10344 shift_mode))
10351 {
10354 }
10356 /* If we can't do that, try to simplify the shift in each arm of the
10357 logical expression, make a new logical expression, and apply
10358 the inverse distributive law. This also can't be done
10359 for some (ashiftrt (xor)). */
10363 shift_mode)))
10364 {
10376 }
10380 /* Convert (lshiftrt (eq FOO 0) C) to (xor FOO 1) if STORE_FLAG_VALUE
10381 says that the sign bit can be tested, FOO has mode MODE, C is
10382 GET_MODE_PRECISION (MODE) - 1, and FOO has only its low-order bit
10383 that may be nonzero. */
10393 {
10397 }
10401 /* (lshiftrt (neg A) C) where A is either 0 or 1 and C is one less
10402 than the number of bits in the mode is equivalent to A. */
10406 {
10410 }
10412 /* NEG commutes with ASHIFT since it is multiplication. Move the
10413 NEG outside to allow shifts to combine. */
10417 {
10420 }
10424 /* (lshiftrt (plus A -1) C) where A is either 0 or 1 and C
10425 is one less than the number of bits in the mode is
10426 equivalent to (xor A 1). */
10433 {
10437 }
10439 /* If we have (xshiftrt (plus FOO BAR) C), and the only bits
10440 that might be nonzero in BAR are those being shifted out and those
10441 bits are known zero in FOO, we can replace the PLUS with FOO.
10442 Similarly in the other operand order. This code occurs when
10443 we are computing the size of a variable-size array. */
10450 {
10453 }
10461 result_mode)))
10462 {
10465 }
10467 /* (ashift (plus foo C) N) is (plus (ashift foo N) C'). */
10476 {
10479 }
10481 /* Check for 'PLUS signbit', which is the canonical form of 'XOR
10482 signbit', and attempt to change the PLUS to an XOR and move it to
10483 the outer operation as is done above in the AND/IOR/XOR case
10484 leg for shift(logical). See details in logical handling above
10485 for reasoning in doing so. */
10495 {
10498 }
10503 /* If we have (xshiftrt (minus (ashiftrt X C)) X) C)
10504 with C the size of VAROP - 1 and the shift is logical if
10505 STORE_FLAG_VALUE is 1 and arithmetic if STORE_FLAG_VALUE is -1,
10506 we have a (gt X 0) operation. If the shift is arithmetic with
10507 STORE_FLAG_VALUE of 1 or logical with STORE_FLAG_VALUE == -1,
10508 we have a (neg (gt X 0)) operation. */
10517 {
10520 const0_rtx);
10526 }
10530 /* Change (lshiftrt (truncate (lshiftrt))) to (truncate (lshiftrt))
10531 if the truncate does not affect the value. */
10538 {
10541 varop_inner
10544 GEN_INT
10549 }
10554 }
10557 }
10562 /* We have now finished analyzing the shift. The result should be
10563 a shift of type CODE with SHIFT_MODE shifting VAROP COUNT places. If
10564 OUTER_OP is non-UNKNOWN, it is an operation that needs to be applied
10565 to the result of the shift. OUTER_CONST is the relevant constant,
10566 but we must turn off all bits turned off in the shift. */
10574 /* Make a SUBREG if necessary. If we can't make it, fail. */
10579 /* If we have an outer operation and we just made a shift, it is
10580 possible that we could have simplified the shift were it not
10581 for the outer operation. So try to do the simplification
10582 recursively. */
10586 else
10592 /* If we were doing an LSHIFTRT in a wider mode than it was originally,
10593 turn off all the bits that the shift would have turned off. */
10598 /* Do the remainder of the processing in RESULT_MODE. */
10601 /* If COMPLEMENT_P is set, we have to complement X before doing the outer
10602 operation. */
10607 {
10615 {
10616 /* This means that we have determined that the result is
10617 equivalent to a constant. This should be rare. */
10620 }
10623 else
10626 }
10629 }
10631 /* Simplify a shift of VAROP by COUNT bits. CODE says what kind of shift.
10632 The result of the shift is RESULT_MODE. If we cannot simplify it,
10633 return X or, if it is NULL, synthesize the expression with
10634 simplify_gen_binary. Otherwise, return a simplified value.
10636 The shift is normally computed in the widest mode we find in VAROP, as
10637 long as it isn't a different number of words than RESULT_MODE. Exceptions
10638 are ASHIFTRT and ROTATE, which are always done in their original mode. */
10640 static rtx
10643 {
10653 }
10655 \f
10656 /* Like recog, but we receive the address of a pointer to a new pattern.
10657 We try to match the rtx that the pointer points to.
10658 If that fails, we may try to modify or replace the pattern,
10659 storing the replacement into the same pointer object.
10661 Modifications include deletion or addition of CLOBBERs.
10663 PNOTES is a pointer to a location where any REG_UNUSED notes added for
10664 the CLOBBERs are placed.
10666 The value is the final insn code from the pattern ultimately matched,
10667 or -1. */
10669 static int
10671 {
10679 /* If PAT is a PARALLEL, check to see if it contains the CLOBBER
10680 we use to indicate that something didn't match. If we find such a
10681 thing, force rejection. */
10695 {
10698 else
10701 }
10703 /* If it isn't, there is the possibility that we previously had an insn
10704 that clobbered some register as a side effect, but the combined
10705 insn doesn't need to do that. So try once more without the clobbers
10706 unless this represents an ASM insn. */
10710 {
10715 {
10718 pos++;
10719 }
10729 {
10732 else
10735 }
10736 }
10740 /* Recognize all noop sets, these will be killed by followup pass. */
10744 /* If we had any clobbers to add, make a new pattern than contains
10745 them. Then check to make sure that all of them are dead. */
10747 {
10757 else
10764 {
10769 {
10773 }
10774 }
10776 }
10782 }
10783 \f
10784 /* Like gen_lowpart_general but for use by combine. In combine it
10785 is not possible to create any new pseudoregs. However, it is
10786 safe to create invalid memory addresses, because combine will
10787 try to recognize them and all they will do is make the combine
10788 attempt fail.
10790 If for some reason this cannot do its job, an rtx
10791 (clobber (const_int 0)) is returned.
10792 An insn containing that will not be recognized. */
10794 static rtx
10796 {
10800 rtx result;
10805 /* We can only support MODE being wider than a word if X is a
10806 constant integer or has a mode the same size. */
10814 /* X might be a paradoxical (subreg (mem)). In that case, gen_lowpart
10815 won't know what to do. So we will strip off the SUBREG here and
10816 process normally. */
10818 {
10821 /* For use in case we fall down into the address adjustments
10822 further below, we need to adjust the known mode and size of
10823 x; imode and isize, since we just adjusted x. */
10830 }
10838 {
10841 /* Refuse to work on a volatile memory ref or one with a mode-dependent
10842 address. */
10846 /* If we want to refer to something bigger than the original memref,
10847 generate a paradoxical subreg instead. That will force a reload
10848 of the original memref X. */
10855 /* Adjust the address so that the address-after-the-data is
10856 unchanged. */
10861 }
10863 /* If X is a comparison operator, rewrite it in a new mode. This
10864 probably won't match, but may allow further simplifications. */
10868 /* If we couldn't simplify X any other way, just enclose it in a
10869 SUBREG. Normally, this SUBREG won't match, but some patterns may
10870 include an explicit SUBREG or we may simplify it further in combine. */
10871 else
10872 {
10874 rtx res;
10878 {
10883 }
10887 }
10889 fail:
10891 }
10892 \f
10893 /* Try to simplify a comparison between OP0 and a constant OP1,
10894 where CODE is the comparison code that will be tested, into a
10895 (CODE OP0 const0_rtx) form.
10897 The result is a possibly different comparison code to use.
10898 *POP1 may be updated. */
10900 static enum rtx_code
10902 {
10907 /* Get the constant we are comparing against and turn off all bits
10908 not on in our mode. */
10912 /* If we are comparing against a constant power of two and the value
10913 being compared can only have that single bit nonzero (e.g., it was
10914 `and'ed with that bit), we can replace this with a comparison
10915 with zero. */
10922 {
10925 }
10927 /* Similarly, if we are comparing a value known to be either -1 or
10928 0 with -1, change it to the opposite comparison against zero. */
10933 {
10936 }
10938 /* Do some canonicalizations based on the comparison code. We prefer
10939 comparisons against zero and then prefer equality comparisons.
10940 If we can reduce the size of a constant, we will do that too. */
10942 {
10944 /* < C is equivalent to <= (C - 1) */
10946 {
10949 /* ... fall through to LE case below. */
10950 }
10951 else
10955 /* <= C is equivalent to < (C + 1); we do this for C < 0 */
10957 {
10960 }
10962 /* If we are doing a <= 0 comparison on a value known to have
10963 a zero sign bit, we can replace this with == 0. */
10973 /* >= C is equivalent to > (C - 1). */
10975 {
10978 /* ... fall through to GT below. */
10979 }
10980 else
10984 /* > C is equivalent to >= (C + 1); we do this for C < 0. */
10986 {
10989 }
10991 /* If we are doing a > 0 comparison on a value known to have
10992 a zero sign bit, we can replace this with != 0. */
11002 /* < C is equivalent to <= (C - 1). */
11004 {
11007 /* ... fall through ... */
11008 }
11009 /* (unsigned) < 0x80000000 is equivalent to >= 0. */
11013 {
11017 }
11018 else
11022 /* unsigned <= 0 is equivalent to == 0 */
11025 /* (unsigned) <= 0x7fffffff is equivalent to >= 0. */
11029 {
11032 }
11036 /* >= C is equivalent to > (C - 1). */
11038 {
11041 /* ... fall through ... */
11042 }
11044 /* (unsigned) >= 0x80000000 is equivalent to < 0. */
11048 {
11052 }
11053 else
11057 /* unsigned > 0 is equivalent to != 0 */
11060 /* (unsigned) > 0x7fffffff is equivalent to < 0. */
11064 {
11067 }
11072 }
11076 }
11077 \f
11078 /* Simplify a comparison between *POP0 and *POP1 where CODE is the
11079 comparison code that will be tested.
11081 The result is a possibly different comparison code to use. *POP0 and
11082 *POP1 may be updated.
11084 It is possible that we might detect that a comparison is either always
11085 true or always false. However, we do not perform general constant
11086 folding in combine, so this knowledge isn't useful. Such tautologies
11087 should have been detected earlier. Hence we ignore all such cases. */
11089 static enum rtx_code
11091 {
11098 /* Try a few ways of applying the same transformation to both operands. */
11100 {
11101 #ifndef WORD_REGISTER_OPERATIONS
11102 /* The test below this one won't handle SIGN_EXTENDs on these machines,
11103 so check specially. */
11118 - (GET_MODE_PRECISION
11120 {
11123 }
11124 #endif
11126 /* If both operands are the same constant shift, see if we can ignore the
11127 shift. We can if the shift is a rotate or if the bits shifted out of
11128 this shift are known to be zero for both inputs and if the type of
11129 comparison is compatible with the shift. */
11142 {
11155 else
11157 }
11159 /* If both operands are AND's of a paradoxical SUBREG by constant, the
11160 SUBREGs are of the same mode, and, in both cases, the AND would
11161 be redundant if the comparison was done in the narrower mode,
11162 do the comparison in the narrower mode (e.g., we are AND'ing with 1
11163 and the operand's possibly nonzero bits are 0xffffff01; in that case
11164 if we only care about QImode, we don't need the AND). This case
11165 occurs if the output mode of an scc insn is not SImode and
11166 STORE_FLAG_VALUE == 1 (e.g., the 386).
11168 Similarly, check for a case where the AND's are ZERO_EXTEND
11169 operations from some narrower mode even though a SUBREG is not
11170 present. */
11175 {
11192 {
11196 /* The resulting comparison is always unsigned since we masked
11197 off the original sign bit. */
11201 }
11208 {
11214 }
11218 }
11220 /* If both operands are NOT, we can strip off the outer operation
11221 and adjust the comparison code for swapped operands; similarly for
11222 NEG, except that this must be an equality comparison. */
11228 else
11230 }
11232 /* If the first operand is a constant, swap the operands and adjust the
11233 comparison code appropriately, but don't do this if the second operand
11234 is already a constant integer. */
11236 {
11239 }
11241 /* We now enter a loop during which we will try to simplify the comparison.
11242 For the most part, we only are concerned with comparisons with zero,
11243 but some things may really be comparisons with zero but not start
11244 out looking that way. */
11247 {
11254 HOST_WIDE_INT const_op;
11256 /* We only want to handle integral modes. This catches VOIDmode,
11257 CCmode, and the floating-point modes. An exception is that we
11258 can handle VOIDmode if OP0 is a COMPARE or a comparison
11259 operation. */
11266 /* Try to simplify the compare to constant, possibly changing the
11267 comparison op, and/or changing op1 to zero. */
11271 /* Compute some predicates to simplify code below. */
11278 /* If this is a sign bit comparison and we can do arithmetic in
11279 MODE, say that we will only be needing the sign bit of OP0. */
11286 /* Now try cases based on the opcode of OP0. If none of the cases
11287 does a "continue", we exit this loop immediately after the
11288 switch. */
11291 {
11293 /* If we are extracting a single bit from a variable position in
11294 a constant that has only a single bit set and are comparing it
11295 with zero, we can convert this into an equality comparison
11296 between the position and the location of the single bit. */
11297 /* Except we can't if SHIFT_COUNT_TRUNCATED is set, since we might
11298 have already reduced the shift count modulo the word size. */
11304 {
11306 {
11307 enum machine_mode new_mode
11311 else
11312 {
11315 }
11316 }
11322 /* Result is nonzero iff shift count is equal to I. */
11325 }
11327 /* ... fall through ... */
11332 {
11335 }
11339 /* If testing for equality, we can take the NOT of the constant. */
11342 {
11346 }
11348 /* If just looking at the sign bit, reverse the sense of the
11349 comparison. */
11351 {
11355 }
11359 /* If testing for equality, we can take the NEG of the constant. */
11362 {
11366 }
11368 /* The remaining cases only apply to comparisons with zero. */
11372 /* When X is ABS or is known positive,
11373 (neg X) is < 0 if and only if X != 0. */
11381 {
11385 }
11387 /* If we have NEG of something whose two high-order bits are the
11388 same, we know that "(-a) < 0" is equivalent to "a > 0". */
11390 {
11394 }
11398 /* If we are testing equality and our count is a constant, we
11399 can perform the inverse operation on our RHS. */
11403 {
11407 }
11409 /* If we are doing a < 0 or >= 0 comparison, it means we are testing
11410 a particular bit. Convert it to an AND of a constant of that
11411 bit. This will be converted into a ZERO_EXTRACT. */
11415 {
11422 }
11424 /* Fall through. */
11427 /* ABS is ignorable inside an equality comparison with zero. */
11429 {
11432 }
11436 /* Can simplify (compare (zero/sign_extend FOO) CONST) to
11437 (compare FOO CONST) if CONST fits in FOO's mode and we
11438 are either testing inequality or have an unsigned
11439 comparison with ZERO_EXTEND or a signed comparison with
11440 SIGN_EXTEND. But don't do it if we don't have a compare
11441 insn of the given mode, since we'd have to revert it
11442 later on, and then we wouldn't know whether to sign- or
11443 zero-extend. */
11446 && ! unsigned_comparison_p
11450 {
11453 }
11457 /* Check for the case where we are comparing A - C1 with C2, that is
11459 (subreg:MODE (plus (A) (-C1))) op (C2)
11461 with C1 a constant, and try to lift the SUBREG, i.e. to do the
11462 comparison in the wider mode. One of the following two conditions
11463 must be true in order for this to be valid:
11465 1. The mode extension results in the same bit pattern being added
11466 on both sides and the comparison is equality or unsigned. As
11467 C2 has been truncated to fit in MODE, the pattern can only be
11468 all 0s or all 1s.
11470 2. The mode extension results in the sign bit being copied on
11471 each side.
11473 The difficulty here is that we have predicates for A but not for
11474 (A - C1) so we need to check that C1 is within proper bounds so
11475 as to perturbate A as little as possible. */
11482 {
11491 /* (A - C1) zero-extends if it is positive and sign-extends
11492 if it is negative, C2 both zero- and sign-extends. */
11496 /* (A - C1) sign-extends if it is positive and 1-extends
11497 if it is negative, C2 both sign- and 1-extends. */
11504 /* (A - C1) always sign-extends, like C2. */
11508 {
11511 }
11512 }
11514 /* If the inner mode is narrower and we are extracting the low part,
11515 we can treat the SUBREG as if it were a ZERO_EXTEND. */
11519 else
11522 /* ... fall through ... */
11532 {
11535 }
11539 /* (eq (plus X A) B) -> (eq X (minus B A)). We can only do
11540 this for equality comparisons due to pathological cases involving
11541 overflows. */
11545 {
11549 }
11551 /* (plus (abs X) (const_int -1)) is < 0 if and only if X == 0. */
11554 {
11558 }
11562 /* We used to optimize signed comparisons against zero, but that
11563 was incorrect. Unsigned comparisons against zero (GTU, LEU)
11564 arrive here as equality comparisons, or (GEU, LTU) are
11565 optimized away. No need to special-case them. */
11567 /* (eq (minus A B) C) -> (eq A (plus B C)) or
11568 (eq B (minus A C)), whichever simplifies. We can only do
11569 this for equality comparisons due to pathological cases involving
11570 overflows. */
11574 {
11578 }
11583 {
11587 }
11589 /* The sign bit of (minus (ashiftrt X C) X), where C is the number
11590 of bits in X minus 1, is one iff X > 0. */
11595 {
11599 }
11603 /* (eq (xor A B) C) -> (eq A (xor B C)). This is a simplification
11604 if C is zero or B is a constant. */
11608 {
11612 }
11620 /* We can't do anything if OP0 is a condition code value, rather
11621 than an actual data value. */
11627 /* Get the two operands being compared. */
11630 else
11633 /* Check for the cases where we simply want the result of the
11634 earlier test or the opposite of that result. */
11638 {
11642 else
11646 {
11651 }
11652 }
11656 /* The sign bit of (ior (plus X (const_int -1)) X) is nonzero
11657 iff X <= 0. */
11661 {
11665 }
11669 /* Convert (and (xshift 1 X) Y) to (and (lshiftrt Y X) 1). This
11670 will be converted to a ZERO_EXTRACT later. */
11674 {
11679 }
11681 /* If we are comparing (and (lshiftrt X C1) C2) for equality with
11682 zero and X is a comparison and C1 and C2 describe only bits set
11683 in STORE_FLAG_VALUE, we can compare with X. */
11691 {
11698 {
11701 }
11702 }
11704 /* If we are doing an equality comparison of an AND of a bit equal
11705 to the sign bit, replace this with a LT or GE comparison of
11706 the underlying value. */
11713 {
11717 }
11719 /* If this AND operation is really a ZERO_EXTEND from a narrower
11720 mode, the constant fits within that mode, and this is either an
11721 equality or unsigned comparison, try to do this comparison in
11722 the narrower mode.
11724 Note that in:
11726 (ne:DI (and:DI (reg:DI 4) (const_int 0xffffffff)) (const_int 0))
11727 -> (ne:DI (reg:SI 4) (const_int 0))
11729 unless TRULY_NOOP_TRUNCATION allows it or the register is
11730 known to hold a value of the required mode the
11731 transformation is invalid. */
11742 {
11745 }
11747 /* If this is (and:M1 (subreg:M2 X 0) (const_int C1)) where C1
11748 fits in both M1 and M2 and the SUBREG is either paradoxical
11749 or represents the low part, permute the SUBREG and the AND
11750 and try again. */
11752 {
11755 /* Require an integral mode, to avoid creating something like
11756 (AND:SF ...). */
11758 /* It is unsafe to commute the AND into the SUBREG if the
11759 SUBREG is paradoxical and WORD_REGISTER_OPERATIONS is
11760 not defined. As originally written the upper bits
11761 have a defined value due to the AND operation.
11762 However, if we commute the AND inside the SUBREG then
11763 they no longer have defined values and the meaning of
11764 the code has been changed. */
11766 #ifdef WORD_REGISTER_OPERATIONS
11769 #endif
11779 {
11785 }
11786 }
11788 /* Convert (ne (and (not X) 1) 0) to (eq (and X 1) 0). */
11792 {
11797 }
11799 /* Convert (ne (and (lshiftrt (not X)) 1) 0) to
11800 (eq (and (lshiftrt X) 1) 0).
11801 Also handle the case where (not X) is expressed using xor. */
11805 {
11817 {
11818 op0
11823 }
11824 }
11828 /* If we have (compare (ashift FOO N) (const_int C)) and
11829 the high order N bits of FOO (N+1 if an inequality comparison)
11830 are known to be zero, we can do this by comparing FOO with C
11831 shifted right N bits so long as the low-order N bits of C are
11832 zero. */
11844 {
11845 /* We must perform a logical shift, not an arithmetic one,
11846 as we want the top N bits of C to be zero. */
11853 }
11855 /* If we are doing a sign bit comparison, it means we are testing
11856 a particular bit. Convert it to the appropriate AND. */
11859 {
11866 }
11868 /* If this an equality comparison with zero and we are shifting
11869 the low bit to the sign bit, we can convert this to an AND of the
11870 low-order bit. */
11874 {
11877 }
11881 /* If this is an equality comparison with zero, we can do this
11882 as a logical shift, which might be much simpler. */
11885 {
11890 }
11892 /* If OP0 is a sign extension and CODE is not an unsigned comparison,
11893 do the comparison in a narrower mode. */
11903 {
11906 }
11908 /* Likewise if OP0 is a PLUS of a sign extension with a
11909 constant, which is usually represented with the PLUS
11910 between the shifts. */
11922 {
11930 new_const);
11932 }
11934 /* ... fall through ... */
11936 /* If we have (compare (xshiftrt FOO N) (const_int C)) and
11937 the low order N bits of FOO are known to be zero, we can do this
11938 by comparing FOO with C shifted left N bits so long as no
11939 overflow occurs. Even if the low order N bits of FOO aren't known
11940 to be zero, if the comparison is >= or < we can use the same
11941 optimization and for > or <= by setting all the low
11942 order N bits in the comparison constant. */
11953 {
11954 unsigned HOST_WIDE_INT low_bits
11959 {
11960 /* If the shift was logical, then we must make the condition
11961 unsigned. */
11969 const_op
11974 }
11975 }
11977 /* If we are using this shift to extract just the sign bit, we
11978 can replace this with an LT or GE comparison. */
11983 {
11987 }
11992 }
11995 }
11997 /* Now make any compound operations involved in this comparison. Then,
11998 check for an outmost SUBREG on OP0 that is not doing anything or is
11999 paradoxical. The latter transformation must only be performed when
12000 it is known that the "extra" bits will be the same in op0 and op1 or
12001 that they don't matter. There are three cases to consider:
12003 1. SUBREG_REG (op0) is a register. In this case the bits are don't
12004 care bits and we can assume they have any convenient value. So
12005 making the transformation is safe.
12007 2. SUBREG_REG (op0) is a memory and LOAD_EXTEND_OP is not defined.
12008 In this case the upper bits of op0 are undefined. We should not make
12009 the simplification in that case as we do not know the contents of
12010 those bits.
12012 3. SUBREG_REG (op0) is a memory and LOAD_EXTEND_OP is defined and not
12013 UNKNOWN. In that case we know those bits are zeros or ones. We must
12014 also be sure that they are the same as the upper bits of op1.
12016 We can never remove a SUBREG for a non-equality comparison because
12017 the sign bit is in a different place in the underlying object. */
12026 {
12028 {
12029 /* For paradoxical subregs, allow case 1 as above. Case 3 isn't
12030 implemented. */
12032 {
12035 }
12036 }
12042 {
12048 }
12049 }
12051 /* We now do the opposite procedure: Some machines don't have compare
12052 insns in all modes. If OP0's mode is an integer mode smaller than a
12053 word and we can't do a compare in that mode, see if there is a larger
12054 mode for which we can do the compare. There are a number of cases in
12055 which we can use the wider mode. */
12065 {
12068 /* If this is a test for negative, we can make an explicit
12069 test of the sign bit. Test this first so we can use
12070 a paradoxical subreg to extend OP0. */
12074 {
12082 }
12084 /* If the only nonzero bits in OP0 and OP1 are those in the
12085 narrower mode and this is an equality or unsigned comparison,
12086 we can use the wider mode. Similarly for sign-extended
12087 values, in which case it is true for all comparisons. */
12104 {
12105 /* If OP0 is an AND and we don't have an AND in MODE either,
12106 make a new AND in the proper mode. */
12114 else
12115 {
12117 {
12120 }
12121 else
12122 {
12125 }
12127 }
12128 }
12129 }
12131 #ifdef CANONICALIZE_COMPARISON
12132 /* If this machine only supports a subset of valid comparisons, see if we
12133 can convert an unsupported one into a supported one. */
12135 #endif
12141 }
12142 \f
12143 /* Utility function for record_value_for_reg. Count number of
12144 rtxs in X. */
12145 static int
12147 {
12154 {
12174 }
12185 }
12186 \f
12187 /* Utility function for following routine. Called when X is part of a value
12188 being stored into last_set_value. Sets last_set_table_tick
12189 for each register mentioned. Similar to mention_regs in cse.c */
12191 static void
12193 {
12199 {
12205 {
12208 }
12211 }
12215 {
12216 /* Check for identical subexpressions. If x contains
12217 identical subexpression we only have to traverse one of
12218 them. */
12220 {
12221 /* Note that at this point x1 has already been
12222 processed. */
12226 /* If x0 and x1 are identical then there is no need to
12227 process x0. */
12231 /* If x0 is identical to a subexpression of x1 then while
12232 processing x1, x0 has already been processed. Thus we
12233 are done with x. */
12238 /* If x1 is identical to a subexpression of x0 then we
12239 still have to process the rest of x0. */
12242 {
12245 }
12246 }
12249 }
12253 }
12255 /* Record that REG is set to VALUE in insn INSN. If VALUE is zero, we
12256 are saying that the register is clobbered and we no longer know its
12257 value. If INSN is zero, don't update reg_stat[].last_set; this is
12258 only permitted with VALUE also zero and is used to invalidate the
12259 register. */
12261 static void
12263 {
12269 /* If VALUE contains REG and we have a previous value for REG, substitute
12270 the previous value. */
12272 {
12273 rtx tem;
12275 /* Set things up so get_last_value is allowed to see anything set up to
12276 our insn. */
12280 /* If TEM is simply a binary operation with two CLOBBERs as operands,
12281 it isn't going to be useful and will take a lot of time to process,
12282 so just use the CLOBBER. */
12285 {
12291 {
12292 /* If there are two or more occurrences of REG in VALUE,
12293 prevent the value from growing too much. */
12296 }
12299 }
12300 }
12302 /* For each register modified, show we don't know its value, that
12303 we don't know about its bitwise content, that its value has been
12304 updated, and that we don't know the location of the death of the
12305 register. */
12307 {
12319 }
12321 /* Mark registers that are being referenced in this value. */
12325 /* Now update the status of each register being set.
12326 If someone is using this register in this block, set this register
12327 to invalid since we will get confused between the two lives in this
12328 basic block. This makes using this register always invalid. In cse, we
12329 scan the table to invalidate all entries using this register, but this
12330 is too much work for us. */
12333 {
12339 else
12341 }
12343 /* The value being assigned might refer to X (like in "x++;"). In that
12344 case, we must replace it with (clobber (const_int 0)) to prevent
12345 infinite loops. */
12348 {
12352 }
12354 /* For the main register being modified, update the value, the mode, the
12355 nonzero bits, and the number of sign bit copies. */
12360 {
12368 rsp->last_set_sign_bit_copies
12370 }
12371 }
12373 /* Called via note_stores from record_dead_and_set_regs to handle one
12374 SET or CLOBBER in an insn. DATA is the instruction in which the
12375 set is occurring. */
12377 static void
12379 {
12386 {
12390 }
12393 {
12394 /* If we are setting the whole register, we know its value. Otherwise
12395 show that we don't know the value. We can handle SUBREG in
12396 some cases. */
12407 else
12409 }
12411 /* Ignore pushes, they clobber nothing. */
12414 }
12416 /* Update the records of when each REG was most recently set or killed
12417 for the things done by INSN. This is the last thing done in processing
12418 INSN in the combiner loop.
12420 We update reg_stat[], in particular fields last_set, last_set_value,
12421 last_set_mode, last_set_nonzero_bits, last_set_sign_bit_copies,
12422 last_death, and also the similar information mem_last_set (which insn
12423 most recently modified memory) and last_call_luid (which insn was the
12424 most recent subroutine call). */
12426 static void
12428 {
12429 rtx link;
12433 {
12436 {
12441 {
12446 }
12447 }
12450 }
12453 {
12456 {
12468 }
12472 /* We can't combine into a call pattern. Remember, though, that
12473 the return value register is set at this LUID. We could
12474 still replace a register with the return value from the
12475 wrong subroutine call! */
12477 }
12478 else
12480 }
12482 /* If a SUBREG has the promoted bit set, it is in fact a property of the
12483 register present in the SUBREG, so for each such SUBREG go back and
12484 adjust nonzero and sign bit information of the registers that are
12485 known to have some zero/sign bits set.
12487 This is needed because when combine blows the SUBREGs away, the
12488 information on zero/sign bits is lost and further combines can be
12489 missed because of that. */
12491 static void
12493 {
12495 rtx set;
12503 {
12512 {
12515 }
12519 {
12522 }
12525 {
12528 }
12529 else
12531 }
12532 }
12534 /* Check if X, a register, is known to contain a value already
12535 truncated to MODE. In this case we can use a subreg to refer to
12536 the truncated value even though in the generic case we would need
12537 an explicit truncation. */
12539 static bool
12541 {
12553 }
12555 /* Callback for for_each_rtx. If *P is a hard reg or a subreg record the mode
12556 that the register is accessed in. For non-TRULY_NOOP_TRUNCATION targets we
12557 might be able to turn a truncate into a subreg using this information.
12558 Return -1 if traversing *P is complete or 0 otherwise. */
12560 static int
12562 {
12568 {
12579 }
12580 /* ??? For hard-regs we now record everything. We might be able to
12581 optimize this using last_set_mode. */
12584 else
12592 {
12595 }
12598 }
12600 /* Callback for note_uses. Find hardregs and subregs of pseudos and
12601 the modes they are used in. This can help truning TRUNCATEs into
12602 SUBREGs. */
12604 static void
12606 {
12608 }
12610 /* Scan X for promoted SUBREGs. For each one found,
12611 note what it implies to the registers used in it. */
12613 static void
12615 {
12620 else
12621 {
12627 {
12637 }
12638 }
12639 }
12640 \f
12641 /* Verify that all the registers and memory references mentioned in *LOC are
12642 still valid. *LOC was part of a value set in INSN when label_tick was
12643 equal to TICK. Return 0 if some are not. If REPLACE is nonzero, replace
12644 the invalid references with (clobber (const_int 0)) and return 1. This
12645 replacement is useful because we often can get useful information about
12646 the form of a value (e.g., if it was produced by a shift that always
12647 produces -1 or 0) even though we don't know exactly what registers it
12648 was produced from. */
12650 static int
12652 {
12659 {
12665 {
12668 /* If this is a pseudo-register that was only set once and not
12669 live at the beginning of the function, it is always valid. */
12672 && (!REGNO_REG_SET_P
12675 {
12679 }
12680 }
12683 }
12684 /* If this is a memory reference, make sure that there were no stores after
12685 it that might have clobbered the value. We don't have alias info, so we
12686 assume any store invalidates it. Moreover, we only have local UIDs, so
12687 we also assume that there were stores in the intervening basic blocks. */
12690 {
12694 }
12697 {
12699 {
12700 /* Check for identical subexpressions. If x contains
12701 identical subexpression we only have to traverse one of
12702 them. */
12704 {
12705 /* Note that at this point x0 has already been checked
12706 and found valid. */
12710 /* If x0 and x1 are identical then x is also valid. */
12714 /* If x1 is identical to a subexpression of x0 then
12715 while checking x0, x1 has already been checked. Thus
12716 it is valid and so as x. */
12721 /* If x0 is identical to a subexpression of x1 then x is
12722 valid iff the rest of x1 is valid. */
12725 return
12729 }
12734 }
12740 }
12742 /* If we haven't found a reason for it to be invalid, it is valid. */
12744 }
12746 /* Get the last value assigned to X, if known. Some registers
12747 in the value may be replaced with (clobber (const_int 0)) if their value
12748 is known longer known reliably. */
12750 static rtx
12752 {
12754 rtx value;
12757 /* If this is a non-paradoxical SUBREG, get the value of its operand and
12758 then convert it to the desired mode. If this is a paradoxical SUBREG,
12759 we cannot predict what values the "extra" bits might have. */
12773 /* If we don't have a value, or if it isn't for this basic block and
12774 it's either a hard register, set more than once, or it's a live
12775 at the beginning of the function, return 0.
12777 Because if it's not live at the beginning of the function then the reg
12778 is always set before being used (is never used without being set).
12779 And, if it's set only once, and it's always set before use, then all
12780 uses must have the same last value, even if it's not from this basic
12781 block. */
12787 || REGNO_REG_SET_P
12791 /* If the value was set in a later insn than the ones we are processing,
12792 we can't use it even if the register was only set once. */
12797 /* If the value has all its registers valid, return it. */
12801 /* Otherwise, make a copy and replace any invalid register with
12802 (clobber (const_int 0)). If that fails for some reason, return 0. */
12809 }
12810 \f
12811 /* Return nonzero if expression X refers to a REG or to memory
12812 that is set in an instruction more recent than FROM_LUID. */
12814 static int
12816 {
12822 {
12826 #ifdef PUSH_ROUNDING
12827 /* Don't allow uses of the stack pointer to be moved,
12828 because we don't know whether the move crosses a push insn. */
12831 #endif
12833 {
12839 }
12841 }
12849 {
12851 {
12856 }
12860 }
12862 }
12863 \f
12864 /* Define three variables used for communication between the following
12865 routines. */
12870 /* Function called via note_stores from reg_dead_at_p.
12872 If DEST is within [reg_dead_regno, reg_dead_endregno), set
12873 reg_dead_flag to 1 if X is a CLOBBER and to -1 it is a SET. */
12875 static void
12877 {
12887 }
12889 /* Return nonzero if REG is known to be dead at INSN.
12891 We scan backwards from INSN. If we hit a REG_DEAD note or a CLOBBER
12892 referencing REG, it is dead. If we hit a SET referencing REG, it is
12893 live. Otherwise, see if it is live or dead at the start of the basic
12894 block we are in. Hard regs marked as being live in NEWPAT_USED_REGS
12895 must be assumed to be always live. */
12897 static int
12899 {
12900 basic_block block;
12903 /* Set variables for reg_dead_at_p_1. */
12909 /* Check that reg isn't mentioned in NEWPAT_USED_REGS. For fixed registers
12910 we allow the machine description to decide whether use-and-clobber
12911 patterns are OK. */
12913 {
12917 }
12919 /* Scan backwards until we find a REG_DEAD note, SET, CLOBBER, or
12920 beginning of basic block. */
12923 {
12925 {
12932 }
12938 }
12940 /* Look at live-in sets for the basic block that we were in. */
12946 }
12947 \f
12948 /* Note hard registers in X that are used. */
12950 static void
12952 {
12958 {
12969 #ifdef HAVE_cc0
12970 /* CC0 must die in the insn after it is set, so we don't need to take
12971 special note of it here. */
12973 #endif
12977 /* If we are clobbering a MEM, mark any hard registers inside the
12978 address as used. */
12985 /* A hard reg in a wide mode may really be multiple registers.
12986 If so, mark all of them just like the first. */
12988 {
12989 /* None of this applies to the stack, frame or arg pointers. */
12991 #if !HARD_FRAME_POINTER_IS_FRAME_POINTER
12993 #endif
12994 #if FRAME_POINTER_REGNUM != ARG_POINTER_REGNUM
12996 #endif
13001 }
13005 {
13006 /* If setting a MEM, or a SUBREG of a MEM, then note any hard regs in
13007 the address. */
13019 }
13024 }
13026 /* Recursively scan the operands of this expression. */
13028 {
13032 {
13036 {
13041 }
13042 }
13043 }
13044 }
13045 \f
13046 /* Remove register number REGNO from the dead registers list of INSN.
13048 Return the note used to record the death, if there was one. */
13050 rtx
13052 {
13059 }
13061 /* For each register (hardware or pseudo) used within expression X, if its
13062 death is in an instruction with luid between FROM_LUID (inclusive) and
13063 TO_INSN (exclusive), put a REG_DEAD note for that register in the
13064 list headed by PNOTES.
13066 That said, don't move registers killed by maybe_kill_insn.
13068 This is done when X is being merged by combination into TO_INSN. These
13069 notes will then be distributed as needed. */
13071 static void
13074 {
13080 {
13084 /* Don't move the register if it gets killed in between from and to. */
13093 {
13096 /* It is possible for the call above to return 0. This can occur
13097 when last_death points to I2 or I1 that we combined with.
13098 In that case make a new note.
13100 We must also check for the case where X is a hard register
13101 and NOTE is a death note for a range of hard registers
13102 including X. In that case, we must put REG_DEAD notes for
13103 the remaining registers in place of NOTE. */
13108 {
13117 }
13119 /* If we didn't find any note, or if we found a REG_DEAD note that
13120 covers only part of the given reg, and we have a multi-reg hard
13121 register, then to be safe we must check for REG_DEAD notes
13122 for each register other than the first. They could have
13123 their own REG_DEAD notes lying around. */
13130 {
13137 else
13143 }
13146 {
13149 }
13150 else
13152 }
13155 }
13158 {
13163 /* In the case of a ZERO_EXTRACT, a STRICT_LOW_PART, or a SUBREG
13164 that accesses one word of a multi-word item, some
13165 piece of everything register in the expression is used by
13166 this insn, so remove any old death. */
13167 /* ??? So why do we test for equality of the sizes? */
13176 {
13179 }
13181 /* If this is some other SUBREG, we know it replaces the entire
13182 value, so use that as the destination. */
13186 /* If this is a MEM, adjust deaths of anything used in the address.
13187 For a REG (the only other possibility), the entire value is
13188 being replaced so the old value is not used in this insn. */
13194 }
13203 {
13205 {
13210 }
13213 }
13214 }
13215 \f
13216 /* Return 1 if X is the target of a bit-field assignment in BODY, the
13217 pattern of an insn. X must be a REG. */
13219 static int
13221 {
13225 {
13227 rtx target;
13234 else
13251 }
13259 }
13260 \f
13261 /* Given a chain of REG_NOTES originally from FROM_INSN, try to place them
13262 as appropriate. I3 and I2 are the insns resulting from the combination
13263 insns including FROM (I2 may be zero).
13265 ELIM_I2 and ELIM_I1 are either zero or registers that we know will
13266 not need REG_DEAD notes because they are being substituted for. This
13267 saves searching in the most common cases.
13269 Each note in the list is either ignored or placed on some insns, depending
13270 on the type of note. */
13272 static void
13275 {
13277 rtx tem;
13280 {
13285 {
13288 /* Doesn't matter much where we put this, as long as it's somewhere.
13289 It is preferable to keep these notes on branches, which is most
13290 likely to be i3. */
13297 else
13298 {
13301 }
13305 /* These notes must remain with the call or trapping instruction. */
13310 else
13311 {
13317 /* ??? Otherwise assume we've combined things such that we
13318 can now prove that the instructions can't trap. Drop the
13319 note in this case. */
13320 }
13324 /* ??? How to distribute between i3-i1. Assume i3 contains the
13325 entire adjustment. Assert i3 contains at least some adjust. */
13327 {
13329 /* fixup_args_size_notes looks at REG_NORETURN note,
13330 so ensure the note is placed there first. */
13332 {
13336 {
13342 }
13343 }
13345 /* emit_call_1 adds for !ACCUMULATE_OUTGOING_ARGS
13346 REG_ARGS_SIZE note to all noreturn calls, allow that here. */
13349 && !ACCUMULATE_OUTGOING_ARGS
13351 }
13357 /* These notes must remain with the call. It should not be
13358 possible for both I2 and I3 to be a call. */
13361 else
13362 {
13365 }
13369 /* Any clobbers for i3 may still exist, and so we must process
13370 REG_UNUSED notes from that insn.
13372 Any clobbers from i2 or i1 can only exist if they were added by
13373 recog_for_combine. In that case, recog_for_combine created the
13374 necessary REG_UNUSED notes. Trying to keep any original
13375 REG_UNUSED notes from these insns can cause incorrect output
13376 if it is for the same register as the original i3 dest.
13377 In that case, we will notice that the register is set in i3,
13378 and then add a REG_UNUSED note for the destination of i3, which
13379 is wrong. However, it is possible to have REG_UNUSED notes from
13380 i2 or i1 for register which were both used and clobbered, so
13381 we keep notes from i2 or i1 if they will turn into REG_DEAD
13382 notes. */
13384 /* If this register is set or clobbered in I3, put the note there
13385 unless there is one already. */
13387 {
13395 }
13396 /* Otherwise, if this register is used by I3, then this register
13397 now dies here, so we must put a REG_DEAD note here unless there
13398 is one already. */
13404 {
13407 }
13413 /* These notes say something about results of an insn. We can
13414 only support them if they used to be on I3 in which case they
13415 remain on I3. Otherwise they are ignored.
13417 If the note refers to an expression that is not a constant, we
13418 must also ignore the note since we cannot tell whether the
13419 equivalence is still true. It might be possible to do
13420 slightly better than this (we only have a problem if I2DEST
13421 or I1DEST is present in the expression), but it doesn't
13422 seem worth the trouble. */
13430 /* These notes say something about how a register is used. They must
13431 be present on any use of the register in I2 or I3. */
13436 {
13439 else
13441 }
13446 /* This can show up in several ways -- either directly in the
13447 pattern, or hidden off in the constant pool with (or without?)
13448 a REG_EQUAL note. */
13449 /* ??? Ignore the without-reg_equal-note problem for now. */
13461 {
13464 else
13466 }
13468 /* For REG_LABEL_TARGET on a JUMP_P, we prefer to put the note
13469 as a JUMP_LABEL or decrement LABEL_NUSES if it's already
13470 there. */
13475 {
13482 }
13488 {
13496 }
13500 /* This note says something about the value of a register prior
13501 to the execution of an insn. It is too much trouble to see
13502 if the note is still correct in all situations. It is better
13503 to simply delete it. */
13507 /* If we replaced the right hand side of FROM_INSN with a
13508 REG_EQUAL note, the original use of the dying register
13509 will not have been combined into I3 and I2. In such cases,
13510 FROM_INSN is guaranteed to be the first of the combined
13511 instructions, so we simply need to search back before
13512 FROM_INSN for the previous use or set of this register,
13513 then alter the notes there appropriately.
13515 If the register is used as an input in I3, it dies there.
13516 Similarly for I2, if it is nonzero and adjacent to I3.
13518 If the register is not used as an input in either I3 or I2
13519 and it is not one of the registers we were supposed to eliminate,
13520 there are two possibilities. We might have a non-adjacent I2
13521 or we might have somehow eliminated an additional register
13522 from a computation. For example, we might have had A & B where
13523 we discover that B will always be zero. In this case we will
13524 eliminate the reference to A.
13526 In both cases, we must search to see if we can find a previous
13527 use of A and put the death note there. */
13533 else
13534 {
13545 && !(i2mod
13547 i2mod_old_rhs)))
13552 }
13555 {
13559 {
13561 {
13565 }
13567 /* If the register is being set at TEM, see if that is all
13568 TEM is doing. If so, delete TEM. Otherwise, make this
13569 into a REG_UNUSED note instead. Don't delete sets to
13570 global register vars. */
13574 {
13577 #ifdef HAVE_cc0
13579 #endif
13587 ;
13589 /* Verify that it was the set, and not a clobber that
13590 modified the register.
13592 CC0 targets must be careful to maintain setter/user
13593 pairs. If we cannot delete the setter due to side
13594 effects, mark the user with an UNUSED note instead
13595 of deleting it. */
13599 #ifdef HAVE_cc0
13603 #endif
13604 )
13605 {
13606 /* Move the notes and links of TEM elsewhere.
13607 This might delete other dead insns recursively.
13608 First set the pattern to something that won't use
13609 any register. */
13623 #ifdef HAVE_cc0
13624 /* Delete the setter too. */
13626 {
13639 }
13640 #endif
13641 }
13642 else
13643 {
13646 /* If there isn't already a REG_UNUSED note, put one
13647 here. Do not place a REG_DEAD note, even if
13648 the register is also used here; that would not
13649 match the algorithm used in lifetime analysis
13650 and can cause the consistency check in the
13651 scheduler to fail. */
13656 }
13657 }
13661 {
13664 /* If we are doing a 3->2 combination, and we have a
13665 register which formerly died in i3 and was not used
13666 by i2, which now no longer dies in i3 and is used in
13667 i2 but does not die in i2, and place is between i2
13668 and i3, then we may need to move a link from place to
13669 i2. */
13671 && from_insn
13674 {
13678 }
13680 }
13684 }
13686 }
13688 /* If the register is set or already dead at PLACE, we needn't do
13689 anything with this note if it is still a REG_DEAD note.
13690 We check here if it is set at all, not if is it totally replaced,
13691 which is what `dead_or_set_p' checks, so also check for it being
13692 set partially. */
13695 {
13701 {
13702 /* Unless the register previously died in PLACE, clear
13703 last_death. [I no longer understand why this is
13704 being done.] */
13708 }
13709 else
13712 /* If this is a death note for a hard reg that is occupying
13713 multiple registers, ensure that we are still using all
13714 parts of the object. If we find a piece of the object
13715 that is unused, we must arrange for an appropriate REG_DEAD
13716 note to be added for it. However, we can't just emit a USE
13717 and tag the note to it, since the register might actually
13718 be dead; so we recourse, and the recursive call then finds
13719 the previous insn that used this register. */
13723 {
13735 {
13736 /* Put only REG_DEAD notes for pieces that are
13737 not already dead or set. */
13741 {
13748 {
13750 NULL_RTX);
13754 NULL_RTX);
13755 }
13761 {
13763 {
13767 }
13771 {
13774 }
13775 }
13777 }
13780 }
13781 }
13782 }
13786 /* Any other notes should not be present at this point in the
13787 compilation. */
13789 }
13792 {
13795 }
13799 }
13800 }
13801 \f
13802 /* Similarly to above, distribute the LOG_LINKS that used to be present on
13803 I3, I2, and I1 to new locations. This is also called to add a link
13804 pointing at I3 when I3's destination is changed. */
13806 static void
13808 {
13812 {
13814 rtx insn;
13819 /* If the insn that this link points to is a NOTE or isn't a single
13820 set, ignore it. In the latter case, it isn't clear what we
13821 can do other than ignore the link, since we can't tell which
13822 register it was for. Such links wouldn't be used by combine
13823 anyway.
13825 It is not possible for the destination of the target of the link to
13826 have been changed by combine. The only potential of this is if we
13827 replace I3, I2, and I1 by I3 and I2. But in that case the
13828 destination of I2 also remains unchanged. */
13839 /* A LOG_LINK is defined as being placed on the first insn that uses
13840 a register and points to the insn that sets the register. Start
13841 searching at the next insn after the target of the link and stop
13842 when we reach a set of the register or the end of the basic block.
13844 Note that this correctly handles the link that used to point from
13845 I3 to I2. Also note that not much searching is typically done here
13846 since most links don't point very far away. */
13855 {
13859 }
13862 {
13865 }
13869 /* If we found a place to put the link, place it there unless there
13870 is already a link to the same insn as LINK at that point. */
13873 {
13881 {
13885 /* Set added_links_insn to the earliest insn we added a
13886 link to. */
13890 }
13891 }
13892 }
13893 }
13894 \f
13895 /* Subroutine of unmentioned_reg_p and callback from for_each_rtx.
13896 Check whether the expression pointer to by LOC is a register or
13897 memory, and if so return 1 if it isn't mentioned in the rtx EXPR.
13898 Otherwise return zero. */
13900 static int
13902 {
13910 }
13912 /* Check for any register or memory mentioned in EQUIV that is not
13913 mentioned in EXPR. This is used to restrict EQUIV to "specializations"
13914 of EXPR where some registers may have been replaced by constants. */
13916 static bool
13918 {
13920 }
13921 \f
13922 void
13924 {
13925 fprintf
13927 ";; Combiner statistics: %d attempts, %d substitutions (%d requiring new space),\n;; %d successes.\n\n",
13929 }
13931 void
13933 {
13934 fprintf
13936 "\n;; Combiner totals: %d attempts, %d substitutions (%d requiring new space),\n;; %d successes.\n",
13938 }
13939 \f
13940 static bool
13942 {
13944 }
13946 /* Try combining insns through substitution. */
13947 static unsigned int
13949 {
13958 rebuild_jump_labels_after_combine
13961 /* Combining insns may have turned an indirect jump into a
13962 direct jump. Rebuild the JUMP_LABEL fields of jumping
13963 instructions. */
13965 {
13970 }
13974 }
13977 {
13978 {
13979 RTL_PASS,
13993 }
13994 };