sys/dev/disk/ahci/ahci_attach.c

   1 /*
   2  * Copyright (c) 2006 David Gwynne <dlg@openbsd.org>
   3  *
   4  * Permission to use, copy, modify, and distribute this software for any
   5  * purpose with or without fee is hereby granted, provided that the above
   6  * copyright notice and this permission notice appear in all copies.
   7  *
   8  * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
   9  * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
  10  * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
  11  * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
  12  * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
  13  * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
  14  * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
  15  *
  16  *
  17  * Copyright (c) 2009 The DragonFly Project.  All rights reserved.
  18  *
  19  * This code is derived from software contributed to The DragonFly Project
  20  * by Matthew Dillon <dillon@backplane.com>
  21  *
  22  * Redistribution and use in source and binary forms, with or without
  23  * modification, are permitted provided that the following conditions
  24  * are met:
  25  *
  26  * 1. Redistributions of source code must retain the above copyright
  27  *    notice, this list of conditions and the following disclaimer.
  28  * 2. Redistributions in binary form must reproduce the above copyright
  29  *    notice, this list of conditions and the following disclaimer in
  30  *    the documentation and/or other materials provided with the
  31  *    distribution.
  32  * 3. Neither the name of The DragonFly Project nor the names of its
  33  *    contributors may be used to endorse or promote products derived
  34  *    from this software without specific, prior written permission.
  35  *
  36  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  37  * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  38  * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
  39  * FOR A PARTICULAR PURPOSE ARE DISCLAIMED.  IN NO EVENT SHALL THE
  40  * COPYRIGHT HOLDERS OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
  41  * INCIDENTAL, SPECIAL, EXEMPLARY OR CONSEQUENTIAL DAMAGES (INCLUDING,
  42  * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
  43  * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
  44  * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
  45  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT
  46  * OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
  47  * SUCH DAMAGE.
  48  *
  49  * $OpenBSD: ahci.c,v 1.147 2009/02/16 21:19:07 miod Exp $
  50  */
  51
  52 #include "ahci.h"
  53
  54 static int      ahci_vt8251_attach(device_t);
  55 static int      ahci_ati_sb600_attach(device_t);
  56 static int      ahci_nvidia_mcp_attach(device_t);
  57 static int      ahci_pci_attach(device_t);
  58 static int      ahci_pci_detach(device_t);
  59
  60 static const struct ahci_device ahci_devices[] = {
  61         { PCI_VENDOR_VIATECH,   PCI_PRODUCT_VIATECH_VT8251_SATA,
  62             ahci_vt8251_attach, ahci_pci_detach, "ViaTech-VT8251-SATA" },
  63         { PCI_VENDOR_ATI,       PCI_PRODUCT_ATI_SB600_SATA,
  64             ahci_ati_sb600_attach, ahci_pci_detach, "ATI-SB600-SATA" },
  65         { PCI_VENDOR_NVIDIA,    PCI_PRODUCT_NVIDIA_MCP65_AHCI_2,
  66             ahci_nvidia_mcp_attach, ahci_pci_detach, "NVidia-MCP65-SATA" },
  67         { PCI_VENDOR_NVIDIA,    PCI_PRODUCT_NVIDIA_MCP67_AHCI_1,
  68             ahci_nvidia_mcp_attach, ahci_pci_detach, "NVidia-MCP67-SATA" },
  69         { PCI_VENDOR_NVIDIA,    PCI_PRODUCT_NVIDIA_MCP77_AHCI_5,
  70             ahci_nvidia_mcp_attach, ahci_pci_detach, "NVidia-MCP77-SATA" },
  71         { 0, 0,
  72             ahci_pci_attach, ahci_pci_detach, "AHCI-PCI-SATA" }
  73 };
  74
  75 /*
  76  * Match during probe and attach.  The device does not yet have a softc.
  77  */
  78 const struct ahci_device *
  79 ahci_lookup_device(device_t dev)
  80 {
  81         const struct ahci_device *ad;
  82         u_int16_t vendor = pci_get_vendor(dev);
  83         u_int16_t product = pci_get_device(dev);
  84         u_int8_t class = pci_get_class(dev);
  85         u_int8_t subclass = pci_get_subclass(dev);
  86         u_int8_t progif = pci_read_config(dev, PCIR_PROGIF, 1);
  87         int is_ahci;
  88
  89         /*
  90          * Generally speaking if the pci device does not identify as
  91          * AHCI we skip it.
  92          */
  93         if (class == PCIC_STORAGE && subclass == PCIS_STORAGE_SATA &&
  94             progif == PCIP_STORAGE_SATA_AHCI_1_0) {
  95                 is_ahci = 1;
  96         } else {
  97                 is_ahci = 0;
  98         }
  99
 100         for (ad = &ahci_devices[0]; ad->ad_vendor; ++ad) {
 101                 if (ad->ad_vendor == vendor && ad->ad_product == product)
 102                         return (ad);
 103         }
 104
 105         /*
 106          * Last ad is the default match if the PCI device matches SATA.
 107          */
 108         if (is_ahci == 0)
 109                 ad = NULL;
 110         return (ad);
 111 }
 112
 113 /*
 114  * Attach functions.  They all eventually fall through to ahci_pci_attach().
 115  */
 116 static int
 117 ahci_vt8251_attach(device_t dev)
 118 {
 119         struct ahci_softc *sc = device_get_softc(dev);
 120
 121         sc->sc_flags |= AHCI_F_NO_NCQ;
 122         return (ahci_pci_attach(dev));
 123 }
 124
 125 static int
 126 ahci_ati_sb600_attach(device_t dev)
 127 {
 128         struct ahci_softc *sc = device_get_softc(dev);
 129         pcireg_t magic;
 130         u_int8_t subclass = pci_get_subclass(dev);
 131         u_int8_t revid;
 132
 133         if (subclass == PCIS_STORAGE_IDE) {
 134                 revid = pci_read_config(dev, PCIR_REVID, 1);
 135                 magic = pci_read_config(dev, AHCI_PCI_ATI_SB600_MAGIC, 4);
 136                 pci_write_config(dev, AHCI_PCI_ATI_SB600_MAGIC,
 137                                  magic | AHCI_PCI_ATI_SB600_LOCKED, 4);
 138                 pci_write_config(dev, PCIR_REVID,
 139                                  (PCIC_STORAGE << 24) |
 140                                  (PCIS_STORAGE_SATA << 16) |
 141                                  (PCIP_STORAGE_SATA_AHCI_1_0 << 8) |
 142                                  revid, 4);
 143                 pci_write_config(dev, AHCI_PCI_ATI_SB600_MAGIC, magic, 4);
 144         }
 145
 146         sc->sc_flags |= AHCI_F_IGN_FR;
 147         return (ahci_pci_attach(dev));
 148 }
 149
 150 static int
 151 ahci_nvidia_mcp_attach(device_t dev)
 152 {
 153         struct ahci_softc *sc = device_get_softc(dev);
 154
 155         sc->sc_flags |= AHCI_F_IGN_FR;
 156         return (ahci_pci_attach(dev));
 157 }
 158
 159 static int
 160 ahci_pci_attach(device_t dev)
 161 {
 162         struct ahci_softc *sc = device_get_softc(dev);
 163         struct ahci_port *ap;
 164         const char *gen;
 165         u_int32_t cap, pi, reg;
 166         bus_addr_t addr;
 167         int i;
 168         int error;
 169         const char *revision;
 170
 171         if (pci_read_config(dev, PCIR_COMMAND, 2) & 0x0400) {
 172                 device_printf(dev, "BIOS disabled PCI interrupt, "
 173                                    "re-enabling\n");
 174                 pci_write_config(dev, PCIR_COMMAND,
 175                         pci_read_config(dev, PCIR_COMMAND, 2) & ~0x0400, 2);
 176         }
 177
 178
 179         /*
 180          * Map the AHCI controller's IRQ and BAR(5) (hardware registers)
 181          */
 182         sc->sc_dev = dev;
 183         sc->sc_rid_irq = AHCI_IRQ_RID;
 184         sc->sc_irq = bus_alloc_resource_any(dev, SYS_RES_IRQ, &sc->sc_rid_irq,
 185                                             RF_SHAREABLE | RF_ACTIVE);
 186         if (sc->sc_irq == NULL) {
 187                 device_printf(dev, "unable to map interrupt\n");
 188                 ahci_pci_detach(dev);
 189                 return (ENXIO);
 190         }
 191
 192         /*
 193          * When mapping the register window store the tag and handle
 194          * separately so we can use the tag with per-port bus handle
 195          * sub-spaces.
 196          */
 197         sc->sc_rid_regs = PCIR_BAR(5);
 198         sc->sc_regs = bus_alloc_resource_any(dev, SYS_RES_MEMORY,
 199                                              &sc->sc_rid_regs, RF_ACTIVE);
 200         if (sc->sc_regs == NULL) {
 201                 device_printf(dev, "unable to map registers\n");
 202                 ahci_pci_detach(dev);
 203                 return (ENXIO);
 204         }
 205         sc->sc_iot = rman_get_bustag(sc->sc_regs);
 206         sc->sc_ioh = rman_get_bushandle(sc->sc_regs);
 207
 208         /*
 209          * Initialize the chipset and then set the interrupt vector up
 210          */
 211         error = ahci_init(sc);
 212         if (error) {
 213                 ahci_pci_detach(dev);
 214                 return (ENXIO);
 215         }
 216
 217         /*
 218          * Get the AHCI capabilities and max number of concurrent
 219          * command tags and set up the DMA tags.
 220          */
 221         cap = ahci_read(sc, AHCI_REG_CAP);
 222         if (sc->sc_flags & AHCI_F_NO_NCQ)
 223                 cap &= ~AHCI_REG_CAP_SNCQ;
 224         sc->sc_cap = cap;
 225
 226         /*
 227          * We assume at least 4 commands.
 228          */
 229         sc->sc_ncmds = AHCI_REG_CAP_NCS(cap);
 230         if (sc->sc_ncmds < 4) {
 231                 device_printf(dev, "NCS must probe a value >= 4\n");
 232                 ahci_pci_detach(dev);
 233                 return (ENXIO);
 234         }
 235
 236         addr = (cap & AHCI_REG_CAP_S64A) ?
 237                 BUS_SPACE_MAXADDR : BUS_SPACE_MAXADDR_32BIT;
 238
 239         /*
 240          * DMA tags for allocation of DMA memory buffers, lists, and so
 241          * forth.  These are typically per-port.
 242          */
 243         error = 0;
 244         error += bus_dma_tag_create(
 245                         NULL,                           /* parent tag */
 246                         256,                            /* alignment */
 247                         PAGE_SIZE,                      /* boundary */
 248                         addr,                           /* loaddr? */
 249                         BUS_SPACE_MAXADDR,              /* hiaddr */
 250                         NULL,                           /* filter */
 251                         NULL,                           /* filterarg */
 252                         sizeof(struct ahci_rfis),       /* [max]size */
 253                         1,                              /* maxsegs */
 254                         sizeof(struct ahci_rfis),       /* maxsegsz */
 255                         0,                              /* flags */
 256                         &sc->sc_tag_rfis);              /* return tag */
 257
 258         error += bus_dma_tag_create(
 259                         NULL,                           /* parent tag */
 260                         32,                             /* alignment */
 261                         4096 * 1024,                    /* boundary */
 262                         addr,                           /* loaddr? */
 263                         BUS_SPACE_MAXADDR,              /* hiaddr */
 264                         NULL,                           /* filter */
 265                         NULL,                           /* filterarg */
 266                         sc->sc_ncmds * sizeof(struct ahci_cmd_hdr),
 267                         1,                              /* maxsegs */
 268                         sc->sc_ncmds * sizeof(struct ahci_cmd_hdr),
 269                         0,                              /* flags */
 270                         &sc->sc_tag_cmdh);              /* return tag */
 271
 272         /*
 273          * NOTE: ahci_cmd_table is sized to a power of 2
 274          */
 275         error += bus_dma_tag_create(
 276                         NULL,                           /* parent tag */
 277                         sizeof(struct ahci_cmd_table),  /* alignment */
 278                         4096 * 1024,                    /* boundary */
 279                         addr,                           /* loaddr? */
 280                         BUS_SPACE_MAXADDR,              /* hiaddr */
 281                         NULL,                           /* filter */
 282                         NULL,                           /* filterarg */
 283                         sc->sc_ncmds * sizeof(struct ahci_cmd_table),
 284                         1,                              /* maxsegs */
 285                         sc->sc_ncmds * sizeof(struct ahci_cmd_table),
 286                         0,                              /* flags */
 287                         &sc->sc_tag_cmdt);              /* return tag */
 288
 289         /*
 290          * The data tag is used for later dmamaps and not immediately
 291          * allocated.
 292          */
 293         error += bus_dma_tag_create(
 294                         NULL,                           /* parent tag */
 295                         4,                              /* alignment */
 296                         0,                              /* boundary */
 297                         addr,                           /* loaddr? */
 298                         BUS_SPACE_MAXADDR,              /* hiaddr */
 299                         NULL,                           /* filter */
 300                         NULL,                           /* filterarg */
 301                         4096 * 1024,                    /* maxiosize */
 302                         AHCI_MAX_PRDT,                  /* maxsegs */
 303                         65536,                          /* maxsegsz */
 304                         0,                              /* flags */
 305                         &sc->sc_tag_data);              /* return tag */
 306
 307         if (error) {
 308                 device_printf(dev, "unable to create dma tags\n");
 309                 ahci_pci_detach(dev);
 310                 return (ENXIO);
 311         }
 312
 313         switch (cap & AHCI_REG_CAP_ISS) {
 314         case AHCI_REG_CAP_ISS_G1:
 315                 gen = "1 (1.5Gbps)";
 316                 break;
 317         case AHCI_REG_CAP_ISS_G1_2:
 318                 gen = "1 (1.5Gbps) and 2 (3Gbps)";
 319                 break;
 320         default:
 321                 gen = "unknown";
 322                 break;
 323         }
 324
 325         /* check the revision */
 326         reg = ahci_read(sc, AHCI_REG_VS);
 327         switch (reg) {
 328         case AHCI_REG_VS_0_95:
 329                 revision = "AHCI 0.95";
 330                 break;
 331         case AHCI_REG_VS_1_0:
 332                 revision = "AHCI 1.0";
 333                 break;
 334         case AHCI_REG_VS_1_1:
 335                 revision = "AHCI 1.1";
 336                 break;
 337         case AHCI_REG_VS_1_2:
 338                 revision = "AHCI 1.2";
 339                 break;
 340         default:
 341                 device_printf(sc->sc_dev,
 342                               "Warning: Unknown AHCI revision 0x%08x\n", reg);
 343                 revision = "AHCI <unknown>";
 344                 break;
 345         }
 346
 347         device_printf(dev,
 348                       "%s capabilities 0x%b, %d ports, %d tags/port, gen %s\n",
 349                       revision,
 350                       cap, AHCI_FMT_CAP,
 351                       AHCI_REG_CAP_NP(cap), sc->sc_ncmds, gen);
 352
 353         pi = ahci_read(sc, AHCI_REG_PI);
 354         DPRINTF(AHCI_D_VERBOSE, "%s: ports implemented: 0x%08x\n",
 355             DEVNAME(sc), pi);
 356
 357 #ifdef AHCI_COALESCE
 358         /* Naive coalescing support - enable for all ports. */
 359         if (cap & AHCI_REG_CAP_CCCS) {
 360                 u_int16_t               ccc_timeout = 20;
 361                 u_int8_t                ccc_numcomplete = 12;
 362                 u_int32_t               ccc_ctl;
 363
 364                 /* disable coalescing during reconfiguration. */
 365                 ccc_ctl = ahci_read(sc, AHCI_REG_CCC_CTL);
 366                 ccc_ctl &= ~0x00000001;
 367                 ahci_write(sc, AHCI_REG_CCC_CTL, ccc_ctl);
 368
 369                 sc->sc_ccc_mask = 1 << AHCI_REG_CCC_CTL_INT(ccc_ctl);
 370                 if (pi & sc->sc_ccc_mask) {
 371                         /* A conflict with the implemented port list? */
 372                         printf("%s: coalescing interrupt/implemented port list "
 373                             "conflict, PI: %08x, ccc_mask: %08x\n",
 374                             DEVNAME(sc), pi, sc->sc_ccc_mask);
 375                         sc->sc_ccc_mask = 0;
 376                         goto noccc;
 377                 }
 378
 379                 /* ahci_port_start will enable each port when it starts. */
 380                 sc->sc_ccc_ports = pi;
 381                 sc->sc_ccc_ports_cur = 0;
 382
 383                 /* program thresholds and enable overall coalescing. */
 384                 ccc_ctl &= ~0xffffff00;
 385                 ccc_ctl |= (ccc_timeout << 16) | (ccc_numcomplete << 8);
 386                 ahci_write(sc, AHCI_REG_CCC_CTL, ccc_ctl);
 387                 ahci_write(sc, AHCI_REG_CCC_PORTS, 0);
 388                 ahci_write(sc, AHCI_REG_CCC_CTL, ccc_ctl | 1);
 389         }
 390 noccc:
 391 #endif
 392         /*
 393          * Allocate per-port resources
 394          *
 395          * Ignore attach errors, leave the port intact for
 396          * rescan and continue the loop.
 397          *
 398          * All ports are attached in parallel but the CAM scan-bus
 399          * is held up until all ports are attached so we get a deterministic
 400          * order.
 401          */
 402         for (i = 0; error == 0 && i < AHCI_MAX_PORTS; i++) {
 403                 if ((pi & (1 << i)) == 0) {
 404                         /* dont allocate stuff if the port isnt implemented */
 405                         continue;
 406                 }
 407                 error = ahci_port_alloc(sc, i);
 408         }
 409
 410         /*
 411          * Setup the interrupt vector and enable interrupts.  Note that
 412          * since the irq may be shared we do not set it up until we are
 413          * ready to go.
 414          */
 415         if (error == 0) {
 416                 error = bus_setup_intr(dev, sc->sc_irq, 0, ahci_intr, sc,
 417                                        &sc->sc_irq_handle, NULL);
 418         }
 419
 420         if (error) {
 421                 device_printf(dev, "unable to install interrupt\n");
 422                 ahci_pci_detach(dev);
 423                 return (ENXIO);
 424         }
 425
 426         /*
 427          * Before marking the sc as good, which allows the interrupt
 428          * subsystem to operate on the ports, wait for all the port threads
 429          * to get past their initial pre-probe init.  Otherwise an interrupt
 430          * may try to process the port before it has been initialized.
 431          */
 432         for (i = 0; i < AHCI_MAX_PORTS; i++) {
 433                 if ((ap = sc->sc_ports[i]) != NULL) {
 434                         while (ap->ap_signal & AP_SIGF_THREAD_SYNC)
 435                                 tsleep(&ap->ap_signal, 0, "ahprb1", hz);
 436                 }
 437         }
 438
 439         /*
 440          * Master interrupt enable, and call ahci_intr() in case we race
 441          * our AHCI_F_INT_GOOD flag.
 442          */
 443         crit_enter();
 444         ahci_write(sc, AHCI_REG_GHC, AHCI_REG_GHC_AE | AHCI_REG_GHC_IE);
 445         sc->sc_flags |= AHCI_F_INT_GOOD;
 446         crit_exit();
 447         ahci_intr(sc);
 448
 449         /*
 450          * All ports are probing in parallel.  Wait for them to finish
 451          * and then issue the cam attachment and bus scan serially so
 452          * the 'da' assignments are deterministic.
 453          */
 454         for (i = 0; i < AHCI_MAX_PORTS; i++) {
 455                 if ((ap = sc->sc_ports[i]) != NULL) {
 456                         while (ap->ap_signal & AP_SIGF_INIT)
 457                                 tsleep(&ap->ap_signal, 0, "ahprb2", hz);
 458                         ahci_os_lock_port(ap);
 459                         if (ahci_cam_attach(ap) == 0) {
 460                                 ahci_cam_changed(ap, NULL, -1);
 461                                 ahci_os_unlock_port(ap);
 462                                 while ((ap->ap_flags & AP_F_SCAN_COMPLETED) == 0) {
 463                                         tsleep(&ap->ap_flags, 0, "ahprb2", hz);
 464                                 }
 465                         } else {
 466                                 ahci_os_unlock_port(ap);
 467                         }
 468                 }
 469         }
 470
 471         return(0);
 472 }
 473
 474 /*
 475  * Device unload / detachment
 476  */
 477 static int
 478 ahci_pci_detach(device_t dev)
 479 {
 480         struct ahci_softc *sc = device_get_softc(dev);
 481         struct ahci_port *ap;
 482         int     i;
 483
 484         /*
 485          * Disable the controller and de-register the interrupt, if any.
 486          *
 487          * XXX interlock last interrupt?
 488          */
 489         sc->sc_flags &= ~AHCI_F_INT_GOOD;
 490         if (sc->sc_regs)
 491                 ahci_write(sc, AHCI_REG_GHC, 0);
 492
 493         if (sc->sc_irq_handle) {
 494                 bus_teardown_intr(dev, sc->sc_irq, sc->sc_irq_handle);
 495                 sc->sc_irq_handle = NULL;
 496         }
 497
 498         /*
 499          * Free port structures and DMA memory
 500          */
 501         for (i = 0; i < AHCI_MAX_PORTS; i++) {
 502                 ap = sc->sc_ports[i];
 503                 if (ap) {
 504                         ahci_cam_detach(ap);
 505                         ahci_port_free(sc, i);
 506                 }
 507         }
 508
 509         /*
 510          * Clean up the bus space
 511          */
 512         if (sc->sc_irq) {
 513                 bus_release_resource(dev, SYS_RES_IRQ,
 514                                      sc->sc_rid_irq, sc->sc_irq);
 515                 sc->sc_irq = NULL;
 516         }
 517         if (sc->sc_regs) {
 518                 bus_release_resource(dev, SYS_RES_MEMORY,
 519                                      sc->sc_rid_regs, sc->sc_regs);
 520                 sc->sc_regs = NULL;
 521         }
 522
 523         if (sc->sc_tag_rfis) {
 524                 bus_dma_tag_destroy(sc->sc_tag_rfis);
 525                 sc->sc_tag_rfis = NULL;
 526         }
 527         if (sc->sc_tag_cmdh) {
 528                 bus_dma_tag_destroy(sc->sc_tag_cmdh);
 529                 sc->sc_tag_cmdh = NULL;
 530         }
 531         if (sc->sc_tag_cmdt) {
 532                 bus_dma_tag_destroy(sc->sc_tag_cmdt);
 533                 sc->sc_tag_cmdt = NULL;
 534         }
 535         if (sc->sc_tag_data) {
 536                 bus_dma_tag_destroy(sc->sc_tag_data);
 537                 sc->sc_tag_data = NULL;
 538         }
 539
 540         return (0);
 541 }