sys/dev/disk/ncv/ncr53c500reg.h

   1 /*      $FreeBSD: src/sys/dev/ncv/ncr53c500reg.h,v 1.1.2.2 2001/07/22 00:21:39 non Exp $        */
   2 /*      $DragonFly: src/sys/dev/disk/ncv/ncr53c500reg.h,v 1.2 2003/06/17 04:28:28 dillon Exp $  */
   3 /*      $NecBSD: ncr53c500reg.h,v 1.5 1998/12/26 11:50:01 honda Exp $   */
   4 /*      $NetBSD$        */
   5
   6 /*
   7  * [NetBSD for NEC PC-98 series]
   8  *  Copyright (c) 1995, 1996, 1997, 1998
   9  *      NetBSD/pc98 porting staff. All rights reserved.
  10  *  Copyright (c) 1995, 1996, 1997, 1998
  11  *      Naofumi HONDA. All rights reserved.
  12  *  Copyright (c) 1995, 1996, 1997, 1998
  13  *      Kouichi Matsuda. All rights reserved.
  14  *
  15  *  Redistribution and use in source and binary forms, with or without
  16  *  modification, are permitted provided that the following conditions
  17  *  are met:
  18  *  1. Redistributions of source code must retain the above copyright
  19  *     notice, this list of conditions and the following disclaimer.
  20  *  2. Redistributions in binary form must reproduce the above copyright
  21  *     notice, this list of conditions and the following disclaimer in the
  22  *     documentation and/or other materials provided with the distribution.
  23  *  3. The name of the author may not be used to endorse or promote products
  24  *     derived from this software without specific prior written permission.
  25  *
  26  * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
  27  * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
  28  * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
  29  * DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT,
  30  * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
  31  * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
  32  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
  33  * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
  34  * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
  35  * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
  36  * POSSIBILITY OF SUCH DAMAGE.
  37  */
  38
  39 #ifndef _NCR53C500REG_H_
  40 #define _NCR53C500REG_H_
  41
  42 /* Control Register Set 0 */
  43 #define NCVIOSZ         0x10
  44
  45 #define cr0_tclsb       0x00    /* RW - Transfer Count Low      */
  46 #define cr0_tcmsb       0x01    /* RW - Transfer Count Mid      */
  47 #define cr0_sfifo       0x02    /* RW - FIFO data               */
  48 #define cr0_cmd         0x03    /* RW - Command (2 deep)        */
  49 #define cr0_stat        0x04    /* RO - Status                  */
  50 #define cr0_dstid       0x04    /* WO - Select/Reselect Bus ID  */
  51 #define cr0_istat       0x05    /* RO - Interrupt               */
  52 #define cr0_srtout      0x05    /* WO - Select/Reselect Timeout */
  53 #define cr0_seq         0x06    /* RO - Sequence Step           */
  54 #define cr0_period      0x06    /* WO - Synch Transfer Period   */
  55 #define cr0_sffl        0x07    /* RO - FIFO FLags              */
  56 #define cr0_offs        0x07    /* WO - Synch Ofset             */
  57 #define cr0_cfg1        0x08    /* RW - Configuration #1        */
  58 #define cr0_clk         0x09    /* WO - Clock Conversion Factor */
  59 #define cr0_tst         0x0a    /* WO - Test (Chip Test Only)   */
  60 #define cr0_cfg2        0x0b    /* RW - Configuration #2        */
  61 #define cr0_cfg3        0x0c    /* RW - Configuration #3        */
  62 #define cr0_cfg4        0x0d    /* RW - Configuration #4        */
  63 #define cr0_tchsb       0x0e    /* RW - Transfer Count High     */
  64 #define cr0_fifo_bottom 0x0f    /* WO - FIFO bottom             */
  65
  66 /* Control Register Set 1 */
  67 #define cr1_jumper      0x00    /* RW - Jumper Sense Port       */
  68 #define cr1_sram_ptr    0x01    /* RW - SRAM Address Pointer    */
  69 #define cr1_sram_data   0x02    /* RW - SRAM Data               */
  70 #define cr1_fdata       0x04    /* RW - PIO FIFO                */
  71 #define cr1_fstat       0x08    /* RW - PIO Status              */
  72 #define cr1_atacmd      0x09    /* RW - ATA Command/Status      */
  73 #define cr1_ataerr      0x0a    /* RW - ATA Features/Error      */
  74 #define cr1_pflag       0x0b    /* RW - PIO Flag Interrupt Enable       */
  75 #define cr1_cfg5        0x0d    /* RW - Configuration #5        */
  76 #define cr1_sig         0x0e    /* RO - Signature               */
  77 #define cr1_cfg6        0x0f    /* RW - Configuration #6        */
  78
  79 /* atacmd (MPS110 ONLY) */
  80 #define ATACMD_POWDOWN  0x2d
  81 #define ATACMD_ENGAGE   0x24
  82
  83 /* cr0_sffl regster */
  84 #define CR0_SFFLR_BMASK 0x1f    /* scsi fifo byte mask */
  85
  86 /* cfg4 */
  87 #define C4_ANE          0x04
  88
  89 /* cfg2 */
  90 #define C2_SCSI2        0x08    /* SCSI-2 Enable        */
  91 #define C2_FE           0x40    /* Features Enable      */
  92
  93 /* cfg1 */
  94 #define C1_SLOW         0x80    /* Slow Cable Mode      */
  95 #define C1_SRR          0x40    /* SCSI Reset Rep Int Dis       */
  96 #define C1_PARENB       0x10    /* Enable Parity Check  */
  97
  98 /* clk factor */
  99 #define CLK_40M_F       0x00
 100 #define CLK_25M_F       0x05
 101 #define CLK_30M_F       0x06
 102 #define CLK_35M_F       0x07
 103
 104 /* interrupt status register */
 105 #define INTR_SBR        0x80    /* SCSI Bus Reset       */
 106 #define INTR_ILL        0x40    /* Illegal Command      */
 107 #define INTR_DIS        0x20    /* Disconnect           */
 108 #define INTR_BS         0x10    /* Bus Service          */
 109 #define INTR_FC         0x08    /* Function Complete    */
 110 #define INTR_RESEL      0x04    /* Reselected           */
 111 #define INTR_SELATN     0x02    /* Select with ATN      */
 112 #define INTR_SEL        0x01    /* Selected             */
 113 #define INTR_RESELECT   (INTR_RESEL | INTR_FC)
 114
 115 /* status register */
 116 #define STAT_INT        0x80    /* Interrupt            */
 117 #define STAT_GE         0x40    /* Gross Error          */
 118 #define STAT_PE         0x20    /* Parity Error         */
 119 #define STAT_TC         0x10    /* Terminal Count       */
 120
 121 /* phase bits */
 122 #define IOI                     0x01
 123 #define CDI                     0x02
 124 #define MSGI                    0x04
 125
 126 /* Information transfer phases */
 127 #define DATA_OUT_PHASE          (0)
 128 #define DATA_IN_PHASE           (IOI)
 129 #define COMMAND_PHASE           (CDI)
 130 #define STATUS_PHASE            (CDI|IOI)
 131 #define MESSAGE_OUT_PHASE       (MSGI|CDI)
 132 #define MESSAGE_IN_PHASE        (MSGI|CDI|IOI)
 133
 134 #define PHASE_MASK              (MSGI|CDI|IOI)
 135
 136 /* fifo status register */
 137 #define FIFO_SMASK      0x1e
 138 #define FIFO_E          0x10            /* fifo empty */
 139 #define FIFO_B          0x00            /* there exists any */
 140 #define FIFO_1          0x08            /* 1/3 <= bytes < 2/3 */
 141 #define FIFO_2          0x04            /* 2/3 <= bytes < full */
 142 #define FIFO_F          0x02            /* full */
 143 #define FIFO_EN         0x01            /* fifo direction */
 144 #define FIFO_BRK        0x40            /* phase miss */
 145
 146 #define FIFO_F_SZ       128
 147 #define FIFO_1_SZ       44
 148 #define FIFO_2_SZ       84
 149
 150 /* pflags */
 151 #define PFR_WRITE       0x01
 152
 153 /* Commands */
 154 #define CMD_DMA         0x80    /* DMA Bit                      */
 155 #define CMD_NOP         0x00    /* No Operation                 */
 156 #define CMD_FLUSH       0x01    /* Flush FIFO                   */
 157 #define CMD_RSTCHIP     0x02    /* Reset Chip                   */
 158 #define CMD_RSTSCSI     0x03    /* Reset SCSI Bus               */
 159 #define CMD_RESEL       0x40    /* Reselect Sequence            */
 160 #define CMD_SELNATN     0x41    /* Select without ATN           */
 161 #define CMD_SELATN      0x42    /* Select with ATN              */
 162 #define CMD_SELATNS     0x43    /* Select with ATN & Stop       */
 163 #define CMD_ENSEL       0x44    /* Enable (Re)Selection         */
 164 #define CMD_DISSEL      0x45    /* Disable (Re)Selection        */
 165 #define CMD_SELATN3     0x46    /* Select with ATN3             */
 166 #define CMD_RESEL3      0x47    /* Reselect3 Sequence           */
 167 #define CMD_SNDMSG      0x20    /* Send Message                 */
 168 #define CMD_SNDSTAT     0x21    /* Send Status                  */
 169 #define CMD_SNDDATA     0x22    /* Send Data                    */
 170 #define CMD_DISCSEQ     0x23    /* Disconnect Sequence          */
 171 #define CMD_TERMSEQ     0x24    /* Terminate Sequence           */
 172 #define CMD_TCCS        0x25    /* Target Command Comp Seq      */
 173 #define CMD_DISC        0x27    /* Disconnect                   */
 174 #define CMD_RECMSG      0x28    /* Receive Message              */
 175 #define CMD_RECCMD      0x29    /* Receive Command              */
 176 #define CMD_RECDATA     0x2a    /* Receive Data                 */
 177 #define CMD_RECCSEQ     0x2b    /* Receive Command Sequence     */
 178 #define CMD_ABORT       0x04    /* Target Abort DMA             */
 179 #define CMD_TRANS       0x10    /* Transfer Information         */
 180 #define CMD_ICCS        0x11    /* Initiator Cmd Comp Seq       */
 181 #define CMD_MSGOK       0x12    /* Message Accepted             */
 182 #define CMD_TRPAD       0x18    /* Transfer Pad                 */
 183 #define CMD_SETATN      0x1a    /* Set ATN                      */
 184 #define CMD_RSTATN      0x1b    /* Reset ATN                    */
 185
 186 /* Default timeout */
 187 #define SEL_TOUT        0xa3
 188 #endif  /* !_NCR53C500REG_H_ */