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Unify vlan_input() and vlan_input_tag():
[dragonfly.git] / sys / dev / netif / re / if_re.c
blob510193f942c9c3931b69ca8947558d30698be9f3
1 /*
2 * Copyright (c) 2004
3 * Joerg Sonnenberger <joerg@bec.de>. All rights reserved.
4 *
5 * Copyright (c) 1997, 1998-2003
6 * Bill Paul <wpaul@windriver.com>. All rights reserved.
7 *
8 * Redistribution and use in source and binary forms, with or without
9 * modification, are permitted provided that the following conditions
10 * are met:
11 * 1. Redistributions of source code must retain the above copyright
12 * notice, this list of conditions and the following disclaimer.
13 * 2. Redistributions in binary form must reproduce the above copyright
14 * notice, this list of conditions and the following disclaimer in the
15 * documentation and/or other materials provided with the distribution.
16 * 3. All advertising materials mentioning features or use of this software
17 * must display the following acknowledgement:
18 * This product includes software developed by Bill Paul.
19 * 4. Neither the name of the author nor the names of any co-contributors
20 * may be used to endorse or promote products derived from this software
21 * without specific prior written permission.
22 *
23 * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND
24 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
25 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
26 * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD
27 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
28 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
29 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
30 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
31 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
32 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
33 * THE POSSIBILITY OF SUCH DAMAGE.
34 *
35 * $FreeBSD: src/sys/dev/re/if_re.c,v 1.25 2004/06/09 14:34:01 naddy Exp $
36 * $DragonFly: src/sys/dev/netif/re/if_re.c,v 1.43 2008/05/16 13:19:12 sephe Exp $
37 */
38
39 /*
40 * RealTek 8139C+/8169/8169S/8110S/8168/8111/8101E PCI NIC driver
41 *
42 * Written by Bill Paul <wpaul@windriver.com>
43 * Senior Networking Software Engineer
44 * Wind River Systems
45 */
46
47 /*
48 * This driver is designed to support RealTek's next generation of
49 * 10/100 and 10/100/1000 PCI ethernet controllers. There are currently
50 * seven devices in this family: the RTL8139C+, the RTL8169, the RTL8169S,
51 * RTL8110S, the RTL8168, the RTL8111 and the RTL8101E.
52 *
53 * The 8139C+ is a 10/100 ethernet chip. It is backwards compatible
54 * with the older 8139 family, however it also supports a special
55 * C+ mode of operation that provides several new performance enhancing
56 * features. These include:
57 *
58 * o Descriptor based DMA mechanism. Each descriptor represents
59 * a single packet fragment. Data buffers may be aligned on
60 * any byte boundary.
61 *
62 * o 64-bit DMA
63 *
64 * o TCP/IP checksum offload for both RX and TX
65 *
66 * o High and normal priority transmit DMA rings
67 *
68 * o VLAN tag insertion and extraction
69 *
70 * o TCP large send (segmentation offload)
71 *
72 * Like the 8139, the 8139C+ also has a built-in 10/100 PHY. The C+
73 * programming API is fairly straightforward. The RX filtering, EEPROM
74 * access and PHY access is the same as it is on the older 8139 series
75 * chips.
76 *
77 * The 8169 is a 64-bit 10/100/1000 gigabit ethernet MAC. It has almost the
78 * same programming API and feature set as the 8139C+ with the following
79 * differences and additions:
80 *
81 * o 1000Mbps mode
82 *
83 * o Jumbo frames
84 *
85 * o GMII and TBI ports/registers for interfacing with copper
86 * or fiber PHYs
87 *
88 * o RX and TX DMA rings can have up to 1024 descriptors
89 * (the 8139C+ allows a maximum of 64)
90 *
91 * o Slight differences in register layout from the 8139C+
92 *
93 * The TX start and timer interrupt registers are at different locations
94 * on the 8169 than they are on the 8139C+. Also, the status word in the
95 * RX descriptor has a slightly different bit layout. The 8169 does not
96 * have a built-in PHY. Most reference boards use a Marvell 88E1000 'Alaska'
97 * copper gigE PHY.
98 *
99 * The 8169S/8110S 10/100/1000 devices have built-in copper gigE PHYs
100 * (the 'S' stands for 'single-chip'). These devices have the same
101 * programming API as the older 8169, but also have some vendor-specific
102 * registers for the on-board PHY. The 8110S is a LAN-on-motherboard
103 * part designed to be pin-compatible with the RealTek 8100 10/100 chip.
104 *
105 * This driver takes advantage of the RX and TX checksum offload and
106 * VLAN tag insertion/extraction features. It also implements TX
107 * interrupt moderation using the timer interrupt registers, which
108 * significantly reduces TX interrupt load. There is also support
109 * for jumbo frames, however the 8169/8169S/8110S can not transmit
110 * jumbo frames larger than 7440, so the max MTU possible with this
111 * driver is 7422 bytes.
112 */
113
114 #include "opt_polling.h"
115
116 #include <sys/param.h>
117 #include <sys/bus.h>
118 #include <sys/endian.h>
119 #include <sys/kernel.h>
120 #include <sys/interrupt.h>
121 #include <sys/malloc.h>
122 #include <sys/mbuf.h>
123 #include <sys/rman.h>
124 #include <sys/serialize.h>
125 #include <sys/socket.h>
126 #include <sys/sockio.h>
127 #include <sys/sysctl.h>
128
129 #include <net/bpf.h>
130 #include <net/ethernet.h>
131 #include <net/if.h>
132 #include <net/ifq_var.h>
133 #include <net/if_arp.h>
134 #include <net/if_dl.h>
135 #include <net/if_media.h>
136 #include <net/if_types.h>
137 #include <net/vlan/if_vlan_var.h>
138 #include <net/vlan/if_vlan_ether.h>
139
140 #include <dev/netif/mii_layer/mii.h>
141 #include <dev/netif/mii_layer/miivar.h>
142
143 #include <bus/pci/pcidevs.h>
144 #include <bus/pci/pcireg.h>
145 #include <bus/pci/pcivar.h>
146
147 /* "device miibus" required. See GENERIC if you get errors here. */
148 #include "miibus_if.h"
149
150 #include <dev/netif/re/if_rereg.h>
151 #include <dev/netif/re/if_revar.h>
152
153 #define RE_CSUM_FEATURES (CSUM_IP | CSUM_TCP | CSUM_UDP)
154 #if 0
155 #define RE_DISABLE_HWCSUM
156 #endif
157
158 /*
159 * Various supported device vendors/types and their names.
160 */
161 static const struct re_type re_devs[] = {
162 { PCI_VENDOR_DLINK, PCI_PRODUCT_DLINK_DGE528T, RE_HWREV_8169S,
163 "D-Link DGE-528(T) Gigabit Ethernet Adapter" },
164 { PCI_VENDOR_REALTEK, PCI_PRODUCT_REALTEK_RT8139, RE_HWREV_8139CPLUS,
165 "RealTek 8139C+ 10/100BaseTX" },
166 { PCI_VENDOR_REALTEK, PCI_PRODUCT_REALTEK_RT8101E, RE_HWREV_8101E,
167 "RealTek 8101E PCIe 10/100baseTX" },
168 { PCI_VENDOR_REALTEK, PCI_PRODUCT_REALTEK_RT8168, RE_HWREV_8168_SPIN1,
169 "RealTek 8168/8111B PCIe Gigabit Ethernet" },
170 { PCI_VENDOR_REALTEK, PCI_PRODUCT_REALTEK_RT8168, RE_HWREV_8168_SPIN2,
171 "RealTek 8168/8111B PCIe Gigabit Ethernet" },
172 { PCI_VENDOR_REALTEK, PCI_PRODUCT_REALTEK_RT8168, RE_HWREV_8168_SPIN3,
173 "RealTek 8168B/8111B PCIe Gigabit Ethernet" },
174 { PCI_VENDOR_REALTEK, PCI_PRODUCT_REALTEK_RT8168, RE_HWREV_8168C,
175 "RealTek 8168C/8111C PCIe Gigabit Ethernet" },
176 { PCI_VENDOR_REALTEK, PCI_PRODUCT_REALTEK_RT8169, RE_HWREV_8169,
177 "RealTek 8169 Gigabit Ethernet" },
178 { PCI_VENDOR_REALTEK, PCI_PRODUCT_REALTEK_RT8169, RE_HWREV_8169S,
179 "RealTek 8169S Single-chip Gigabit Ethernet" },
180 { PCI_VENDOR_REALTEK, PCI_PRODUCT_REALTEK_RT8169, RE_HWREV_8169_8110SB,
181 "RealTek 8169SB/8110SB Single-chip Gigabit Ethernet" },
182 { PCI_VENDOR_REALTEK, PCI_PRODUCT_REALTEK_RT8169, RE_HWREV_8169_8110SC,
183 "RealTek 8169SC/8110SC Single-chip Gigabit Ethernet" },
184 { PCI_VENDOR_REALTEK, PCI_PRODUCT_REALTEK_RT8169SC, RE_HWREV_8169_8110SC,
185 "RealTek 8169SC/8110SC Single-chip Gigabit Ethernet" },
186 { PCI_VENDOR_REALTEK, PCI_PRODUCT_REALTEK_RT8169, RE_HWREV_8110S,
187 "RealTek 8110S Single-chip Gigabit Ethernet" },
188 { PCI_VENDOR_COREGA, PCI_PRODUCT_COREGA_CG_LAPCIGT, RE_HWREV_8169S,
189 "Corega CG-LAPCIGT Gigabit Ethernet" },
190 { PCI_VENDOR_LINKSYS, PCI_PRODUCT_LINKSYS_EG1032, RE_HWREV_8169S,
191 "Linksys EG1032 Gigabit Ethernet" },
192 { PCI_VENDOR_USR2, PCI_PRODUCT_USR2_997902, RE_HWREV_8169S,
193 "US Robotics 997902 Gigabit Ethernet" },
194 { 0, 0, 0, NULL }
195 };
196
197 static const struct re_hwrev re_hwrevs[] = {
198 { RE_HWREV_8139CPLUS, RE_8139CPLUS, RE_F_HASMPC, "C+" },
199 { RE_HWREV_8168_SPIN1, RE_8169, RE_F_PCIE, "8168" },
200 { RE_HWREV_8168_SPIN2, RE_8169, RE_F_PCIE, "8168" },
201 { RE_HWREV_8168_SPIN3, RE_8169, RE_F_PCIE, "8168" },
202 { RE_HWREV_8168C, RE_8169, RE_F_PCIE, "8168C" },
203 { RE_HWREV_8169, RE_8169, RE_F_HASMPC, "8169" },
204 { RE_HWREV_8169S, RE_8169, RE_F_HASMPC, "8169S" },
205 { RE_HWREV_8110S, RE_8169, RE_F_HASMPC, "8110S" },
206 { RE_HWREV_8169_8110SB, RE_8169, RE_F_HASMPC, "8169SB" },
207 { RE_HWREV_8169_8110SC, RE_8169, 0, "8169SC" },
208 { RE_HWREV_8100E, RE_8169, RE_F_HASMPC, "8100E" },
209 { RE_HWREV_8101E, RE_8169, RE_F_PCIE, "8101E" },
210 { 0, 0, 0, NULL }
211 };
212
213 static int re_probe(device_t);
214 static int re_attach(device_t);
215 static int re_detach(device_t);
216
217 static int re_encap(struct re_softc *, struct mbuf **, int *, int *);
218
219 static void re_dma_map_addr(void *, bus_dma_segment_t *, int, int);
220 static void re_dma_map_desc(void *, bus_dma_segment_t *, int,
221 bus_size_t, int);
222 static int re_allocmem(device_t, struct re_softc *);
223 static int re_newbuf(struct re_softc *, int, struct mbuf *);
224 static int re_rx_list_init(struct re_softc *);
225 static int re_tx_list_init(struct re_softc *);
226 static void re_rxeof(struct re_softc *);
227 static void re_txeof(struct re_softc *);
228 static void re_intr(void *);
229 static void re_tick(void *);
230 static void re_tick_serialized(void *);
231 static void re_start(struct ifnet *);
232 static int re_ioctl(struct ifnet *, u_long, caddr_t, struct ucred *);
233 static void re_init(void *);
234 static void re_stop(struct re_softc *);
235 static void re_watchdog(struct ifnet *);
236 static int re_suspend(device_t);
237 static int re_resume(device_t);
238 static void re_shutdown(device_t);
239 static int re_ifmedia_upd(struct ifnet *);
240 static void re_ifmedia_sts(struct ifnet *, struct ifmediareq *);
241
242 static void re_eeprom_putbyte(struct re_softc *, int);
243 static void re_eeprom_getword(struct re_softc *, int, u_int16_t *);
244 static void re_read_eeprom(struct re_softc *, caddr_t, int, int);
245 static int re_gmii_readreg(device_t, int, int);
246 static int re_gmii_writereg(device_t, int, int, int);
247
248 static int re_miibus_readreg(device_t, int, int);
249 static int re_miibus_writereg(device_t, int, int, int);
250 static void re_miibus_statchg(device_t);
251
252 static void re_setmulti(struct re_softc *);
253 static void re_reset(struct re_softc *);
254
255 #ifdef RE_DIAG
256 static int re_diag(struct re_softc *);
257 #endif
258
259 #ifdef DEVICE_POLLING
260 static void re_poll(struct ifnet *ifp, enum poll_cmd cmd, int count);
261 #endif
262
263 static int re_sysctl_tx_moderation(SYSCTL_HANDLER_ARGS);
264
265 static device_method_t re_methods[] = {
266 /* Device interface */
267 DEVMETHOD(device_probe, re_probe),
268 DEVMETHOD(device_attach, re_attach),
269 DEVMETHOD(device_detach, re_detach),
270 DEVMETHOD(device_suspend, re_suspend),
271 DEVMETHOD(device_resume, re_resume),
272 DEVMETHOD(device_shutdown, re_shutdown),
273
274 /* bus interface */
275 DEVMETHOD(bus_print_child, bus_generic_print_child),
276 DEVMETHOD(bus_driver_added, bus_generic_driver_added),
277
278 /* MII interface */
279 DEVMETHOD(miibus_readreg, re_miibus_readreg),
280 DEVMETHOD(miibus_writereg, re_miibus_writereg),
281 DEVMETHOD(miibus_statchg, re_miibus_statchg),
282
283 { 0, 0 }
284 };
285
286 static driver_t re_driver = {
287 "re",
288 re_methods,
289 sizeof(struct re_softc)
290 };
291
292 static devclass_t re_devclass;
293
294 DECLARE_DUMMY_MODULE(if_re);
295 DRIVER_MODULE(if_re, pci, re_driver, re_devclass, 0, 0);
296 DRIVER_MODULE(if_re, cardbus, re_driver, re_devclass, 0, 0);
297 DRIVER_MODULE(miibus, re, miibus_driver, miibus_devclass, 0, 0);
298
299 #define EE_SET(x) \
300 CSR_WRITE_1(sc, RE_EECMD, CSR_READ_1(sc, RE_EECMD) | (x))
301
302 #define EE_CLR(x) \
303 CSR_WRITE_1(sc, RE_EECMD, CSR_READ_1(sc, RE_EECMD) & ~(x))
304
305 /*
306 * Send a read command and address to the EEPROM, check for ACK.
307 */
308 static void
309 re_eeprom_putbyte(struct re_softc *sc, int addr)
310 {
311 int d, i;
312
313 d = addr | (RE_9346_READ << sc->re_eewidth);
314
315 /*
316 * Feed in each bit and strobe the clock.
317 */
318 for (i = 1 << (sc->re_eewidth + 3); i; i >>= 1) {
319 if (d & i)
320 EE_SET(RE_EE_DATAIN);
321 else
322 EE_CLR(RE_EE_DATAIN);
323 DELAY(100);
324 EE_SET(RE_EE_CLK);
325 DELAY(150);
326 EE_CLR(RE_EE_CLK);
327 DELAY(100);
328 }
329 }
330
331 /*
332 * Read a word of data stored in the EEPROM at address 'addr.'
333 */
334 static void
335 re_eeprom_getword(struct re_softc *sc, int addr, uint16_t *dest)
336 {
337 int i;
338 uint16_t word = 0;
339
340 /*
341 * Send address of word we want to read.
342 */
343 re_eeprom_putbyte(sc, addr);
344
345 /*
346 * Start reading bits from EEPROM.
347 */
348 for (i = 0x8000; i != 0; i >>= 1) {
349 EE_SET(RE_EE_CLK);
350 DELAY(100);
351 if (CSR_READ_1(sc, RE_EECMD) & RE_EE_DATAOUT)
352 word |= i;
353 EE_CLR(RE_EE_CLK);
354 DELAY(100);
355 }
356
357 *dest = word;
358 }
359
360 /*
361 * Read a sequence of words from the EEPROM.
362 */
363 static void
364 re_read_eeprom(struct re_softc *sc, caddr_t dest, int off, int cnt)
365 {
366 int i;
367 uint16_t word = 0, *ptr;
368
369 CSR_SETBIT_1(sc, RE_EECMD, RE_EEMODE_PROGRAM);
370 DELAY(100);
371
372 for (i = 0; i < cnt; i++) {
373 CSR_SETBIT_1(sc, RE_EECMD, RE_EE_SEL);
374 re_eeprom_getword(sc, off + i, &word);
375 CSR_CLRBIT_1(sc, RE_EECMD, RE_EE_SEL);
376 ptr = (uint16_t *)(dest + (i * 2));
377 *ptr = word;
378 }
379
380 CSR_CLRBIT_1(sc, RE_EECMD, RE_EEMODE_PROGRAM);
381 }
382
383 static int
384 re_gmii_readreg(device_t dev, int phy, int reg)
385 {
386 struct re_softc *sc = device_get_softc(dev);
387 u_int32_t rval;
388 int i;
389
390 if (phy != 1)
391 return(0);
392
393 /* Let the rgephy driver read the GMEDIASTAT register */
394
395 if (reg == RE_GMEDIASTAT)
396 return(CSR_READ_1(sc, RE_GMEDIASTAT));
397
398 CSR_WRITE_4(sc, RE_PHYAR, reg << 16);
399 DELAY(1000);
400
401 for (i = 0; i < RE_TIMEOUT; i++) {
402 rval = CSR_READ_4(sc, RE_PHYAR);
403 if (rval & RE_PHYAR_BUSY)
404 break;
405 DELAY(100);
406 }
407
408 if (i == RE_TIMEOUT) {
409 device_printf(dev, "PHY read failed\n");
410 return(0);
411 }
412
413 return(rval & RE_PHYAR_PHYDATA);
414 }
415
416 static int
417 re_gmii_writereg(device_t dev, int phy, int reg, int data)
418 {
419 struct re_softc *sc = device_get_softc(dev);
420 uint32_t rval;
421 int i;
422
423 CSR_WRITE_4(sc, RE_PHYAR,
424 (reg << 16) | (data & RE_PHYAR_PHYDATA) | RE_PHYAR_BUSY);
425 DELAY(1000);
426
427 for (i = 0; i < RE_TIMEOUT; i++) {
428 rval = CSR_READ_4(sc, RE_PHYAR);
429 if ((rval & RE_PHYAR_BUSY) == 0)
430 break;
431 DELAY(100);
432 }
433
434 if (i == RE_TIMEOUT)
435 device_printf(dev, "PHY write failed\n");
436
437 return(0);
438 }
439
440 static int
441 re_miibus_readreg(device_t dev, int phy, int reg)
442 {
443 struct re_softc *sc = device_get_softc(dev);
444 uint16_t rval = 0;
445 uint16_t re8139_reg = 0;
446
447 if (sc->re_type == RE_8169) {
448 rval = re_gmii_readreg(dev, phy, reg);
449 return(rval);
450 }
451
452 /* Pretend the internal PHY is only at address 0 */
453 if (phy)
454 return(0);
455
456 switch(reg) {
457 case MII_BMCR:
458 re8139_reg = RE_BMCR;
459 break;
460 case MII_BMSR:
461 re8139_reg = RE_BMSR;
462 break;
463 case MII_ANAR:
464 re8139_reg = RE_ANAR;
465 break;
466 case MII_ANER:
467 re8139_reg = RE_ANER;
468 break;
469 case MII_ANLPAR:
470 re8139_reg = RE_LPAR;
471 break;
472 case MII_PHYIDR1:
473 case MII_PHYIDR2:
474 return(0);
475 /*
476 * Allow the rlphy driver to read the media status
477 * register. If we have a link partner which does not
478 * support NWAY, this is the register which will tell
479 * us the results of parallel detection.
480 */
481 case RE_MEDIASTAT:
482 return(CSR_READ_1(sc, RE_MEDIASTAT));
483 default:
484 device_printf(dev, "bad phy register\n");
485 return(0);
486 }
487 rval = CSR_READ_2(sc, re8139_reg);
488 if (sc->re_type == RE_8139CPLUS && re8139_reg == RE_BMCR) {
489 /* 8139C+ has different bit layout. */
490 rval &= ~(BMCR_LOOP | BMCR_ISO);
491 }
492 return(rval);
493 }
494
495 static int
496 re_miibus_writereg(device_t dev, int phy, int reg, int data)
497 {
498 struct re_softc *sc= device_get_softc(dev);
499 u_int16_t re8139_reg = 0;
500
501 if (sc->re_type == RE_8169)
502 return(re_gmii_writereg(dev, phy, reg, data));
503
504 /* Pretend the internal PHY is only at address 0 */
505 if (phy)
506 return(0);
507
508 switch(reg) {
509 case MII_BMCR:
510 re8139_reg = RE_BMCR;
511 if (sc->re_type == RE_8139CPLUS) {
512 /* 8139C+ has different bit layout. */
513 data &= ~(BMCR_LOOP | BMCR_ISO);
514 }
515 break;
516 case MII_BMSR:
517 re8139_reg = RE_BMSR;
518 break;
519 case MII_ANAR:
520 re8139_reg = RE_ANAR;
521 break;
522 case MII_ANER:
523 re8139_reg = RE_ANER;
524 break;
525 case MII_ANLPAR:
526 re8139_reg = RE_LPAR;
527 break;
528 case MII_PHYIDR1:
529 case MII_PHYIDR2:
530 return(0);
531 default:
532 device_printf(dev, "bad phy register\n");
533 return(0);
534 }
535 CSR_WRITE_2(sc, re8139_reg, data);
536 return(0);
537 }
538
539 static void
540 re_miibus_statchg(device_t dev)
541 {
542 }
543
544 /*
545 * Program the 64-bit multicast hash filter.
546 */
547 static void
548 re_setmulti(struct re_softc *sc)
549 {
550 struct ifnet *ifp = &sc->arpcom.ac_if;
551 int h = 0;
552 uint32_t hashes[2] = { 0, 0 };
553 struct ifmultiaddr *ifma;
554 uint32_t rxfilt;
555 int mcnt = 0;
556
557 rxfilt = CSR_READ_4(sc, RE_RXCFG);
558
559 if (ifp->if_flags & IFF_ALLMULTI || ifp->if_flags & IFF_PROMISC) {
560 rxfilt |= RE_RXCFG_RX_MULTI;
561 CSR_WRITE_4(sc, RE_RXCFG, rxfilt);
562 CSR_WRITE_4(sc, RE_MAR0, 0xFFFFFFFF);
563 CSR_WRITE_4(sc, RE_MAR4, 0xFFFFFFFF);
564 return;
565 }
566
567 /* first, zot all the existing hash bits */
568 CSR_WRITE_4(sc, RE_MAR0, 0);
569 CSR_WRITE_4(sc, RE_MAR4, 0);
570
571 /* now program new ones */
572 LIST_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) {
573 if (ifma->ifma_addr->sa_family != AF_LINK)
574 continue;
575 h = ether_crc32_be(LLADDR((struct sockaddr_dl *)
576 ifma->ifma_addr), ETHER_ADDR_LEN) >> 26;
577 if (h < 32)
578 hashes[0] |= (1 << h);
579 else
580 hashes[1] |= (1 << (h - 32));
581 mcnt++;
582 }
583
584 if (mcnt)
585 rxfilt |= RE_RXCFG_RX_MULTI;
586 else
587 rxfilt &= ~RE_RXCFG_RX_MULTI;
588
589 CSR_WRITE_4(sc, RE_RXCFG, rxfilt);
590
591 /*
592 * For some unfathomable reason, RealTek decided to reverse
593 * the order of the multicast hash registers in the PCI Express
594 * parts. This means we have to write the hash pattern in reverse
595 * order for those devices.
596 */
597 if (sc->re_flags & RE_F_PCIE) {
598 CSR_WRITE_4(sc, RE_MAR0, bswap32(hashes[0]));
599 CSR_WRITE_4(sc, RE_MAR4, bswap32(hashes[1]));
600 } else {
601 CSR_WRITE_4(sc, RE_MAR0, hashes[0]);
602 CSR_WRITE_4(sc, RE_MAR4, hashes[1]);
603 }
604 }
605
606 static void
607 re_reset(struct re_softc *sc)
608 {
609 int i;
610
611 CSR_WRITE_1(sc, RE_COMMAND, RE_CMD_RESET);
612
613 for (i = 0; i < RE_TIMEOUT; i++) {
614 DELAY(10);
615 if ((CSR_READ_1(sc, RE_COMMAND) & RE_CMD_RESET) == 0)
616 break;
617 }
618 if (i == RE_TIMEOUT)
619 if_printf(&sc->arpcom.ac_if, "reset never completed!\n");
620
621 CSR_WRITE_1(sc, 0x82, 1);
622 }
623
624 #ifdef RE_DIAG
625 /*
626 * The following routine is designed to test for a defect on some
627 * 32-bit 8169 cards. Some of these NICs have the REQ64# and ACK64#
628 * lines connected to the bus, however for a 32-bit only card, they
629 * should be pulled high. The result of this defect is that the
630 * NIC will not work right if you plug it into a 64-bit slot: DMA
631 * operations will be done with 64-bit transfers, which will fail
632 * because the 64-bit data lines aren't connected.
633 *
634 * There's no way to work around this (short of talking a soldering
635 * iron to the board), however we can detect it. The method we use
636 * here is to put the NIC into digital loopback mode, set the receiver
637 * to promiscuous mode, and then try to send a frame. We then compare
638 * the frame data we sent to what was received. If the data matches,
639 * then the NIC is working correctly, otherwise we know the user has
640 * a defective NIC which has been mistakenly plugged into a 64-bit PCI
641 * slot. In the latter case, there's no way the NIC can work correctly,
642 * so we print out a message on the console and abort the device attach.
643 */
644
645 static int
646 re_diag(struct re_softc *sc)
647 {
648 struct ifnet *ifp = &sc->arpcom.ac_if;
649 struct mbuf *m0;
650 struct ether_header *eh;
651 struct re_desc *cur_rx;
652 uint16_t status;
653 uint32_t rxstat;
654 int total_len, i, error = 0, phyaddr;
655 uint8_t dst[ETHER_ADDR_LEN] = { 0x00, 'h', 'e', 'l', 'l', 'o' };
656 uint8_t src[ETHER_ADDR_LEN] = { 0x00, 'w', 'o', 'r', 'l', 'd' };
657
658 /* Allocate a single mbuf */
659
660 MGETHDR(m0, MB_DONTWAIT, MT_DATA);
661 if (m0 == NULL)
662 return(ENOBUFS);
663
664 /*
665 * Initialize the NIC in test mode. This sets the chip up
666 * so that it can send and receive frames, but performs the
667 * following special functions:
668 * - Puts receiver in promiscuous mode
669 * - Enables digital loopback mode
670 * - Leaves interrupts turned off
671 */
672
673 ifp->if_flags |= IFF_PROMISC;
674 sc->re_testmode = 1;
675 re_reset(sc);
676 re_init(sc);
677 sc->re_link = 1;
678 if (sc->re_type == RE_8169)
679 phyaddr = 1;
680 else
681 phyaddr = 0;
682
683 re_miibus_writereg(sc->re_dev, phyaddr, MII_BMCR, BMCR_RESET);
684 for (i = 0; i < RE_TIMEOUT; i++) {
685 status = re_miibus_readreg(sc->re_dev, phyaddr, MII_BMCR);
686 if (!(status & BMCR_RESET))
687 break;
688 }
689
690 re_miibus_writereg(sc->re_dev, phyaddr, MII_BMCR, BMCR_LOOP);
691 CSR_WRITE_2(sc, RE_ISR, RE_INTRS_DIAG);
692
693 DELAY(100000);
694
695 /* Put some data in the mbuf */
696
697 eh = mtod(m0, struct ether_header *);
698 bcopy (dst, eh->ether_dhost, ETHER_ADDR_LEN);
699 bcopy (src, eh->ether_shost, ETHER_ADDR_LEN);
700 eh->ether_type = htons(ETHERTYPE_IP);
701 m0->m_pkthdr.len = m0->m_len = ETHER_MIN_LEN - ETHER_CRC_LEN;
702
703 /*
704 * Queue the packet, start transmission.
705 * Note: ifq_handoff() ultimately calls re_start() for us.
706 */
707
708 CSR_WRITE_2(sc, RE_ISR, 0xFFFF);
709 error = ifq_handoff(ifp, m0, NULL);
710 if (error) {
711 m0 = NULL;
712 goto done;
713 }
714 m0 = NULL;
715
716 /* Wait for it to propagate through the chip */
717
718 DELAY(100000);
719 for (i = 0; i < RE_TIMEOUT; i++) {
720 status = CSR_READ_2(sc, RE_ISR);
721 CSR_WRITE_2(sc, RE_ISR, status);
722 if ((status & (RE_ISR_TIMEOUT_EXPIRED|RE_ISR_RX_OK)) ==
723 (RE_ISR_TIMEOUT_EXPIRED|RE_ISR_RX_OK))
724 break;
725 DELAY(10);
726 }
727
728 if (i == RE_TIMEOUT) {
729 if_printf(ifp, "diagnostic failed to receive packet "
730 "in loopback mode\n");
731 error = EIO;
732 goto done;
733 }
734
735 /*
736 * The packet should have been dumped into the first
737 * entry in the RX DMA ring. Grab it from there.
738 */
739
740 bus_dmamap_sync(sc->re_ldata.re_rx_list_tag,
741 sc->re_ldata.re_rx_list_map, BUS_DMASYNC_POSTREAD);
742 bus_dmamap_sync(sc->re_ldata.re_mtag, sc->re_ldata.re_rx_dmamap[0],
743 BUS_DMASYNC_POSTWRITE);
744 bus_dmamap_unload(sc->re_ldata.re_mtag, sc->re_ldata.re_rx_dmamap[0]);
745
746 m0 = sc->re_ldata.re_rx_mbuf[0];
747 sc->re_ldata.re_rx_mbuf[0] = NULL;
748 eh = mtod(m0, struct ether_header *);
749
750 cur_rx = &sc->re_ldata.re_rx_list[0];
751 total_len = RE_RXBYTES(cur_rx);
752 rxstat = le32toh(cur_rx->re_cmdstat);
753
754 if (total_len != ETHER_MIN_LEN) {
755 if_printf(ifp, "diagnostic failed, received short packet\n");
756 error = EIO;
757 goto done;
758 }
759
760 /* Test that the received packet data matches what we sent. */
761
762 if (bcmp(eh->ether_dhost, dst, ETHER_ADDR_LEN) ||
763 bcmp(eh->ether_shost, &src, ETHER_ADDR_LEN) ||
764 be16toh(eh->ether_type) != ETHERTYPE_IP) {
765 if_printf(ifp, "WARNING, DMA FAILURE!\n");
766 if_printf(ifp, "expected TX data: %6D/%6D/0x%x\n",
767 dst, ":", src, ":", ETHERTYPE_IP);
768 if_printf(ifp, "received RX data: %6D/%6D/0x%x\n",
769 eh->ether_dhost, ":", eh->ether_shost, ":",
770 ntohs(eh->ether_type));
771 if_printf(ifp, "You may have a defective 32-bit NIC plugged "
772 "into a 64-bit PCI slot.\n");
773 if_printf(ifp, "Please re-install the NIC in a 32-bit slot "
774 "for proper operation.\n");
775 if_printf(ifp, "Read the re(4) man page for more details.\n");
776 error = EIO;
777 }
778
779 done:
780 /* Turn interface off, release resources */
781
782 sc->re_testmode = 0;
783 sc->re_link = 0;
784 ifp->if_flags &= ~IFF_PROMISC;
785 re_stop(sc);
786 if (m0 != NULL)
787 m_freem(m0);
788
789 return (error);
790 }
791 #endif /* RE_DIAG */
792
793 /*
794 * Probe for a RealTek 8139C+/8169/8110 chip. Check the PCI vendor and device
795 * IDs against our list and return a device name if we find a match.
796 */
797 static int
798 re_probe(device_t dev)
799 {
800 const struct re_type *t;
801 struct re_softc *sc;
802 int rid;
803 uint32_t hwrev;
804 uint16_t vendor, product;
805
806 t = re_devs;
807
808 vendor = pci_get_vendor(dev);
809 product = pci_get_device(dev);
810
811 /*
812 * Only attach to rev.3 of the Linksys EG1032 adapter.
813 * Rev.2 is supported by sk(4).
814 */
815 if (vendor == PCI_VENDOR_LINKSYS &&
816 product == PCI_PRODUCT_LINKSYS_EG1032 &&
817 pci_get_subdevice(dev) != PCI_SUBDEVICE_LINKSYS_EG1032_REV3)
818 return ENXIO;
819
820 for (t = re_devs; t->re_name != NULL; t++) {
821 if (product == t->re_did && vendor == t->re_vid)
822 break;
823 }
824
825 /*
826 * Check if we found a RealTek device.
827 */
828 if (t->re_name == NULL)
829 return(ENXIO);
830
831 /*
832 * Temporarily map the I/O space so we can read the chip ID register.
833 */
834 sc = kmalloc(sizeof(*sc), M_TEMP, M_WAITOK | M_ZERO);
835 rid = RE_PCI_LOIO;
836 sc->re_res = bus_alloc_resource_any(dev, SYS_RES_IOPORT, &rid,
837 RF_ACTIVE);
838 if (sc->re_res == NULL) {
839 device_printf(dev, "couldn't map ports/memory\n");
840 kfree(sc, M_TEMP);
841 return(ENXIO);
842 }
843
844 sc->re_btag = rman_get_bustag(sc->re_res);
845 sc->re_bhandle = rman_get_bushandle(sc->re_res);
846
847 hwrev = CSR_READ_4(sc, RE_TXCFG) & RE_TXCFG_HWREV;
848 bus_release_resource(dev, SYS_RES_IOPORT, RE_PCI_LOIO, sc->re_res);
849 kfree(sc, M_TEMP);
850
851 /*
852 * and continue matching for the specific chip...
853 */
854 for (; t->re_name != NULL; t++) {
855 if (product == t->re_did && vendor == t->re_vid &&
856 t->re_basetype == hwrev) {
857 device_set_desc(dev, t->re_name);
858 return(0);
859 }
860 }
861
862 if (bootverbose)
863 kprintf("re: unknown hwrev %#x\n", hwrev);
864 return(ENXIO);
865 }
866
867 /*
868 * This routine takes the segment list provided as the result of
869 * a bus_dma_map_load() operation and assigns the addresses/lengths
870 * to RealTek DMA descriptors. This can be called either by the RX
871 * code or the TX code. In the RX case, we'll probably wind up mapping
872 * at most one segment. For the TX case, there could be any number of
873 * segments since TX packets may span multiple mbufs. In either case,
874 * if the number of segments is larger than the re_maxsegs limit
875 * specified by the caller, we abort the mapping operation. Sadly,
876 * whoever designed the buffer mapping API did not provide a way to
877 * return an error from here, so we have to fake it a bit.
878 */
879
880 static void
881 re_dma_map_desc(void *arg, bus_dma_segment_t *segs, int nseg,
882 bus_size_t mapsize, int error)
883 {
884 struct re_dmaload_arg *ctx;
885 struct re_desc *d = NULL;
886 int i = 0, idx;
887 uint32_t cmdstat;
888
889 if (error)
890 return;
891
892 ctx = arg;
893
894 /* Signal error to caller if there's too many segments */
895 if (nseg > ctx->re_maxsegs) {
896 ctx->re_maxsegs = 0;
897 return;
898 }
899
900 /*
901 * Map the segment array into descriptors. Note that we set the
902 * start-of-frame and end-of-frame markers for either TX or RX, but
903 * they really only have meaning in the TX case. (In the RX case,
904 * it's the chip that tells us where packets begin and end.)
905 * We also keep track of the end of the ring and set the
906 * end-of-ring bits as needed, and we set the ownership bits
907 * in all except the very first descriptor. (The caller will
908 * set this descriptor later when it start transmission or
909 * reception.)
910 */
911 idx = ctx->re_idx;
912 for (;;) {
913 d = &ctx->re_ring[idx];
914 if (le32toh(d->re_cmdstat) & RE_RDESC_STAT_OWN) {
915 ctx->re_maxsegs = 0;
916 return;
917 }
918 cmdstat = segs[i].ds_len;
919 d->re_bufaddr_lo = htole32(RE_ADDR_LO(segs[i].ds_addr));
920 d->re_bufaddr_hi = htole32(RE_ADDR_HI(segs[i].ds_addr));
921 if (i == 0)
922 cmdstat |= RE_TDESC_CMD_SOF;
923 else
924 cmdstat |= RE_TDESC_CMD_OWN;
925 if (idx == (RE_RX_DESC_CNT - 1))
926 cmdstat |= RE_TDESC_CMD_EOR;
927 d->re_cmdstat = htole32(cmdstat | ctx->re_flags);
928 i++;
929 if (i == nseg)
930 break;
931 RE_DESC_INC(idx);
932 }
933
934 d->re_cmdstat |= htole32(RE_TDESC_CMD_EOF);
935 ctx->re_maxsegs = nseg;
936 ctx->re_idx = idx;
937 }
938
939 /*
940 * Map a single buffer address.
941 */
942
943 static void
944 re_dma_map_addr(void *arg, bus_dma_segment_t *segs, int nseg, int error)
945 {
946 uint32_t *addr;
947
948 if (error)
949 return;
950
951 KASSERT(nseg == 1, ("too many DMA segments, %d should be 1", nseg));
952 addr = arg;
953 *addr = segs->ds_addr;
954 }
955
956 static int
957 re_allocmem(device_t dev, struct re_softc *sc)
958 {
959 int error, i, nseg;
960
961 /*
962 * Allocate map for RX mbufs.
963 */
964 nseg = 32;
965 error = bus_dma_tag_create(sc->re_parent_tag, ETHER_ALIGN, 0,
966 BUS_SPACE_MAXADDR_32BIT, BUS_SPACE_MAXADDR, NULL,
967 NULL, MCLBYTES * nseg, nseg, MCLBYTES, BUS_DMA_ALLOCNOW,
968 &sc->re_ldata.re_mtag);
969 if (error) {
970 device_printf(dev, "could not allocate dma tag\n");
971 return(error);
972 }
973
974 /*
975 * Allocate map for TX descriptor list.
976 */
977 error = bus_dma_tag_create(sc->re_parent_tag, RE_RING_ALIGN,
978 0, BUS_SPACE_MAXADDR_32BIT, BUS_SPACE_MAXADDR, NULL,
979 NULL, RE_TX_LIST_SZ, 1, RE_TX_LIST_SZ, BUS_DMA_ALLOCNOW,
980 &sc->re_ldata.re_tx_list_tag);
981 if (error) {
982 device_printf(dev, "could not allocate dma tag\n");
983 return(error);
984 }
985
986 /* Allocate DMA'able memory for the TX ring */
987
988 error = bus_dmamem_alloc(sc->re_ldata.re_tx_list_tag,
989 (void **)&sc->re_ldata.re_tx_list, BUS_DMA_WAITOK | BUS_DMA_ZERO,
990 &sc->re_ldata.re_tx_list_map);
991 if (error) {
992 device_printf(dev, "could not allocate TX ring\n");
993 return(error);
994 }
995
996 /* Load the map for the TX ring. */
997
998 error = bus_dmamap_load(sc->re_ldata.re_tx_list_tag,
999 sc->re_ldata.re_tx_list_map, sc->re_ldata.re_tx_list,
1000 RE_TX_LIST_SZ, re_dma_map_addr,
1001 &sc->re_ldata.re_tx_list_addr, BUS_DMA_NOWAIT);
1002 if (error) {
1003 device_printf(dev, "could not get address of TX ring\n");
1004 return(error);
1005 }
1006
1007 /* Create DMA maps for TX buffers */
1008
1009 for (i = 0; i < RE_TX_DESC_CNT; i++) {
1010 error = bus_dmamap_create(sc->re_ldata.re_mtag, 0,
1011 &sc->re_ldata.re_tx_dmamap[i]);
1012 if (error) {
1013 device_printf(dev, "can't create DMA map for TX\n");
1014 return(error);
1015 }
1016 }
1017
1018 /*
1019 * Allocate map for RX descriptor list.
1020 */
1021 error = bus_dma_tag_create(sc->re_parent_tag, RE_RING_ALIGN,
1022 0, BUS_SPACE_MAXADDR_32BIT, BUS_SPACE_MAXADDR, NULL,
1023 NULL, RE_RX_LIST_SZ, 1, RE_RX_LIST_SZ, BUS_DMA_ALLOCNOW,
1024 &sc->re_ldata.re_rx_list_tag);
1025 if (error) {
1026 device_printf(dev, "could not allocate dma tag\n");
1027 return(error);
1028 }
1029
1030 /* Allocate DMA'able memory for the RX ring */
1031
1032 error = bus_dmamem_alloc(sc->re_ldata.re_rx_list_tag,
1033 (void **)&sc->re_ldata.re_rx_list, BUS_DMA_WAITOK | BUS_DMA_ZERO,
1034 &sc->re_ldata.re_rx_list_map);
1035 if (error) {
1036 device_printf(dev, "could not allocate RX ring\n");
1037 return(error);
1038 }
1039
1040 /* Load the map for the RX ring. */
1041
1042 error = bus_dmamap_load(sc->re_ldata.re_rx_list_tag,
1043 sc->re_ldata.re_rx_list_map, sc->re_ldata.re_rx_list,
1044 RE_RX_LIST_SZ, re_dma_map_addr,
1045 &sc->re_ldata.re_rx_list_addr, BUS_DMA_NOWAIT);
1046 if (error) {
1047 device_printf(dev, "could not get address of RX ring\n");
1048 return(error);
1049 }
1050
1051 /* Create DMA maps for RX buffers */
1052
1053 for (i = 0; i < RE_RX_DESC_CNT; i++) {
1054 error = bus_dmamap_create(sc->re_ldata.re_mtag, 0,
1055 &sc->re_ldata.re_rx_dmamap[i]);
1056 if (error) {
1057 device_printf(dev, "can't create DMA map for RX\n");
1058 return(ENOMEM);
1059 }
1060 }
1061
1062 return(0);
1063 }
1064
1065 /*
1066 * Attach the interface. Allocate softc structures, do ifmedia
1067 * setup and ethernet/BPF attach.
1068 */
1069 static int
1070 re_attach(device_t dev)
1071 {
1072 struct re_softc *sc = device_get_softc(dev);
1073 struct ifnet *ifp;
1074 const struct re_hwrev *hw_rev;
1075 uint8_t eaddr[ETHER_ADDR_LEN];
1076 uint16_t as[ETHER_ADDR_LEN / 2];
1077 uint16_t re_did = 0;
1078 uint32_t hwrev;
1079 int error = 0, rid, i;
1080
1081 callout_init(&sc->re_timer);
1082 #ifdef RE_DIAG
1083 sc->re_dev = dev;
1084 #endif
1085
1086 RE_ENABLE_TX_MODERATION(sc);
1087
1088 sysctl_ctx_init(&sc->re_sysctl_ctx);
1089 sc->re_sysctl_tree = SYSCTL_ADD_NODE(&sc->re_sysctl_ctx,
1090 SYSCTL_STATIC_CHILDREN(_hw),
1091 OID_AUTO,
1092 device_get_nameunit(dev),
1093 CTLFLAG_RD, 0, "");
1094 if (sc->re_sysctl_tree == NULL) {
1095 device_printf(dev, "can't add sysctl node\n");
1096 error = ENXIO;
1097 goto fail;
1098 }
1099 SYSCTL_ADD_PROC(&sc->re_sysctl_ctx,
1100 SYSCTL_CHILDREN(sc->re_sysctl_tree),
1101 OID_AUTO, "tx_moderation",
1102 CTLTYPE_INT | CTLFLAG_RW,
1103 sc, 0, re_sysctl_tx_moderation, "I",
1104 "Enable/Disable TX moderation");
1105
1106 #ifndef BURN_BRIDGES
1107 /*
1108 * Handle power management nonsense.
1109 */
1110
1111 if (pci_get_powerstate(dev) != PCI_POWERSTATE_D0) {
1112 uint32_t membase, irq;
1113
1114 /* Save important PCI config data. */
1115 membase = pci_read_config(dev, RE_PCI_LOMEM, 4);
1116 irq = pci_read_config(dev, PCIR_INTLINE, 4);
1117
1118 /* Reset the power state. */
1119 device_printf(dev, "chip is in D%d power mode "
1120 "-- setting to D0\n", pci_get_powerstate(dev));
1121
1122 pci_set_powerstate(dev, PCI_POWERSTATE_D0);
1123
1124 /* Restore PCI config data. */
1125 pci_write_config(dev, RE_PCI_LOMEM, membase, 4);
1126 pci_write_config(dev, PCIR_INTLINE, irq, 4);
1127 }
1128 #endif
1129 /*
1130 * Map control/status registers.
1131 */
1132 pci_enable_busmaster(dev);
1133
1134 rid = RE_PCI_LOIO;
1135 sc->re_res = bus_alloc_resource_any(dev, SYS_RES_IOPORT, &rid,
1136 RF_ACTIVE);
1137
1138 if (sc->re_res == NULL) {
1139 device_printf(dev, "couldn't map ports\n");
1140 error = ENXIO;
1141 goto fail;
1142 }
1143
1144 sc->re_btag = rman_get_bustag(sc->re_res);
1145 sc->re_bhandle = rman_get_bushandle(sc->re_res);
1146
1147 /* Allocate interrupt */
1148 rid = 0;
1149 sc->re_irq = bus_alloc_resource_any(dev, SYS_RES_IRQ, &rid,
1150 RF_SHAREABLE | RF_ACTIVE);
1151
1152 if (sc->re_irq == NULL) {
1153 device_printf(dev, "couldn't map interrupt\n");
1154 error = ENXIO;
1155 goto fail;
1156 }
1157
1158 /* Reset the adapter. */
1159 re_reset(sc);
1160
1161 hwrev = CSR_READ_4(sc, RE_TXCFG) & RE_TXCFG_HWREV;
1162 for (hw_rev = re_hwrevs; hw_rev->re_desc != NULL; hw_rev++) {
1163 if (hw_rev->re_rev == hwrev) {
1164 sc->re_type = hw_rev->re_type;
1165 sc->re_flags = hw_rev->re_flags;
1166 break;
1167 }
1168 }
1169
1170 sc->re_eewidth = 6;
1171 re_read_eeprom(sc, (caddr_t)&re_did, 0, 1);
1172 if (re_did != 0x8129)
1173 sc->re_eewidth = 8;
1174
1175 /*
1176 * Get station address from the EEPROM.
1177 */
1178 re_read_eeprom(sc, (caddr_t)as, RE_EE_EADDR, 3);
1179 for (i = 0; i < ETHER_ADDR_LEN / 2; i++)
1180 as[i] = le16toh(as[i]);
1181 bcopy(as, eaddr, sizeof(eaddr));
1182
1183 if (sc->re_type == RE_8169) {
1184 /* Set RX length mask */
1185 sc->re_rxlenmask = RE_RDESC_STAT_GFRAGLEN;
1186 sc->re_txstart = RE_GTXSTART;
1187 } else {
1188 /* Set RX length mask */
1189 sc->re_rxlenmask = RE_RDESC_STAT_FRAGLEN;
1190 sc->re_txstart = RE_TXSTART;
1191 }
1192
1193 /*
1194 * Allocate the parent bus DMA tag appropriate for PCI.
1195 */
1196 #define RE_NSEG_NEW 32
1197 error = bus_dma_tag_create(NULL, /* parent */
1198 1, 0, /* alignment, boundary */
1199 BUS_SPACE_MAXADDR_32BIT,/* lowaddr */
1200 BUS_SPACE_MAXADDR, /* highaddr */
1201 NULL, NULL, /* filter, filterarg */
1202 MAXBSIZE, RE_NSEG_NEW, /* maxsize, nsegments */
1203 BUS_SPACE_MAXSIZE_32BIT,/* maxsegsize */
1204 BUS_DMA_ALLOCNOW, /* flags */
1205 &sc->re_parent_tag);
1206 if (error)
1207 goto fail;
1208
1209 error = re_allocmem(dev, sc);
1210
1211 if (error)
1212 goto fail;
1213
1214 /* Do MII setup */
1215 if (mii_phy_probe(dev, &sc->re_miibus,
1216 re_ifmedia_upd, re_ifmedia_sts)) {
1217 device_printf(dev, "MII without any phy!\n");
1218 error = ENXIO;
1219 goto fail;
1220 }
1221
1222 ifp = &sc->arpcom.ac_if;
1223 ifp->if_softc = sc;
1224 if_initname(ifp, device_get_name(dev), device_get_unit(dev));
1225 ifp->if_mtu = ETHERMTU;
1226 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST;
1227 ifp->if_ioctl = re_ioctl;
1228 ifp->if_start = re_start;
1229 ifp->if_capabilities = IFCAP_VLAN_MTU | IFCAP_VLAN_HWTAGGING;
1230 if (hwrev != RE_HWREV_8168C) /* XXX does not work yet */
1231 ifp->if_capabilities |= IFCAP_HWCSUM;
1232 #ifdef DEVICE_POLLING
1233 ifp->if_poll = re_poll;
1234 #endif
1235 ifp->if_watchdog = re_watchdog;
1236 ifp->if_init = re_init;
1237 if (sc->re_type == RE_8169)
1238 ifp->if_baudrate = 1000000000;
1239 else
1240 ifp->if_baudrate = 100000000;
1241 ifq_set_maxlen(&ifp->if_snd, RE_IFQ_MAXLEN);
1242 ifq_set_ready(&ifp->if_snd);
1243
1244 #ifdef RE_DISABLE_HWCSUM
1245 ifp->if_capenable = ifp->if_capabilities & ~IFCAP_HWCSUM;
1246 ifp->if_hwassist = 0;
1247 #else
1248 ifp->if_capenable = ifp->if_capabilities;
1249 if (ifp->if_capabilities & IFCAP_HWCSUM)
1250 ifp->if_hwassist = RE_CSUM_FEATURES;
1251 else
1252 ifp->if_hwassist = 0;
1253 #endif /* RE_DISABLE_HWCSUM */
1254
1255 /*
1256 * Call MI attach routine.
1257 */
1258 ether_ifattach(ifp, eaddr, NULL);
1259
1260 #ifdef RE_DIAG
1261 /*
1262 * Perform hardware diagnostic on the original RTL8169.
1263 * Some 32-bit cards were incorrectly wired and would
1264 * malfunction if plugged into a 64-bit slot.
1265 */
1266 if (hwrev == RE_HWREV_8169) {
1267 lwkt_serialize_enter(ifp->if_serializer);
1268 error = re_diag(sc);
1269 lwkt_serialize_exit(ifp->if_serializer);
1270
1271 if (error) {
1272 device_printf(dev, "hardware diagnostic failure\n");
1273 ether_ifdetach(ifp);
1274 goto fail;
1275 }
1276 }
1277 #endif /* RE_DIAG */
1278
1279 /* Hook interrupt last to avoid having to lock softc */
1280 error = bus_setup_intr(dev, sc->re_irq, INTR_NETSAFE, re_intr, sc,
1281 &sc->re_intrhand, ifp->if_serializer);
1282
1283 if (error) {
1284 device_printf(dev, "couldn't set up irq\n");
1285 ether_ifdetach(ifp);
1286 goto fail;
1287 }
1288
1289 ifp->if_cpuid = ithread_cpuid(rman_get_start(sc->re_irq));
1290 KKASSERT(ifp->if_cpuid >= 0 && ifp->if_cpuid < ncpus);
1291
1292 fail:
1293 if (error)
1294 re_detach(dev);
1295
1296 return (error);
1297 }
1298
1299 /*
1300 * Shutdown hardware and free up resources. This can be called any
1301 * time after the mutex has been initialized. It is called in both
1302 * the error case in attach and the normal detach case so it needs
1303 * to be careful about only freeing resources that have actually been
1304 * allocated.
1305 */
1306 static int
1307 re_detach(device_t dev)
1308 {
1309 struct re_softc *sc = device_get_softc(dev);
1310 struct ifnet *ifp = &sc->arpcom.ac_if;
1311 int i;
1312
1313 /* These should only be active if attach succeeded */
1314 if (device_is_attached(dev)) {
1315 lwkt_serialize_enter(ifp->if_serializer);
1316 re_stop(sc);
1317 bus_teardown_intr(dev, sc->re_irq, sc->re_intrhand);
1318 lwkt_serialize_exit(ifp->if_serializer);
1319
1320 ether_ifdetach(ifp);
1321 }
1322 if (sc->re_miibus)
1323 device_delete_child(dev, sc->re_miibus);
1324 bus_generic_detach(dev);
1325
1326 if (sc->re_irq)
1327 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->re_irq);
1328 if (sc->re_res) {
1329 bus_release_resource(dev, SYS_RES_IOPORT, RE_PCI_LOIO,
1330 sc->re_res);
1331 }
1332
1333 /* Unload and free the RX DMA ring memory and map */
1334
1335 if (sc->re_ldata.re_rx_list_tag) {
1336 bus_dmamap_unload(sc->re_ldata.re_rx_list_tag,
1337 sc->re_ldata.re_rx_list_map);
1338 bus_dmamem_free(sc->re_ldata.re_rx_list_tag,
1339 sc->re_ldata.re_rx_list,
1340 sc->re_ldata.re_rx_list_map);
1341 bus_dma_tag_destroy(sc->re_ldata.re_rx_list_tag);
1342 }
1343
1344 /* Unload and free the TX DMA ring memory and map */
1345
1346 if (sc->re_ldata.re_tx_list_tag) {
1347 bus_dmamap_unload(sc->re_ldata.re_tx_list_tag,
1348 sc->re_ldata.re_tx_list_map);
1349 bus_dmamem_free(sc->re_ldata.re_tx_list_tag,
1350 sc->re_ldata.re_tx_list,
1351 sc->re_ldata.re_tx_list_map);
1352 bus_dma_tag_destroy(sc->re_ldata.re_tx_list_tag);
1353 }
1354
1355 /* Destroy all the RX and TX buffer maps */
1356
1357 if (sc->re_ldata.re_mtag) {
1358 for (i = 0; i < RE_TX_DESC_CNT; i++)
1359 bus_dmamap_destroy(sc->re_ldata.re_mtag,
1360 sc->re_ldata.re_tx_dmamap[i]);
1361 for (i = 0; i < RE_RX_DESC_CNT; i++)
1362 bus_dmamap_destroy(sc->re_ldata.re_mtag,
1363 sc->re_ldata.re_rx_dmamap[i]);
1364 bus_dma_tag_destroy(sc->re_ldata.re_mtag);
1365 }
1366
1367 /* Unload and free the stats buffer and map */
1368
1369 if (sc->re_ldata.re_stag) {
1370 bus_dmamap_unload(sc->re_ldata.re_stag,
1371 sc->re_ldata.re_rx_list_map);
1372 bus_dmamem_free(sc->re_ldata.re_stag,
1373 sc->re_ldata.re_stats,
1374 sc->re_ldata.re_smap);
1375 bus_dma_tag_destroy(sc->re_ldata.re_stag);
1376 }
1377
1378 if (sc->re_parent_tag)
1379 bus_dma_tag_destroy(sc->re_parent_tag);
1380
1381 return(0);
1382 }
1383
1384 static int
1385 re_newbuf(struct re_softc *sc, int idx, struct mbuf *m)
1386 {
1387 struct re_dmaload_arg arg;
1388 struct mbuf *n = NULL;
1389 int error;
1390
1391 if (m == NULL) {
1392 n = m_getcl(MB_DONTWAIT, MT_DATA, M_PKTHDR);
1393 if (n == NULL)
1394 return(ENOBUFS);
1395 m = n;
1396 } else
1397 m->m_data = m->m_ext.ext_buf;
1398
1399 m->m_len = m->m_pkthdr.len = MCLBYTES;
1400
1401 /*
1402 * NOTE:
1403 * Some re(4) chips(e.g. RTL8101E) need address of the receive buffer
1404 * to be 8-byte aligned, so don't call m_adj(m, ETHER_ALIGN) here.
1405 */
1406
1407 arg.sc = sc;
1408 arg.re_idx = idx;
1409 arg.re_maxsegs = 1;
1410 arg.re_flags = 0;
1411 arg.re_ring = sc->re_ldata.re_rx_list;
1412
1413 error = bus_dmamap_load_mbuf(sc->re_ldata.re_mtag,
1414 sc->re_ldata.re_rx_dmamap[idx], m, re_dma_map_desc,
1415 &arg, BUS_DMA_NOWAIT);
1416 if (error || arg.re_maxsegs != 1) {
1417 if (n != NULL)
1418 m_freem(n);
1419 return (ENOMEM);
1420 }
1421
1422 sc->re_ldata.re_rx_list[idx].re_cmdstat |= htole32(RE_RDESC_CMD_OWN);
1423 sc->re_ldata.re_rx_mbuf[idx] = m;
1424
1425 bus_dmamap_sync(sc->re_ldata.re_mtag, sc->re_ldata.re_rx_dmamap[idx],
1426 BUS_DMASYNC_PREREAD);
1427
1428 return(0);
1429 }
1430
1431 static int
1432 re_tx_list_init(struct re_softc *sc)
1433 {
1434 bzero(sc->re_ldata.re_tx_list, RE_TX_LIST_SZ);
1435 bzero(&sc->re_ldata.re_tx_mbuf, RE_TX_DESC_CNT * sizeof(struct mbuf *));
1436
1437 bus_dmamap_sync(sc->re_ldata.re_tx_list_tag,
1438 sc->re_ldata.re_tx_list_map, BUS_DMASYNC_PREWRITE);
1439 sc->re_ldata.re_tx_prodidx = 0;
1440 sc->re_ldata.re_tx_considx = 0;
1441 sc->re_ldata.re_tx_free = RE_TX_DESC_CNT;
1442
1443 return(0);
1444 }
1445
1446 static int
1447 re_rx_list_init(struct re_softc *sc)
1448 {
1449 int i, error;
1450
1451 bzero(sc->re_ldata.re_rx_list, RE_RX_LIST_SZ);
1452 bzero(&sc->re_ldata.re_rx_mbuf, RE_RX_DESC_CNT * sizeof(struct mbuf *));
1453
1454 for (i = 0; i < RE_RX_DESC_CNT; i++) {
1455 error = re_newbuf(sc, i, NULL);
1456 if (error)
1457 return(error);
1458 }
1459
1460 /* Flush the RX descriptors */
1461
1462 bus_dmamap_sync(sc->re_ldata.re_rx_list_tag,
1463 sc->re_ldata.re_rx_list_map, BUS_DMASYNC_PREWRITE);
1464
1465 sc->re_ldata.re_rx_prodidx = 0;
1466 sc->re_head = sc->re_tail = NULL;
1467
1468 return(0);
1469 }
1470
1471 /*
1472 * RX handler for C+ and 8169. For the gigE chips, we support
1473 * the reception of jumbo frames that have been fragmented
1474 * across multiple 2K mbuf cluster buffers.
1475 */
1476 static void
1477 re_rxeof(struct re_softc *sc)
1478 {
1479 struct ifnet *ifp = &sc->arpcom.ac_if;
1480 struct mbuf *m;
1481 struct re_desc *cur_rx;
1482 uint32_t rxstat, rxvlan;
1483 int i, total_len;
1484
1485 /* Invalidate the descriptor memory */
1486
1487 bus_dmamap_sync(sc->re_ldata.re_rx_list_tag,
1488 sc->re_ldata.re_rx_list_map, BUS_DMASYNC_POSTREAD);
1489
1490 for (i = sc->re_ldata.re_rx_prodidx;
1491 RE_OWN(&sc->re_ldata.re_rx_list[i]) == 0 ; RE_DESC_INC(i)) {
1492 cur_rx = &sc->re_ldata.re_rx_list[i];
1493 m = sc->re_ldata.re_rx_mbuf[i];
1494 total_len = RE_RXBYTES(cur_rx);
1495 rxstat = le32toh(cur_rx->re_cmdstat);
1496 rxvlan = le32toh(cur_rx->re_vlanctl);
1497
1498 /* Invalidate the RX mbuf and unload its map */
1499
1500 bus_dmamap_sync(sc->re_ldata.re_mtag,
1501 sc->re_ldata.re_rx_dmamap[i],
1502 BUS_DMASYNC_POSTWRITE);
1503 bus_dmamap_unload(sc->re_ldata.re_mtag,
1504 sc->re_ldata.re_rx_dmamap[i]);
1505
1506 if ((rxstat & RE_RDESC_STAT_EOF) == 0) {
1507 m->m_len = MCLBYTES - ETHER_ALIGN;
1508 if (sc->re_head == NULL) {
1509 sc->re_head = sc->re_tail = m;
1510 } else {
1511 sc->re_tail->m_next = m;
1512 sc->re_tail = m;
1513 }
1514 re_newbuf(sc, i, NULL);
1515 continue;
1516 }
1517
1518 /*
1519 * NOTE: for the 8139C+, the frame length field
1520 * is always 12 bits in size, but for the gigE chips,
1521 * it is 13 bits (since the max RX frame length is 16K).
1522 * Unfortunately, all 32 bits in the status word
1523 * were already used, so to make room for the extra
1524 * length bit, RealTek took out the 'frame alignment
1525 * error' bit and shifted the other status bits
1526 * over one slot. The OWN, EOR, FS and LS bits are
1527 * still in the same places. We have already extracted
1528 * the frame length and checked the OWN bit, so rather
1529 * than using an alternate bit mapping, we shift the
1530 * status bits one space to the right so we can evaluate
1531 * them using the 8169 status as though it was in the
1532 * same format as that of the 8139C+.
1533 */
1534 if (sc->re_type == RE_8169)
1535 rxstat >>= 1;
1536
1537 if (rxstat & RE_RDESC_STAT_RXERRSUM) {
1538 ifp->if_ierrors++;
1539 /*
1540 * If this is part of a multi-fragment packet,
1541 * discard all the pieces.
1542 */
1543 if (sc->re_head != NULL) {
1544 m_freem(sc->re_head);
1545 sc->re_head = sc->re_tail = NULL;
1546 }
1547 re_newbuf(sc, i, m);
1548 continue;
1549 }
1550
1551 /*
1552 * If allocating a replacement mbuf fails,
1553 * reload the current one.
1554 */
1555
1556 if (re_newbuf(sc, i, NULL)) {
1557 ifp->if_ierrors++;
1558 if (sc->re_head != NULL) {
1559 m_freem(sc->re_head);
1560 sc->re_head = sc->re_tail = NULL;
1561 }
1562 re_newbuf(sc, i, m);
1563 continue;
1564 }
1565
1566 if (sc->re_head != NULL) {
1567 m->m_len = total_len % (MCLBYTES - ETHER_ALIGN);
1568 /*
1569 * Special case: if there's 4 bytes or less
1570 * in this buffer, the mbuf can be discarded:
1571 * the last 4 bytes is the CRC, which we don't
1572 * care about anyway.
1573 */
1574 if (m->m_len <= ETHER_CRC_LEN) {
1575 sc->re_tail->m_len -=
1576 (ETHER_CRC_LEN - m->m_len);
1577 m_freem(m);
1578 } else {
1579 m->m_len -= ETHER_CRC_LEN;
1580 sc->re_tail->m_next = m;
1581 }
1582 m = sc->re_head;
1583 sc->re_head = sc->re_tail = NULL;
1584 m->m_pkthdr.len = total_len - ETHER_CRC_LEN;
1585 } else
1586 m->m_pkthdr.len = m->m_len =
1587 (total_len - ETHER_CRC_LEN);
1588
1589 ifp->if_ipackets++;
1590 m->m_pkthdr.rcvif = ifp;
1591
1592 /* Do RX checksumming if enabled */
1593
1594 if (ifp->if_capenable & IFCAP_RXCSUM) {
1595
1596 /* Check IP header checksum */
1597 if (rxstat & RE_RDESC_STAT_PROTOID)
1598 m->m_pkthdr.csum_flags |= CSUM_IP_CHECKED;
1599 if ((rxstat & RE_RDESC_STAT_IPSUMBAD) == 0)
1600 m->m_pkthdr.csum_flags |= CSUM_IP_VALID;
1601
1602 /* Check TCP/UDP checksum */
1603 if ((RE_TCPPKT(rxstat) &&
1604 (rxstat & RE_RDESC_STAT_TCPSUMBAD) == 0) ||
1605 (RE_UDPPKT(rxstat) &&
1606 (rxstat & RE_RDESC_STAT_UDPSUMBAD)) == 0) {
1607 m->m_pkthdr.csum_flags |=
1608 CSUM_DATA_VALID|CSUM_PSEUDO_HDR|
1609 CSUM_FRAG_NOT_CHECKED;
1610 m->m_pkthdr.csum_data = 0xffff;
1611 }
1612 }
1613
1614 if (rxvlan & RE_RDESC_VLANCTL_TAG) {
1615 m->m_flags |= M_VLANTAG;
1616 m->m_pkthdr.ether_vlantag =
1617 be16toh((rxvlan & RE_RDESC_VLANCTL_DATA));
1618 }
1619 ifp->if_input(ifp, m);
1620 }
1621
1622 /* Flush the RX DMA ring */
1623
1624 bus_dmamap_sync(sc->re_ldata.re_rx_list_tag,
1625 sc->re_ldata.re_rx_list_map, BUS_DMASYNC_PREWRITE);
1626
1627 sc->re_ldata.re_rx_prodidx = i;
1628 }
1629
1630 static void
1631 re_txeof(struct re_softc *sc)
1632 {
1633 struct ifnet *ifp = &sc->arpcom.ac_if;
1634 uint32_t txstat;
1635 int idx;
1636
1637 /* Invalidate the TX descriptor list */
1638
1639 bus_dmamap_sync(sc->re_ldata.re_tx_list_tag,
1640 sc->re_ldata.re_tx_list_map, BUS_DMASYNC_POSTREAD);
1641
1642 for (idx = sc->re_ldata.re_tx_considx;
1643 sc->re_ldata.re_tx_free < RE_TX_DESC_CNT; RE_DESC_INC(idx)) {
1644 txstat = le32toh(sc->re_ldata.re_tx_list[idx].re_cmdstat);
1645 if (txstat & RE_TDESC_CMD_OWN)
1646 break;
1647
1648 sc->re_ldata.re_tx_list[idx].re_bufaddr_lo = 0;
1649
1650 /*
1651 * We only stash mbufs in the last descriptor
1652 * in a fragment chain, which also happens to
1653 * be the only place where the TX status bits
1654 * are valid.
1655 */
1656 if (txstat & RE_TDESC_CMD_EOF) {
1657 m_freem(sc->re_ldata.re_tx_mbuf[idx]);
1658 sc->re_ldata.re_tx_mbuf[idx] = NULL;
1659 bus_dmamap_unload(sc->re_ldata.re_mtag,
1660 sc->re_ldata.re_tx_dmamap[idx]);
1661 if (txstat & (RE_TDESC_STAT_EXCESSCOL|
1662 RE_TDESC_STAT_COLCNT))
1663 ifp->if_collisions++;
1664 if (txstat & RE_TDESC_STAT_TXERRSUM)
1665 ifp->if_oerrors++;
1666 else
1667 ifp->if_opackets++;
1668 }
1669 sc->re_ldata.re_tx_free++;
1670 }
1671
1672 /* No changes made to the TX ring, so no flush needed */
1673 if (sc->re_ldata.re_tx_free) {
1674 sc->re_ldata.re_tx_considx = idx;
1675 ifp->if_flags &= ~IFF_OACTIVE;
1676 ifp->if_timer = 0;
1677 }
1678
1679 /*
1680 * Some chips will ignore a second TX request issued while an
1681 * existing transmission is in progress. If the transmitter goes
1682 * idle but there are still packets waiting to be sent, we need
1683 * to restart the channel here to flush them out. This only seems
1684 * to be required with the PCIe devices.
1685 */
1686 if (sc->re_ldata.re_tx_free < RE_TX_DESC_CNT)
1687 CSR_WRITE_1(sc, sc->re_txstart, RE_TXSTART_START);
1688
1689 /*
1690 * If not all descriptors have been released reaped yet,
1691 * reload the timer so that we will eventually get another
1692 * interrupt that will cause us to re-enter this routine.
1693 * This is done in case the transmitter has gone idle.
1694 */
1695 if (RE_TX_MODERATION_IS_ENABLED(sc) &&
1696 sc->re_ldata.re_tx_free < RE_TX_DESC_CNT)
1697 CSR_WRITE_4(sc, RE_TIMERCNT, 1);
1698 }
1699
1700 static void
1701 re_tick(void *xsc)
1702 {
1703 struct re_softc *sc = xsc;
1704
1705 lwkt_serialize_enter(sc->arpcom.ac_if.if_serializer);
1706 re_tick_serialized(xsc);
1707 lwkt_serialize_exit(sc->arpcom.ac_if.if_serializer);
1708 }
1709
1710 static void
1711 re_tick_serialized(void *xsc)
1712 {
1713 struct re_softc *sc = xsc;
1714 struct ifnet *ifp = &sc->arpcom.ac_if;
1715 struct mii_data *mii;
1716
1717 mii = device_get_softc(sc->re_miibus);
1718 mii_tick(mii);
1719 if (sc->re_link) {
1720 if (!(mii->mii_media_status & IFM_ACTIVE))
1721 sc->re_link = 0;
1722 } else {
1723 if (mii->mii_media_status & IFM_ACTIVE &&
1724 IFM_SUBTYPE(mii->mii_media_active) != IFM_NONE) {
1725 sc->re_link = 1;
1726 if (!ifq_is_empty(&ifp->if_snd))
1727 if_devstart(ifp);
1728 }
1729 }
1730
1731 callout_reset(&sc->re_timer, hz, re_tick, sc);
1732 }
1733
1734 #ifdef DEVICE_POLLING
1735
1736 static void
1737 re_poll(struct ifnet *ifp, enum poll_cmd cmd, int count)
1738 {
1739 struct re_softc *sc = ifp->if_softc;
1740
1741 switch(cmd) {
1742 case POLL_REGISTER:
1743 /* disable interrupts */
1744 CSR_WRITE_2(sc, RE_IMR, 0x0000);
1745 break;
1746 case POLL_DEREGISTER:
1747 /* enable interrupts */
1748 CSR_WRITE_2(sc, RE_IMR, sc->re_intrs);
1749 break;
1750 default:
1751 sc->rxcycles = count;
1752 re_rxeof(sc);
1753 re_txeof(sc);
1754
1755 if (!ifq_is_empty(&ifp->if_snd))
1756 if_devstart(ifp);
1757
1758 if (cmd == POLL_AND_CHECK_STATUS) { /* also check status register */
1759 uint16_t status;
1760
1761 status = CSR_READ_2(sc, RE_ISR);
1762 if (status == 0xffff)
1763 return;
1764 if (status)
1765 CSR_WRITE_2(sc, RE_ISR, status);
1766
1767 /*
1768 * XXX check behaviour on receiver stalls.
1769 */
1770
1771 if (status & RE_ISR_SYSTEM_ERR) {
1772 re_reset(sc);
1773 re_init(sc);
1774 }
1775 }
1776 break;
1777 }
1778 }
1779 #endif /* DEVICE_POLLING */
1780
1781 static void
1782 re_intr(void *arg)
1783 {
1784 struct re_softc *sc = arg;
1785 struct ifnet *ifp = &sc->arpcom.ac_if;
1786 uint16_t status;
1787
1788 if (sc->suspended || (ifp->if_flags & IFF_UP) == 0)
1789 return;
1790
1791 for (;;) {
1792 status = CSR_READ_2(sc, RE_ISR);
1793 /* If the card has gone away the read returns 0xffff. */
1794 if (status == 0xffff)
1795 break;
1796 if (status)
1797 CSR_WRITE_2(sc, RE_ISR, status);
1798
1799 if ((status & sc->re_intrs) == 0)
1800 break;
1801
1802 if (status & (RE_ISR_RX_OK | RE_ISR_RX_ERR | RE_ISR_FIFO_OFLOW))
1803 re_rxeof(sc);
1804
1805 if ((status & sc->re_tx_ack) ||
1806 (status & RE_ISR_TX_ERR) ||
1807 (status & RE_ISR_TX_DESC_UNAVAIL))
1808 re_txeof(sc);
1809
1810 if (status & RE_ISR_SYSTEM_ERR) {
1811 re_reset(sc);
1812 re_init(sc);
1813 }
1814
1815 if (status & RE_ISR_LINKCHG) {
1816 callout_stop(&sc->re_timer);
1817 re_tick_serialized(sc);
1818 }
1819 }
1820
1821 if (!ifq_is_empty(&ifp->if_snd))
1822 if_devstart(ifp);
1823 }
1824
1825 static int
1826 re_encap(struct re_softc *sc, struct mbuf **m_head, int *idx, int *called_defrag)
1827 {
1828 struct ifnet *ifp = &sc->arpcom.ac_if;
1829 struct mbuf *m, *m_new = NULL;
1830 struct re_dmaload_arg arg;
1831 bus_dmamap_t map;
1832 int error;
1833
1834 KASSERT(sc->re_ldata.re_tx_free > 4, ("not enough free TX desc\n"));
1835
1836 *called_defrag = 0;
1837 m = *m_head;
1838
1839 /*
1840 * Set up checksum offload. Note: checksum offload bits must
1841 * appear in all descriptors of a multi-descriptor transmit
1842 * attempt. (This is according to testing done with an 8169
1843 * chip. I'm not sure if this is a requirement or a bug.)
1844 */
1845
1846 arg.re_flags = 0;
1847
1848 if (m->m_pkthdr.csum_flags & CSUM_IP)
1849 arg.re_flags |= RE_TDESC_CMD_IPCSUM;
1850 if (m->m_pkthdr.csum_flags & CSUM_TCP)
1851 arg.re_flags |= RE_TDESC_CMD_TCPCSUM;
1852 if (m->m_pkthdr.csum_flags & CSUM_UDP)
1853 arg.re_flags |= RE_TDESC_CMD_UDPCSUM;
1854
1855 arg.sc = sc;
1856 arg.re_idx = *idx;
1857 arg.re_maxsegs = sc->re_ldata.re_tx_free;
1858 if (arg.re_maxsegs > 4)
1859 arg.re_maxsegs -= 4;
1860 arg.re_ring = sc->re_ldata.re_tx_list;
1861
1862 map = sc->re_ldata.re_tx_dmamap[*idx];
1863
1864 /*
1865 * With some of the RealTek chips, using the checksum offload
1866 * support in conjunction with the autopadding feature results
1867 * in the transmission of corrupt frames. For example, if we
1868 * need to send a really small IP fragment that's less than 60
1869 * bytes in size, and IP header checksumming is enabled, the
1870 * resulting ethernet frame that appears on the wire will
1871 * have garbled payload. To work around this, if TX checksum
1872 * offload is enabled, we always manually pad short frames out
1873 * to the minimum ethernet frame size. We do this by pretending
1874 * the mbuf chain has too many fragments so the coalescing code
1875 * below can assemble the packet into a single buffer that's
1876 * padded out to the mininum frame size.
1877 *
1878 * Note: this appears unnecessary for TCP, and doing it for TCP
1879 * with PCIe adapters seems to result in bad checksums.
1880 */
1881 if (arg.re_flags && !(arg.re_flags & RE_TDESC_CMD_TCPCSUM) &&
1882 m->m_pkthdr.len < RE_MIN_FRAMELEN) {
1883 error = EFBIG;
1884 } else {
1885 error = bus_dmamap_load_mbuf(sc->re_ldata.re_mtag, map,
1886 m, re_dma_map_desc, &arg, BUS_DMA_NOWAIT);
1887 }
1888
1889 if (error && error != EFBIG) {
1890 if_printf(ifp, "can't map mbuf (error %d)\n", error);
1891 return(ENOBUFS);
1892 }
1893
1894 /* Too many segments to map, coalesce into a single mbuf */
1895
1896 if (error || arg.re_maxsegs == 0) {
1897 m_new = m_defrag_nofree(m, MB_DONTWAIT);
1898 if (m_new == NULL) {
1899 return(1);
1900 } else {
1901 m = m_new;
1902 *m_head = m;
1903 }
1904
1905 /*
1906 * Manually pad short frames, and zero the pad space
1907 * to avoid leaking data.
1908 */
1909 if (m_new->m_pkthdr.len < RE_MIN_FRAMELEN) {
1910 bzero(mtod(m_new, char *) + m_new->m_pkthdr.len,
1911 RE_MIN_FRAMELEN - m_new->m_pkthdr.len);
1912 m_new->m_pkthdr.len += RE_MIN_FRAMELEN -
1913 m_new->m_pkthdr.len;
1914 m_new->m_len = m_new->m_pkthdr.len;
1915 }
1916
1917 *called_defrag = 1;
1918 arg.sc = sc;
1919 arg.re_idx = *idx;
1920 arg.re_maxsegs = sc->re_ldata.re_tx_free;
1921 arg.re_ring = sc->re_ldata.re_tx_list;
1922
1923 error = bus_dmamap_load_mbuf(sc->re_ldata.re_mtag, map,
1924 m, re_dma_map_desc, &arg, BUS_DMA_NOWAIT);
1925 if (error) {
1926 m_freem(m);
1927 if_printf(ifp, "can't map mbuf (error %d)\n", error);
1928 return(EFBIG);
1929 }
1930 }
1931
1932 /*
1933 * Insure that the map for this transmission
1934 * is placed at the array index of the last descriptor
1935 * in this chain.
1936 */
1937 sc->re_ldata.re_tx_dmamap[*idx] =
1938 sc->re_ldata.re_tx_dmamap[arg.re_idx];
1939 sc->re_ldata.re_tx_dmamap[arg.re_idx] = map;
1940
1941 sc->re_ldata.re_tx_mbuf[arg.re_idx] = m;
1942 sc->re_ldata.re_tx_free -= arg.re_maxsegs;
1943
1944 /*
1945 * Set up hardware VLAN tagging. Note: vlan tag info must
1946 * appear in the first descriptor of a multi-descriptor
1947 * transmission attempt.
1948 */
1949
1950 if (m->m_flags & M_VLANTAG) {
1951 sc->re_ldata.re_tx_list[*idx].re_vlanctl =
1952 htole32(htobe16(m->m_pkthdr.ether_vlantag) |
1953 RE_TDESC_VLANCTL_TAG);
1954 }
1955
1956 /* Transfer ownership of packet to the chip. */
1957
1958 sc->re_ldata.re_tx_list[arg.re_idx].re_cmdstat |=
1959 htole32(RE_TDESC_CMD_OWN);
1960 if (*idx != arg.re_idx)
1961 sc->re_ldata.re_tx_list[*idx].re_cmdstat |=
1962 htole32(RE_TDESC_CMD_OWN);
1963
1964 RE_DESC_INC(arg.re_idx);
1965 *idx = arg.re_idx;
1966
1967 return(0);
1968 }
1969
1970 /*
1971 * Main transmit routine for C+ and gigE NICs.
1972 */
1973
1974 static void
1975 re_start(struct ifnet *ifp)
1976 {
1977 struct re_softc *sc = ifp->if_softc;
1978 struct mbuf *m_head;
1979 struct mbuf *m_head2;
1980 int called_defrag, idx, need_trans;
1981
1982 if (!sc->re_link) {
1983 ifq_purge(&ifp->if_snd);
1984 return;
1985 }
1986
1987 if ((ifp->if_flags & (IFF_OACTIVE | IFF_RUNNING)) != IFF_RUNNING)
1988 return;
1989
1990 idx = sc->re_ldata.re_tx_prodidx;
1991
1992 need_trans = 0;
1993 while (sc->re_ldata.re_tx_mbuf[idx] == NULL) {
1994 if (sc->re_ldata.re_tx_free <= 4) {
1995 ifp->if_flags |= IFF_OACTIVE;
1996 break;
1997 }
1998
1999 m_head = ifq_dequeue(&ifp->if_snd, NULL);
2000 if (m_head == NULL)
2001 break;
2002
2003 m_head2 = m_head;
2004 if (re_encap(sc, &m_head2, &idx, &called_defrag)) {
2005 /*
2006 * If we could not encapsulate the defragged packet,
2007 * the returned m_head2 is garbage and we must dequeue
2008 * and throw away the original packet.
2009 */
2010 if (called_defrag)
2011 m_freem(m_head);
2012 ifp->if_flags |= IFF_OACTIVE;
2013 break;
2014 }
2015
2016 /*
2017 * Clean out the packet we encapsulated. If we defragged
2018 * the packet the m_head2 is the one that got encapsulated
2019 * and the original must be thrown away. Otherwise m_head2
2020 * *IS* the original.
2021 */
2022 if (called_defrag)
2023 m_freem(m_head);
2024 need_trans = 1;
2025
2026 /*
2027 * If there's a BPF listener, bounce a copy of this frame
2028 * to him.
2029 */
2030 ETHER_BPF_MTAP(ifp, m_head2);
2031 }
2032
2033 if (!need_trans) {
2034 if (RE_TX_MODERATION_IS_ENABLED(sc) &&
2035 sc->re_ldata.re_tx_free != RE_TX_DESC_CNT)
2036 CSR_WRITE_4(sc, RE_TIMERCNT, 1);
2037 return;
2038 }
2039
2040 /* Flush the TX descriptors */
2041 bus_dmamap_sync(sc->re_ldata.re_tx_list_tag,
2042 sc->re_ldata.re_tx_list_map, BUS_DMASYNC_PREWRITE);
2043
2044 sc->re_ldata.re_tx_prodidx = idx;
2045
2046 /*
2047 * RealTek put the TX poll request register in a different
2048 * location on the 8169 gigE chip. I don't know why.
2049 */
2050 CSR_WRITE_1(sc, sc->re_txstart, RE_TXSTART_START);
2051
2052 if (RE_TX_MODERATION_IS_ENABLED(sc)) {
2053 /*
2054 * Use the countdown timer for interrupt moderation.
2055 * 'TX done' interrupts are disabled. Instead, we reset the
2056 * countdown timer, which will begin counting until it hits
2057 * the value in the TIMERINT register, and then trigger an
2058 * interrupt. Each time we write to the TIMERCNT register,
2059 * the timer count is reset to 0.
2060 */
2061 CSR_WRITE_4(sc, RE_TIMERCNT, 1);
2062 }
2063
2064 /*
2065 * Set a timeout in case the chip goes out to lunch.
2066 */
2067 ifp->if_timer = 5;
2068 }
2069
2070 static void
2071 re_init(void *xsc)
2072 {
2073 struct re_softc *sc = xsc;
2074 struct ifnet *ifp = &sc->arpcom.ac_if;
2075 struct mii_data *mii;
2076 uint32_t rxcfg = 0;
2077
2078 mii = device_get_softc(sc->re_miibus);
2079
2080 /*
2081 * Cancel pending I/O and free all RX/TX buffers.
2082 */
2083 re_stop(sc);
2084
2085 /*
2086 * Enable C+ RX and TX mode, as well as VLAN stripping and
2087 * RX checksum offload. We must configure the C+ register
2088 * before all others.
2089 */
2090 CSR_WRITE_2(sc, RE_CPLUS_CMD, RE_CPLUSCMD_RXENB | RE_CPLUSCMD_TXENB |
2091 RE_CPLUSCMD_PCI_MRW | RE_CPLUSCMD_VLANSTRIP |
2092 (ifp->if_capenable & IFCAP_RXCSUM ?
2093 RE_CPLUSCMD_RXCSUM_ENB : 0));
2094
2095 /*
2096 * Init our MAC address. Even though the chipset
2097 * documentation doesn't mention it, we need to enter "Config
2098 * register write enable" mode to modify the ID registers.
2099 */
2100 CSR_WRITE_1(sc, RE_EECMD, RE_EEMODE_WRITECFG);
2101 CSR_WRITE_4(sc, RE_IDR0,
2102 htole32(*(uint32_t *)(&sc->arpcom.ac_enaddr[0])));
2103 CSR_WRITE_2(sc, RE_IDR4,
2104 htole16(*(uint16_t *)(&sc->arpcom.ac_enaddr[4])));
2105 CSR_WRITE_1(sc, RE_EECMD, RE_EEMODE_OFF);
2106
2107 /*
2108 * For C+ mode, initialize the RX descriptors and mbufs.
2109 */
2110 re_rx_list_init(sc);
2111 re_tx_list_init(sc);
2112
2113 /*
2114 * Load the addresses of the RX and TX lists into the chip.
2115 */
2116 CSR_WRITE_4(sc, RE_RXLIST_ADDR_HI,
2117 RE_ADDR_HI(sc->re_ldata.re_rx_list_addr));
2118 CSR_WRITE_4(sc, RE_RXLIST_ADDR_LO,
2119 RE_ADDR_LO(sc->re_ldata.re_rx_list_addr));
2120
2121 CSR_WRITE_4(sc, RE_TXLIST_ADDR_HI,
2122 RE_ADDR_HI(sc->re_ldata.re_tx_list_addr));
2123 CSR_WRITE_4(sc, RE_TXLIST_ADDR_LO,
2124 RE_ADDR_LO(sc->re_ldata.re_tx_list_addr));
2125
2126 /*
2127 * Enable transmit and receive.
2128 */
2129 CSR_WRITE_1(sc, RE_COMMAND, RE_CMD_TX_ENB|RE_CMD_RX_ENB);
2130
2131 /*
2132 * Set the initial TX and RX configuration.
2133 */
2134 if (sc->re_testmode) {
2135 if (sc->re_type == RE_8169)
2136 CSR_WRITE_4(sc, RE_TXCFG,
2137 RE_TXCFG_CONFIG | RE_LOOPTEST_ON);
2138 else
2139 CSR_WRITE_4(sc, RE_TXCFG,
2140 RE_TXCFG_CONFIG | RE_LOOPTEST_ON_CPLUS);
2141 } else
2142 CSR_WRITE_4(sc, RE_TXCFG, RE_TXCFG_CONFIG);
2143
2144 CSR_WRITE_1(sc, RE_EARLY_TX_THRESH, 16);
2145
2146 CSR_WRITE_4(sc, RE_RXCFG, RE_RXCFG_CONFIG);
2147
2148 /* Set the individual bit to receive frames for this host only. */
2149 rxcfg = CSR_READ_4(sc, RE_RXCFG);
2150 rxcfg |= RE_RXCFG_RX_INDIV;
2151
2152 /* If we want promiscuous mode, set the allframes bit. */
2153 if (ifp->if_flags & IFF_PROMISC) {
2154 rxcfg |= RE_RXCFG_RX_ALLPHYS;
2155 CSR_WRITE_4(sc, RE_RXCFG, rxcfg);
2156 } else {
2157 rxcfg &= ~RE_RXCFG_RX_ALLPHYS;
2158 CSR_WRITE_4(sc, RE_RXCFG, rxcfg);
2159 }
2160
2161 /*
2162 * Set capture broadcast bit to capture broadcast frames.
2163 */
2164 if (ifp->if_flags & IFF_BROADCAST) {
2165 rxcfg |= RE_RXCFG_RX_BROAD;
2166 CSR_WRITE_4(sc, RE_RXCFG, rxcfg);
2167 } else {
2168 rxcfg &= ~RE_RXCFG_RX_BROAD;
2169 CSR_WRITE_4(sc, RE_RXCFG, rxcfg);
2170 }
2171
2172 /*
2173 * Program the multicast filter, if necessary.
2174 */
2175 re_setmulti(sc);
2176
2177 #ifdef DEVICE_POLLING
2178 /*
2179 * Disable interrupts if we are polling.
2180 */
2181 if (ifp->if_flags & IFF_POLLING)
2182 CSR_WRITE_2(sc, RE_IMR, 0);
2183 else /* otherwise ... */
2184 #endif /* DEVICE_POLLING */
2185 /*
2186 * Enable interrupts.
2187 */
2188 if (sc->re_testmode)
2189 CSR_WRITE_2(sc, RE_IMR, 0);
2190 else
2191 CSR_WRITE_2(sc, RE_IMR, sc->re_intrs);
2192 CSR_WRITE_2(sc, RE_ISR, sc->re_intrs);
2193
2194 /* Set initial TX threshold */
2195 sc->re_txthresh = RE_TX_THRESH_INIT;
2196
2197 /* Start RX/TX process. */
2198 if (sc->re_flags & RE_F_HASMPC)
2199 CSR_WRITE_4(sc, RE_MISSEDPKT, 0);
2200 #ifdef notdef
2201 /* Enable receiver and transmitter. */
2202 CSR_WRITE_1(sc, RE_COMMAND, RE_CMD_TX_ENB|RE_CMD_RX_ENB);
2203 #endif
2204
2205 if (RE_TX_MODERATION_IS_ENABLED(sc)) {
2206 /*
2207 * Initialize the timer interrupt register so that
2208 * a timer interrupt will be generated once the timer
2209 * reaches a certain number of ticks. The timer is
2210 * reloaded on each transmit. This gives us TX interrupt
2211 * moderation, which dramatically improves TX frame rate.
2212 */
2213 if (sc->re_type == RE_8169)
2214 CSR_WRITE_4(sc, RE_TIMERINT_8169, 0x800);
2215 else
2216 CSR_WRITE_4(sc, RE_TIMERINT, 0x400);
2217 }
2218
2219 /*
2220 * For 8169 gigE NICs, set the max allowed RX packet
2221 * size so we can receive jumbo frames.
2222 */
2223 if (sc->re_type == RE_8169)
2224 CSR_WRITE_2(sc, RE_MAXRXPKTLEN, 16383);
2225
2226 if (sc->re_testmode) {
2227 return;
2228 }
2229
2230 mii_mediachg(mii);
2231
2232 CSR_WRITE_1(sc, RE_CFG1, RE_CFG1_DRVLOAD|RE_CFG1_FULLDUPLEX);
2233
2234 ifp->if_flags |= IFF_RUNNING;
2235 ifp->if_flags &= ~IFF_OACTIVE;
2236
2237 sc->re_link = 0;
2238 callout_reset(&sc->re_timer, hz, re_tick, sc);
2239 }
2240
2241 /*
2242 * Set media options.
2243 */
2244 static int
2245 re_ifmedia_upd(struct ifnet *ifp)
2246 {
2247 struct re_softc *sc = ifp->if_softc;
2248 struct mii_data *mii;
2249
2250 mii = device_get_softc(sc->re_miibus);
2251 mii_mediachg(mii);
2252
2253 return(0);
2254 }
2255
2256 /*
2257 * Report current media status.
2258 */
2259 static void
2260 re_ifmedia_sts(struct ifnet *ifp, struct ifmediareq *ifmr)
2261 {
2262 struct re_softc *sc = ifp->if_softc;
2263 struct mii_data *mii;
2264
2265 mii = device_get_softc(sc->re_miibus);
2266
2267 mii_pollstat(mii);
2268 ifmr->ifm_active = mii->mii_media_active;
2269 ifmr->ifm_status = mii->mii_media_status;
2270 }
2271
2272 static int
2273 re_ioctl(struct ifnet *ifp, u_long command, caddr_t data, struct ucred *cr)
2274 {
2275 struct re_softc *sc = ifp->if_softc;
2276 struct ifreq *ifr = (struct ifreq *) data;
2277 struct mii_data *mii;
2278 int error = 0;
2279
2280 switch(command) {
2281 case SIOCSIFMTU:
2282 if (ifr->ifr_mtu > RE_JUMBO_MTU)
2283 error = EINVAL;
2284 ifp->if_mtu = ifr->ifr_mtu;
2285 break;
2286 case SIOCSIFFLAGS:
2287 if (ifp->if_flags & IFF_UP)
2288 re_init(sc);
2289 else if (ifp->if_flags & IFF_RUNNING)
2290 re_stop(sc);
2291 break;
2292 case SIOCADDMULTI:
2293 case SIOCDELMULTI:
2294 re_setmulti(sc);
2295 error = 0;
2296 break;
2297 case SIOCGIFMEDIA:
2298 case SIOCSIFMEDIA:
2299 mii = device_get_softc(sc->re_miibus);
2300 error = ifmedia_ioctl(ifp, ifr, &mii->mii_media, command);
2301 break;
2302 case SIOCSIFCAP:
2303 ifp->if_capenable &= ~(IFCAP_HWCSUM);
2304 ifp->if_capenable |=
2305 ifr->ifr_reqcap & (IFCAP_HWCSUM);
2306 if (ifp->if_capenable & IFCAP_TXCSUM)
2307 ifp->if_hwassist = RE_CSUM_FEATURES;
2308 else
2309 ifp->if_hwassist = 0;
2310 if (ifp->if_flags & IFF_RUNNING)
2311 re_init(sc);
2312 break;
2313 default:
2314 error = ether_ioctl(ifp, command, data);
2315 break;
2316 }
2317 return(error);
2318 }
2319
2320 static void
2321 re_watchdog(struct ifnet *ifp)
2322 {
2323 struct re_softc *sc = ifp->if_softc;
2324
2325 if_printf(ifp, "watchdog timeout\n");
2326
2327 ifp->if_oerrors++;
2328
2329 re_txeof(sc);
2330 re_rxeof(sc);
2331
2332 re_init(sc);
2333
2334 if (!ifq_is_empty(&ifp->if_snd))
2335 if_devstart(ifp);
2336 }
2337
2338 /*
2339 * Stop the adapter and free any mbufs allocated to the
2340 * RX and TX lists.
2341 */
2342 static void
2343 re_stop(struct re_softc *sc)
2344 {
2345 struct ifnet *ifp = &sc->arpcom.ac_if;
2346 int i;
2347
2348 ifp->if_timer = 0;
2349 callout_stop(&sc->re_timer);
2350
2351 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE);
2352
2353 CSR_WRITE_1(sc, RE_COMMAND, 0x00);
2354 CSR_WRITE_2(sc, RE_IMR, 0x0000);
2355 CSR_WRITE_2(sc, RE_ISR, 0xFFFF);
2356
2357 if (sc->re_head != NULL) {
2358 m_freem(sc->re_head);
2359 sc->re_head = sc->re_tail = NULL;
2360 }
2361
2362 /* Free the TX list buffers. */
2363 for (i = 0; i < RE_TX_DESC_CNT; i++) {
2364 if (sc->re_ldata.re_tx_mbuf[i] != NULL) {
2365 bus_dmamap_unload(sc->re_ldata.re_mtag,
2366 sc->re_ldata.re_tx_dmamap[i]);
2367 m_freem(sc->re_ldata.re_tx_mbuf[i]);
2368 sc->re_ldata.re_tx_mbuf[i] = NULL;
2369 }
2370 }
2371
2372 /* Free the RX list buffers. */
2373 for (i = 0; i < RE_RX_DESC_CNT; i++) {
2374 if (sc->re_ldata.re_rx_mbuf[i] != NULL) {
2375 bus_dmamap_unload(sc->re_ldata.re_mtag,
2376 sc->re_ldata.re_rx_dmamap[i]);
2377 m_freem(sc->re_ldata.re_rx_mbuf[i]);
2378 sc->re_ldata.re_rx_mbuf[i] = NULL;
2379 }
2380 }
2381 }
2382
2383 /*
2384 * Device suspend routine. Stop the interface and save some PCI
2385 * settings in case the BIOS doesn't restore them properly on
2386 * resume.
2387 */
2388 static int
2389 re_suspend(device_t dev)
2390 {
2391 #ifndef BURN_BRIDGES
2392 int i;
2393 #endif
2394 struct re_softc *sc = device_get_softc(dev);
2395
2396 re_stop(sc);
2397
2398 #ifndef BURN_BRIDGES
2399 for (i = 0; i < 5; i++)
2400 sc->saved_maps[i] = pci_read_config(dev, PCIR_MAPS + i * 4, 4);
2401 sc->saved_biosaddr = pci_read_config(dev, PCIR_BIOS, 4);
2402 sc->saved_intline = pci_read_config(dev, PCIR_INTLINE, 1);
2403 sc->saved_cachelnsz = pci_read_config(dev, PCIR_CACHELNSZ, 1);
2404 sc->saved_lattimer = pci_read_config(dev, PCIR_LATTIMER, 1);
2405 #endif
2406
2407 sc->suspended = 1;
2408
2409 return (0);
2410 }
2411
2412 /*
2413 * Device resume routine. Restore some PCI settings in case the BIOS
2414 * doesn't, re-enable busmastering, and restart the interface if
2415 * appropriate.
2416 */
2417 static int
2418 re_resume(device_t dev)
2419 {
2420 struct re_softc *sc = device_get_softc(dev);
2421 struct ifnet *ifp = &sc->arpcom.ac_if;
2422 #ifndef BURN_BRIDGES
2423 int i;
2424 #endif
2425
2426 #ifndef BURN_BRIDGES
2427 /* better way to do this? */
2428 for (i = 0; i < 5; i++)
2429 pci_write_config(dev, PCIR_MAPS + i * 4, sc->saved_maps[i], 4);
2430 pci_write_config(dev, PCIR_BIOS, sc->saved_biosaddr, 4);
2431 pci_write_config(dev, PCIR_INTLINE, sc->saved_intline, 1);
2432 pci_write_config(dev, PCIR_CACHELNSZ, sc->saved_cachelnsz, 1);
2433 pci_write_config(dev, PCIR_LATTIMER, sc->saved_lattimer, 1);
2434
2435 /* reenable busmastering */
2436 pci_enable_busmaster(dev);
2437 pci_enable_io(dev, SYS_RES_IOPORT);
2438 #endif
2439
2440 /* reinitialize interface if necessary */
2441 if (ifp->if_flags & IFF_UP)
2442 re_init(sc);
2443
2444 sc->suspended = 0;
2445
2446 return (0);
2447 }
2448
2449 /*
2450 * Stop all chip I/O so that the kernel's probe routines don't
2451 * get confused by errant DMAs when rebooting.
2452 */
2453 static void
2454 re_shutdown(device_t dev)
2455 {
2456 struct re_softc *sc = device_get_softc(dev);
2457 struct ifnet *ifp = &sc->arpcom.ac_if;
2458
2459 lwkt_serialize_enter(ifp->if_serializer);
2460 re_stop(sc);
2461 lwkt_serialize_exit(ifp->if_serializer);
2462 }
2463
2464 static int
2465 re_sysctl_tx_moderation(SYSCTL_HANDLER_ARGS)
2466 {
2467 struct re_softc *sc = arg1;
2468 struct ifnet *ifp = &sc->arpcom.ac_if;
2469 int error = 0, mod, mod_old;
2470
2471 lwkt_serialize_enter(ifp->if_serializer);
2472
2473 mod_old = mod = RE_TX_MODERATION_IS_ENABLED(sc);
2474
2475 error = sysctl_handle_int(oidp, &mod, 0, req);
2476 if (error || req->newptr == NULL || mod == mod_old)
2477 goto back;
2478 if (mod != 0 && mod != 1) {
2479 error = EINVAL;
2480 goto back;
2481 }
2482
2483 if (mod)
2484 RE_ENABLE_TX_MODERATION(sc);
2485 else
2486 RE_DISABLE_TX_MODERATION(sc);
2487
2488 if ((ifp->if_flags & (IFF_RUNNING | IFF_UP)) == (IFF_RUNNING | IFF_UP))
2489 re_init(sc);
2490 back:
2491 lwkt_serialize_exit(ifp->if_serializer);
2492 return error;
2493 }
DragonFly BSD