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hyperv/vmbus: Complete vmbus initialization; interrupt cputimer is enabled
[dragonfly.git] / sys / platform / pc64 / x86_64 / identcpu.c
blobb3f0ce915d35cfab640c38cd2da4e4ccea13604a
1 /*-
2 * Copyright (c) 1992 Terrence R. Lambert.
3 * Copyright (c) 1982, 1987, 1990 The Regents of the University of California.
4 * Copyright (c) 1997 KATO Takenori.
5 * Copyright (c) 2008 The DragonFly Project.
6 * All rights reserved.
7 *
8 * This code is derived from software contributed to Berkeley by
9 * William Jolitz.
10 *
11 * Redistribution and use in source and binary forms, with or without
12 * modification, are permitted provided that the following conditions
13 * are met:
14 * 1. Redistributions of source code must retain the above copyright
15 * notice, this list of conditions and the following disclaimer.
16 * 2. Redistributions in binary form must reproduce the above copyright
17 * notice, this list of conditions and the following disclaimer in the
18 * documentation and/or other materials provided with the distribution.
19 * 3. All advertising materials mentioning features or use of this software
20 * must display the following acknowledgement:
21 * This product includes software developed by the University of
22 * California, Berkeley and its contributors.
23 * 4. Neither the name of the University nor the names of its contributors
24 * may be used to endorse or promote products derived from this software
25 * without specific prior written permission.
26 *
27 * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND
28 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
29 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
30 * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE
31 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
32 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
33 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
34 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
35 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
36 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
37 * SUCH DAMAGE.
38 *
39 * from: Id: machdep.c,v 1.193 1996/06/18 01:22:04 bde Exp
40 */
41
42 #include "opt_cpu.h"
43
44 #include <sys/param.h>
45 #include <sys/bus.h>
46 #include <sys/eventhandler.h>
47 #include <sys/systm.h>
48 #include <sys/kernel.h>
49 #include <sys/sysctl.h>
50 #include <sys/power.h>
51
52 #include <machine/asmacros.h>
53 #include <machine/clock.h>
54 #include <machine/cputypes.h>
55 #include <machine/frame.h>
56 #include <machine/segments.h>
57 #include <machine/specialreg.h>
58 #include <machine/md_var.h>
59 #include <machine/npx.h>
60
61 /* XXX - should be in header file: */
62 void printcpuinfo(void);
63 void identify_cpu(void);
64 void earlysetcpuclass(void);
65 void panicifcpuunsupported(void);
66
67 static u_int find_cpu_vendor_id(void);
68 static void print_AMD_info(void);
69 static void print_AMD_assoc(int i);
70 static void print_via_padlock_info(void);
71
72 int cpu_class;
73 char machine[] = "x86_64";
74 SYSCTL_STRING(_hw, HW_MACHINE, machine, CTLFLAG_RD,
75 machine, 0, "Machine class");
76
77 static char cpu_model[128];
78 SYSCTL_STRING(_hw, HW_MODEL, model, CTLFLAG_RD,
79 cpu_model, 0, "Machine model");
80
81 static int hw_clockrate;
82 SYSCTL_INT(_hw, OID_AUTO, clockrate, CTLFLAG_RD,
83 &hw_clockrate, 0, "CPU instruction clock rate");
84
85 static char cpu_brand[48];
86
87 static struct {
88 char *cpu_name;
89 int cpu_class;
90 } x86_64_cpus[] = {
91 { "Clawhammer", CPUCLASS_K8 }, /* CPU_CLAWHAMMER */
92 { "Sledgehammer", CPUCLASS_K8 }, /* CPU_SLEDGEHAMMER */
93 };
94
95 static struct {
96 char *vendor;
97 u_int vendor_id;
98 } cpu_vendors[] = {
99 { INTEL_VENDOR_ID, CPU_VENDOR_INTEL }, /* GenuineIntel */
100 { AMD_VENDOR_ID, CPU_VENDOR_AMD }, /* AuthenticAMD */
101 { CENTAUR_VENDOR_ID, CPU_VENDOR_CENTAUR }, /* CentaurHauls */
102 };
103
104 #ifdef foo
105 static int cpu_cores;
106 static int cpu_logical;
107 #endif
108
109 void
110 printcpuinfo(void)
111 {
112 u_int regs[4], i;
113 char *brand;
114
115 cpu_class = x86_64_cpus[cpu].cpu_class;
116 kprintf("CPU: ");
117 strncpy(cpu_model, x86_64_cpus[cpu].cpu_name, sizeof (cpu_model));
118
119 /* Check for extended CPUID information and a processor name. */
120 if (cpu_exthigh >= 0x80000004) {
121 brand = cpu_brand;
122 for (i = 0x80000002; i < 0x80000005; i++) {
123 do_cpuid(i, regs);
124 memcpy(brand, regs, sizeof(regs));
125 brand += sizeof(regs);
126 }
127 }
128
129 switch (cpu_vendor_id) {
130 case CPU_VENDOR_INTEL:
131 /* Please make up your mind folks! */
132 strcat(cpu_model, "EM64T");
133 break;
134 case CPU_VENDOR_AMD:
135 /*
136 * Values taken from AMD Processor Recognition
137 * http://www.amd.com/K6/k6docs/pdf/20734g.pdf
138 * (also describes ``Features'' encodings.
139 */
140 strcpy(cpu_model, "AMD ");
141 if ((cpu_id & 0xf00) == 0xf00)
142 strcat(cpu_model, "AMD64 Processor");
143 else
144 strcat(cpu_model, "Unknown");
145 break;
146 case CPU_VENDOR_CENTAUR:
147 strcpy(cpu_model, "VIA ");
148 if ((cpu_id & 0xff0) == 0x6f0)
149 strcat(cpu_model, "Nano Processor");
150 else
151 strcat(cpu_model, "Unknown");
152 break;
153 default:
154 strcat(cpu_model, "Unknown");
155 break;
156 }
157
158 /*
159 * Replace cpu_model with cpu_brand minus leading spaces if
160 * we have one.
161 */
162 brand = cpu_brand;
163 while (*brand == ' ')
164 ++brand;
165 if (*brand != '\0')
166 strcpy(cpu_model, brand);
167
168 kprintf("%s (", cpu_model);
169 switch(cpu_class) {
170 case CPUCLASS_K8:
171 hw_clockrate = (tsc_frequency + 5000) / 1000000;
172 kprintf("%jd.%02d-MHz ",
173 (intmax_t)(tsc_frequency + 4999) / 1000000,
174 (u_int)((tsc_frequency + 4999) / 10000) % 100);
175 kprintf("K8");
176 break;
177 default:
178 kprintf("Unknown"); /* will panic below... */
179 }
180 kprintf("-class CPU)\n");
181 if (*cpu_vendor)
182 kprintf(" Origin = \"%s\"", cpu_vendor);
183 if (cpu_id)
184 kprintf(" Id = 0x%x", cpu_id);
185
186 if (cpu_vendor_id == CPU_VENDOR_INTEL ||
187 cpu_vendor_id == CPU_VENDOR_AMD ||
188 cpu_vendor_id == CPU_VENDOR_CENTAUR) {
189 kprintf(" Stepping = %u", cpu_id & 0xf);
190 if (cpu_high > 0) {
191 #if 0
192 u_int cmp = 1, htt = 1;
193 #endif
194
195 /*
196 * Here we should probably set up flags indicating
197 * whether or not various features are available.
198 * The interesting ones are probably VME, PSE, PAE,
199 * and PGE. The code already assumes without bothering
200 * to check that all CPUs >= Pentium have a TSC and
201 * MSRs.
202 */
203 kprintf("\n Features=0x%b", cpu_feature,
204 "\020"
205 "\001FPU" /* Integral FPU */
206 "\002VME" /* Extended VM86 mode support */
207 "\003DE" /* Debugging Extensions (CR4.DE) */
208 "\004PSE" /* 4MByte page tables */
209 "\005TSC" /* Timestamp counter */
210 "\006MSR" /* Machine specific registers */
211 "\007PAE" /* Physical address extension */
212 "\010MCE" /* Machine Check support */
213 "\011CX8" /* CMPEXCH8 instruction */
214 "\012APIC" /* SMP local APIC */
215 "\013oldMTRR" /* Previous implementation of MTRR */
216 "\014SEP" /* Fast System Call */
217 "\015MTRR" /* Memory Type Range Registers */
218 "\016PGE" /* PG_G (global bit) support */
219 "\017MCA" /* Machine Check Architecture */
220 "\020CMOV" /* CMOV instruction */
221 "\021PAT" /* Page attributes table */
222 "\022PSE36" /* 36 bit address space support */
223 "\023PN" /* Processor Serial number */
224 "\024CLFLUSH" /* Has the CLFLUSH instruction */
225 "\025<b20>"
226 "\026DTS" /* Debug Trace Store */
227 "\027ACPI" /* ACPI support */
228 "\030MMX" /* MMX instructions */
229 "\031FXSR" /* FXSAVE/FXRSTOR */
230 "\032SSE" /* Streaming SIMD Extensions */
231 "\033SSE2" /* Streaming SIMD Extensions #2 */
232 "\034SS" /* Self snoop */
233 "\035HTT" /* Hyperthreading (see EBX bit 16-23) */
234 "\036TM" /* Thermal Monitor clock slowdown */
235 "\037IA64" /* CPU can execute IA64 instructions */
236 "\040PBE" /* Pending Break Enable */
237 );
238
239 if (cpu_feature2 != 0) {
240 kprintf("\n Features2=0x%b", cpu_feature2,
241 "\020"
242 "\001SSE3" /* SSE3 */
243 "\002PCLMULQDQ" /* Carry-Less Mul Quadword */
244 "\003DTES64" /* 64-bit Debug Trace */
245 "\004MON" /* MONITOR/MWAIT Instructions */
246 "\005DS_CPL" /* CPL Qualified Debug Store */
247 "\006VMX" /* Virtual Machine Extensions */
248 "\007SMX" /* Safer Mode Extensions */
249 "\010EST" /* Enhanced SpeedStep */
250 "\011TM2" /* Thermal Monitor 2 */
251 "\012SSSE3" /* SSSE3 */
252 "\013CNXT-ID" /* L1 context ID available */
253 "\014SDBG" /* IA-32 silicon debug */
254 "\015FMA" /* Fused Multiply Add */
255 "\016CX16" /* CMPXCHG16B Instruction */
256 "\017xTPR" /* Send Task Priority Messages */
257 "\020PDCM" /* Perf/Debug Capability MSR */
258 "\021<b16>"
259 "\022PCID" /* Process-context Identifiers */
260 "\023DCA" /* Direct Cache Access */
261 "\024SSE4.1" /* SSE 4.1 */
262 "\025SSE4.2" /* SSE 4.2 */
263 "\026x2APIC" /* xAPIC Extensions */
264 "\027MOVBE" /* MOVBE Instruction */
265 "\030POPCNT" /* POPCNT Instruction */
266 "\031TSCDLT" /* TSC-Deadline Timer */
267 "\032AESNI" /* AES Crypto */
268 "\033XSAVE" /* XSAVE/XRSTOR States */
269 "\034OSXSAVE" /* OS-Enabled State Management */
270 "\035AVX" /* Advanced Vector Extensions */
271 "\036F16C" /* Half-precision conversions */
272 "\037RDRND" /* RDRAND RNG function */
273 "\040VMM" /* Running on a hypervisor */
274 );
275 }
276
277 /*
278 * AMD64 Architecture Programmer's Manual Volume 3:
279 * General-Purpose and System Instructions
280 * http://www.amd.com/us-en/assets/content_type/white_papers_and_tech_docs/24594.pdf
281 *
282 * IA-32 Intel Architecture Software Developer's Manual,
283 * Volume 2A: Instruction Set Reference, A-M
284 * ftp://download.intel.com/design/Pentium4/manuals/25366617.pdf
285 */
286 if (amd_feature != 0) {
287 kprintf("\n AMD Features=0x%b", amd_feature,
288 "\020" /* in hex */
289 "\001<s0>" /* Same */
290 "\002<s1>" /* Same */
291 "\003<s2>" /* Same */
292 "\004<s3>" /* Same */
293 "\005<s4>" /* Same */
294 "\006<s5>" /* Same */
295 "\007<s6>" /* Same */
296 "\010<s7>" /* Same */
297 "\011<s8>" /* Same */
298 "\012<s9>" /* Same */
299 "\013<b10>" /* Undefined */
300 "\014SYSCALL" /* Have SYSCALL/SYSRET */
301 "\015<s12>" /* Same */
302 "\016<s13>" /* Same */
303 "\017<s14>" /* Same */
304 "\020<s15>" /* Same */
305 "\021<s16>" /* Same */
306 "\022<s17>" /* Same */
307 "\023<b18>" /* Reserved, unknown */
308 "\024MP" /* Multiprocessor Capable */
309 "\025NX" /* Has EFER.NXE, NX */
310 "\026<b21>" /* Undefined */
311 "\027MMX+" /* AMD MMX Extensions */
312 "\030<s23>" /* Same */
313 "\031<s24>" /* Same */
314 "\032FFXSR" /* Fast FXSAVE/FXRSTOR */
315 "\033Page1GB" /* 1-GB large page support */
316 "\034RDTSCP" /* RDTSCP */
317 "\035<b28>" /* Undefined */
318 "\036LM" /* 64 bit long mode */
319 "\0373DNow!+" /* AMD 3DNow! Extensions */
320 "\0403DNow!" /* AMD 3DNow! */
321 );
322 }
323
324 if (amd_feature2 != 0) {
325 kprintf("\n AMD Features2=0x%b", amd_feature2,
326 "\020"
327 "\001LAHF" /* LAHF/SAHF in long mode */
328 "\002CMP" /* CMP legacy */
329 "\003SVM" /* Secure Virtual Mode */
330 "\004ExtAPIC" /* Extended APIC register */
331 "\005CR8" /* CR8 in legacy mode */
332 "\006ABM" /* LZCNT instruction */
333 "\007SSE4A" /* SSE4A */
334 "\010MAS" /* Misaligned SSE mode */
335 "\011Prefetch" /* 3DNow! Prefetch/PrefetchW */
336 "\012OSVW" /* OS visible workaround */
337 "\013IBS" /* Instruction based sampling */
338 "\014XOP" /* XOP extended instructions */
339 "\015SKINIT" /* SKINIT/STGI */
340 "\016WDT" /* Watchdog timer */
341 "\017<b14>"
342 "\020LWP" /* Lightweight Profiling */
343 "\021FMA4" /* 4-operand FMA instructions */
344 "\022TCE" /* Translation Cache Extension */
345 "\023<b18>"
346 "\024NodeId" /* NodeId MSR support */
347 "\025<b20>"
348 "\026TBM" /* Trailing Bit Manipulation */
349 "\027Topology" /* Topology Extensions */
350 "\030PCX_CORE" /* Core Performance Counter */
351 "\031PCX_NB" /* NB Performance Counter */
352 "\032SPM" /* Streaming Perf Monitor */
353 "\033DBE" /* Data Breakpoint Extension */
354 "\034PTSC" /* Performance TSC */
355 "\035PCX_L2I" /* L2I Performance Counter */
356 "\036<b29>"
357 "\037<b30>"
358 "\040<b31>"
359 );
360 }
361
362 if (cpu_stdext_feature != 0) {
363 kprintf("\n Structured Extended Features=0x%b",
364 cpu_stdext_feature,
365 "\020"
366 /* RDFSBASE/RDGSBASE/WRFSBASE/WRGSBASE */
367 "\001GSFSBASE"
368 "\002TSCADJ"
369 /* Bit Manipulation Instructions */
370 "\004BMI1"
371 /* Hardware Lock Elision */
372 "\005HLE"
373 /* Advanced Vector Instructions 2 */
374 "\006AVX2"
375 /* Supervisor Mode Execution Prot. */
376 "\010SMEP"
377 /* Bit Manipulation Instructions */
378 "\011BMI2"
379 "\012ENHMOVSB"
380 /* Invalidate Processor Context ID */
381 "\013INVPCID"
382 /* Restricted Transactional Memory */
383 "\014RTM"
384 /* Enhanced NRBG */
385 "\023RDSEED"
386 /* ADCX + ADOX */
387 "\024ADX"
388 /* Supervisor Mode Access Prevention */
389 "\025SMAP"
390 );
391 }
392
393 if (cpu_thermal_feature != 0) {
394 kprintf("\n Thermal and PM Features=0x%b",
395 cpu_thermal_feature,
396 "\020"
397 /* Digital temperature sensor */
398 "\001SENSOR"
399 /* Turbo boost */
400 "\002TURBO"
401 /* APIC-Timer-always-running */
402 "\003ARAT"
403 /* Power limit notification controls */
404 "\005PLN"
405 /* Clock modulation duty cycle extension */
406 "\006ECMD"
407 /* Package thermal management */
408 "\007PTM"
409 );
410 }
411
412 if (cpu_mwait_feature != 0) {
413 kprintf("\n MONITOR/MWAIT Features=0x%b",
414 cpu_mwait_feature,
415 "\020"
416 /* Enumeration of Monitor-Mwait extension */
417 "\001CST"
418 /* interrupts as break-event for MWAIT */
419 "\002INTBRK"
420 );
421 }
422
423 if (cpu_vendor_id == CPU_VENDOR_CENTAUR)
424 print_via_padlock_info();
425 /*
426 * INVALID CPU TOPOLOGY INFORMATION PRINT
427 * DEPRECATED - CPU_TOPOLOGY_DETECTION moved to
428 * - sys/platform/pc64/x86_64/mp_machdep.c
429 * - sys/kern/subr_cpu_topology
430 */
431
432 #if 0
433 if ((cpu_feature & CPUID_HTT) &&
434 cpu_vendor_id == CPU_VENDOR_AMD)
435 cpu_feature &= ~CPUID_HTT;
436 #endif
437
438 /*
439 * If this CPU supports HTT or CMP then mention the
440 * number of physical/logical cores it contains.
441 */
442 #if 0
443 if (cpu_feature & CPUID_HTT)
444 htt = (cpu_procinfo & CPUID_HTT_CORES) >> 16;
445 if (cpu_vendor_id == CPU_VENDOR_AMD &&
446 (amd_feature2 & AMDID2_CMP))
447 cmp = (cpu_procinfo2 & AMDID_CMP_CORES) + 1;
448 else if (cpu_vendor_id == CPU_VENDOR_INTEL &&
449 (cpu_high >= 4)) {
450 cpuid_count(4, 0, regs);
451 if ((regs[0] & 0x1f) != 0)
452 cmp = ((regs[0] >> 26) & 0x3f) + 1;
453 }
454 #endif
455 #ifdef foo
456 /*
457 * XXX For Intel CPUs, this is max number of cores per
458 * package, not the actual cores per package.
459 */
460 #if 0
461 cpu_cores = cmp;
462 cpu_logical = htt / cmp;
463
464 if (cpu_cores > 1)
465 kprintf("\n Cores per package: %d", cpu_cores);
466 if (cpu_logical > 1) {
467 kprintf("\n Logical CPUs per core: %d",
468 cpu_logical);
469 }
470 #endif
471 #endif
472 }
473 }
474 /* Avoid ugly blank lines: only print newline when we have to. */
475 if (*cpu_vendor || cpu_id)
476 kprintf("\n");
477
478 if (!bootverbose)
479 return;
480
481 if (cpu_vendor_id == CPU_VENDOR_AMD)
482 print_AMD_info();
483
484 kprintf("npx mask: 0x%8.8x\n", npx_mxcsr_mask);
485 }
486
487 void
488 panicifcpuunsupported(void)
489 {
490
491 #ifndef HAMMER_CPU
492 #error "You need to specify a cpu type"
493 #endif
494 /*
495 * Now that we have told the user what they have,
496 * let them know if that machine type isn't configured.
497 */
498 switch (cpu_class) {
499 case CPUCLASS_X86:
500 #ifndef HAMMER_CPU
501 case CPUCLASS_K8:
502 #endif
503 panic("CPU class not configured");
504 default:
505 break;
506 }
507 }
508
509
510 #if 0 /* JG */
511 /* Update TSC freq with the value indicated by the caller. */
512 static void
513 tsc_freq_changed(void *arg, const struct cf_level *level, int status)
514 {
515 /* If there was an error during the transition, don't do anything. */
516 if (status != 0)
517 return;
518
519 /* Total setting for this level gives the new frequency in MHz. */
520 hw_clockrate = level->total_set.freq;
521 }
522
523 EVENTHANDLER_DEFINE(cpufreq_post_change, tsc_freq_changed, NULL,
524 EVENTHANDLER_PRI_ANY);
525 #endif
526
527 /*
528 * Final stage of CPU identification.
529 */
530 void
531 identify_cpu(void)
532 {
533 u_int regs[4], cpu_stdext_disable;
534
535 do_cpuid(0, regs);
536 cpu_high = regs[0];
537 ((u_int *)&cpu_vendor)[0] = regs[1];
538 ((u_int *)&cpu_vendor)[1] = regs[3];
539 ((u_int *)&cpu_vendor)[2] = regs[2];
540 cpu_vendor[12] = '\0';
541 cpu_vendor_id = find_cpu_vendor_id();
542
543 do_cpuid(1, regs);
544 cpu_id = regs[0];
545 cpu_procinfo = regs[1];
546 cpu_feature = regs[3];
547 cpu_feature2 = regs[2];
548
549 if (cpu_high >= 5) {
550 do_cpuid(5, regs);
551 cpu_mwait_feature = regs[2];
552 if (cpu_mwait_feature & CPUID_MWAIT_EXT) {
553 cpu_mwait_extemu = regs[3];
554 /* At least one C1 */
555 if (CPUID_MWAIT_CX_SUBCNT(cpu_mwait_extemu, 1) == 0) {
556 /* No C1 at all, no MWAIT EXT then */
557 cpu_mwait_feature &= ~CPUID_MWAIT_EXT;
558 cpu_mwait_extemu = 0;
559 }
560 }
561 }
562 if (cpu_high >= 6) {
563 do_cpuid(6, regs);
564 cpu_thermal_feature = regs[0];
565 }
566 if (cpu_high >= 7) {
567 cpuid_count(7, 0, regs);
568 cpu_stdext_feature = regs[1];
569
570 /*
571 * Some hypervisors fail to filter out unsupported
572 * extended features. For now, disable the
573 * extensions, activation of which requires setting a
574 * bit in CR4, and which VM monitors do not support.
575 */
576 if (cpu_feature2 & CPUID2_VMM) {
577 cpu_stdext_disable = CPUID_STDEXT_FSGSBASE |
578 CPUID_STDEXT_SMEP;
579 } else
580 cpu_stdext_disable = 0;
581 TUNABLE_INT_FETCH("hw.cpu_stdext_disable", &cpu_stdext_disable);
582 cpu_stdext_feature &= ~cpu_stdext_disable;
583 }
584
585 if (cpu_vendor_id == CPU_VENDOR_INTEL ||
586 cpu_vendor_id == CPU_VENDOR_AMD ||
587 cpu_vendor_id == CPU_VENDOR_CENTAUR) {
588 do_cpuid(0x80000000, regs);
589 cpu_exthigh = regs[0];
590 }
591 if (cpu_exthigh >= 0x80000001) {
592 do_cpuid(0x80000001, regs);
593 amd_feature = regs[3] & ~(cpu_feature & 0x0183f3ff);
594 amd_feature2 = regs[2];
595 }
596 if (cpu_exthigh >= 0x80000008) {
597 do_cpuid(0x80000008, regs);
598 cpu_procinfo2 = regs[2];
599 }
600
601 /* XXX */
602 cpu = CPU_CLAWHAMMER;
603
604 if (cpu_feature & CPUID_SSE2)
605 cpu_mi_feature |= CPU_MI_BZERONT;
606
607 if (cpu_feature2 & CPUID2_MON)
608 cpu_mi_feature |= CPU_MI_MONITOR;
609
610 /*
611 * We do assume that all CPUs have the same
612 * SSE/FXSR features
613 */
614 if ((cpu_feature & CPUID_XMM) &&
615 (cpu_feature & CPUID_FXSR)) {
616 npxprobemask();
617 }
618 }
619
620 static u_int
621 find_cpu_vendor_id(void)
622 {
623 int i;
624
625 for (i = 0; i < NELEM(cpu_vendors); i++)
626 if (strcmp(cpu_vendor, cpu_vendors[i].vendor) == 0)
627 return (cpu_vendors[i].vendor_id);
628 return (0);
629 }
630
631 static void
632 print_AMD_assoc(int i)
633 {
634 if (i == 255)
635 kprintf(", fully associative\n");
636 else
637 kprintf(", %d-way associative\n", i);
638 }
639
640 static void
641 print_AMD_l2_assoc(int i)
642 {
643 switch (i & 0x0f) {
644 case 0: kprintf(", disabled/not present\n"); break;
645 case 1: kprintf(", direct mapped\n"); break;
646 case 2: kprintf(", 2-way associative\n"); break;
647 case 4: kprintf(", 4-way associative\n"); break;
648 case 6: kprintf(", 8-way associative\n"); break;
649 case 8: kprintf(", 16-way associative\n"); break;
650 case 15: kprintf(", fully associative\n"); break;
651 default: kprintf(", reserved configuration\n"); break;
652 }
653 }
654
655 static void
656 print_AMD_info(void)
657 {
658 u_int regs[4];
659
660 if (cpu_exthigh < 0x80000005)
661 return;
662
663 do_cpuid(0x80000005, regs);
664 kprintf("L1 2MB data TLB: %d entries", (regs[0] >> 16) & 0xff);
665 print_AMD_assoc(regs[0] >> 24);
666
667 kprintf("L1 2MB instruction TLB: %d entries", regs[0] & 0xff);
668 print_AMD_assoc((regs[0] >> 8) & 0xff);
669
670 kprintf("L1 4KB data TLB: %d entries", (regs[1] >> 16) & 0xff);
671 print_AMD_assoc(regs[1] >> 24);
672
673 kprintf("L1 4KB instruction TLB: %d entries", regs[1] & 0xff);
674 print_AMD_assoc((regs[1] >> 8) & 0xff);
675
676 kprintf("L1 data cache: %d kbytes", regs[2] >> 24);
677 kprintf(", %d bytes/line", regs[2] & 0xff);
678 kprintf(", %d lines/tag", (regs[2] >> 8) & 0xff);
679 print_AMD_assoc((regs[2] >> 16) & 0xff);
680
681 kprintf("L1 instruction cache: %d kbytes", regs[3] >> 24);
682 kprintf(", %d bytes/line", regs[3] & 0xff);
683 kprintf(", %d lines/tag", (regs[3] >> 8) & 0xff);
684 print_AMD_assoc((regs[3] >> 16) & 0xff);
685
686 if (cpu_exthigh >= 0x80000006) {
687 do_cpuid(0x80000006, regs);
688 if ((regs[0] >> 16) != 0) {
689 kprintf("L2 2MB data TLB: %d entries",
690 (regs[0] >> 16) & 0xfff);
691 print_AMD_l2_assoc(regs[0] >> 28);
692 kprintf("L2 2MB instruction TLB: %d entries",
693 regs[0] & 0xfff);
694 print_AMD_l2_assoc((regs[0] >> 28) & 0xf);
695 } else {
696 kprintf("L2 2MB unified TLB: %d entries",
697 regs[0] & 0xfff);
698 print_AMD_l2_assoc((regs[0] >> 28) & 0xf);
699 }
700 if ((regs[1] >> 16) != 0) {
701 kprintf("L2 4KB data TLB: %d entries",
702 (regs[1] >> 16) & 0xfff);
703 print_AMD_l2_assoc(regs[1] >> 28);
704
705 kprintf("L2 4KB instruction TLB: %d entries",
706 (regs[1] >> 16) & 0xfff);
707 print_AMD_l2_assoc((regs[1] >> 28) & 0xf);
708 } else {
709 kprintf("L2 4KB unified TLB: %d entries",
710 (regs[1] >> 16) & 0xfff);
711 print_AMD_l2_assoc((regs[1] >> 28) & 0xf);
712 }
713 kprintf("L2 unified cache: %d kbytes", regs[2] >> 16);
714 kprintf(", %d bytes/line", regs[2] & 0xff);
715 kprintf(", %d lines/tag", (regs[2] >> 8) & 0x0f);
716 print_AMD_l2_assoc((regs[2] >> 12) & 0x0f);
717 }
718 }
719
720 static void
721 print_via_padlock_info(void)
722 {
723 u_int regs[4];
724
725 /* Check for supported models. */
726 switch (cpu_id & 0xff0) {
727 case 0x690:
728 if ((cpu_id & 0xf) < 3)
729 return;
730 case 0x6a0:
731 case 0x6d0:
732 case 0x6f0:
733 break;
734 default:
735 return;
736 }
737
738 do_cpuid(0xc0000000, regs);
739 if (regs[0] >= 0xc0000001)
740 do_cpuid(0xc0000001, regs);
741 else
742 return;
743
744 kprintf("\n VIA Padlock Features=0x%b", regs[3],
745 "\020"
746 "\003RNG" /* RNG */
747 "\007AES" /* ACE */
748 "\011AES-CTR" /* ACE2 */
749 "\013SHA1,SHA256" /* PHE */
750 "\015RSA" /* PMM */
751 );
752 }
DragonFly BSD