| blob | 8dd7f9fdd04967e1dd8cf4cdfb24c0aea686f93d |
1 /******************************************************************************
3 Copyright (c) 2001-2017, Intel Corporation
4 All rights reserved.
6 Redistribution and use in source and binary forms, with or without
7 modification, are permitted provided that the following conditions are met:
9 1. Redistributions of source code must retain the above copyright notice,
10 this list of conditions and the following disclaimer.
12 2. Redistributions in binary form must reproduce the above copyright
13 notice, this list of conditions and the following disclaimer in the
14 documentation and/or other materials provided with the distribution.
16 3. Neither the name of the Intel Corporation nor the names of its
17 contributors may be used to endorse or promote products derived from
18 this software without specific prior written permission.
20 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
21 AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
22 IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
23 ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
24 LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
25 CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
26 SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
27 INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
28 CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
29 ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
30 POSSIBILITY OF SUCH DAMAGE.
32 ******************************************************************************/
33 /*$FreeBSD$*/
47 u16 count);
61 u16 offset);
63 /**
64 * ixgbe_init_ops_generic - Inits function ptrs
65 * @hw: pointer to the hardware structure
66 *
67 * Initialize the function pointers.
68 **/
70 {
77 /* EEPROM */
79 /* If EEPROM is valid (bit 8 = 1), use EERD otherwise use bit bang */
86 ixgbe_read_eeprom_buffer_bit_bang_generic;
87 }
91 ixgbe_validate_eeprom_checksum_generic;
95 /* MAC */
112 /* LEDs */
119 /* RAR, Multicast, VLAN */
137 /* Flow Control */
142 /* Link */
151 }
153 /**
154 * ixgbe_device_supports_autoneg_fc - Check if device supports autonegotiation
155 * of flow control
156 * @hw: pointer to hardware structure
157 *
158 * This function returns TRUE if the device supports flow control
159 * autonegotiation, and FALSE if it does not.
160 *
161 **/
163 {
165 ixgbe_link_speed speed;
174 /* flow control autoneg black list */
184 /* if link is down, assume supported */
188 else
190 }
196 else
200 /* only some copper devices support flow control autoneg */
216 }
219 }
226 }
228 /**
229 * ixgbe_setup_fc_generic - Set up flow control
230 * @hw: pointer to hardware structure
231 *
232 * Called at init time to set up flow control.
233 **/
235 {
243 /* Validate the requested mode */
249 }
251 /*
252 * 10gig parts do not have a word in the EEPROM to determine the
253 * default flow control setting, so we explicitly set it to full.
254 */
258 /*
259 * Set up the 1G and 10G flow control advertisement registers so the
260 * HW will be able to do fc autoneg once the cable is plugged in. If
261 * we link at 10G, the 1G advertisement is harmless and vice versa.
262 */
265 /* some MAC's need RMW protection on AUTOC */
270 /* fall through - only backplane uses autoc */
283 }
285 /*
286 * The possible values of fc.requested_mode are:
287 * 0: Flow control is completely disabled
288 * 1: Rx flow control is enabled (we can receive pause frames,
289 * but not send pause frames).
290 * 2: Tx flow control is enabled (we can send pause frames but
291 * we do not support receiving pause frames).
292 * 3: Both Rx and Tx flow control (symmetric) are enabled.
293 * other: Invalid.
294 */
297 /* Flow control completely disabled by software override. */
301 IXGBE_AUTOC_ASM_PAUSE);
306 /*
307 * Tx Flow control is enabled, and Rx Flow control is
308 * disabled by software override.
309 */
318 }
321 /*
322 * Rx Flow control is enabled and Tx Flow control is
323 * disabled by software override. Since there really
324 * isn't a way to advertise that we are capable of RX
325 * Pause ONLY, we will advertise that we support both
326 * symmetric and asymmetric Rx PAUSE, as such we fall
327 * through to the fc_full statement. Later, we will
328 * disable the adapter's ability to send PAUSE frames.
329 */
331 /* Flow control (both Rx and Tx) is enabled by SW override. */
335 IXGBE_AUTOC_ASM_PAUSE;
345 }
348 /*
349 * Enable auto-negotiation between the MAC & PHY;
350 * the MAC will advertise clause 37 flow control.
351 */
355 /* Disable AN timeout */
361 }
363 /*
364 * AUTOC restart handles negotiation of 1G and 10G on backplane
365 * and copper. There is no need to set the PCS1GCTL register.
366 *
367 */
377 }
380 out:
382 }
384 /**
385 * ixgbe_start_hw_generic - Prepare hardware for Tx/Rx
386 * @hw: pointer to hardware structure
387 *
388 * Starts the hardware by filling the bus info structure and media type, clears
389 * all on chip counters, initializes receive address registers, multicast
390 * table, VLAN filter table, calls routine to set up link and flow control
391 * settings, and leaves transmit and receive units disabled and uninitialized
392 **/
394 {
395 s32 ret_val;
396 u32 ctrl_ext;
397 u16 device_caps;
401 /* Set the media type */
404 /* PHY ops initialization must be done in reset_hw() */
406 /* Clear the VLAN filter table */
409 /* Clear statistics registers */
412 /* Set No Snoop Disable */
418 /* Setup flow control */
423 }
425 /* Cache bit indicating need for crosstalk fix */
433 else
439 }
441 /* Clear adapter stopped flag */
445 }
447 /**
448 * ixgbe_start_hw_gen2 - Init sequence for common device family
449 * @hw: pointer to hw structure
450 *
451 * Performs the init sequence common to the second generation
452 * of 10 GbE devices.
453 * Devices in the second generation:
454 * 82599
455 * X540
456 **/
458 {
459 u32 i;
460 u32 regval;
462 /* Clear the rate limiters */
466 }
469 /* Disable relaxed ordering */
474 }
479 IXGBE_DCA_RXCTRL_HEAD_WRO_EN);
481 }
484 }
486 /**
487 * ixgbe_init_hw_generic - Generic hardware initialization
488 * @hw: pointer to hardware structure
489 *
490 * Initialize the hardware by resetting the hardware, filling the bus info
491 * structure and media type, clears all on chip counters, initializes receive
492 * address registers, multicast table, VLAN filter table, calls routine to set
493 * up link and flow control settings, and leaves transmit and receive units
494 * disabled and uninitialized
495 **/
497 {
498 s32 status;
502 /* Reset the hardware */
506 /* Start the HW */
508 }
510 /* Initialize the LED link active for LED blink support */
518 }
520 /**
521 * ixgbe_clear_hw_cntrs_generic - Generic clear hardware counters
522 * @hw: pointer to hardware structure
523 *
524 * Clears all hardware statistics counters by reading them from the hardware
525 * Statistics counters are clear on read.
526 **/
528 {
551 }
562 }
563 }
615 }
616 }
629 }
632 }
634 /**
635 * ixgbe_read_pba_string_generic - Reads part number string from EEPROM
636 * @hw: pointer to hardware structure
637 * @pba_num: stores the part number string from the EEPROM
638 * @pba_num_size: part number string buffer length
639 *
640 * Reads the part number string from the EEPROM.
641 **/
643 u32 pba_num_size)
644 {
645 s32 ret_val;
646 u16 data;
647 u16 pba_ptr;
648 u16 offset;
649 u16 length;
656 }
662 }
668 }
670 /*
671 * if data is not ptr guard the PBA must be in legacy format which
672 * means pba_ptr is actually our second data word for the PBA number
673 * and we can decode it into an ascii string
674 */
678 /* we will need 11 characters to store the PBA */
682 }
684 /* extract hex string from data and pba_ptr */
696 /* put a null character on the end of our string */
699 /* switch all the data but the '-' to hex char */
705 }
708 }
714 }
719 }
721 /* check if pba_num buffer is big enough */
725 }
727 /* trim pba length from start of string */
728 pba_ptr++;
729 length--;
736 }
739 }
743 }
745 /**
746 * ixgbe_read_pba_num_generic - Reads part number from EEPROM
747 * @hw: pointer to hardware structure
748 * @pba_num: stores the part number from the EEPROM
749 *
750 * Reads the part number from the EEPROM.
751 **/
753 {
754 s32 ret_val;
755 u16 data;
766 }
773 }
777 }
779 /**
780 * ixgbe_read_pba_raw
781 * @hw: pointer to the HW structure
782 * @eeprom_buf: optional pointer to EEPROM image
783 * @eeprom_buf_size: size of EEPROM image in words
784 * @max_pba_block_size: PBA block size limit
785 * @pba: pointer to output PBA structure
786 *
787 * Reads PBA from EEPROM image when eeprom_buf is not NULL.
788 * Reads PBA from physical EEPROM device when eeprom_buf is NULL.
789 *
790 **/
794 {
795 s32 ret_val;
796 u16 pba_block_size;
812 }
813 }
820 eeprom_buf_size,
830 pba_block_size,
836 pba_block_size)) {
842 }
843 }
844 }
847 }
849 /**
850 * ixgbe_write_pba_raw
851 * @hw: pointer to the HW structure
852 * @eeprom_buf: optional pointer to EEPROM image
853 * @eeprom_buf_size: size of EEPROM image in words
854 * @pba: pointer to PBA structure
855 *
856 * Writes PBA to EEPROM image when eeprom_buf is not NULL.
857 * Writes PBA to physical EEPROM device when eeprom_buf is NULL.
858 *
859 **/
862 {
863 s32 ret_val;
879 }
880 }
900 }
901 }
902 }
905 }
907 /**
908 * ixgbe_get_pba_block_size
909 * @hw: pointer to the HW structure
910 * @eeprom_buf: optional pointer to EEPROM image
911 * @eeprom_buf_size: size of EEPROM image in words
912 * @pba_data_size: pointer to output variable
913 *
914 * Returns the size of the PBA block in words. Function operates on EEPROM
915 * image if the eeprom_buf pointer is not NULL otherwise it accesses physical
916 * EEPROM device.
917 *
918 **/
921 {
922 s32 ret_val;
924 u16 length;
939 }
940 }
951 else
953 }
958 /* PBA number in legacy format, there is no PBA Block. */
960 }
966 }
968 /**
969 * ixgbe_get_mac_addr_generic - Generic get MAC address
970 * @hw: pointer to hardware structure
971 * @mac_addr: Adapter MAC address
972 *
973 * Reads the adapter's MAC address from first Receive Address Register (RAR0)
974 * A reset of the adapter must be performed prior to calling this function
975 * in order for the MAC address to have been loaded from the EEPROM into RAR0
976 **/
978 {
979 u32 rar_high;
980 u32 rar_low;
981 u16 i;
995 }
997 /**
998 * ixgbe_set_pci_config_data_generic - Generic store PCI bus info
999 * @hw: pointer to hardware structure
1000 * @link_status: the link status returned by the PCI config space
1001 *
1002 * Stores the PCI bus info (speed, width, type) within the ixgbe_hw structure
1003 **/
1005 {
1027 }
1042 }
1045 }
1047 /**
1048 * ixgbe_get_bus_info_generic - Generic set PCI bus info
1049 * @hw: pointer to hardware structure
1050 *
1051 * Gets the PCI bus info (speed, width, type) then calls helper function to
1052 * store this data within the ixgbe_hw structure.
1053 **/
1055 {
1056 u16 link_status;
1060 /* Get the negotiated link width and speed from PCI config space */
1066 }
1068 /**
1069 * ixgbe_set_lan_id_multi_port_pcie - Set LAN id for PCIe multiple port devices
1070 * @hw: pointer to the HW structure
1071 *
1072 * Determines the LAN function id by reading memory-mapped registers and swaps
1073 * the port value if requested, and set MAC instance for devices that share
1074 * CS4227.
1075 **/
1077 {
1079 u32 reg;
1080 u16 ee_ctrl_4;
1088 /* check for a port swap */
1093 /* Get MAC instance from EEPROM for configuring CS4227 */
1097 IXGBE_EE_CTRL_4_INST_ID_SHIFT;
1098 }
1099 }
1101 /**
1102 * ixgbe_stop_adapter_generic - Generic stop Tx/Rx units
1103 * @hw: pointer to hardware structure
1104 *
1105 * Sets the adapter_stopped flag within ixgbe_hw struct. Clears interrupts,
1106 * disables transmit and receive units. The adapter_stopped flag is used by
1107 * the shared code and drivers to determine if the adapter is in a stopped
1108 * state and should not touch the hardware.
1109 **/
1111 {
1112 u32 reg_val;
1113 u16 i;
1117 /*
1118 * Set the adapter_stopped flag so other driver functions stop touching
1119 * the hardware
1120 */
1123 /* Disable the receive unit */
1126 /* Clear interrupt mask to stop interrupts from being generated */
1129 /* Clear any pending interrupts, flush previous writes */
1132 /* Disable the transmit unit. Each queue must be disabled. */
1136 /* Disable the receive unit by stopping each queue */
1142 }
1144 /* flush all queues disables */
1148 /*
1149 * Prevent the PCI-E bus from hanging by disabling PCI-E master
1150 * access and verify no pending requests
1151 */
1153 }
1155 /**
1156 * ixgbe_init_led_link_act_generic - Store the LED index link/activity.
1157 * @hw: pointer to hardware structure
1158 *
1159 * Store the index for the link active LED. This will be used to support
1160 * blinking the LED.
1161 **/
1163 {
1166 u8 i;
1170 /* Get LED link active from the LEDCTL register */
1175 IXGBE_LED_LINK_ACTIVE) {
1178 }
1179 }
1181 /*
1182 * If LEDCTL register does not have the LED link active set, then use
1183 * known MAC defaults.
1184 */
1192 }
1194 }
1196 /**
1197 * ixgbe_led_on_generic - Turns on the software controllable LEDs.
1198 * @hw: pointer to hardware structure
1199 * @index: led number to turn on
1200 **/
1202 {
1210 /* To turn on the LED, set mode to ON. */
1217 }
1219 /**
1220 * ixgbe_led_off_generic - Turns off the software controllable LEDs.
1221 * @hw: pointer to hardware structure
1222 * @index: led number to turn off
1223 **/
1225 {
1233 /* To turn off the LED, set mode to OFF. */
1240 }
1242 /**
1243 * ixgbe_init_eeprom_params_generic - Initialize EEPROM params
1244 * @hw: pointer to hardware structure
1245 *
1246 * Initializes the EEPROM parameters ixgbe_eeprom_info within the
1247 * ixgbe_hw struct in order to set up EEPROM access.
1248 **/
1250 {
1252 u32 eec;
1253 u16 eeprom_size;
1259 /* Set default semaphore delay to 10ms which is a well
1260 * tested value */
1262 /* Clear EEPROM page size, it will be initialized as needed */
1265 /*
1266 * Check for EEPROM present first.
1267 * If not present leave as none
1268 */
1273 /*
1274 * SPI EEPROM is assumed here. This code would need to
1275 * change if a future EEPROM is not SPI.
1276 */
1278 IXGBE_EEC_SIZE_SHIFT);
1280 IXGBE_EEPROM_WORD_SIZE_SHIFT);
1281 }
1285 else
1290 }
1293 }
1295 /**
1296 * ixgbe_write_eeprom_buffer_bit_bang_generic - Write EEPROM using bit-bang
1297 * @hw: pointer to hardware structure
1298 * @offset: offset within the EEPROM to write
1299 * @words: number of word(s)
1300 * @data: 16 bit word(s) to write to EEPROM
1301 *
1302 * Reads 16 bit word(s) from EEPROM through bit-bang method
1303 **/
1306 {
1317 }
1322 }
1324 /*
1325 * The EEPROM page size cannot be queried from the chip. We do lazy
1326 * initialization. It is worth to do that when we write large buffer.
1327 */
1332 /*
1333 * We cannot hold synchronization semaphores for too long
1334 * to avoid other entity starvation. However it is more efficient
1335 * to read in bursts than synchronizing access for each word.
1336 */
1345 }
1347 out:
1349 }
1351 /**
1352 * ixgbe_write_eeprom_buffer_bit_bang - Writes 16 bit word(s) to EEPROM
1353 * @hw: pointer to hardware structure
1354 * @offset: offset within the EEPROM to be written to
1355 * @words: number of word(s)
1356 * @data: 16 bit word(s) to be written to the EEPROM
1357 *
1358 * If ixgbe_eeprom_update_checksum is not called after this function, the
1359 * EEPROM will most likely contain an invalid checksum.
1360 **/
1363 {
1364 s32 status;
1365 u16 word;
1366 u16 page_size;
1367 u16 i;
1372 /* Prepare the EEPROM for writing */
1379 }
1380 }
1386 /* Send the WRITE ENABLE command (8 bit opcode ) */
1388 IXGBE_EEPROM_WREN_OPCODE_SPI,
1389 IXGBE_EEPROM_OPCODE_BITS);
1393 /*
1394 * Some SPI eeproms use the 8th address bit embedded
1395 * in the opcode
1396 */
1401 /* Send the Write command (8-bit opcode + addr) */
1403 IXGBE_EEPROM_OPCODE_BITS);
1409 /* Send the data in burst via SPI*/
1418 /* do not wrap around page */
1426 }
1427 /* Done with writing - release the EEPROM */
1429 }
1432 }
1434 /**
1435 * ixgbe_write_eeprom_generic - Writes 16 bit value to EEPROM
1436 * @hw: pointer to hardware structure
1437 * @offset: offset within the EEPROM to be written to
1438 * @data: 16 bit word to be written to the EEPROM
1439 *
1440 * If ixgbe_eeprom_update_checksum is not called after this function, the
1441 * EEPROM will most likely contain an invalid checksum.
1442 **/
1444 {
1445 s32 status;
1454 }
1458 out:
1460 }
1462 /**
1463 * ixgbe_read_eeprom_buffer_bit_bang_generic - Read EEPROM using bit-bang
1464 * @hw: pointer to hardware structure
1465 * @offset: offset within the EEPROM to be read
1466 * @data: read 16 bit words(s) from EEPROM
1467 * @words: number of word(s)
1468 *
1469 * Reads 16 bit word(s) from EEPROM through bit-bang method
1470 **/
1473 {
1484 }
1489 }
1491 /*
1492 * We cannot hold synchronization semaphores for too long
1493 * to avoid other entity starvation. However it is more efficient
1494 * to read in bursts than synchronizing access for each word.
1495 */
1505 }
1507 out:
1509 }
1511 /**
1512 * ixgbe_read_eeprom_buffer_bit_bang - Read EEPROM using bit-bang
1513 * @hw: pointer to hardware structure
1514 * @offset: offset within the EEPROM to be read
1515 * @words: number of word(s)
1516 * @data: read 16 bit word(s) from EEPROM
1517 *
1518 * Reads 16 bit word(s) from EEPROM through bit-bang method
1519 **/
1522 {
1523 s32 status;
1524 u16 word_in;
1526 u16 i;
1530 /* Prepare the EEPROM for reading */
1537 }
1538 }
1543 /*
1544 * Some SPI eeproms use the 8th address bit embedded
1545 * in the opcode
1546 */
1551 /* Send the READ command (opcode + addr) */
1553 IXGBE_EEPROM_OPCODE_BITS);
1557 /* Read the data. */
1560 }
1562 /* End this read operation */
1564 }
1567 }
1569 /**
1570 * ixgbe_read_eeprom_bit_bang_generic - Read EEPROM word using bit-bang
1571 * @hw: pointer to hardware structure
1572 * @offset: offset within the EEPROM to be read
1573 * @data: read 16 bit value from EEPROM
1574 *
1575 * Reads 16 bit value from EEPROM through bit-bang method
1576 **/
1579 {
1580 s32 status;
1589 }
1593 out:
1595 }
1597 /**
1598 * ixgbe_read_eerd_buffer_generic - Read EEPROM word(s) using EERD
1599 * @hw: pointer to hardware structure
1600 * @offset: offset of word in the EEPROM to read
1601 * @words: number of word(s)
1602 * @data: 16 bit word(s) from the EEPROM
1603 *
1604 * Reads a 16 bit word(s) from the EEPROM using the EERD register.
1605 **/
1608 {
1609 u32 eerd;
1611 u32 i;
1621 }
1627 }
1631 IXGBE_EEPROM_RW_REG_START;
1638 IXGBE_EEPROM_RW_REG_DATA);
1642 }
1643 }
1644 out:
1646 }
1648 /**
1649 * ixgbe_detect_eeprom_page_size_generic - Detect EEPROM page size
1650 * @hw: pointer to hardware structure
1651 * @offset: offset within the EEPROM to be used as a scratch pad
1652 *
1653 * Discover EEPROM page size by writing marching data at given offset.
1654 * This function is called only when we are writing a new large buffer
1655 * at given offset so the data would be overwritten anyway.
1656 **/
1658 u16 offset)
1659 {
1662 u16 i;
1680 /*
1681 * When writing in burst more than the actual page size
1682 * EEPROM address wraps around current page.
1683 */
1688 out:
1690 }
1692 /**
1693 * ixgbe_read_eerd_generic - Read EEPROM word using EERD
1694 * @hw: pointer to hardware structure
1695 * @offset: offset of word in the EEPROM to read
1696 * @data: word read from the EEPROM
1697 *
1698 * Reads a 16 bit word from the EEPROM using the EERD register.
1699 **/
1701 {
1703 }
1705 /**
1706 * ixgbe_write_eewr_buffer_generic - Write EEPROM word(s) using EEWR
1707 * @hw: pointer to hardware structure
1708 * @offset: offset of word in the EEPROM to write
1709 * @words: number of word(s)
1710 * @data: word(s) write to the EEPROM
1711 *
1712 * Write a 16 bit word(s) to the EEPROM using the EEWR register.
1713 **/
1716 {
1717 u32 eewr;
1719 u16 i;
1729 }
1735 }
1740 IXGBE_EEPROM_RW_REG_START;
1746 }
1754 }
1755 }
1757 out:
1759 }
1761 /**
1762 * ixgbe_write_eewr_generic - Write EEPROM word using EEWR
1763 * @hw: pointer to hardware structure
1764 * @offset: offset of word in the EEPROM to write
1765 * @data: word write to the EEPROM
1766 *
1767 * Write a 16 bit word to the EEPROM using the EEWR register.
1768 **/
1770 {
1772 }
1774 /**
1775 * ixgbe_poll_eerd_eewr_done - Poll EERD read or EEWR write status
1776 * @hw: pointer to hardware structure
1777 * @ee_reg: EEPROM flag for polling
1778 *
1779 * Polls the status bit (bit 1) of the EERD or EEWR to determine when the
1780 * read or write is done respectively.
1781 **/
1783 {
1784 u32 i;
1785 u32 reg;
1793 else
1799 }
1801 }
1808 }
1810 /**
1811 * ixgbe_acquire_eeprom - Acquire EEPROM using bit-bang
1812 * @hw: pointer to hardware structure
1813 *
1814 * Prepares EEPROM for access using bit-bang method. This function should
1815 * be called before issuing a command to the EEPROM.
1816 **/
1818 {
1820 u32 eec;
1821 u32 i;
1832 /* Request EEPROM Access */
1841 }
1843 /* Release if grant not acquired */
1851 }
1853 /* Setup EEPROM for Read/Write */
1855 /* Clear CS and SK */
1860 }
1861 }
1863 }
1865 /**
1866 * ixgbe_get_eeprom_semaphore - Get hardware semaphore
1867 * @hw: pointer to hardware structure
1868 *
1869 * Sets the hardware semaphores so EEPROM access can occur for bit-bang method
1870 **/
1872 {
1875 u32 i;
1876 u32 swsm;
1881 /* Get SMBI software semaphore between device drivers first */
1883 /*
1884 * If the SMBI bit is 0 when we read it, then the bit will be
1885 * set and we have the semaphore
1886 */
1891 }
1893 }
1898 /*
1899 * this release is particularly important because our attempts
1900 * above to get the semaphore may have succeeded, and if there
1901 * was a timeout, we should unconditionally clear the semaphore
1902 * bits to free the driver to make progress
1903 */
1907 /*
1908 * one last try
1909 * If the SMBI bit is 0 when we read it, then the bit will be
1910 * set and we have the semaphore
1911 */
1915 }
1917 /* Now get the semaphore between SW/FW through the SWESMBI bit */
1922 /* Set the SW EEPROM semaphore bit to request access */
1926 /*
1927 * If we set the bit successfully then we got the
1928 * semaphore.
1929 */
1935 }
1937 /*
1938 * Release semaphores and return error if SW EEPROM semaphore
1939 * was not granted because we don't have access to the EEPROM
1940 */
1946 }
1949 "Software semaphore SMBI between device drivers "
1951 }
1954 }
1956 /**
1957 * ixgbe_release_eeprom_semaphore - Release hardware semaphore
1958 * @hw: pointer to hardware structure
1959 *
1960 * This function clears hardware semaphore bits.
1961 **/
1963 {
1964 u32 swsm;
1970 /* Release both semaphores by writing 0 to the bits SWESMBI and SMBI */
1974 }
1976 /**
1977 * ixgbe_ready_eeprom - Polls for EEPROM ready
1978 * @hw: pointer to hardware structure
1979 **/
1981 {
1983 u16 i;
1984 u8 spi_stat_reg;
1988 /*
1989 * Read "Status Register" repeatedly until the LSB is cleared. The
1990 * EEPROM will signal that the command has been completed by clearing
1991 * bit 0 of the internal status register. If it's not cleared within
1992 * 5 milliseconds, then error out.
1993 */
1996 IXGBE_EEPROM_OPCODE_BITS);
2003 };
2005 /*
2006 * On some parts, SPI write time could vary from 0-20mSec on 3.3V
2007 * devices (and only 0-5mSec on 5V devices)
2008 */
2012 }
2015 }
2017 /**
2018 * ixgbe_standby_eeprom - Returns EEPROM to a "standby" state
2019 * @hw: pointer to hardware structure
2020 **/
2022 {
2023 u32 eec;
2029 /* Toggle CS to flush commands */
2038 }
2040 /**
2041 * ixgbe_shift_out_eeprom_bits - Shift data bits out to the EEPROM.
2042 * @hw: pointer to hardware structure
2043 * @data: data to send to the EEPROM
2044 * @count: number of bits to shift out
2045 **/
2047 u16 count)
2048 {
2049 u32 eec;
2050 u32 mask;
2051 u32 i;
2057 /*
2058 * Mask is used to shift "count" bits of "data" out to the EEPROM
2059 * one bit at a time. Determine the starting bit based on count
2060 */
2064 /*
2065 * A "1" is shifted out to the EEPROM by setting bit "DI" to a
2066 * "1", and then raising and then lowering the clock (the SK
2067 * bit controls the clock input to the EEPROM). A "0" is
2068 * shifted out to the EEPROM by setting "DI" to "0" and then
2069 * raising and then lowering the clock.
2070 */
2073 else
2084 /*
2085 * Shift mask to signify next bit of data to shift in to the
2086 * EEPROM
2087 */
2089 };
2091 /* We leave the "DI" bit set to "0" when we leave this routine. */
2095 }
2097 /**
2098 * ixgbe_shift_in_eeprom_bits - Shift data bits in from the EEPROM
2099 * @hw: pointer to hardware structure
2100 **/
2102 {
2103 u32 eec;
2104 u32 i;
2109 /*
2110 * In order to read a register from the EEPROM, we need to shift
2111 * 'count' bits in from the EEPROM. Bits are "shifted in" by raising
2112 * the clock input to the EEPROM (setting the SK bit), and then reading
2113 * the value of the "DO" bit. During this "shifting in" process the
2114 * "DI" bit should always be clear.
2115 */
2131 }
2134 }
2136 /**
2137 * ixgbe_raise_eeprom_clk - Raises the EEPROM's clock input.
2138 * @hw: pointer to hardware structure
2139 * @eec: EEC register's current value
2140 **/
2142 {
2145 /*
2146 * Raise the clock input to the EEPROM
2147 * (setting the SK bit), then delay
2148 */
2153 }
2155 /**
2156 * ixgbe_lower_eeprom_clk - Lowers the EEPROM's clock input.
2157 * @hw: pointer to hardware structure
2158 * @eecd: EECD's current value
2159 **/
2161 {
2164 /*
2165 * Lower the clock input to the EEPROM (clearing the SK bit), then
2166 * delay
2167 */
2172 }
2174 /**
2175 * ixgbe_release_eeprom - Release EEPROM, release semaphores
2176 * @hw: pointer to hardware structure
2177 **/
2179 {
2180 u32 eec;
2194 /* Stop requesting EEPROM access */
2200 /* Delay before attempt to obtain semaphore again to allow FW access */
2202 }
2204 /**
2205 * ixgbe_calc_eeprom_checksum_generic - Calculates and returns the checksum
2206 * @hw: pointer to hardware structure
2207 *
2208 * Returns a negative error code on error, or the 16-bit checksum
2209 **/
2211 {
2212 u16 i;
2213 u16 j;
2221 /* Include 0x0-0x3F in the checksum */
2226 }
2228 }
2230 /* Include all data from pointers except for the fw pointer */
2235 }
2237 /* If the pointer seems invalid */
2244 }
2253 }
2255 }
2256 }
2261 }
2263 /**
2264 * ixgbe_validate_eeprom_checksum_generic - Validate EEPROM checksum
2265 * @hw: pointer to hardware structure
2266 * @checksum_val: calculated checksum
2267 *
2268 * Performs checksum calculation and validates the EEPROM checksum. If the
2269 * caller does not need checksum_val, the value can be NULL.
2270 **/
2273 {
2274 s32 status;
2275 u16 checksum;
2280 /* Read the first word from the EEPROM. If this times out or fails, do
2281 * not continue or we could be in for a very long wait while every
2282 * EEPROM read fails
2283 */
2288 }
2300 }
2302 /* Verify read checksum from EEPROM is the same as
2303 * calculated checksum
2304 */
2308 /* If the user cares, return the calculated checksum */
2313 }
2315 /**
2316 * ixgbe_update_eeprom_checksum_generic - Updates the EEPROM checksum
2317 * @hw: pointer to hardware structure
2318 **/
2320 {
2321 s32 status;
2322 u16 checksum;
2326 /* Read the first word from the EEPROM. If this times out or fails, do
2327 * not continue or we could be in for a very long wait while every
2328 * EEPROM read fails
2329 */
2334 }
2345 }
2347 /**
2348 * ixgbe_validate_mac_addr - Validate MAC address
2349 * @mac_addr: pointer to MAC address.
2350 *
2351 * Tests a MAC address to ensure it is a valid Individual Address.
2352 **/
2354 {
2359 /* Make sure it is not a multicast address */
2362 /* Not a broadcast address */
2365 /* Reject the zero address */
2369 }
2371 }
2373 /**
2374 * ixgbe_set_rar_generic - Set Rx address register
2375 * @hw: pointer to hardware structure
2376 * @index: Receive address register to write
2377 * @addr: Address to put into receive address register
2378 * @vmdq: VMDq "set" or "pool" index
2379 * @enable_addr: set flag that address is active
2380 *
2381 * Puts an ethernet address into a receive address register.
2382 **/
2384 u32 enable_addr)
2385 {
2391 /* Make sure we are using a valid rar index range */
2396 }
2398 /* setup VMDq pool selection before this RAR gets enabled */
2401 /*
2402 * HW expects these in little endian so we reverse the byte
2403 * order from network order (big endian) to little endian
2404 */
2409 /*
2410 * Some parts put the VMDq setting in the extra RAH bits,
2411 * so save everything except the lower 16 bits that hold part
2412 * of the address and the address valid bit.
2413 */
2425 }
2427 /**
2428 * ixgbe_clear_rar_generic - Remove Rx address register
2429 * @hw: pointer to hardware structure
2430 * @index: Receive address register to write
2431 *
2432 * Clears an ethernet address from a receive address register.
2433 **/
2435 {
2436 u32 rar_high;
2441 /* Make sure we are using a valid rar index range */
2446 }
2448 /*
2449 * Some parts put the VMDq setting in the extra RAH bits,
2450 * so save everything except the lower 16 bits that hold part
2451 * of the address and the address valid bit.
2452 */
2459 /* clear VMDq pool/queue selection for this RAR */
2463 }
2465 /**
2466 * ixgbe_init_rx_addrs_generic - Initializes receive address filters.
2467 * @hw: pointer to hardware structure
2468 *
2469 * Places the MAC address in receive address register 0 and clears the rest
2470 * of the receive address registers. Clears the multicast table. Assumes
2471 * the receiver is in reset when the routine is called.
2472 **/
2474 {
2475 u32 i;
2480 /*
2481 * If the current mac address is valid, assume it is a software override
2482 * to the permanent address.
2483 * Otherwise, use the permanent address from the eeprom.
2484 */
2486 IXGBE_ERR_INVALID_MAC_ADDR) {
2487 /* Get the MAC address from the RAR0 for later reference */
2496 /* Setup the receive address. */
2505 }
2507 /* clear VMDq pool/queue selection for RAR 0 */
2514 /* Zero out the other receive addresses. */
2519 }
2521 /* Clear the MTA */
2532 }
2534 /**
2535 * ixgbe_add_uc_addr - Adds a secondary unicast address.
2536 * @hw: pointer to hardware structure
2537 * @addr: new address
2538 *
2539 * Adds it to unused receive address register or goes into promiscuous mode.
2540 **/
2542 {
2544 u32 rar;
2551 /*
2552 * Place this address in the RAR if there is room,
2553 * else put the controller into promiscuous mode
2554 */
2562 }
2565 }
2567 /**
2568 * ixgbe_update_uc_addr_list_generic - Updates MAC list of secondary addresses
2569 * @hw: pointer to hardware structure
2570 * @addr_list: the list of new addresses
2571 * @addr_count: number of addresses
2572 * @next: iterator function to walk the address list
2573 *
2574 * The given list replaces any existing list. Clears the secondary addrs from
2575 * receive address registers. Uses unused receive address registers for the
2576 * first secondary addresses, and falls back to promiscuous mode as needed.
2577 *
2578 * Drivers using secondary unicast addresses must set user_set_promisc when
2579 * manually putting the device into promiscuous mode.
2580 **/
2583 {
2585 u32 i;
2587 u32 uc_addr_in_use;
2588 u32 fctrl;
2589 u32 vmdq;
2593 /*
2594 * Clear accounting of old secondary address list,
2595 * don't count RAR[0]
2596 */
2601 /* Zero out the other receive addresses */
2606 }
2608 /* Add the new addresses */
2613 }
2616 /* enable promisc if not already in overflow or set by user */
2622 }
2624 /* only disable if set by overflow, not by user */
2630 }
2631 }
2635 }
2637 /**
2638 * ixgbe_mta_vector - Determines bit-vector in multicast table to set
2639 * @hw: pointer to hardware structure
2640 * @mc_addr: the multicast address
2641 *
2642 * Extracts the 12 bits, from a multicast address, to determine which
2643 * bit-vector to set in the multicast table. The hardware uses 12 bits, from
2644 * incoming rx multicast addresses, to determine the bit-vector to check in
2645 * the MTA. Which of the 4 combination, of 12-bits, the hardware uses is set
2646 * by the MO field of the MCSTCTRL. The MO field is set during initialization
2647 * to mc_filter_type.
2648 **/
2650 {
2672 }
2674 /* vector can only be 12-bits or boundary will be exceeded */
2677 }
2679 /**
2680 * ixgbe_set_mta - Set bit-vector in multicast table
2681 * @hw: pointer to hardware structure
2682 * @hash_value: Multicast address hash value
2683 *
2684 * Sets the bit-vector in the multicast table.
2685 **/
2687 {
2688 u32 vector;
2689 u32 vector_bit;
2690 u32 vector_reg;
2699 /*
2700 * The MTA is a register array of 128 32-bit registers. It is treated
2701 * like an array of 4096 bits. We want to set bit
2702 * BitArray[vector_value]. So we figure out what register the bit is
2703 * in, read it, OR in the new bit, then write back the new value. The
2704 * register is determined by the upper 7 bits of the vector value and
2705 * the bit within that register are determined by the lower 5 bits of
2706 * the value.
2707 */
2711 }
2713 /**
2714 * ixgbe_update_mc_addr_list_generic - Updates MAC list of multicast addresses
2715 * @hw: pointer to hardware structure
2716 * @mc_addr_list: the list of new multicast addresses
2717 * @mc_addr_count: number of addresses
2718 * @next: iterator function to walk the multicast address list
2719 * @clear: flag, when set clears the table beforehand
2720 *
2721 * When the clear flag is set, the given list replaces any existing list.
2722 * Hashes the given addresses into the multicast table.
2723 **/
2727 {
2728 u32 i;
2729 u32 vmdq;
2733 /*
2734 * Set the new number of MC addresses that we are being requested to
2735 * use.
2736 */
2740 /* Clear mta_shadow */
2744 }
2746 /* Update mta_shadow */
2750 }
2752 /* Enable mta */
2763 }
2765 /**
2766 * ixgbe_enable_mc_generic - Enable multicast address in RAR
2767 * @hw: pointer to hardware structure
2768 *
2769 * Enables multicast address in RAR and the use of the multicast hash table.
2770 **/
2772 {
2782 }
2784 /**
2785 * ixgbe_disable_mc_generic - Disable multicast address in RAR
2786 * @hw: pointer to hardware structure
2787 *
2788 * Disables multicast address in RAR and the use of the multicast hash table.
2789 **/
2791 {
2800 }
2802 /**
2803 * ixgbe_fc_enable_generic - Enable flow control
2804 * @hw: pointer to hardware structure
2805 *
2806 * Enable flow control according to the current settings.
2807 **/
2809 {
2812 u32 reg;
2818 /* Validate the water mark configuration */
2822 }
2824 /* Low water mark of zero causes XOFF floods */
2833 }
2834 }
2835 }
2837 /* Negotiate the fc mode to use */
2840 /* Disable any previous flow control settings */
2847 /*
2848 * The possible values of fc.current_mode are:
2849 * 0: Flow control is completely disabled
2850 * 1: Rx flow control is enabled (we can receive pause frames,
2851 * but not send pause frames).
2852 * 2: Tx flow control is enabled (we can send pause frames but
2853 * we do not support receiving pause frames).
2854 * 3: Both Rx and Tx flow control (symmetric) are enabled.
2855 * other: Invalid.
2856 */
2859 /*
2860 * Flow control is disabled by software override or autoneg.
2861 * The code below will actually disable it in the HW.
2862 */
2865 /*
2866 * Rx Flow control is enabled and Tx Flow control is
2867 * disabled by software override. Since there really
2868 * isn't a way to advertise that we are capable of RX
2869 * Pause ONLY, we will advertise that we support both
2870 * symmetric and asymmetric Rx PAUSE. Later, we will
2871 * disable the adapter's ability to send PAUSE frames.
2872 */
2876 /*
2877 * Tx Flow control is enabled, and Rx Flow control is
2878 * disabled by software override.
2879 */
2883 /* Flow control (both Rx and Tx) is enabled by SW override. */
2893 }
2895 /* Set 802.3x based flow control settings. */
2901 /* Set up and enable Rx high/low water mark thresholds, enable XON. */
2910 /*
2911 * In order to prevent Tx hangs when the internal Tx
2912 * switch is enabled we must set the high water mark
2913 * to the Rx packet buffer size - 24KB. This allows
2914 * the Tx switch to function even under heavy Rx
2915 * workloads.
2916 */
2918 }
2921 }
2923 /* Configure pause time (2 TCs per register) */
2928 /* Configure flow control refresh threshold value */
2931 out:
2933 }
2935 /**
2936 * ixgbe_negotiate_fc - Negotiate flow control
2937 * @hw: pointer to hardware structure
2938 * @adv_reg: flow control advertised settings
2939 * @lp_reg: link partner's flow control settings
2940 * @adv_sym: symmetric pause bit in advertisement
2941 * @adv_asm: asymmetric pause bit in advertisement
2942 * @lp_sym: symmetric pause bit in link partner advertisement
2943 * @lp_asm: asymmetric pause bit in link partner advertisement
2944 *
2945 * Find the intersection between advertised settings and link partner's
2946 * advertised settings
2947 **/
2950 {
2953 "Local or link partner's advertised flow control "
2957 }
2960 /*
2961 * Now we need to check if the user selected Rx ONLY
2962 * of pause frames. In this case, we had to advertise
2963 * FULL flow control because we could not advertise RX
2964 * ONLY. Hence, we must now check to see if we need to
2965 * turn OFF the TRANSMISSION of PAUSE frames.
2966 */
2973 }
2985 }
2987 }
2989 /**
2990 * ixgbe_fc_autoneg_fiber - Enable flow control on 1 gig fiber
2991 * @hw: pointer to hardware structure
2992 *
2993 * Enable flow control according on 1 gig fiber.
2994 **/
2996 {
3000 /*
3001 * On multispeed fiber at 1g, bail out if
3002 * - link is up but AN did not complete, or if
3003 * - link is up and AN completed but timed out
3004 */
3011 }
3018 IXGBE_PCS1GANA_ASM_PAUSE,
3019 IXGBE_PCS1GANA_SYM_PAUSE,
3020 IXGBE_PCS1GANA_ASM_PAUSE);
3022 out:
3024 }
3026 /**
3027 * ixgbe_fc_autoneg_backplane - Enable flow control IEEE clause 37
3028 * @hw: pointer to hardware structure
3029 *
3030 * Enable flow control according to IEEE clause 37.
3031 **/
3033 {
3037 /*
3038 * On backplane, bail out if
3039 * - backplane autoneg was not completed, or if
3040 * - we are 82599 and link partner is not AN enabled
3041 */
3046 }
3053 }
3054 }
3055 /*
3056 * Read the 10g AN autoc and LP ability registers and resolve
3057 * local flow control settings accordingly
3058 */
3066 out:
3068 }
3070 /**
3071 * ixgbe_fc_autoneg_copper - Enable flow control IEEE clause 37
3072 * @hw: pointer to hardware structure
3073 *
3074 * Enable flow control according to IEEE clause 37.
3075 **/
3077 {
3082 IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
3085 IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
3092 }
3094 /**
3095 * ixgbe_fc_autoneg - Configure flow control
3096 * @hw: pointer to hardware structure
3097 *
3098 * Compares our advertised flow control capabilities to those advertised by
3099 * our link partner, and determines the proper flow control mode to use.
3100 **/
3102 {
3104 ixgbe_link_speed speed;
3109 /*
3110 * AN should have completed when the cable was plugged in.
3111 * Look for reasons to bail out. Bail out if:
3112 * - FC autoneg is disabled, or if
3113 * - link is not up.
3114 */
3119 }
3125 }
3128 /* Autoneg flow control on fiber adapters */
3136 /* Autoneg flow control on backplane adapters */
3141 /* Autoneg flow control on copper adapters */
3149 }
3151 out:
3157 }
3158 }
3160 /*
3161 * ixgbe_pcie_timeout_poll - Return number of times to poll for completion
3162 * @hw: pointer to hardware structure
3163 *
3164 * System-wide timeout range is encoded in PCIe Device Control2 register.
3165 *
3166 * Add 10% to specified maximum and return the number of times to poll for
3167 * completion timeout, in units of 100 microsec. Never return less than
3168 * 800 = 80 millisec.
3169 */
3171 {
3172 s16 devctl2;
3173 u32 pollcnt;
3201 }
3203 /* add 10% to spec maximum */
3205 }
3207 /**
3208 * ixgbe_disable_pcie_master - Disable PCI-express master access
3209 * @hw: pointer to hardware structure
3210 *
3211 * Disables PCI-Express master access and verifies there are no pending
3212 * requests. IXGBE_ERR_MASTER_REQUESTS_PENDING is returned if master disable
3213 * bit hasn't caused the master requests to be disabled, else IXGBE_SUCCESS
3214 * is returned signifying master requests disabled.
3215 **/
3217 {
3220 u16 value;
3224 /* Always set this bit to ensure any future transactions are blocked */
3227 /* Exit if master requests are blocked */
3232 /* Poll for master request bit to clear */
3237 }
3239 /*
3240 * Two consecutive resets are required via CTRL.RST per datasheet
3241 * 5.2.5.3.2 Master Disable. We set a flag to inform the reset routine
3242 * of this need. The first reset prevents new master requests from
3243 * being issued by our device. We then must wait 1usec or more for any
3244 * remaining completions from the PCIe bus to trickle in, and then reset
3245 * again to clear out any effects they may have had on our device.
3246 */
3253 /*
3254 * Before proceeding, make sure that the PCIe block does not have
3255 * transactions pending.
3256 */
3265 }
3271 out:
3273 }
3275 /**
3276 * ixgbe_acquire_swfw_sync - Acquire SWFW semaphore
3277 * @hw: pointer to hardware structure
3278 * @mask: Mask to specify which semaphore to acquire
3279 *
3280 * Acquires the SWFW semaphore through the GSSR register for the specified
3281 * function (CSR, PHY0, PHY1, EEPROM, Flash)
3282 **/
3284 {
3289 u32 i;
3294 /*
3295 * SW NVM semaphore bit is used for access to all
3296 * SW_FW_SYNC bits (not just NVM)
3297 */
3308 /* Resource is currently in use by FW or SW */
3311 }
3312 }
3314 /* If time expired clear the bits holding the lock and retry */
3320 }
3322 /**
3323 * ixgbe_release_swfw_sync - Release SWFW semaphore
3324 * @hw: pointer to hardware structure
3325 * @mask: Mask to specify which semaphore to release
3326 *
3327 * Releases the SWFW semaphore through the GSSR register for the specified
3328 * function (CSR, PHY0, PHY1, EEPROM, Flash)
3329 **/
3331 {
3332 u32 gssr;
3344 }
3346 /**
3347 * ixgbe_disable_sec_rx_path_generic - Stops the receive data path
3348 * @hw: pointer to hardware structure
3349 *
3350 * Stops the receive data path and waits for the HW to internally empty
3351 * the Rx security block
3352 **/
3354 {
3355 #define IXGBE_MAX_SECRX_POLL 4000
3370 else
3371 /* Use interrupt-safe sleep just in case */
3373 }
3375 /* For informational purposes only */
3381 }
3383 /**
3384 * prot_autoc_read_generic - Hides MAC differences needed for AUTOC read
3385 * @hw: pointer to hardware structure
3386 * @reg_val: Value we read from AUTOC
3387 *
3388 * The default case requires no protection so just to the register read.
3389 */
3391 {
3395 }
3397 /**
3398 * prot_autoc_write_generic - Hides MAC differences needed for AUTOC write
3399 * @hw: pointer to hardware structure
3400 * @reg_val: value to write to AUTOC
3401 * @locked: bool to indicate whether the SW/FW lock was already taken by
3402 * previous read.
3403 *
3404 * The default case requires no protection so just to the register write.
3405 */
3407 {
3412 }
3414 /**
3415 * ixgbe_enable_sec_rx_path_generic - Enables the receive data path
3416 * @hw: pointer to hardware structure
3417 *
3418 * Enables the receive data path.
3419 **/
3421 {
3422 u32 secrxreg;
3432 }
3434 /**
3435 * ixgbe_enable_rx_dma_generic - Enable the Rx DMA unit
3436 * @hw: pointer to hardware structure
3437 * @regval: register value to write to RXCTRL
3438 *
3439 * Enables the Rx DMA unit
3440 **/
3442 {
3447 else
3451 }
3453 /**
3454 * ixgbe_blink_led_start_generic - Blink LED based on index.
3455 * @hw: pointer to hardware structure
3456 * @index: led number to blink
3457 **/
3459 {
3472 /*
3473 * Link must be up to auto-blink the LEDs;
3474 * Force it if link is down.
3475 */
3492 }
3499 out:
3501 }
3503 /**
3504 * ixgbe_blink_led_stop_generic - Stop blinking LED based on index.
3505 * @hw: pointer to hardware structure
3506 * @index: led number to stop blinking
3507 **/
3509 {
3538 out:
3540 }
3542 /**
3543 * ixgbe_get_san_mac_addr_offset - Get SAN MAC address offset from the EEPROM
3544 * @hw: pointer to hardware structure
3545 * @san_mac_offset: SAN MAC address offset
3546 *
3547 * This function will read the EEPROM location for the SAN MAC address
3548 * pointer, and returns the value at that location. This is used in both
3549 * get and set mac_addr routines.
3550 **/
3553 {
3554 s32 ret_val;
3558 /*
3559 * First read the EEPROM pointer to see if the MAC addresses are
3560 * available.
3561 */
3563 san_mac_offset);
3567 IXGBE_SAN_MAC_ADDR_PTR);
3568 }
3571 }
3573 /**
3574 * ixgbe_get_san_mac_addr_generic - SAN MAC address retrieval from the EEPROM
3575 * @hw: pointer to hardware structure
3576 * @san_mac_addr: SAN MAC address
3577 *
3578 * Reads the SAN MAC address from the EEPROM, if it's available. This is
3579 * per-port, so set_lan_id() must be called before reading the addresses.
3580 * set_lan_id() is called by identify_sfp(), but this cannot be relied
3581 * upon for non-SFP connections, so we must call it here.
3582 **/
3584 {
3586 u8 i;
3587 s32 ret_val;
3591 /*
3592 * First read the EEPROM pointer to see if the MAC addresses are
3593 * available. If they're not, no point in calling set_lan_id() here.
3594 */
3599 /* make sure we know which port we need to program */
3601 /* apply the port offset to the address offset */
3610 san_mac_offset);
3612 }
3615 san_mac_offset++;
3616 }
3619 san_mac_addr_out:
3620 /*
3621 * No addresses available in this EEPROM. It's not an
3622 * error though, so just wipe the local address and return.
3623 */
3627 }
3629 /**
3630 * ixgbe_set_san_mac_addr_generic - Write the SAN MAC address to the EEPROM
3631 * @hw: pointer to hardware structure
3632 * @san_mac_addr: SAN MAC address
3633 *
3634 * Write a SAN MAC address to the EEPROM.
3635 **/
3637 {
3638 s32 ret_val;
3640 u8 i;
3644 /* Look for SAN mac address pointer. If not defined, return */
3649 /* Make sure we know which port we need to write */
3651 /* Apply the port offset to the address offset */
3659 san_mac_offset++;
3660 }
3663 }
3665 /**
3666 * ixgbe_get_pcie_msix_count_generic - Gets MSI-X vector count
3667 * @hw: pointer to hardware structure
3668 *
3669 * Read PCIe configuration space, and get the MSI-X vector count from
3670 * the capabilities table.
3671 **/
3673 {
3675 u16 max_msix_count;
3676 u16 pcie_offset;
3693 }
3701 /* MSI-X count is zero-based in HW */
3702 msix_count++;
3708 }
3710 /**
3711 * ixgbe_insert_mac_addr_generic - Find a RAR for this mac address
3712 * @hw: pointer to hardware structure
3713 * @addr: Address to put into receive address register
3714 * @vmdq: VMDq pool to assign
3715 *
3716 * Puts an ethernet address into a receive address register, or
3717 * finds the rar that it is aleady in; adds to the pool list
3718 **/
3720 {
3723 u32 rar;
3729 /* swap bytes for HW little endian */
3735 /*
3736 * Either find the mac_id in rar or find the first empty space.
3737 * rar_highwater points to just after the highest currently used
3738 * rar in order to shorten the search. It grows when we add a new
3739 * rar to the top.
3740 */
3751 }
3752 }
3755 /* already there so just add to the pool bits */
3758 /* stick it into first empty RAR slot we found */
3762 /* add it to the top of the list and inc the highwater mark */
3767 }
3769 /*
3770 * If we found rar[0], make sure the default pool bit (we use pool 0)
3771 * remains cleared to be sure default pool packets will get delivered
3772 */
3777 }
3779 /**
3780 * ixgbe_clear_vmdq_generic - Disassociate a VMDq pool index from a rx address
3781 * @hw: pointer to hardware struct
3782 * @rar: receive address register index to disassociate
3783 * @vmdq: VMDq pool index to remove from the rar
3784 **/
3786 {
3792 /* Make sure we are using a valid rar index range */
3797 }
3812 }
3816 }
3823 }
3825 /* was that the last pool using this rar? */
3829 done:
3831 }
3833 /**
3834 * ixgbe_set_vmdq_generic - Associate a VMDq pool index with a rx address
3835 * @hw: pointer to hardware struct
3836 * @rar: receive address register index to associate with a VMDq index
3837 * @vmdq: VMDq pool index
3838 **/
3840 {
3841 u32 mpsar;
3846 /* Make sure we are using a valid rar index range */
3851 }
3861 }
3863 }
3865 /**
3866 * This function should only be involved in the IOV mode.
3867 * In IOV mode, Default pool is next pool after the number of
3868 * VFs advertized and not 0.
3869 * MPSAR table needs to be updated for SAN_MAC RAR [hw->mac.san_mac_rar_index]
3870 *
3871 * ixgbe_set_vmdq_san_mac - Associate default VMDq pool index with a rx address
3872 * @hw: pointer to hardware struct
3873 * @vmdq: VMDq pool index
3874 **/
3876 {
3887 }
3890 }
3892 /**
3893 * ixgbe_init_uta_tables_generic - Initialize the Unicast Table Array
3894 * @hw: pointer to hardware structure
3895 **/
3897 {
3907 }
3909 /**
3910 * ixgbe_find_vlvf_slot - find the vlanid or the first empty slot
3911 * @hw: pointer to hardware structure
3912 * @vlan: VLAN id to write to VLAN filter
3913 *
3914 * return the VLVF index where this VLAN id should be placed
3915 *
3916 **/
3918 {
3920 u32 bits;
3922 /* short cut the special case */
3926 /* if vlvf_bypass is set we don't want to use an empty slot, we
3927 * will simply bypass the VLVF if there are no entries present in the
3928 * VLVF that contain our VLAN
3929 */
3932 /* add VLAN enable bit for comparison */
3935 /* Search for the vlan id in the VLVF entries. Save off the first empty
3936 * slot found along the way.
3937 *
3938 * pre-decrement loop covering (IXGBE_VLVF_ENTRIES - 1) .. 1
3939 */
3946 }
3948 /* If we are here then we didn't find the VLAN. Return first empty
3949 * slot we found during our search, else error.
3950 */
3955 }
3957 /**
3958 * ixgbe_set_vfta_generic - Set VLAN filter table
3959 * @hw: pointer to hardware structure
3960 * @vlan: VLAN id to write to VLAN filter
3961 * @vind: VMDq output index that maps queue to VLAN id in VLVFB
3962 * @vlan_on: boolean flag to turn on/off VLAN
3963 * @vlvf_bypass: boolean flag indicating updating default pool is okay
3964 *
3965 * Turn on/off specified VLAN in the VLAN filter table.
3966 **/
3969 {
3971 s32 ret_val;
3978 /*
3979 * this is a 2 part operation - first the VFTA, then the
3980 * VLVF and VLVFB if VT Mode is set
3981 * We don't write the VFTA until we know the VLVF part succeeded.
3982 */
3984 /* Part 1
3985 * The VFTA is a bitstring made up of 128 32-bit registers
3986 * that enable the particular VLAN id, much like the MTA:
3987 * bits[11-5]: which register
3988 * bits[4-0]: which bit in the register
3989 */
3994 /*
3995 * vfta_delta represents the difference between the current value
3996 * of vfta and the value we want in the register. Since the diff
3997 * is an XOR mask we can just update the vfta using an XOR
3998 */
4002 /* Part 2
4003 * Call ixgbe_set_vlvf_generic to set VLVFB and VLVF
4004 */
4011 }
4013 vfta_update:
4014 /* Update VFTA now that we are ready for traffic */
4019 }
4021 /**
4022 * ixgbe_set_vlvf_generic - Set VLAN Pool Filter
4023 * @hw: pointer to hardware structure
4024 * @vlan: VLAN id to write to VLAN filter
4025 * @vind: VMDq output index that maps queue to VLAN id in VLVFB
4026 * @vlan_on: boolean flag to turn on/off VLAN in VLVF
4027 * @vfta_delta: pointer to the difference between the current value of VFTA
4028 * and the desired value
4029 * @vfta: the desired value of the VFTA
4030 * @vlvf_bypass: boolean flag indicating updating default pool is okay
4031 *
4032 * Turn on/off specified bit in VLVF table.
4033 **/
4037 {
4038 u32 bits;
4039 s32 vlvf_index;
4046 /* If VT Mode is set
4047 * Either vlan_on
4048 * make sure the vlan is in VLVF
4049 * set the vind bit in the matching VLVFB
4050 * Or !vlan_on
4051 * clear the pool bit and possibly the vind
4052 */
4062 /* set the pool bit */
4067 /* clear the pool bit */
4072 /* Clear VFTA first, then disable VLVF. Otherwise
4073 * we run the risk of stray packets leaking into
4074 * the PF via the default pool
4075 */
4079 /* disable VLVF and clear remaining bit from pool */
4084 }
4086 /* If there are still bits set in the VLVFB registers
4087 * for the VLAN ID indicated we need to see if the
4088 * caller is requesting that we clear the VFTA entry bit.
4089 * If the caller has requested that we clear the VFTA
4090 * entry bit but there are still pools/VFs using this VLAN
4091 * ID entry then ignore the request. We're not worried
4092 * about the case where we're turning the VFTA VLAN ID
4093 * entry bit on, only when requested to turn it off as
4094 * there may be multiple pools and/or VFs using the
4095 * VLAN ID entry. In that case we cannot clear the
4096 * VFTA bit until all pools/VFs using that VLAN ID have also
4097 * been cleared. This will be indicated by "bits" being
4098 * zero.
4099 */
4102 vlvf_update:
4103 /* record pool change and enable VLAN ID if not already enabled */
4108 }
4110 /**
4111 * ixgbe_clear_vfta_generic - Clear VLAN filter table
4112 * @hw: pointer to hardware structure
4113 *
4114 * Clears the VLAN filer table, and the VMDq index associated with the filter
4115 **/
4117 {
4118 u32 offset;
4129 }
4132 }
4134 /**
4135 * ixgbe_need_crosstalk_fix - Determine if we need to do cross talk fix
4136 * @hw: pointer to hardware structure
4137 *
4138 * Contains the logic to identify if we need to verify link for the
4139 * crosstalk fix
4140 **/
4142 {
4144 /* Does FW say we need the fix */
4148 /* Only consider SFP+ PHYs i.e. media type fiber */
4155 }
4158 }
4160 /**
4161 * ixgbe_check_mac_link_generic - Determine link and speed status
4162 * @hw: pointer to hardware structure
4163 * @speed: pointer to link speed
4164 * @link_up: TRUE when link is up
4165 * @link_up_wait_to_complete: bool used to wait for link up or not
4166 *
4167 * Reads the links register to determine if link is up and the current speed
4168 **/
4171 {
4173 u32 i;
4177 /* If Crosstalk fix enabled do the sanity check of making sure
4178 * the SFP+ cage is full.
4179 */
4181 u32 sfp_cage_full;
4186 IXGBE_ESDP_SDP2;
4191 IXGBE_ESDP_SDP0;
4194 /* sanity check - No SFP+ devices here */
4197 }
4203 }
4204 }
4206 /* clear the old state */
4214 }
4223 }
4226 }
4230 else
4232 }
4240 }
4250 }
4260 }
4263 }
4265 /**
4266 * ixgbe_get_wwn_prefix_generic - Get alternative WWNN/WWPN prefix from
4267 * the EEPROM
4268 * @hw: pointer to hardware structure
4269 * @wwnn_prefix: the alternative WWNN prefix
4270 * @wwpn_prefix: the alternative WWPN prefix
4271 *
4272 * This function will read the EEPROM from the alternative SAN MAC address
4273 * block to check the support for the alternative WWNN/WWPN prefix support.
4274 **/
4277 {
4279 u16 alt_san_mac_blk_offset;
4283 /* clear output first */
4287 /* check if alternative SAN MAC is supported */
4296 /* check capability in alternative san mac address block */
4303 /* get the corresponding prefix for WWNN/WWPN */
4308 }
4314 wwn_prefix_out:
4317 wwn_prefix_err:
4321 }
4323 /**
4324 * ixgbe_get_fcoe_boot_status_generic - Get FCOE boot status from EEPROM
4325 * @hw: pointer to hardware structure
4326 * @bs: the fcoe boot status
4327 *
4328 * This function will read the FCOE boot status from the iSCSI FCOE block
4329 **/
4331 {
4333 s32 status;
4337 /* clear output first */
4340 /* check if FCOE IBA block is present */
4349 /* check if iSCSI FCOE block is populated */
4357 /* read fcoe flags in iSCSI FCOE block */
4365 else
4368 out:
4370 }
4372 /**
4373 * ixgbe_set_mac_anti_spoofing - Enable/Disable MAC anti-spoofing
4374 * @hw: pointer to hardware structure
4375 * @enable: enable or disable switch for MAC anti-spoofing
4376 * @vf: Virtual Function pool - VF Pool to set for MAC anti-spoofing
4377 *
4378 **/
4380 {
4383 u32 pfvfspoof;
4391 else
4394 }
4396 /**
4397 * ixgbe_set_vlan_anti_spoofing - Enable/Disable VLAN anti-spoofing
4398 * @hw: pointer to hardware structure
4399 * @enable: enable or disable switch for VLAN anti-spoofing
4400 * @vf: Virtual Function pool - VF Pool to set for VLAN anti-spoofing
4401 *
4402 **/
4404 {
4407 u32 pfvfspoof;
4415 else
4418 }
4420 /**
4421 * ixgbe_get_device_caps_generic - Get additional device capabilities
4422 * @hw: pointer to hardware structure
4423 * @device_caps: the EEPROM word with the extra device capabilities
4424 *
4425 * This function will read the EEPROM location for the device capabilities,
4426 * and return the word through device_caps.
4427 **/
4429 {
4435 }
4437 /**
4438 * ixgbe_enable_relaxed_ordering_gen2 - Enable relaxed ordering
4439 * @hw: pointer to hardware structure
4440 *
4441 **/
4443 {
4444 u32 regval;
4445 u32 i;
4449 /* Enable relaxed ordering */
4454 }
4459 IXGBE_DCA_RXCTRL_HEAD_WRO_EN;
4461 }
4463 }
4465 /**
4466 * ixgbe_calculate_checksum - Calculate checksum for buffer
4467 * @buffer: pointer to EEPROM
4468 * @length: size of EEPROM to calculate a checksum for
4469 * Calculates the checksum for some buffer on a specified length. The
4470 * checksum calculated is returned.
4471 **/
4473 {
4474 u32 i;
4486 }
4488 /**
4489 * ixgbe_hic_unlocked - Issue command to manageability block unlocked
4490 * @hw: pointer to the HW structure
4491 * @buffer: command to write and where the return status will be placed
4492 * @length: length of buffer, must be multiple of 4 bytes
4493 * @timeout: time in ms to wait for command completion
4494 *
4495 * Communicates with the manageability block. On success return IXGBE_SUCCESS
4496 * else returns semaphore error when encountering an error acquiring
4497 * semaphore or IXGBE_ERR_HOST_INTERFACE_COMMAND when command fails.
4498 *
4499 * This function assumes that the IXGBE_GSSR_SW_MNG_SM semaphore is held
4500 * by the caller.
4501 **/
4503 u32 timeout)
4504 {
4506 u16 dword_len;
4513 }
4515 /* Set bit 9 of FWSTS clearing FW reset indication */
4519 /* Check that the host interface is enabled. */
4524 }
4526 /* Calculate length in DWORDs. We must be DWORD aligned */
4530 }
4534 /* The device driver writes the relevant command block
4535 * into the ram area.
4536 */
4541 /* Setting this bit tells the ARC that a new command is pending. */
4549 }
4551 /* Check command completion */
4557 }
4560 }
4562 /**
4563 * ixgbe_host_interface_command - Issue command to manageability block
4564 * @hw: pointer to the HW structure
4565 * @buffer: contains the command to write and where the return status will
4566 * be placed
4567 * @length: length of buffer, must be multiple of 4 bytes
4568 * @timeout: time in ms to wait for command completion
4569 * @return_data: read and return data from the buffer (TRUE) or not (FALSE)
4570 * Needed because FW structures are big endian and decoding of
4571 * these fields can be 8 bit or 16 bit based on command. Decoding
4572 * is not easily understood without making a table of commands.
4573 * So we will leave this up to the caller to read back the data
4574 * in these cases.
4575 *
4576 * Communicates with the manageability block. On success return IXGBE_SUCCESS
4577 * else returns semaphore error when encountering an error acquiring
4578 * semaphore or IXGBE_ERR_HOST_INTERFACE_COMMAND when command fails.
4579 **/
4582 {
4584 u16 dword_len;
4585 u16 buf_len;
4586 s32 status;
4587 u32 bi;
4594 }
4596 /* Take management host interface semaphore */
4608 /* Calculate length in DWORDs */
4611 /* first pull in the header so we know the buffer length */
4615 }
4617 /* If there is any thing in data position pull it in */
4626 }
4628 /* Calculate length in DWORDs, add 3 for odd lengths */
4631 /* Pull in the rest of the buffer (bi is where we left off) */
4635 }
4637 rel_out:
4641 }
4643 /**
4644 * ixgbe_set_fw_drv_ver_generic - Sends driver version to firmware
4645 * @hw: pointer to the HW structure
4646 * @maj: driver version major number
4647 * @min: driver version minor number
4648 * @build: driver version build number
4649 * @sub: driver version sub build number
4650 *
4651 * Sends driver version number to firmware through the manageability
4652 * block. On success return IXGBE_SUCCESS
4653 * else returns IXGBE_ERR_SWFW_SYNC when encountering an error acquiring
4654 * semaphore or IXGBE_ERR_HOST_INTERFACE_COMMAND when command fails.
4655 **/
4659 {
4684 IXGBE_HI_COMMAND_TIMEOUT,
4685 TRUE);
4690 FW_CEM_RESP_STATUS_SUCCESS)
4692 else
4696 }
4699 }
4701 /**
4702 * ixgbe_set_rxpba_generic - Initialize Rx packet buffer
4703 * @hw: pointer to hardware structure
4704 * @num_pb: number of packet buffers to allocate
4705 * @headroom: reserve n KB of headroom
4706 * @strategy: packet buffer allocation strategy
4707 **/
4710 {
4715 /* Reserve headroom */
4721 /* Divide remaining packet buffer space amongst the number of packet
4722 * buffers requested using supplied strategy.
4723 */
4726 /* ixgbe_dcb_pba_80_48 strategy weight first half of packet
4727 * buffer with 5/8 of the packet buffer space.
4728 */
4734 /* fall through - configure remaining packet buffers */
4742 }
4744 /* Only support an equally distributed Tx packet buffer strategy. */
4750 }
4752 /* Clear unused TCs, if any, to zero buffer size*/
4757 }
4758 }
4760 /**
4761 * ixgbe_clear_tx_pending - Clear pending TX work from the PCIe fifo
4762 * @hw: pointer to the hardware structure
4763 *
4764 * The 82599 and x540 MACs can experience issues if TX work is still pending
4765 * when a reset occurs. This function prevents this by flushing the PCIe
4766 * buffers on the system.
4767 **/
4769 {
4771 u16 value;
4773 /*
4774 * If double reset is not requested then all transactions should
4775 * already be clear and as such there is no work to do
4776 */
4780 /*
4781 * Set loopback enable to prevent any transmits from being sent
4782 * should the link come up. This assumes that the RXCTRL.RXEN bit
4783 * has already been cleared.
4784 */
4788 /* Wait for a last completion before clearing buffers */
4792 /*
4793 * Before proceeding, make sure that the PCIe block does not have
4794 * transactions pending.
4795 */
4804 }
4806 out:
4807 /* initiate cleaning flow for buffers in the PCIe transaction layer */
4812 /* Flush all writes and allow 20usec for all transactions to clear */
4816 /* restore previous register values */
4819 }
4821 /**
4822 * ixgbe_bypass_rw_generic - Bit bang data into by_pass FW
4823 *
4824 * @hw: pointer to hardware structure
4825 * @cmd: Command we send to the FW
4826 * @status: The reply from the FW
4827 *
4828 * Bit-bangs the cmd to the by_pass FW status points to what is returned.
4829 **/
4830 #define IXGBE_BYPASS_BB_WAIT 1
4832 {
4835 u32 esdp;
4842 /* SDP vary by MAC type */
4862 }
4864 /* Set SDP pins direction */
4875 /* Generate start condition */
4886 /* Clock out the new control word and clock in the status */
4894 }
4911 else
4914 }
4916 /* stop condition */
4927 /* set the page bits to match the cmd that the status it belongs to */
4931 }
4933 /**
4934 * ixgbe_bypass_valid_rd_generic - Verify valid return from bit-bang.
4935 *
4936 * If we send a write we can't be sure it took until we can read back
4937 * that same register. It can be a problem as some of the feilds may
4938 * for valid reasons change inbetween the time wrote the register and
4939 * we read it again to verify. So this function check everything we
4940 * can check and then assumes it worked.
4941 *
4942 * @u32 in_reg - The register cmd for the bit-bang read.
4943 * @u32 out_reg - The register returned from a bit-bang read.
4944 **/
4946 {
4947 u32 mask;
4949 /* Page must match for all control pages */
4955 /* All the following can't change since the last write
4956 * - All the event actions
4957 * - The timeout value
4958 */
4961 BYPASS_WDTIMEOUT_M |
4962 BYPASS_WDT_VALUE_M;
4966 /* 0x0 is never a valid value for bypass status */
4971 /* All the following can't change since the last write
4972 * - time valid bit
4973 * - time we last sent
4974 */
4980 /* All we can check in this page is control number
4981 * which is already done above.
4982 */
4984 }
4986 /* We are as sure as we can be return TRUE */
4988 }
4990 /**
4991 * ixgbe_bypass_set_generic - Set a bypass field in the FW CTRL Regiter.
4992 *
4993 * @hw: pointer to hardware structure
4994 * @cmd: The control word we are setting.
4995 * @event: The event we are setting in the FW. This also happens to
4996 * be the mask for the event we are setting (handy)
4997 * @action: The action we set the event to in the FW. This is in a
4998 * bit field that happens to be what we want to put in
4999 * the event spot (also handy)
5000 **/
5002 u32 action)
5003 {
5008 /* Get current values */
5013 /* Set to new action */
5018 /* Page 0 force a FW eeprom write which is slow so verify */
5029 /* We have give the FW time for the write to stick */
5031 }
5034 }
5036 /**
5037 * ixgbe_bypass_rd_eep_generic - Read the bypass FW eeprom addres.
5038 *
5039 * @hw: pointer to hardware structure
5040 * @addr: The bypass eeprom address to read.
5041 * @value: The 8b of data at the address above.
5042 **/
5044 {
5045 u32 cmd;
5046 u32 status;
5049 /* send the request */
5055 /* We have give the FW time for the write to stick */
5058 /* now read the results */
5066 }
5068 /**
5069 * ixgbe_get_orom_version - Return option ROM from EEPROM
5070 *
5071 * @hw: pointer to hardware structure
5072 * @nvm_ver: pointer to output structure
5073 *
5074 * if valid option ROM version, nvm_ver->or_valid set to TRUE
5075 * else nvm_ver->or_valid is FALSE.
5076 **/
5079 {
5083 /* Option Rom may or may not be present. Start with pointer */
5086 /* make sure offset is valid */
5093 /* option rom exists and is valid */
5104 }
5106 /**
5107 * ixgbe_get_oem_prod_version - Return OEM Product version
5108 *
5109 * @hw: pointer to hardware structure
5110 * @nvm_ver: pointer to output structure
5111 *
5112 * if valid OEM product version, nvm_ver->oem_valid set to TRUE
5113 * else nvm_ver->oem_valid is FALSE.
5114 **/
5117 {
5123 /* Return is offset to OEM Product Version block is invalid */
5127 /* Read product version block */
5131 /* Return if OEM product version block is invalid */
5139 /* Return if version is invalid */
5148 }
5150 /**
5151 * ixgbe_get_etk_id - Return Etrack ID from EEPROM
5152 *
5153 * @hw: pointer to hardware structure
5154 * @nvm_ver: pointer to output structure
5155 *
5156 * word read errors will return 0xFFFF
5157 **/
5159 {
5167 /* The word order for the version format is determined by high order
5168 * word bit 15.
5169 */
5176 }
5177 }
5180 /**
5181 * ixgbe_dcb_get_rtrup2tc_generic - read rtrup2tc reg
5182 * @hw: pointer to hardware structure
5183 * @map: pointer to u8 arr for returning map
5184 *
5185 * Read the rtrup2tc HW register and resolve its content into map
5186 **/
5188 {
5196 }
5199 {
5200 u32 pfdtxgswc;
5201 u32 rxctrl;
5213 }
5214 }
5217 }
5218 }
5221 {
5222 u32 pfdtxgswc;
5223 u32 rxctrl;
5234 }
5235 }
5236 }
5238 /**
5239 * ixgbe_mng_present - returns TRUE when management capability is present
5240 * @hw: pointer to hardware structure
5241 */
5243 {
5244 u32 fwsm;
5252 }
5254 /**
5255 * ixgbe_mng_enabled - Is the manageability engine enabled?
5256 * @hw: pointer to hardware structure
5257 *
5258 * Returns TRUE if the manageability engine is enabled.
5259 **/
5261 {
5276 }
5279 }
5281 /**
5282 * ixgbe_setup_mac_link_multispeed_fiber - Set MAC link speed
5283 * @hw: pointer to hardware structure
5284 * @speed: new link speed
5285 * @autoneg_wait_to_complete: TRUE when waiting for completion is needed
5286 *
5287 * Set the link speed in the MAC and/or PHY register and restarts link.
5288 **/
5290 ixgbe_link_speed speed,
5292 {
5302 /* Mask off requested but non-supported speeds */
5309 /* Try each speed one by one, highest priority first. We do this in
5310 * software because 10Gb fiber doesn't support speed autonegotiation.
5311 */
5313 speedcnt++;
5316 /* Set the module link speed */
5321 IXGBE_LINK_SPEED_10GB_FULL);
5324 /* QSFP module automatically detects MAC link speed */
5329 }
5331 /* Allow module to change analog characteristics (1G->10G) */
5335 IXGBE_LINK_SPEED_10GB_FULL,
5336 autoneg_wait_to_complete);
5340 /* Flap the Tx laser if it has not already been done */
5343 /* Wait for the controller to acquire link. Per IEEE 802.3ap,
5344 * Section 73.10.2, we may have to wait up to 500ms if KR is
5345 * attempted. 82599 uses the same timing for 10g SFI.
5346 */
5348 /* Wait for the link partner to also set speed */
5351 /* If we have link, just jump out */
5359 }
5360 }
5363 speedcnt++;
5367 /* Set the module link speed */
5372 IXGBE_LINK_SPEED_1GB_FULL);
5375 /* QSFP module automatically detects link speed */
5380 }
5382 /* Allow module to change analog characteristics (10G->1G) */
5386 IXGBE_LINK_SPEED_1GB_FULL,
5387 autoneg_wait_to_complete);
5391 /* Flap the Tx laser if it has not already been done */
5394 /* Wait for the link partner to also set speed */
5397 /* If we have link, just jump out */
5404 }
5406 /* We didn't get link. Configure back to the highest speed we tried,
5407 * (if there was more than one). We call ourselves back with just the
5408 * single highest speed that the user requested.
5409 */
5412 highest_link_speed,
5413 autoneg_wait_to_complete);
5415 out:
5416 /* Set autoneg_advertised value based on input link speed */
5426 }
5428 /**
5429 * ixgbe_set_soft_rate_select_speed - Set module link speed
5430 * @hw: pointer to hardware structure
5431 * @speed: link speed to set
5432 *
5433 * Set module link speed via the soft rate select.
5434 */
5436 ixgbe_link_speed speed)
5437 {
5438 s32 status;
5443 /* one bit mask same as setting on */
5452 }
5454 /* Set RS0 */
5456 IXGBE_I2C_EEPROM_DEV_ADDR2,
5461 }
5466 IXGBE_I2C_EEPROM_DEV_ADDR2,
5467 eeprom_data);
5471 }
5473 /* Set RS1 */
5475 IXGBE_I2C_EEPROM_DEV_ADDR2,
5480 }
5485 IXGBE_I2C_EEPROM_DEV_ADDR2,
5486 eeprom_data);
5490 }
5491 out:
5493 }