sys/dev/netif/ix/if_ix.h

   1 /*
   2  * Copyright (c) 2001-2013, Intel Corporation
   3  * All rights reserved.
   4  *
   5  * Redistribution and use in source and binary forms, with or without
   6  * modification, are permitted provided that the following conditions are met:
   7  *
   8  *  1. Redistributions of source code must retain the above copyright notice,
   9  *     this list of conditions and the following disclaimer.
  10  *
  11  *  2. Redistributions in binary form must reproduce the above copyright
  12  *     notice, this list of conditions and the following disclaimer in the
  13  *     documentation and/or other materials provided with the distribution.
  14  *
  15  *  3. Neither the name of the Intel Corporation nor the names of its
  16  *     contributors may be used to endorse or promote products derived from
  17  *     this software without specific prior written permission.
  18  *
  19  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
  20  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
  21  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
  22  * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
  23  * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
  24  * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
  25  * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
  26  * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
  27  * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
  28  * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
  29  * POSSIBILITY OF SUCH DAMAGE.
  30  */
  31
  32 #ifndef _IF_IX_H_
  33 #define _IF_IX_H_
  34
  35 /* Tunables */
  36
  37 /*
  38  * MSI-X count
  39  */
  40 #define IX_MAX_MSIX             64
  41 #define IX_MAX_MSIX_82598       16
  42
  43 /*
  44  * RX ring count
  45  */
  46 #define IX_MAX_RXRING           16
  47 #define IX_MAX_RXRING_X550      64
  48 #define IX_MIN_RXRING_RSS       2
  49
  50 /*
  51  * TX ring count
  52  */
  53 #define IX_MAX_TXRING           16
  54 #define IX_MAX_TXRING_82598     32
  55 #define IX_MAX_TXRING_82599     64
  56 #define IX_MAX_TXRING_X540      64
  57 #define IX_MAX_TXRING_X550      64
  58
  59 /*
  60  * Default number of segments received before writing to RX related registers
  61  */
  62 #define IX_DEF_RXWREG_NSEGS     32
  63
  64 /*
  65  * Default number of segments sent before writing to TX related registers
  66  */
  67 #define IX_DEF_TXWREG_NSEGS     8
  68
  69 /*
  70  * TxDescriptors Valid Range: 64-4096 Default Value: 256 This value is the
  71  * number of transmit descriptors allocated by the driver. Increasing this
  72  * value allows the driver to queue more transmits. Each descriptor is 16
  73  * bytes. Performance tests have show the 2K value to be optimal for top
  74  * performance.
  75  */
  76 #define IX_DEF_TXD              1024
  77 #define IX_PERF_TXD             2048
  78 #define IX_MAX_TXD              4096
  79 #define IX_MIN_TXD              64
  80
  81 /*
  82  * RxDescriptors Valid Range: 64-4096 Default Value: 256 This value is the
  83  * number of receive descriptors allocated for each RX queue. Increasing this
  84  * value allows the driver to buffer more incoming packets. Each descriptor
  85  * is 16 bytes.  A receive buffer is also allocated for each descriptor.
  86  *
  87  * Note: with 8 rings and a dual port card, it is possible to bump up
  88  *      against the system mbuf pool limit, you can tune nmbclusters
  89  *      to adjust for this.
  90  */
  91 #define IX_DEF_RXD              1024
  92 #define IX_PERF_RXD             2048
  93 #define IX_MAX_RXD              4096
  94 #define IX_MIN_RXD              64
  95
  96 /* Alignment for rings */
  97 #define IX_DBA_ALIGN            128
  98
  99 #define IX_MAX_FRAME_SIZE       9728
 100 #define IX_MTU_HDR              (ETHER_HDR_LEN + ETHER_CRC_LEN + EVL_ENCAPLEN)
 101 #define IX_MAX_MTU              (IX_MAX_FRAME_SIZE - IX_MTU_HDR)
 102
 103
 104 /* Flow control constants */
 105 #define IX_FC_PAUSE             0xFFFF
 106 #define IX_FC_HI                0x20000
 107 #define IX_FC_LO                0x10000
 108
 109 /*
 110  * RSS related registers
 111  */
 112 #define IX_NRSSRK               10
 113 #define IX_RSSRK_SIZE           4
 114 #define IX_RSSRK_VAL(key, i)    (key[(i) * IX_RSSRK_SIZE] | \
 115                                  key[(i) * IX_RSSRK_SIZE + 1] << 8 | \
 116                                  key[(i) * IX_RSSRK_SIZE + 2] << 16 | \
 117                                  key[(i) * IX_RSSRK_SIZE + 3] << 24)
 118 #define IX_NRETA                32
 119 #define IX_NRETA_X550           128
 120 #define IX_NRETA_MAX            128
 121 #define IX_RETA_SIZE            4
 122
 123 #define IX_RDRTABLE_SIZE        (IX_NRETA_MAX * IX_RETA_SIZE)
 124
 125 /*
 126  * EITR
 127  */
 128 #define IX_EITR_INTVL_MASK_82598 0xffff
 129 #define IX_EITR_INTVL_MASK      0x0fff
 130 #define IX_EITR_INTVL_RSVD_MASK 0x0007
 131 #define IX_EITR_INTVL_MIN       IXGBE_MIN_EITR
 132 #define IX_EITR_INTVL_MAX       IXGBE_MAX_EITR
 133
 134 /*
 135  * Used for optimizing small rx mbufs.  Effort is made to keep the copy
 136  * small and aligned for the CPU L1 cache.
 137  *
 138  * MHLEN is typically 168 bytes, giving us 8-byte alignment.  Getting
 139  * 32 byte alignment needed for the fast bcopy results in 8 bytes being
 140  * wasted.  Getting 64 byte alignment, which _should_ be ideal for
 141  * modern Intel CPUs, results in 40 bytes wasted and a significant drop
 142  * in observed efficiency of the optimization, 97.9% -> 81.8%.
 143  */
 144 #define IX_RX_COPY_LEN          160
 145 #define IX_RX_COPY_ALIGN        (MHLEN - IX_RX_COPY_LEN)
 146
 147 #define IX_MAX_MCASTADDR        128
 148
 149 #define IX_MSIX_BAR_82598       3
 150 #define IX_MSIX_BAR_82599       4
 151
 152 #define IX_TSO_SIZE             (IP_MAXPACKET + \
 153                                  sizeof(struct ether_vlan_header))
 154
 155 /*
 156  * MUST be less than 38.  Though 82598 does not have this limit,
 157  * we don't want long TX chain.  33 should be large enough even
 158  * for 64K TSO (32 x 2K mbuf cluster and 1 x mbuf header).
 159  *
 160  * Reference:
 161  * - 82599 datasheet 7.2.1.1
 162  * - X540 datasheet 7.2.1.1
 163  */
 164 #define IX_MAX_SCATTER          33
 165 #define IX_TX_RESERVED          3       /* 1 for TX ctx, 2 reserved */
 166
 167 /* MSI and legacy interrupt */
 168 #define IX_TX_INTR_VEC          0
 169 #define IX_TX_INTR_MASK         (1 << IX_TX_INTR_VEC)
 170 #define IX_RX0_INTR_VEC         1
 171 #define IX_RX0_INTR_MASK        (1 << IX_RX0_INTR_VEC)
 172 #define IX_RX1_INTR_VEC         2
 173 #define IX_RX1_INTR_MASK        (1 << IX_RX1_INTR_VEC)
 174
 175 #define IX_INTR_RATE            8000
 176 #define IX_MSIX_RX_RATE         8000
 177 #define IX_MSIX_TX_RATE         6000
 178
 179 /* IOCTL define to gather SFP+ Diagnostic data */
 180 #define SIOCGI2C                SIOCGIFGENERIC
 181
 182 /* TX checksum offload */
 183 #define CSUM_OFFLOAD            (CSUM_IP|CSUM_TCP|CSUM_UDP)
 184
 185 #define IX_EICR_STATUS          (IXGBE_EICR_LSC | IXGBE_EICR_ECC | \
 186                                  IXGBE_EICR_GPI_SDP1 | IXGBE_EICR_GPI_SDP2 | \
 187                                  IXGBE_EICR_TS)
 188
 189 /* This is used to get SFP+ module data */
 190 struct ix_i2c_req {
 191         uint8_t         dev_addr;
 192         uint8_t         offset;
 193         uint8_t         len;
 194         uint8_t         data[8];
 195 };
 196
 197 struct ix_mc_addr {
 198         uint8_t         addr[IXGBE_ETH_LENGTH_OF_ADDRESS];
 199         uint32_t        vmdq;
 200 };
 201
 202 struct ix_tx_buf {
 203         struct mbuf     *m_head;
 204         bus_dmamap_t    map;
 205 };
 206
 207 struct ix_rx_buf {
 208         struct mbuf     *m_head;
 209         struct mbuf     *fmp;
 210         struct mbuf     *lmp;
 211         bus_dmamap_t    map;
 212         bus_addr_t      paddr;
 213         u_int           flags;
 214 #define IX_RX_COPY      0x1
 215 };
 216
 217 struct ix_softc;
 218
 219 struct ix_tx_ring {
 220         struct lwkt_serialize   tx_serialize;
 221         struct ifaltq_subque    *tx_ifsq;
 222         struct ix_softc         *tx_sc;
 223         volatile uint32_t       *tx_hdr;
 224         union ixgbe_adv_tx_desc *tx_base;
 225         struct ix_tx_buf        *tx_buf;
 226         bus_dma_tag_t           tx_tag;
 227         int8_t                  tx_running;
 228 #define IX_TX_RUNNING           100
 229 #define IX_TX_RUNNING_DEC       25
 230         uint8_t                 tx_flags;
 231 #define IX_TXFLAG_ENABLED       0x1
 232         uint16_t                tx_nmbuf;
 233         uint32_t                tx_idx;
 234         uint16_t                tx_avail;
 235         uint16_t                tx_next_avail;
 236         uint16_t                tx_next_clean;
 237         uint16_t                tx_ndesc;
 238         uint16_t                tx_wreg_nsegs;
 239         uint16_t                tx_intr_nsegs;
 240         uint16_t                tx_nsegs;
 241         int16_t                 tx_intr_vec;
 242         int                     tx_intr_cpuid;
 243         uint32_t                tx_eims;
 244         uint32_t                tx_eims_val;
 245         struct ifsubq_watchdog  tx_watchdog;
 246         struct callout          tx_gc_timer;
 247
 248         u_long                  tx_gc;
 249
 250         bus_dma_tag_t           tx_base_dtag;
 251         bus_dmamap_t            tx_base_map;
 252         bus_addr_t              tx_base_paddr;
 253
 254         bus_dma_tag_t           tx_hdr_dtag;
 255         bus_dmamap_t            tx_hdr_map;
 256         bus_addr_t              tx_hdr_paddr;
 257 } __cachealign;
 258
 259 struct ix_rx_ring {
 260         struct lwkt_serialize   rx_serialize;
 261         struct ix_softc         *rx_sc;
 262         union ixgbe_adv_rx_desc *rx_base;
 263         struct ix_rx_buf        *rx_buf;
 264         bus_dma_tag_t           rx_tag;
 265         bus_dmamap_t            rx_sparemap;
 266         uint32_t                rx_idx;
 267         uint16_t                rx_flags;
 268 #define IX_RXRING_FLAG_LRO      0x01
 269 #define IX_RXRING_FLAG_DISC     0x02
 270         uint16_t                rx_next_check;
 271         uint16_t                rx_ndesc;
 272         uint16_t                rx_mbuf_sz;
 273         uint16_t                rx_wreg_nsegs;
 274         int16_t                 rx_intr_vec;
 275         uint32_t                rx_eims;
 276         uint32_t                rx_eims_val;
 277         struct ix_tx_ring       *rx_txr;        /* piggybacked TX ring */
 278
 279 #ifdef IX_RSS_DEBUG
 280         u_long                  rx_pkts;
 281 #endif
 282
 283         bus_dma_tag_t           rx_base_dtag;
 284         bus_dmamap_t            rx_base_map;
 285         bus_addr_t              rx_base_paddr;
 286 } __cachealign;
 287
 288 struct ix_intr_data {
 289         struct lwkt_serialize   *intr_serialize;
 290         driver_intr_t           *intr_func;
 291         void                    *intr_hand;
 292         struct resource         *intr_res;
 293         void                    *intr_funcarg;
 294         int                     intr_rid;
 295         int                     intr_cpuid;
 296         int                     intr_rate;
 297         int                     intr_use;
 298 #define IX_INTR_USE_RXTX        0
 299 #define IX_INTR_USE_STATUS      1
 300 #define IX_INTR_USE_RX          2
 301 #define IX_INTR_USE_TX          3
 302         const char              *intr_desc;
 303         char                    intr_desc0[64];
 304 };
 305
 306 struct ix_softc {
 307         struct arpcom           arpcom;
 308
 309         struct ixgbe_hw         hw;
 310         struct ixgbe_osdep      osdep;
 311
 312         struct lwkt_serialize   main_serialize;
 313         uint32_t                intr_mask;
 314
 315         boolean_t               link_active;
 316
 317         int                     rx_ring_inuse;
 318         int                     tx_ring_inuse;
 319
 320         struct ix_rx_ring       *rx_rings;
 321         struct ix_tx_ring       *tx_rings;
 322
 323         struct callout          timer;
 324         int                     timer_cpuid;
 325
 326         int                     ifm_media;      /* IFM_ */
 327         uint32_t                link_speed;
 328         bool                    link_up;
 329         boolean_t               sfp_probe;      /* plyggable optics */
 330         uint32_t                phy_layer;
 331
 332         uint32_t                caps;           /* IX_CAP_ */
 333 #define IX_CAP_DETECT_FANFAIL   0x0001
 334 #define IX_CAP_TEMP_SENSOR      0x0002
 335 #define IX_CAP_EEE              0x0004
 336 #define IX_CAP_LEGACY_INTR      0x0008
 337
 338         struct ixgbe_hw_stats   stats;
 339
 340         int                     rx_ring_cnt;
 341         int                     rx_ring_msix;
 342
 343         int                     tx_ring_cnt;
 344         int                     tx_ring_msix;
 345
 346         int                     intr_type;
 347         int                     intr_cnt;
 348         struct ix_intr_data     *intr_data;
 349
 350         device_t                dev;
 351         bus_dma_tag_t           parent_tag;
 352         struct ifmedia          media;
 353
 354         struct resource         *mem_res;
 355         int                     mem_rid;
 356
 357         struct resource         *msix_mem_res;
 358         int                     msix_mem_rid;
 359
 360         int                     nserialize;
 361         struct lwkt_serialize   **serializes;
 362
 363         struct ix_mc_addr       *mta;           /* Multicast array memory */
 364
 365         int                     if_flags;
 366         int                     advspeed;       /* advertised link speeds */
 367         uint32_t                wufc;           /* power management */
 368         uint16_t                dmac;           /* DMA coalescing */
 369         uint16_t                max_frame_size;
 370         int16_t                 sts_msix_vec;   /* status MSI-X vector */
 371
 372         struct if_ringmap       *tx_rmap;
 373         struct if_ringmap       *tx_rmap_intr;
 374         struct if_ringmap       *rx_rmap;
 375         struct if_ringmap       *rx_rmap_intr;
 376
 377         int                     rdr_table[IX_RDRTABLE_SIZE];
 378
 379         struct task             wdog_task;
 380         int                     direct_input;
 381 #ifdef IX_RSS_DEBUG
 382         int                     rss_debug;
 383 #endif
 384 };
 385
 386 #define IX_ENABLE_HWRSS(sc)     ((sc)->rx_ring_cnt > 1)
 387 #define IX_ENABLE_HWTSS(sc)     ((sc)->tx_ring_cnt > 1)
 388
 389 #endif /* _IF_IX_H_ */