2 .\" Copyright (c) 1995, 1996, 1997, 1998, 2000
3 .\" Justin T. Gibbs. All rights reserved.
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27 .\" $FreeBSD: src/share/man/man4/ahc.4,v 1.38.2.1 2006/06/05 19:30:28 brueffer Exp $
28 .\" $DragonFly: src/share/man/man4/ahc.4,v 1.7 2008/05/02 02:05:05 swildner Exp $
30 .Dd September 26, 2007
35 .Nd Adaptec VL/EISA/PCI SCSI host adapter driver
37 To compile this driver into the kernel,
38 place the following lines in your
39 kernel configuration file:
40 .Bd -ragged -offset indent
44 For one or more VL/EISA cards:
47 For one or more PCI cards:
50 To allow PCI adapters to use memory mapped I/O if enabled:
51 .Cd options AHC_ALLOW_MEMIO
53 To compile in debugging code:
55 .Cd options AHC_DEBUG_OPTS=<bitmask of options>
56 .Cd options AHC_REG_PRETTY_PRINT
58 To configure one or more controllers to assume the target role:
59 .Cd options AHC_TMODE_ENABLE <bitmask of units>
62 Alternatively, to load the driver as a
63 module at boot time, place the following lines in
65 .Bd -literal -offset indent
72 This driver provides access to the
74 bus(es) connected to the Adaptec AIC77xx and AIC78xx
77 Driver features include support for twin and wide busses,
78 fast, ultra or ultra2 synchronous transfers depending on controller type,
79 tagged queueing, SCB paging, and target mode.
81 Memory mapped I/O can be enabled for PCI devices with the
82 .Dq Dv AHC_ALLOW_MEMIO
84 Memory mapped I/O is more efficient than the alternative, programmed I/O.
85 Most PCI BIOSes will map devices so that either technique for communicating
86 with the card is available.
88 usually when the PCI device is sitting behind a PCI->PCI bridge,
89 the BIOS may fail to properly initialize the chip for memory mapped I/O.
90 The typical symptom of this problem is a system hang if memory mapped I/O
92 Most modern motherboards perform the initialization correctly and work fine
93 with this option enabled.
97 option is used to control which diagnostic messages are printed to the
101 Logically OR the following bits together:
102 .Bl -column -offset indent Value Function
104 0x0001 Show miscellaneous information
105 0x0002 Show sense data
106 0x0004 Show Serial EEPROM contents
107 0x0008 Show bus termination settings
108 0x0010 Show host memory usage
109 0x0020 Show SCSI protocol messages
110 .\"0x0040 XXX: AHC_SHOW_DV
111 0x0080 Show selection timeouts
112 0x0200 Show Queue Full status
113 0x0400 Show SCB queue status
114 0x0800 Show inbound packet information
115 .\"0x1000 XXX: AHC_SHOW_MASKED_ERRORS
116 0x2000 Enable extra diagnostic code in the firmware
120 .Dv AHC_REG_PRETTY_PRINT
121 option compiles in support for human-readable bit definitions for each register
122 that is printed by the debugging code.
124 Individual controllers may be configured to operate in the target role
126 .Dq Dv AHC_TMODE_ENABLE
127 configuration option.
128 The value assigned to this option should be a bitmap
129 of all units where target mode is desired.
130 For example, a value of 0x25, would enable target mode on units 0, 2, and 5.
131 A value of 0x8a enables it for units 1, 3, and 7.
133 Per target configuration performed in the
135 menu, accessible at boot
141 configuration utility for
144 is honored by this driver.
145 This includes synchronous/asynchronous transfers,
146 maximum synchronous negotiation rate,
149 the host adapter's SCSI ID,
153 Twin Channel controllers,
154 the primary channel selection.
155 For systems that store non-volatile settings in a system specific manner
156 rather than a serial eeprom directly connected to the aic7xxx controller,
159 must be enabled for the driver to access this information.
160 This restriction applies to all
162 and many motherboard configurations.
164 Note that I/O addresses are determined automatically by the probe routines,
165 but care should be taken when using a 284x
166 .Pq Tn VESA No local bus controller
170 The jumpers setting the I/O area for the 284x should match the
172 slot into which the card is inserted to prevent conflicts with other
176 Performance and feature sets vary throughout the aic7xxx product line.
177 The following table provides a comparison of the different chips supported
181 Note that wide and twin channel features, although always supported
182 by a particular chip, may be disabled in a particular motherboard or card
184 .Bd -ragged -offset indent
185 .Bl -column "aic7770 " "10 " "EISA/VL " "10MHz " "16bit " "SCBs " Features
186 .Em "Chip MIPS Bus MaxSync MaxWidth SCBs Features"
187 aic7770 10 EISA/VL 10MHz 16Bit 4 1
188 aic7850 10 PCI/32 10MHz 8Bit 3
189 aic7860 10 PCI/32 20MHz 8Bit 3
190 aic7870 10 PCI/32 10MHz 16Bit 16
191 aic7880 10 PCI/32 20MHz 16Bit 16
192 aic7890 20 PCI/32 40MHz 16Bit 16 3 4 5 6 7 8
193 aic7891 20 PCI/64 40MHz 16Bit 16 3 4 5 6 7 8
194 aic7892 20 PCI/64 80MHz 16Bit 16 3 4 5 6 7 8
195 aic7895 15 PCI/32 20MHz 16Bit 16 2 3 4 5
196 aic7895C 15 PCI/32 20MHz 16Bit 16 2 3 4 5 8
197 aic7896 20 PCI/32 40MHz 16Bit 16 2 3 4 5 6 7 8
198 aic7897 20 PCI/64 40MHz 16Bit 16 2 3 4 5 6 7 8
199 aic7899 20 PCI/64 80MHz 16Bit 16 2 3 4 5 6 7 8
204 Multiplexed Twin Channel Device - One controller servicing two busses.
206 Multi-function Twin Channel Device - Two controllers on one chip.
208 Command Channel Secondary DMA Engine - Allows scatter gather list and
211 64 Byte SCB Support - SCSI CDB is embedded in the SCB to eliminate an extra DMA.
213 Block Move Instruction Support - Doubles the speed of certain sequencer
217 style Scatter Gather Engine - Improves S/G prefetch performance.
219 Queuing Registers - Allows queueing of new transactions without pausing the
222 Multiple Target IDs - Allows the controller to respond to selection as a
223 target on multiple SCSI IDs.
229 driver supports the following
231 host adapter chips and
387 NEC PC-9821Xt13 (PC-98)
391 NEC PC-9821X-B02L/B09 (PC-98)
393 NEC SV-98/2-B03 (PC-98)
395 Many motherboards with on-board
399 .Sh SCSI CONTROL BLOCKS (SCBs)
400 Every transaction sent to a device on the SCSI bus is assigned a
401 .Sq SCSI Control Block
403 The SCB contains all of the information required by the
404 controller to process a transaction.
405 The chip feature table lists
406 the number of SCBs that can be stored in on-chip memory.
408 with model numbers greater than or equal to 7870 allow for the on chip
409 SCB space to be augmented with external SRAM up to a maximum of 255 SCBs.
410 Very few Adaptec controller configurations have external SRAM.
412 If external SRAM is not available, SCBs are a limited resource.
413 Using the SCBs in a straight forward manner would only allow the driver to
414 handle as many concurrent transactions as there are physical SCBs.
415 To fully utilize the SCSI bus and the devices on it,
416 requires much more concurrency.
417 The solution to this problem is
419 a concept similar to memory paging.
420 SCB paging takes advantage of
421 the fact that devices usually disconnect from the SCSI bus for long
422 periods of time without talking to the controller.
423 The SCBs for disconnected transactions are only of use to the controller
424 when the transfer is resumed.
425 When the host queues another transaction
426 for the controller to execute, the controller firmware will use a
427 free SCB if one is available.
428 Otherwise, the state of the most recently
429 disconnected (and therefore most likely to stay disconnected) SCB is
430 saved, via dma, to host memory, and the local SCB reused to start
432 This allows the controller to queue up to
433 255 transactions regardless of the amount of SCB space.
435 local SCB space serves as a cache for disconnected transactions, the
436 more SCB space available, the less host bus traffic consumed saving
437 and restoring SCB data.
455 sequencer-code assembler,
456 and the firmware running on the aic7xxx chips was written by
457 .An Justin T. Gibbs .
459 Some Quantum drives (at least the Empire 2100 and 1080s) will not run on an
461 Rev B in synchronous mode at 10MHz.
462 Controllers with this problem have a
463 42 MHz clock crystal on them and run slightly above 10MHz.
464 This confuses the drive and hangs the bus.
465 Setting a maximum synchronous negotiation rate of 8MHz in the
467 utility will allow normal operation.
469 Although the Ultra2 and Ultra160 products have sufficient instruction
470 ram space to support both the initiator and target roles concurrently,
471 this configuration is disabled in favor of allowing the target role
472 to respond on multiple target ids.
473 A method for configuring dual role mode should be provided.
475 Tagged Queuing is not supported in target mode.
477 Reselection in target mode fails to function correctly on all high
478 voltage differential boards as shipped by Adaptec.
480 how to modify HVD board to work correctly in target mode is available