?  search:
summary | log | graphiclog1 | graphiclog2 | commit | commitdiff | tree | refs | edit | fork
blame | history | raw | HEAD
Sync with HEAD.
[dragonfly.git] / sys / dev / netif / mn / if_mn.c
blobc2d541e6b395a84ca8aed61865e97cc5e18d34f4
1 /*
2 * ----------------------------------------------------------------------------
3 * "THE BEER-WARE LICENSE" (Revision 42):
4 * <phk@FreeBSD.org> wrote this file. As long as you retain this notice you
5 * can do whatever you want with this stuff. If we meet some day, and you think
6 * this stuff is worth it, you can buy me a beer in return. Poul-Henning Kamp
7 * ----------------------------------------------------------------------------
8 *
9 * $Id: if_mn.c,v 1.1 1999/02/01 13:06:40 phk Exp $
10 *
11 * Driver for Siemens reference design card "Easy321-R1".
12 *
13 * This card contains a FALC54 E1/T1 framer and a MUNICH32X 32-channel HDLC
14 * controller.
15 *
16 * The driver supports E1 mode with up to 31 channels. We send CRC4 but don't
17 * check it coming in.
18 *
19 * The FALC54 and MUNICH32X have far too many registers and weird modes for
20 * comfort, so I have not bothered typing it all into a "fooreg.h" file,
21 * you will (badly!) need the documentation anyway if you want to mess with
22 * this gadget.
23 *
24 * $FreeBSD: src/sys/pci/if_mn.c,v 1.11.2.3 2001/01/23 12:47:09 phk Exp $
25 * $DragonFly: src/sys/dev/netif/mn/if_mn.c,v 1.17 2007/06/03 20:51:08 dillon Exp $
26 */
27
28 /*
29 * Stuff to describe the MUNIC32X and FALC54 chips.
30 */
31
32 #define M32_CHAN 32 /* We have 32 channels */
33 #define M32_TS 32 /* We have 32 timeslots */
34
35 #define NG_MN_NODE_TYPE "mn"
36
37 #include <sys/param.h>
38 #include <sys/systm.h>
39 #include <sys/kernel.h>
40 #include <sys/sysctl.h>
41 #include <sys/bus.h>
42 #include <sys/mbuf.h>
43 #include <sys/malloc.h>
44 #include <sys/rman.h>
45
46 #include <bus/pci/pcireg.h>
47 #include <bus/pci/pcivar.h>
48 #include "pci_if.h"
49
50 #include <machine/clock.h>
51
52 #include <vm/vm.h>
53 #include <vm/pmap.h>
54
55 #include <netgraph/ng_message.h>
56 #include <netgraph/netgraph.h>
57
58
59 static int mn_maxlatency = 1000;
60 SYSCTL_INT(_debug, OID_AUTO, mn_maxlatency, CTLFLAG_RW,
61 &mn_maxlatency, 0,
62 "The number of milliseconds a packet is allowed to spend in the output queue. "
63 "If the output queue is longer than this number of milliseconds when the packet "
64 "arrives for output, the packet will be dropped."
65 );
66
67 #ifndef NMN
68 /* Most machines don't support more than 4 busmaster PCI slots, if even that many */
69 #define NMN 4
70 #endif
71
72 /* From: PEB 20321 data sheet, p187, table 22 */
73 struct m32xreg {
74 u_int32_t conf, cmd, stat, imask;
75 u_int32_t fill10, piqba, piql, fill1c;
76 u_int32_t mode1, mode2, ccba, txpoll;
77 u_int32_t tiqba, tiql, riqba, riql;
78 u_int32_t lconf, lccba, fill48, ltran;
79 u_int32_t ltiqba, ltiql, lriqba, lriql;
80 u_int32_t lreg0, lreg1, lreg2, lreg3;
81 u_int32_t lreg4, lreg5, lre6, lstat;
82 u_int32_t gpdir, gpdata, gpod, fill8c;
83 u_int32_t ssccon, sscbr, ssctb, sscrb;
84 u_int32_t ssccse, sscim, fillab, fillac;
85 u_int32_t iomcon1, iomcon2, iomstat, fillbc;
86 u_int32_t iomcit0, iomcit1, iomcir0, iomcir1;
87 u_int32_t iomtmo, iomrmo, filld8, filldc;
88 u_int32_t mbcmd, mbdata1, mbdata2, mbdata3;
89 u_int32_t mbdata4, mbdata5, mbdata6, mbdata7;
90 };
91
92 /* From: PEB 2254 data sheet, p80, table 10 */
93 struct f54wreg {
94 u_int16_t xfifo;
95 u_int8_t cmdr, mode, rah1, rah2, ral1, ral2;
96 u_int8_t ipc, ccr1, ccr3, pre, rtr1, rtr2, rtr3, rtr4;
97 u_int8_t ttr1, ttr2, ttr3, ttr4, imr0, imr1, imr2, imr3;
98 u_int8_t imr4, fill19, fmr0, fmr1, fmr2, loop, xsw, xsp;
99 u_int8_t xc0, xc1, rc0, rc1, xpm0, xpm1, xpm2, tswm;
100 u_int8_t test1, idle, xsa4, xsa5, xsa6, xsa7, xsa8, fmr3;
101 u_int8_t icb1, icb2, icb3, icb4, lim0, lim1, pcd, pcr;
102 u_int8_t lim2, fill39[7];
103 u_int8_t fill40[8];
104 u_int8_t fill48[8];
105 u_int8_t fill50[8];
106 u_int8_t fill58[8];
107 u_int8_t dec, fill61, test2, fill63[5];
108 u_int8_t fill68[8];
109 u_int8_t xs[16];
110 };
111
112 /* From: PEB 2254 data sheet, p117, table 10 */
113 struct f54rreg {
114 u_int16_t rfifo;
115 u_int8_t fill2, mode, rah1, rah2, ral1, ral2;
116 u_int8_t ipc, ccr1, ccr3, pre, rtr1, rtr2, rtr3, rtr4;
117 u_int8_t ttr1, ttr2, ttr3, ttr4, imr0, imr1, imr2, imr3;
118 u_int8_t imr4, fill19, fmr0, fmr1, fmr2, loop, xsw, xsp;
119 u_int8_t xc0, xc1, rc0, rc1, xpm0, xpm1, xpm2, tswm;
120 u_int8_t test, idle, xsa4, xsa5, xsa6, xsa7, xsa8, fmr13;
121 u_int8_t icb1, icb2, icb3, icb4, lim0, lim1, pcd, pcr;
122 u_int8_t lim2, fill39[7];
123 u_int8_t fill40[8];
124 u_int8_t fill48[4], frs0, frs1, rsw, rsp;
125 u_int16_t fec, cvc, cec1, ebc;
126 u_int16_t cec2, cec3;
127 u_int8_t rsa4, rsa5, rsa6, rsa7;
128 u_int8_t rsa8, rsa6s, tsr0, tsr1, sis, rsis;
129 u_int16_t rbc;
130 u_int8_t isr0, isr1, isr2, isr3, fill6c, fill6d, gis, vstr;
131 u_int8_t rs[16];
132 };
133
134 /* Transmit & receive descriptors */
135 struct trxd {
136 u_int32_t flags;
137 vm_offset_t next;
138 vm_offset_t data;
139 u_int32_t status; /* only used for receive */
140 struct mbuf *m; /* software use only */
141 struct trxd *vnext; /* software use only */
142 };
143
144 /* Channel specification */
145 struct cspec {
146 u_int32_t flags;
147 vm_offset_t rdesc;
148 vm_offset_t tdesc;
149 u_int32_t itbs;
150 };
151
152 struct m32_mem {
153 vm_offset_t csa;
154 u_int32_t ccb;
155 u_int32_t reserve1[2];
156 u_int32_t ts[M32_TS];
157 struct cspec cs[M32_CHAN];
158 vm_offset_t crxd[M32_CHAN];
159 vm_offset_t ctxd[M32_CHAN];
160 };
161
162 struct softc;
163 struct sockaddr;
164 struct rtentry;
165
166 static int mn_probe (device_t self);
167 static int mn_attach (device_t self);
168 static void mn_create_channel(struct softc *sc, int chan);
169 static int mn_reset(struct softc *sc);
170 static struct trxd * mn_alloc_desc(void);
171 static void mn_free_desc(struct trxd *dp);
172 static void mn_intr(void *xsc);
173 static u_int32_t mn_parse_ts(const char *s, int *nbit);
174 #ifdef notyet
175 static void m32_dump(struct softc *sc);
176 static void f54_dump(struct softc *sc);
177 static void mn_fmt_ts(char *p, u_int32_t ts);
178 #endif /* notyet */
179 static void f54_init(struct softc *sc);
180
181 static ng_constructor_t ngmn_constructor;
182 static ng_rcvmsg_t ngmn_rcvmsg;
183 static ng_shutdown_t ngmn_shutdown;
184 static ng_newhook_t ngmn_newhook;
185 static ng_connect_t ngmn_connect;
186 static ng_rcvdata_t ngmn_rcvdata;
187 static ng_disconnect_t ngmn_disconnect;
188
189 static struct ng_type mntypestruct = {
190 NG_VERSION,
191 NG_MN_NODE_TYPE,
192 NULL,
193 ngmn_constructor,
194 ngmn_rcvmsg,
195 ngmn_shutdown,
196 ngmn_newhook,
197 NULL,
198 ngmn_connect,
199 ngmn_rcvdata,
200 ngmn_rcvdata,
201 ngmn_disconnect,
202 NULL
203 };
204
205 static MALLOC_DEFINE(M_MN, "mn", "Mx driver related");
206
207 #define NIQB 64
208
209 struct schan {
210 enum {DOWN, UP} state;
211 struct softc *sc;
212 int chan;
213 u_int32_t ts;
214 char name[8];
215 struct trxd *r1, *rl;
216 struct trxd *x1, *xl;
217 hook_p hook;
218
219 time_t last_recv;
220 time_t last_rxerr;
221 time_t last_xmit;
222
223 u_long rx_error;
224
225 u_long short_error;
226 u_long crc_error;
227 u_long dribble_error;
228 u_long long_error;
229 u_long abort_error;
230 u_long overflow_error;
231
232 int last_error;
233 int prev_error;
234
235 u_long tx_pending;
236 u_long tx_limit;
237 };
238
239 enum framing {WHOKNOWS, E1, E1U, T1, T1U};
240
241 struct softc {
242 int unit;
243 device_t dev;
244 struct resource *irq;
245 void *intrhand;
246 enum framing framing;
247 int nhooks;
248 void *m0v, *m1v;
249 vm_offset_t m0p, m1p;
250 struct m32xreg *m32x;
251 struct f54wreg *f54w;
252 struct f54rreg *f54r;
253 struct m32_mem m32_mem;
254 u_int32_t tiqb[NIQB];
255 u_int32_t riqb[NIQB];
256 u_int32_t piqb[NIQB];
257 u_int32_t ltiqb[NIQB];
258 u_int32_t lriqb[NIQB];
259 char name[8];
260 u_int32_t falc_irq, falc_state, framer_state;
261 struct schan *ch[M32_CHAN];
262 char nodename[NG_NODESIZ];
263 node_p node;
264
265 u_long cnt_fec;
266 u_long cnt_cvc;
267 u_long cnt_cec1;
268 u_long cnt_ebc;
269 u_long cnt_cec2;
270 u_long cnt_cec3;
271 u_long cnt_rbc;
272 };
273
274 static int
275 ngmn_constructor(node_p *nodep)
276 {
277
278 return (EINVAL);
279 }
280
281 static int
282 ngmn_shutdown(node_p nodep)
283 {
284
285 return (EINVAL);
286 }
287
288 static void
289 ngmn_config(node_p node, char *set, char *ret)
290 {
291 struct softc *sc;
292 enum framing wframing;
293
294 sc = node->private;
295
296 if (set != NULL) {
297 if (!strncmp(set, "line ", 5)) {
298 wframing = sc->framing;
299 if (!strcmp(set, "line e1")) {
300 wframing = E1;
301 } else if (!strcmp(set, "line e1u")) {
302 wframing = E1U;
303 } else {
304 strcat(ret, "ENOGROK\n");
305 return;
306 }
307 if (wframing == sc->framing)
308 return;
309 if (sc->nhooks > 0) {
310 ksprintf(ret, "Cannot change line when %d hooks open\n", sc->nhooks);
311 return;
312 }
313 sc->framing = wframing;
314 #if 1
315 f54_init(sc);
316 #else
317 mn_reset(sc);
318 #endif
319 } else {
320 kprintf("%s CONFIG SET [%s]\n", sc->nodename, set);
321 strcat(ret, "ENOGROK\n");
322 return;
323 }
324 }
325
326 }
327
328 static int
329 ngmn_rcvmsg(node_p node, struct ng_mesg *msg, const char *retaddr, struct ng_mesg **resp)
330 {
331 struct softc *sc;
332 struct schan *sch;
333 char *s, *r;
334 int pos, i;
335
336 sc = node->private;
337
338 if (msg->header.typecookie != NGM_GENERIC_COOKIE) {
339 if (resp != NULL)
340 *resp = NULL;
341 FREE(msg, M_NETGRAPH);
342 return (EINVAL);
343 }
344
345 if (msg->header.cmd != NGM_TEXT_CONFIG &&
346 msg->header.cmd != NGM_TEXT_STATUS) {
347 if (resp != NULL)
348 *resp = NULL;
349 FREE(msg, M_NETGRAPH);
350 return (EINVAL);
351 }
352
353 NG_MKRESPONSE(*resp, msg, sizeof(struct ng_mesg) + NG_TEXTRESPONSE,
354 M_INTWAIT);
355 if (*resp == NULL) {
356 FREE(msg, M_NETGRAPH);
357 return (ENOMEM);
358 }
359
360 if (msg->header.arglen)
361 s = (char *)msg->data;
362 else
363 s = NULL;
364 r = (char *)(*resp)->data;
365 *r = '\0';
366
367 if (msg->header.cmd == NGM_TEXT_CONFIG) {
368 ngmn_config(node, s, r);
369 (*resp)->header.arglen = strlen(r) + 1;
370 FREE(msg, M_NETGRAPH);
371 return (0);
372 }
373
374 pos = 0;
375 pos += ksprintf(pos + r,"Framer status %b;\n", sc->framer_state, "\20"
376 "\40LOS\37AIS\36LFA\35RRA"
377 "\34AUXP\33NMF\32LMFA\31frs0.0"
378 "\30frs1.7\27TS16RA\26TS16LOS\25TS16AIS"
379 "\24TS16LFA\23frs1.2\22XLS\21XLO"
380 "\20RS1\17rsw.6\16RRA\15RY0"
381 "\14RY1\13RY2\12RY3\11RY4"
382 "\10SI1\7SI2\6rsp.5\5rsp.4"
383 "\4rsp.3\3RSIF\2RS13\1RS15");
384 pos += ksprintf(pos + r," Framing errors: %lu", sc->cnt_fec);
385 pos += ksprintf(pos + r," Code Violations: %lu\n", sc->cnt_cvc);
386
387 pos += ksprintf(pos + r," Falc State %b;\n", sc->falc_state, "\20"
388 "\40LOS\37AIS\36LFA\35RRA"
389 "\34AUXP\33NMF\32LMFA\31frs0.0"
390 "\30frs1.7\27TS16RA\26TS16LOS\25TS16AIS"
391 "\24TS16LFA\23frs1.2\22XLS\21XLO"
392 "\20RS1\17rsw.6\16RRA\15RY0"
393 "\14RY1\13RY2\12RY3\11RY4"
394 "\10SI1\7SI2\6rsp.5\5rsp.4"
395 "\4rsp.3\3RSIF\2RS13\1RS15");
396 pos += ksprintf(pos + r, " Falc IRQ %b\n", sc->falc_irq, "\20"
397 "\40RME\37RFS\36T8MS\35RMB\34CASC\33CRC4\32SA6SC\31RPF"
398 "\30b27\27RDO\26ALLS\25XDU\24XMB\23b22\22XLSC\21XPR"
399 "\20FAR\17LFA\16MFAR\15T400MS\14AIS\13LOS\12RAR\11RA"
400 "\10ES\7SEC\6LMFA16\5AIS16\4RA16\3API\2SLN\1SLP");
401 for (i = 0; i < M32_CHAN; i++) {
402 if (!sc->ch[i])
403 continue;
404 sch = sc->ch[i];
405
406 pos += ksprintf(r + pos, " Chan %d <%s> ",
407 i, sch->hook->name);
408
409 pos += ksprintf(r + pos, " Last Rx: ");
410 if (sch->last_recv)
411 pos += ksprintf(r + pos, "%lu s", time_second - sch->last_recv);
412 else
413 pos += ksprintf(r + pos, "never");
414
415 pos += ksprintf(r + pos, ", last RxErr: ");
416 if (sch->last_rxerr)
417 pos += ksprintf(r + pos, "%lu s", time_second - sch->last_rxerr);
418 else
419 pos += ksprintf(r + pos, "never");
420
421 pos += ksprintf(r + pos, ", last Tx: ");
422 if (sch->last_xmit)
423 pos += ksprintf(r + pos, "%lu s\n", time_second - sch->last_xmit);
424 else
425 pos += ksprintf(r + pos, "never\n");
426
427 pos += ksprintf(r + pos, " RX error(s) %lu", sch->rx_error);
428 pos += ksprintf(r + pos, " Short: %lu", sch->short_error);
429 pos += ksprintf(r + pos, " CRC: %lu", sch->crc_error);
430 pos += ksprintf(r + pos, " Mod8: %lu", sch->dribble_error);
431 pos += ksprintf(r + pos, " Long: %lu", sch->long_error);
432 pos += ksprintf(r + pos, " Abort: %lu", sch->abort_error);
433 pos += ksprintf(r + pos, " Overflow: %lu\n", sch->overflow_error);
434
435 pos += ksprintf(r + pos, " Last error: %b Prev error: %b\n",
436 sch->last_error, "\20\7SHORT\5CRC\4MOD8\3LONG\2ABORT\1OVERRUN",
437 sch->prev_error, "\20\7SHORT\5CRC\4MOD8\3LONG\2ABORT\1OVERRUN");
438 pos += ksprintf(r + pos, " Xmit bytes pending %ld\n",
439 sch->tx_pending);
440 }
441 (*resp)->header.arglen = pos + 1;
442 FREE(msg, M_NETGRAPH);
443 return (0);
444 }
445
446 static int
447 ngmn_newhook(node_p node, hook_p hook, const char *name)
448 {
449 u_int32_t ts, chan;
450 struct softc *sc;
451 int nbit;
452
453 sc = node->private;
454
455 if (name[0] != 't' || name[1] != 's')
456 return (EINVAL);
457
458 ts = mn_parse_ts(name + 2, &nbit);
459 kprintf("%d bits %x\n", nbit, ts);
460 if (sc->framing == E1 && (ts & 1))
461 return (EINVAL);
462 if (sc->framing == E1U && nbit != 32)
463 return (EINVAL);
464 if (ts == 0)
465 return (EINVAL);
466 if (sc->framing == E1)
467 chan = ffs(ts) - 1;
468 else
469 chan = 1;
470 if (!sc->ch[chan])
471 mn_create_channel(sc, chan);
472 else if (sc->ch[chan]->state == UP)
473 return (EBUSY);
474 sc->ch[chan]->ts = ts;
475 sc->ch[chan]->hook = hook;
476 sc->ch[chan]->tx_limit = nbit * 8;
477 hook->private = sc->ch[chan];
478 sc->nhooks++;
479 return(0);
480 }
481
482
483 static struct trxd *mn_desc_free;
484
485 static struct trxd *
486 mn_alloc_desc(void)
487 {
488 struct trxd *dp;
489
490 dp = mn_desc_free;
491 if (dp)
492 mn_desc_free = dp->vnext;
493 else
494 dp = (struct trxd *)kmalloc(sizeof *dp, M_MN, M_INTWAIT);
495 return (dp);
496 }
497
498 static void
499 mn_free_desc(struct trxd *dp)
500 {
501 dp->vnext = mn_desc_free;
502 mn_desc_free = dp;
503 }
504
505 static u_int32_t
506 mn_parse_ts(const char *s, int *nbit)
507 {
508 unsigned r;
509 int i, j;
510 char *p;
511
512 r = 0;
513 j = -1;
514 *nbit = 0;
515 while(*s) {
516 i = strtol(s, &p, 0);
517 if (i < 0 || i > 31)
518 return (0);
519 while (j != -1 && j < i) {
520 r |= 1 << j++;
521 (*nbit)++;
522 }
523 j = -1;
524 r |= 1 << i;
525 (*nbit)++;
526 if (*p == ',') {
527 s = p + 1;
528 continue;
529 } else if (*p == '-') {
530 j = i + 1;
531 s = p + 1;
532 continue;
533 } else if (!*p) {
534 break;
535 } else {
536 return (0);
537 }
538 }
539 return (r);
540 }
541
542 #ifdef notyet
543 static void
544 mn_fmt_ts(char *p, u_int32_t ts)
545 {
546 char *s;
547 int j;
548
549 s = "";
550 ts &= 0xffffffff;
551 for (j = 0; j < 32; j++) {
552 if (!(ts & (1 << j)))
553 continue;
554 ksprintf(p, "%s%d", s, j);
555 p += strlen(p);
556 s = ",";
557 if (!(ts & (1 << (j+1))))
558 continue;
559 for (; j < 32; j++)
560 if (!(ts & (1 << (j+1))))
561 break;
562 ksprintf(p, "-%d", j);
563 p += strlen(p);
564 s = ",";
565 }
566 }
567 #endif /* notyet */
568
569 /*
570 * OUTPUT
571 */
572
573 static int
574 ngmn_rcvdata(hook_p hook, struct mbuf *m, meta_p meta)
575 {
576 struct mbuf *m2;
577 struct trxd *dp, *dp2;
578 struct schan *sch;
579 struct softc *sc;
580 int chan, pitch, len;
581
582 sch = hook->private;
583 sc = sch->sc;
584 chan = sch->chan;
585
586 if (sch->state != UP) {
587 NG_FREE_DATA(m, meta);
588 return (0);
589 }
590 if (sch->tx_pending + m->m_pkthdr.len > sch->tx_limit * mn_maxlatency) {
591 NG_FREE_DATA(m, meta);
592 return (0);
593 }
594 NG_FREE_META(meta);
595 pitch = 0;
596 m2 = m;
597 dp2 = sc->ch[chan]->xl;
598 len = m->m_pkthdr.len;
599 while (len) {
600 dp = mn_alloc_desc();
601 if (!dp) {
602 pitch++;
603 m_freem(m);
604 sc->ch[chan]->xl = dp2;
605 dp = dp2->vnext;
606 while (dp) {
607 dp2 = dp->vnext;
608 mn_free_desc(dp);
609 dp = dp2;
610 }
611 sc->ch[chan]->xl->vnext = 0;
612 break;
613 }
614 dp->data = vtophys(m2->m_data);
615 dp->flags = m2->m_len << 16;
616 dp->flags += 1;
617 len -= m2->m_len;
618 dp->next = vtophys(dp);
619 dp->vnext = 0;
620 sc->ch[chan]->xl->next = vtophys(dp);
621 sc->ch[chan]->xl->vnext = dp;
622 sc->ch[chan]->xl = dp;
623 if (!len) {
624 dp->m = m;
625 dp->flags |= 0xc0000000;
626 dp2->flags &= ~0x40000000;
627 } else {
628 dp->m = 0;
629 m2 = m2->m_next;
630 }
631 }
632 if (pitch)
633 kprintf("%s%d: Short on mem, pitched %d packets\n",
634 sc->name, chan, pitch);
635 else {
636 #if 0
637 kprintf("%d = %d + %d (%p)\n",
638 sch->tx_pending + m->m_pkthdr.len,
639 sch->tx_pending , m->m_pkthdr.len, m);
640 #endif
641 sch->tx_pending += m->m_pkthdr.len;
642 sc->m32x->txpoll &= ~(1 << chan);
643 }
644 return (0);
645 }
646
647 /*
648 * OPEN
649 */
650 static int
651 ngmn_connect(hook_p hook)
652 {
653 int i, nts, chan;
654 struct trxd *dp, *dp2;
655 struct mbuf *m;
656 struct softc *sc;
657 struct schan *sch;
658 u_int32_t u;
659
660 sch = hook->private;
661 chan = sch->chan;
662 sc = sch->sc;
663
664 if (sch->state == UP)
665 return (0);
666 sch->state = UP;
667
668 /* Count and configure the timeslots for this channel */
669 for (nts = i = 0; i < 32; i++)
670 if (sch->ts & (1 << i)) {
671 sc->m32_mem.ts[i] = 0x00ff00ff |
672 (chan << 24) | (chan << 8);
673 nts++;
674 }
675
676 /* Init the receiver & xmitter to HDLC */
677 sc->m32_mem.cs[chan].flags = 0x80e90006;
678 /* Allocate two buffers per timeslot */
679 if (nts == 32)
680 sc->m32_mem.cs[chan].itbs = 63;
681 else
682 sc->m32_mem.cs[chan].itbs = nts * 2;
683
684 /* Setup a transmit chain with one descriptor */
685 /* XXX: we actually send a 1 byte packet */
686 dp = mn_alloc_desc();
687 MGETHDR(m, MB_WAIT, MT_DATA);
688 if (m == NULL)
689 return (ENOBUFS);
690 m->m_pkthdr.len = 0;
691 dp->m = m;
692 dp->flags = 0xc0000000 + (1 << 16);
693 dp->next = vtophys(dp);
694 dp->vnext = 0;
695 dp->data = vtophys(sc->name);
696 sc->m32_mem.cs[chan].tdesc = vtophys(dp);
697 sc->ch[chan]->x1 = dp;
698 sc->ch[chan]->xl = dp;
699
700 /* Setup a receive chain with 5 + NTS descriptors */
701
702 dp = mn_alloc_desc();
703 m = NULL;
704 MGETHDR(m, MB_WAIT, MT_DATA);
705 if (m == NULL) {
706 mn_free_desc(dp);
707 return (ENOBUFS);
708 }
709 MCLGET(m, MB_WAIT);
710 if ((m->m_flags & M_EXT) == 0) {
711 mn_free_desc(dp);
712 m_freem(m);
713 return (ENOBUFS);
714 }
715 dp->m = m;
716 dp->data = vtophys(m->m_data);
717 dp->flags = 0x40000000;
718 dp->flags += 1600 << 16;
719 dp->next = vtophys(dp);
720 dp->vnext = 0;
721 sc->ch[chan]->rl = dp;
722
723 for (i = 0; i < (nts + 10); i++) {
724 dp2 = dp;
725 dp = mn_alloc_desc();
726 m = NULL;
727 MGETHDR(m, MB_WAIT, MT_DATA);
728 if (m == NULL) {
729 mn_free_desc(dp);
730 m_freem(m);
731 return (ENOBUFS);
732 }
733 MCLGET(m, MB_WAIT);
734 if ((m->m_flags & M_EXT) == 0) {
735 mn_free_desc(dp);
736 m_freem(m);
737 return (ENOBUFS);
738 }
739 dp->m = m;
740 dp->data = vtophys(m->m_data);
741 dp->flags = 0x00000000;
742 dp->flags += 1600 << 16;
743 dp->next = vtophys(dp2);
744 dp->vnext = dp2;
745 }
746 sc->m32_mem.cs[chan].rdesc = vtophys(dp);
747 sc->ch[chan]->r1 = dp;
748
749 /* Initialize this channel */
750 sc->m32_mem.ccb = 0x00008000 + (chan << 8);
751 sc->m32x->cmd = 0x1;
752 DELAY(1000);
753 u = sc->m32x->stat;
754 if (!(u & 1))
755 kprintf("%s: init chan %d stat %08x\n", sc->name, chan, u);
756 sc->m32x->stat = 1;
757
758 return (0);
759 }
760
761 /*
762 * CLOSE
763 */
764 static int
765 ngmn_disconnect(hook_p hook)
766 {
767 int chan, i;
768 struct softc *sc;
769 struct schan *sch;
770 struct trxd *dp, *dp2;
771 u_int32_t u;
772
773 sch = hook->private;
774 chan = sch->chan;
775 sc = sch->sc;
776
777 if (sch->state == DOWN)
778 return (0);
779 sch->state = DOWN;
780
781 /* Set receiver & transmitter off */
782 sc->m32_mem.cs[chan].flags = 0x80920006;
783 sc->m32_mem.cs[chan].itbs = 0;
784
785 /* free the timeslots */
786 for (i = 0; i < 32; i++)
787 if (sc->ch[chan]->ts & (1 << i))
788 sc->m32_mem.ts[i] = 0x20002000;
789
790 /* Initialize this channel */
791 sc->m32_mem.ccb = 0x00008000 + (chan << 8);
792 sc->m32x->cmd = 0x1;
793 DELAY(30);
794 u = sc->m32x->stat;
795 if (!(u & 1))
796 kprintf("%s: zap chan %d stat %08x\n", sc->name, chan, u);
797 sc->m32x->stat = 1;
798
799 /* Free all receive descriptors and mbufs */
800 for (dp = sc->ch[chan]->r1; dp ; dp = dp2) {
801 if (dp->m)
802 m_freem(dp->m);
803 sc->ch[chan]->r1 = dp2 = dp->vnext;
804 mn_free_desc(dp);
805 }
806
807 /* Free all transmit descriptors and mbufs */
808 for (dp = sc->ch[chan]->x1; dp ; dp = dp2) {
809 if (dp->m) {
810 sc->ch[chan]->tx_pending -= dp->m->m_pkthdr.len;
811 m_freem(dp->m);
812 }
813 sc->ch[chan]->x1 = dp2 = dp->vnext;
814 mn_free_desc(dp);
815 }
816 sc->nhooks--;
817 return(0);
818 }
819
820 /*
821 * Create a new channel.
822 */
823 static void
824 mn_create_channel(struct softc *sc, int chan)
825 {
826 struct schan *sch;
827
828 sch = sc->ch[chan] = (struct schan *)kmalloc(sizeof *sc->ch[chan],
829 M_MN, M_WAITOK | M_ZERO);
830 sch->sc = sc;
831 sch->state = DOWN;
832 sch->chan = chan;
833 ksprintf(sch->name, "%s%d", sc->name, chan);
834 return;
835 }
836
837 #ifdef notyet
838 /*
839 * Dump Munich32x state
840 */
841 static void
842 m32_dump(struct softc *sc)
843 {
844 u_int32_t *tp4;
845 int i, j;
846
847 kprintf("mn%d: MUNICH32X dump\n", sc->unit);
848 tp4 = (u_int32_t *)sc->m0v;
849 for(j = 0; j < 64; j += 8) {
850 kprintf("%02x", j * sizeof *tp4);
851 for(i = 0; i < 8; i++)
852 kprintf(" %08x", tp4[i+j]);
853 kprintf("\n");
854 }
855 for(j = 0; j < M32_CHAN; j++) {
856 if (!sc->ch[j])
857 continue;
858 kprintf("CH%d: state %d ts %08x",
859 j, sc->ch[j]->state, sc->ch[j]->ts);
860 kprintf(" %08x %08x %08x %08x %08x %08x\n",
861 sc->m32_mem.cs[j].flags,
862 sc->m32_mem.cs[j].rdesc,
863 sc->m32_mem.cs[j].tdesc,
864 sc->m32_mem.cs[j].itbs,
865 sc->m32_mem.crxd[j],
866 sc->m32_mem.ctxd[j] );
867 }
868 }
869
870 /*
871 * Dump Falch54 state
872 */
873 static void
874 f54_dump(struct softc *sc)
875 {
876 u_int8_t *tp1;
877 int i, j;
878
879 kprintf("%s: FALC54 dump\n", sc->name);
880 tp1 = (u_int8_t *)sc->m1v;
881 for(j = 0; j < 128; j += 16) {
882 kprintf("%s: %02x |", sc->name, j * sizeof *tp1);
883 for(i = 0; i < 16; i++)
884 kprintf(" %02x", tp1[i+j]);
885 kprintf("\n");
886 }
887 }
888 #endif /* notyet */
889
890 /*
891 * Init Munich32x
892 */
893 static void
894 m32_init(struct softc *sc)
895 {
896
897 sc->m32x->conf = 0x00000000;
898 sc->m32x->mode1 = 0x81048000 + 1600; /* XXX: temp */
899 #if 1
900 sc->m32x->mode2 = 0x00000081;
901 sc->m32x->txpoll = 0xffffffff;
902 #elif 1
903 sc->m32x->mode2 = 0x00000081;
904 sc->m32x->txpoll = 0xffffffff;
905 #else
906 sc->m32x->mode2 = 0x00000101;
907 #endif
908 sc->m32x->lconf = 0x6060009B;
909 sc->m32x->imask = 0x00000000;
910 }
911
912 /*
913 * Init the Falc54
914 */
915 static void
916 f54_init(struct softc *sc)
917 {
918 sc->f54w->ipc = 0x07;
919
920 sc->f54w->xpm0 = 0xbd;
921 sc->f54w->xpm1 = 0x03;
922 sc->f54w->xpm2 = 0x00;
923
924 sc->f54w->imr0 = 0x18; /* RMB, CASC */
925 sc->f54w->imr1 = 0x08; /* XMB */
926 sc->f54w->imr2 = 0x00;
927 sc->f54w->imr3 = 0x38; /* LMFA16, AIS16, RA16 */
928 sc->f54w->imr4 = 0x00;
929
930 sc->f54w->fmr0 = 0xf0; /* X: HDB3, R: HDB3 */
931 sc->f54w->fmr1 = 0x0e; /* Send CRC4, 2Mbit, ECM */
932 if (sc->framing == E1)
933 sc->f54w->fmr2 = 0x03; /* Auto Rem-Alarm, Auto resync */
934 else if (sc->framing == E1U)
935 sc->f54w->fmr2 = 0x33; /* dais, rtm, Auto Rem-Alarm, Auto resync */
936
937 sc->f54w->lim1 = 0xb0; /* XCLK=8kHz, .62V threshold */
938 sc->f54w->pcd = 0x0a;
939 sc->f54w->pcr = 0x15;
940 sc->f54w->xsw = 0x9f; /* fmr4 */
941 if (sc->framing == E1)
942 sc->f54w->xsp = 0x1c; /* fmr5 */
943 else if (sc->framing == E1U)
944 sc->f54w->xsp = 0x3c; /* tt0, fmr5 */
945 sc->f54w->xc0 = 0x07;
946 sc->f54w->xc1 = 0x3d;
947 sc->f54w->rc0 = 0x05;
948 sc->f54w->rc1 = 0x00;
949 sc->f54w->cmdr = 0x51;
950 }
951
952 static int
953 mn_reset(struct softc *sc)
954 {
955 u_int32_t u;
956 int i;
957
958 sc->m32x->ccba = vtophys(&sc->m32_mem.csa);
959 sc->m32_mem.csa = vtophys(&sc->m32_mem.ccb);
960
961 bzero(sc->tiqb, sizeof sc->tiqb);
962 sc->m32x->tiqba = vtophys(&sc->tiqb);
963 sc->m32x->tiql = NIQB / 16 - 1;
964
965 bzero(sc->riqb, sizeof sc->riqb);
966 sc->m32x->riqba = vtophys(&sc->riqb);
967 sc->m32x->riql = NIQB / 16 - 1;
968
969 bzero(sc->ltiqb, sizeof sc->ltiqb);
970 sc->m32x->ltiqba = vtophys(&sc->ltiqb);
971 sc->m32x->ltiql = NIQB / 16 - 1;
972
973 bzero(sc->lriqb, sizeof sc->lriqb);
974 sc->m32x->lriqba = vtophys(&sc->lriqb);
975 sc->m32x->lriql = NIQB / 16 - 1;
976
977 bzero(sc->piqb, sizeof sc->piqb);
978 sc->m32x->piqba = vtophys(&sc->piqb);
979 sc->m32x->piql = NIQB / 16 - 1;
980
981 m32_init(sc);
982 f54_init(sc);
983
984 u = sc->m32x->stat;
985 sc->m32x->stat = u;
986 sc->m32_mem.ccb = 0x4;
987 sc->m32x->cmd = 0x1;
988 DELAY(1000);
989 u = sc->m32x->stat;
990 sc->m32x->stat = u;
991
992 /* set all timeslots to known state */
993 for (i = 0; i < 32; i++)
994 sc->m32_mem.ts[i] = 0x20002000;
995
996 if (!(u & 1)) {
997 kprintf(
998 "mn%d: WARNING: Controller failed the PCI bus-master test.\n"
999 "mn%d: WARNING: Use a PCI slot which can support bus-master cards.\n",
1000 sc->unit, sc->unit);
1001 return (0);
1002 }
1003 return (1);
1004 }
1005
1006 /*
1007 * FALC54 interrupt handling
1008 */
1009 static void
1010 f54_intr(struct softc *sc)
1011 {
1012 unsigned g, u, s;
1013
1014 g = sc->f54r->gis;
1015 u = sc->f54r->isr0 << 24;
1016 u |= sc->f54r->isr1 << 16;
1017 u |= sc->f54r->isr2 << 8;
1018 u |= sc->f54r->isr3;
1019 sc->falc_irq = u;
1020 /* don't chat about the 1 sec heart beat */
1021 if (u & ~0x40) {
1022 #if 0
1023 kprintf("%s*: FALC54 IRQ GIS:%02x %b\n", sc->name, g, u, "\20"
1024 "\40RME\37RFS\36T8MS\35RMB\34CASC\33CRC4\32SA6SC\31RPF"
1025 "\30b27\27RDO\26ALLS\25XDU\24XMB\23b22\22XLSC\21XPR"
1026 "\20FAR\17LFA\16MFAR\15T400MS\14AIS\13LOS\12RAR\11RA"
1027 "\10ES\7SEC\6LMFA16\5AIS16\4RA16\3API\2SLN\1SLP");
1028 #endif
1029 s = sc->f54r->frs0 << 24;
1030 s |= sc->f54r->frs1 << 16;
1031 s |= sc->f54r->rsw << 8;
1032 s |= sc->f54r->rsp;
1033 sc->falc_state = s;
1034
1035 s &= ~0x01844038; /* undefined or static bits */
1036 s &= ~0x00009fc7; /* bits we don't care about */
1037 s &= ~0x00780000; /* XXX: TS16 related */
1038 s &= ~0x06000000; /* XXX: Multiframe related */
1039 #if 0
1040 kprintf("%s*: FALC54 Status %b\n", sc->name, s, "\20"
1041 "\40LOS\37AIS\36LFA\35RRA\34AUXP\33NMF\32LMFA\31frs0.0"
1042 "\30frs1.7\27TS16RA\26TS16LOS\25TS16AIS\24TS16LFA\23frs1.2\22XLS\21XLO"
1043 "\20RS1\17rsw.6\16RRA\15RY0\14RY1\13RY2\12RY3\11RY4"
1044 "\10SI1\7SI2\6rsp.5\5rsp.4\4rsp.3\3RSIF\2RS13\1RS15");
1045 #endif
1046 if (s != sc->framer_state) {
1047 #if 0
1048 for (i = 0; i < M32_CHAN; i++) {
1049 if (!sc->ch[i])
1050 continue;
1051 sp = &sc->ch[i]->ifsppp;
1052 if (!(sp->pp_if.if_flags & IFF_UP))
1053 continue;
1054 if (s)
1055 timeout((timeout_t *)sp->pp_down, sp, 1 * hz);
1056 else
1057 timeout((timeout_t *)sp->pp_up, sp, 1 * hz);
1058 }
1059 #endif
1060 sc->framer_state = s;
1061 }
1062 }
1063 /* Once per second check error counters */
1064 /* XXX: not clear if this is actually ok */
1065 if (!(u & 0x40))
1066 return;
1067 sc->cnt_fec += sc->f54r->fec;
1068 sc->cnt_cvc += sc->f54r->cvc;
1069 sc->cnt_cec1 += sc->f54r->cec1;
1070 sc->cnt_ebc += sc->f54r->ebc;
1071 sc->cnt_cec2 += sc->f54r->cec2;
1072 sc->cnt_cec3 += sc->f54r->cec3;
1073 sc->cnt_rbc += sc->f54r->rbc;
1074 }
1075
1076 /*
1077 * Transmit interrupt for one channel
1078 */
1079 static void
1080 mn_tx_intr(struct softc *sc, u_int32_t vector)
1081 {
1082 u_int32_t chan;
1083 struct trxd *dp;
1084 struct mbuf *m;
1085
1086 chan = vector & 0x1f;
1087 if (!sc->ch[chan])
1088 return;
1089 if (sc->ch[chan]->state != UP) {
1090 kprintf("%s: tx_intr when not UP\n", sc->name);
1091 return;
1092 }
1093 for (;;) {
1094 dp = sc->ch[chan]->x1;
1095 if (vtophys(dp) == sc->m32_mem.ctxd[chan])
1096 return;
1097 m = dp->m;
1098 if (m) {
1099 #if 0
1100 kprintf("%d = %d - %d (%p)\n",
1101 sc->ch[chan]->tx_pending - m->m_pkthdr.len,
1102 sc->ch[chan]->tx_pending , m->m_pkthdr.len, m);
1103 #endif
1104 sc->ch[chan]->tx_pending -= m->m_pkthdr.len;
1105 m_freem(m);
1106 }
1107 sc->ch[chan]->last_xmit = time_second;
1108 sc->ch[chan]->x1 = dp->vnext;
1109 mn_free_desc(dp);
1110 }
1111 }
1112
1113 /*
1114 * Receive interrupt for one channel
1115 */
1116 static void
1117 mn_rx_intr(struct softc *sc, u_int32_t vector)
1118 {
1119 u_int32_t chan, err;
1120 struct trxd *dp;
1121 struct mbuf *m;
1122 struct schan *sch;
1123
1124 chan = vector & 0x1f;
1125 if (!sc->ch[chan])
1126 return;
1127 sch = sc->ch[chan];
1128 if (sch->state != UP) {
1129 kprintf("%s: rx_intr when not UP\n", sc->name);
1130 return;
1131 }
1132 vector &= ~0x1f;
1133 if (vector == 0x30000b00)
1134 sch->rx_error++;
1135 for (;;) {
1136 dp = sch->r1;
1137 if (vtophys(dp) == sc->m32_mem.crxd[chan])
1138 return;
1139 m = dp->m;
1140 dp->m = 0;
1141 m->m_pkthdr.len = m->m_len = (dp->status >> 16) & 0x1fff;
1142 err = (dp->status >> 8) & 0xff;
1143 if (!err) {
1144 ng_queue_data(sch->hook, m, NULL);
1145 sch->last_recv = time_second;
1146 m = 0;
1147 /* we could be down by now... */
1148 if (sch->state != UP)
1149 return;
1150 } else if (err & 0x40) {
1151 sch->short_error++;
1152 } else if (err & 0x10) {
1153 sch->crc_error++;
1154 } else if (err & 0x08) {
1155 sch->dribble_error++;
1156 } else if (err & 0x04) {
1157 sch->long_error++;
1158 } else if (err & 0x02) {
1159 sch->abort_error++;
1160 } else if (err & 0x01) {
1161 sch->overflow_error++;
1162 }
1163 if (err) {
1164 sch->last_rxerr = time_second;
1165 sch->prev_error = sch->last_error;
1166 sch->last_error = err;
1167 }
1168
1169 sc->ch[chan]->r1 = dp->vnext;
1170
1171 /* Replenish desc + mbuf supplies */
1172 if (!m) {
1173 MGETHDR(m, MB_DONTWAIT, MT_DATA);
1174 if (m == NULL) {
1175 mn_free_desc(dp);
1176 return; /* ENOBUFS */
1177 }
1178 MCLGET(m, MB_DONTWAIT);
1179 if((m->m_flags & M_EXT) == 0) {
1180 mn_free_desc(dp);
1181 m_freem(m);
1182 return; /* ENOBUFS */
1183 }
1184 }
1185 dp->m = m;
1186 dp->data = vtophys(m->m_data);
1187 dp->flags = 0x40000000;
1188 dp->flags += 1600 << 16;
1189 dp->next = vtophys(dp);
1190 dp->vnext = 0;
1191 sc->ch[chan]->rl->next = vtophys(dp);
1192 sc->ch[chan]->rl->vnext = dp;
1193 sc->ch[chan]->rl->flags &= ~0x40000000;
1194 sc->ch[chan]->rl = dp;
1195 }
1196 }
1197
1198
1199 /*
1200 * Interupt handler
1201 */
1202
1203 static void
1204 mn_intr(void *xsc)
1205 {
1206 struct softc *sc;
1207 u_int32_t stat, lstat, u;
1208 int i, j;
1209
1210 sc = xsc;
1211 stat = sc->m32x->stat;
1212 lstat = sc->m32x->lstat;
1213 #if 0
1214 if (!stat && !(lstat & 2))
1215 return;
1216 #endif
1217
1218 if (stat & ~0xc200) {
1219 kprintf("%s: I stat=%08x lstat=%08x\n", sc->name, stat, lstat);
1220 }
1221
1222 if ((stat & 0x200) || (lstat & 2))
1223 f54_intr(sc);
1224
1225 for (j = i = 0; i < 64; i ++) {
1226 u = sc->riqb[i];
1227 if (u) {
1228 sc->riqb[i] = 0;
1229 mn_rx_intr(sc, u);
1230 if ((u & ~0x1f) == 0x30000800 || (u & ~0x1f) == 0x30000b00)
1231 continue;
1232 u &= ~0x30000400; /* bits we don't care about */
1233 if ((u & ~0x1f) == 0x00000900)
1234 continue;
1235 if (!(u & ~0x1f))
1236 continue;
1237 if (!j)
1238 kprintf("%s*: RIQB:", sc->name);
1239 kprintf(" [%d]=%08x", i, u);
1240 j++;
1241 }
1242 }
1243 if (j)
1244 kprintf("\n");
1245
1246 for (j = i = 0; i < 64; i ++) {
1247 u = sc->tiqb[i];
1248 if (u) {
1249 sc->tiqb[i] = 0;
1250 mn_tx_intr(sc, u);
1251 if ((u & ~0x1f) == 0x20000800)
1252 continue;
1253 u &= ~0x20000000; /* bits we don't care about */
1254 if (!u)
1255 continue;
1256 if (!j)
1257 kprintf("%s*: TIQB:", sc->name);
1258 kprintf(" [%d]=%08x", i, u);
1259 j++;
1260 }
1261 }
1262 if (j)
1263 kprintf("\n");
1264 sc->m32x->stat = stat;
1265 }
1266
1267 /*
1268 * PCI initialization stuff
1269 */
1270
1271 static int
1272 mn_probe (device_t self)
1273 {
1274 u_int id = pci_get_devid(self);
1275
1276 if (sizeof (struct m32xreg) != 256) {
1277 kprintf("MN: sizeof(struct m32xreg) = %d, should have been 256\n", sizeof (struct m32xreg));
1278 return (ENXIO);
1279 }
1280 if (sizeof (struct f54rreg) != 128) {
1281 kprintf("MN: sizeof(struct f54rreg) = %d, should have been 128\n", sizeof (struct f54rreg));
1282 return (ENXIO);
1283 }
1284 if (sizeof (struct f54wreg) != 128) {
1285 kprintf("MN: sizeof(struct f54wreg) = %d, should have been 128\n", sizeof (struct f54wreg));
1286 return (ENXIO);
1287 }
1288
1289 if (id != 0x2101110a)
1290 return (ENXIO);
1291
1292 device_set_desc_copy(self, "Munich32X E1/T1 HDLC Controller");
1293 return (0);
1294 }
1295
1296 static int
1297 mn_attach (device_t self)
1298 {
1299 struct softc *sc;
1300 u_int32_t u;
1301 u_int32_t ver;
1302 static int once;
1303 int rid, error;
1304 struct resource *res;
1305
1306 if (!once) {
1307 if (ng_newtype(&mntypestruct))
1308 kprintf("ng_newtype failed\n");
1309 once++;
1310 }
1311
1312 sc = (struct softc *)kmalloc(sizeof *sc, M_MN, M_WAITOK | M_ZERO);
1313 device_set_softc(self, sc);
1314
1315 sc->dev = self;
1316 sc->unit = device_get_unit(self);
1317 sc->framing = E1;
1318 ksprintf(sc->name, "mn%d", sc->unit);
1319
1320 rid = PCIR_MAPS;
1321 res = bus_alloc_resource_any(self, SYS_RES_MEMORY, &rid, RF_ACTIVE);
1322 if (res == NULL) {
1323 device_printf(self, "Could not map memory\n");
1324 return ENXIO;
1325 }
1326 sc->m0v = rman_get_virtual(res);
1327 sc->m0p = rman_get_start(res);
1328
1329 rid = PCIR_MAPS + 4;
1330 res = bus_alloc_resource_any(self, SYS_RES_MEMORY, &rid, RF_ACTIVE);
1331 if (res == NULL) {
1332 device_printf(self, "Could not map memory\n");
1333 return ENXIO;
1334 }
1335 sc->m1v = rman_get_virtual(res);
1336 sc->m1p = rman_get_start(res);
1337
1338 /* Allocate interrupt */
1339 rid = 0;
1340 sc->irq = bus_alloc_resource_any(self, SYS_RES_IRQ, &rid,
1341 RF_SHAREABLE | RF_ACTIVE);
1342
1343 if (sc->irq == NULL) {
1344 kprintf("couldn't map interrupt\n");
1345 return(ENXIO);
1346 }
1347
1348 error = bus_setup_intr(self, sc->irq, INTR_NETSAFE, mn_intr, sc,
1349 &sc->intrhand, NULL);
1350
1351 if (error) {
1352 kprintf("couldn't set up irq\n");
1353 return(ENXIO);
1354 }
1355
1356 u = pci_read_config(self, PCIR_COMMAND, 1);
1357 kprintf("%x\n", u);
1358 pci_write_config(self, PCIR_COMMAND, u | PCIM_CMD_PERRESPEN | PCIM_CMD_BUSMASTEREN | PCIM_CMD_MEMEN, 1);
1359 #if 0
1360 pci_write_config(self, PCIR_COMMAND, 0x02800046, 4);
1361 #endif
1362 u = pci_read_config(self, PCIR_COMMAND, 1);
1363 kprintf("%x\n", u);
1364
1365 ver = pci_get_revid(self);
1366
1367 sc->m32x = (struct m32xreg *) sc->m0v;
1368 sc->f54w = (struct f54wreg *) sc->m1v;
1369 sc->f54r = (struct f54rreg *) sc->m1v;
1370
1371 /* We must reset before poking at FALC54 registers */
1372 u = mn_reset(sc);
1373 if (!u)
1374 return (0);
1375
1376 kprintf("mn%d: Munich32X", sc->unit);
1377 switch (ver) {
1378 case 0x13:
1379 kprintf(" Rev 2.2");
1380 break;
1381 default:
1382 kprintf(" Rev 0x%x\n", ver);
1383 }
1384 kprintf(", Falc54");
1385 switch (sc->f54r->vstr) {
1386 case 0:
1387 kprintf(" Rev < 1.3\n");
1388 break;
1389 case 1:
1390 kprintf(" Rev 1.3\n");
1391 break;
1392 case 2:
1393 kprintf(" Rev 1.4\n");
1394 break;
1395 case 0x10:
1396 kprintf("-LH Rev 1.1\n");
1397 break;
1398 case 0x13:
1399 kprintf("-LH Rev 1.3\n");
1400 break;
1401 default:
1402 kprintf(" Rev 0x%x\n", sc->f54r->vstr);
1403 }
1404
1405 if (ng_make_node_common(&mntypestruct, &sc->node) != 0) {
1406 kprintf("ng_make_node_common failed\n");
1407 return (0);
1408 }
1409 sc->node->private = sc;
1410 ksprintf(sc->nodename, "%s%d", NG_MN_NODE_TYPE, sc->unit);
1411 if (ng_name_node(sc->node, sc->nodename)) {
1412 ng_rmnode(sc->node);
1413 ng_unref(sc->node);
1414 return (0);
1415 }
1416
1417 return (0);
1418 }
1419
1420
1421 static device_method_t mn_methods[] = {
1422 /* Device interface */
1423 DEVMETHOD(device_probe, mn_probe),
1424 DEVMETHOD(device_attach, mn_attach),
1425 DEVMETHOD(device_suspend, bus_generic_suspend),
1426 DEVMETHOD(device_resume, bus_generic_resume),
1427 DEVMETHOD(device_shutdown, bus_generic_shutdown),
1428
1429 {0, 0}
1430 };
1431
1432 static driver_t mn_driver = {
1433 "mn",
1434 mn_methods,
1435 0
1436 };
1437
1438 static devclass_t mn_devclass;
1439
1440 DECLARE_DUMMY_MODULE(if_mn);
1441 DRIVER_MODULE(if_mn, pci, mn_driver, mn_devclass, 0, 0);
1442
DragonFly BSD