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[dragonfly.git] / sys / dev / drm / savage_bci.c
blob16f7df64e5342beee65631d10e9c6599346876ff
1 /* savage_bci.c -- BCI support for Savage
2 *
3 * Copyright 2004 Felix Kuehling
4 * All Rights Reserved.
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * the rights to use, copy, modify, merge, publish, distribute, sub license,
10 * and/or sell copies of the Software, and to permit persons to whom the
11 * Software is furnished to do so, subject to the following conditions:
12 *
13 * The above copyright notice and this permission notice (including the
14 * next paragraph) shall be included in all copies or substantial portions
15 * of the Software.
16 *
17 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
18 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
19 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
20 * NON-INFRINGEMENT. IN NO EVENT SHALL FELIX KUEHLING BE LIABLE FOR
21 * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF
22 * CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
23 * WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
24 *
25 * $DragonFly: src/sys/dev/drm/savage_bci.c,v 1.1 2008/04/05 18:12:29 hasso Exp $
26 */
27 #include "drmP.h"
28 #include "savage_drm.h"
29 #include "savage_drv.h"
30
31 /* Need a long timeout for shadow status updates can take a while
32 * and so can waiting for events when the queue is full. */
33 #define SAVAGE_DEFAULT_USEC_TIMEOUT 1000000 /* 1s */
34 #define SAVAGE_EVENT_USEC_TIMEOUT 5000000 /* 5s */
35 #define SAVAGE_FREELIST_DEBUG 0
36
37 static int savage_do_cleanup_bci(struct drm_device *dev);
38
39 static int
40 savage_bci_wait_fifo_shadow(drm_savage_private_t *dev_priv, unsigned int n)
41 {
42 uint32_t mask = dev_priv->status_used_mask;
43 uint32_t threshold = dev_priv->bci_threshold_hi;
44 uint32_t status;
45 int i;
46
47 #if SAVAGE_BCI_DEBUG
48 if (n > dev_priv->cob_size + SAVAGE_BCI_FIFO_SIZE - threshold)
49 DRM_ERROR("Trying to emit %d words "
50 "(more than guaranteed space in COB)\n", n);
51 #endif
52
53 for (i = 0; i < SAVAGE_DEFAULT_USEC_TIMEOUT; i++) {
54 DRM_MEMORYBARRIER();
55 status = dev_priv->status_ptr[0];
56 if ((status & mask) < threshold)
57 return 0;
58 DRM_UDELAY(1);
59 }
60
61 #if SAVAGE_BCI_DEBUG
62 DRM_ERROR("failed!\n");
63 DRM_INFO(" status=0x%08x, threshold=0x%08x\n", status, threshold);
64 #endif
65 return -EBUSY;
66 }
67
68 static int
69 savage_bci_wait_fifo_s3d(drm_savage_private_t *dev_priv, unsigned int n)
70 {
71 uint32_t maxUsed = dev_priv->cob_size + SAVAGE_BCI_FIFO_SIZE - n;
72 uint32_t status;
73 int i;
74
75 for (i = 0; i < SAVAGE_DEFAULT_USEC_TIMEOUT; i++) {
76 status = SAVAGE_READ(SAVAGE_STATUS_WORD0);
77 if ((status & SAVAGE_FIFO_USED_MASK_S3D) <= maxUsed)
78 return 0;
79 DRM_UDELAY(1);
80 }
81
82 #if SAVAGE_BCI_DEBUG
83 DRM_ERROR("failed!\n");
84 DRM_INFO(" status=0x%08x\n", status);
85 #endif
86 return -EBUSY;
87 }
88
89 static int
90 savage_bci_wait_fifo_s4(drm_savage_private_t *dev_priv, unsigned int n)
91 {
92 uint32_t maxUsed = dev_priv->cob_size + SAVAGE_BCI_FIFO_SIZE - n;
93 uint32_t status;
94 int i;
95
96 for (i = 0; i < SAVAGE_DEFAULT_USEC_TIMEOUT; i++) {
97 status = SAVAGE_READ(SAVAGE_ALT_STATUS_WORD0);
98 if ((status & SAVAGE_FIFO_USED_MASK_S4) <= maxUsed)
99 return 0;
100 DRM_UDELAY(1);
101 }
102
103 #if SAVAGE_BCI_DEBUG
104 DRM_ERROR("failed!\n");
105 DRM_INFO(" status=0x%08x\n", status);
106 #endif
107 return -EBUSY;
108 }
109
110 /*
111 * Waiting for events.
112 *
113 * The BIOSresets the event tag to 0 on mode changes. Therefore we
114 * never emit 0 to the event tag. If we find a 0 event tag we know the
115 * BIOS stomped on it and return success assuming that the BIOS waited
116 * for engine idle.
117 *
118 * Note: if the Xserver uses the event tag it has to follow the same
119 * rule. Otherwise there may be glitches every 2^16 events.
120 */
121 static int
122 savage_bci_wait_event_shadow(drm_savage_private_t *dev_priv, uint16_t e)
123 {
124 uint32_t status;
125 int i;
126
127 for (i = 0; i < SAVAGE_EVENT_USEC_TIMEOUT; i++) {
128 DRM_MEMORYBARRIER();
129 status = dev_priv->status_ptr[1];
130 if ((((status & 0xffff) - e) & 0xffff) <= 0x7fff ||
131 (status & 0xffff) == 0)
132 return 0;
133 DRM_UDELAY(1);
134 }
135
136 #if SAVAGE_BCI_DEBUG
137 DRM_ERROR("failed!\n");
138 DRM_INFO(" status=0x%08x, e=0x%04x\n", status, e);
139 #endif
140
141 return -EBUSY;
142 }
143
144 static int
145 savage_bci_wait_event_reg(drm_savage_private_t *dev_priv, uint16_t e)
146 {
147 uint32_t status;
148 int i;
149
150 for (i = 0; i < SAVAGE_EVENT_USEC_TIMEOUT; i++) {
151 status = SAVAGE_READ(SAVAGE_STATUS_WORD1);
152 if ((((status & 0xffff) - e) & 0xffff) <= 0x7fff ||
153 (status & 0xffff) == 0)
154 return 0;
155 DRM_UDELAY(1);
156 }
157
158 #if SAVAGE_BCI_DEBUG
159 DRM_ERROR("failed!\n");
160 DRM_INFO(" status=0x%08x, e=0x%04x\n", status, e);
161 #endif
162
163 return -EBUSY;
164 }
165
166 uint16_t savage_bci_emit_event(drm_savage_private_t *dev_priv,
167 unsigned int flags)
168 {
169 uint16_t count;
170 BCI_LOCALS;
171
172 if (dev_priv->status_ptr) {
173 /* coordinate with Xserver */
174 count = dev_priv->status_ptr[1023];
175 if (count < dev_priv->event_counter)
176 dev_priv->event_wrap++;
177 } else {
178 count = dev_priv->event_counter;
179 }
180 count = (count + 1) & 0xffff;
181 if (count == 0) {
182 count++; /* See the comment above savage_wait_event_*. */
183 dev_priv->event_wrap++;
184 }
185 dev_priv->event_counter = count;
186 if (dev_priv->status_ptr)
187 dev_priv->status_ptr[1023] = (uint32_t)count;
188
189 if ((flags & (SAVAGE_WAIT_2D | SAVAGE_WAIT_3D))) {
190 unsigned int wait_cmd = BCI_CMD_WAIT;
191 if ((flags & SAVAGE_WAIT_2D))
192 wait_cmd |= BCI_CMD_WAIT_2D;
193 if ((flags & SAVAGE_WAIT_3D))
194 wait_cmd |= BCI_CMD_WAIT_3D;
195 BEGIN_BCI(2);
196 BCI_WRITE(wait_cmd);
197 } else {
198 BEGIN_BCI(1);
199 }
200 BCI_WRITE(BCI_CMD_UPDATE_EVENT_TAG | (uint32_t)count);
201
202 return count;
203 }
204
205 /*
206 * Freelist management
207 */
208 static int savage_freelist_init(struct drm_device *dev)
209 {
210 drm_savage_private_t *dev_priv = dev->dev_private;
211 struct drm_device_dma *dma = dev->dma;
212 struct drm_buf *buf;
213 drm_savage_buf_priv_t *entry;
214 int i;
215 DRM_DEBUG("count=%d\n", dma->buf_count);
216
217 dev_priv->head.next = &dev_priv->tail;
218 dev_priv->head.prev = NULL;
219 dev_priv->head.buf = NULL;
220
221 dev_priv->tail.next = NULL;
222 dev_priv->tail.prev = &dev_priv->head;
223 dev_priv->tail.buf = NULL;
224
225 for (i = 0; i < dma->buf_count; i++) {
226 buf = dma->buflist[i];
227 entry = buf->dev_private;
228
229 SET_AGE(&entry->age, 0, 0);
230 entry->buf = buf;
231
232 entry->next = dev_priv->head.next;
233 entry->prev = &dev_priv->head;
234 dev_priv->head.next->prev = entry;
235 dev_priv->head.next = entry;
236 }
237
238 return 0;
239 }
240
241 static struct drm_buf *savage_freelist_get(struct drm_device *dev)
242 {
243 drm_savage_private_t *dev_priv = dev->dev_private;
244 drm_savage_buf_priv_t *tail = dev_priv->tail.prev;
245 uint16_t event;
246 unsigned int wrap;
247 DRM_DEBUG("\n");
248
249 UPDATE_EVENT_COUNTER();
250 if (dev_priv->status_ptr)
251 event = dev_priv->status_ptr[1] & 0xffff;
252 else
253 event = SAVAGE_READ(SAVAGE_STATUS_WORD1) & 0xffff;
254 wrap = dev_priv->event_wrap;
255 if (event > dev_priv->event_counter)
256 wrap--; /* hardware hasn't passed the last wrap yet */
257
258 DRM_DEBUG(" tail=0x%04x %d\n", tail->age.event, tail->age.wrap);
259 DRM_DEBUG(" head=0x%04x %d\n", event, wrap);
260
261 if (tail->buf && (TEST_AGE(&tail->age, event, wrap) || event == 0)) {
262 drm_savage_buf_priv_t *next = tail->next;
263 drm_savage_buf_priv_t *prev = tail->prev;
264 prev->next = next;
265 next->prev = prev;
266 tail->next = tail->prev = NULL;
267 return tail->buf;
268 }
269
270 DRM_DEBUG("returning NULL, tail->buf=%p!\n", tail->buf);
271 return NULL;
272 }
273
274 void savage_freelist_put(struct drm_device *dev, struct drm_buf *buf)
275 {
276 drm_savage_private_t *dev_priv = dev->dev_private;
277 drm_savage_buf_priv_t *entry = buf->dev_private, *prev, *next;
278
279 DRM_DEBUG("age=0x%04x wrap=%d\n", entry->age.event, entry->age.wrap);
280
281 if (entry->next != NULL || entry->prev != NULL) {
282 DRM_ERROR("entry already on freelist.\n");
283 return;
284 }
285
286 prev = &dev_priv->head;
287 next = prev->next;
288 prev->next = entry;
289 next->prev = entry;
290 entry->prev = prev;
291 entry->next = next;
292 }
293
294 /*
295 * Command DMA
296 */
297 static int savage_dma_init(drm_savage_private_t *dev_priv)
298 {
299 unsigned int i;
300
301 dev_priv->nr_dma_pages = dev_priv->cmd_dma->size /
302 (SAVAGE_DMA_PAGE_SIZE*4);
303 dev_priv->dma_pages = drm_alloc(sizeof(drm_savage_dma_page_t) *
304 dev_priv->nr_dma_pages, DRM_MEM_DRIVER);
305 if (dev_priv->dma_pages == NULL)
306 return -ENOMEM;
307
308 for (i = 0; i < dev_priv->nr_dma_pages; ++i) {
309 SET_AGE(&dev_priv->dma_pages[i].age, 0, 0);
310 dev_priv->dma_pages[i].used = 0;
311 dev_priv->dma_pages[i].flushed = 0;
312 }
313 SET_AGE(&dev_priv->last_dma_age, 0, 0);
314
315 dev_priv->first_dma_page = 0;
316 dev_priv->current_dma_page = 0;
317
318 return 0;
319 }
320
321 void savage_dma_reset(drm_savage_private_t *dev_priv)
322 {
323 uint16_t event;
324 unsigned int wrap, i;
325 event = savage_bci_emit_event(dev_priv, 0);
326 wrap = dev_priv->event_wrap;
327 for (i = 0; i < dev_priv->nr_dma_pages; ++i) {
328 SET_AGE(&dev_priv->dma_pages[i].age, event, wrap);
329 dev_priv->dma_pages[i].used = 0;
330 dev_priv->dma_pages[i].flushed = 0;
331 }
332 SET_AGE(&dev_priv->last_dma_age, event, wrap);
333 dev_priv->first_dma_page = dev_priv->current_dma_page = 0;
334 }
335
336 void savage_dma_wait(drm_savage_private_t *dev_priv, unsigned int page)
337 {
338 uint16_t event;
339 unsigned int wrap;
340
341 /* Faked DMA buffer pages don't age. */
342 if (dev_priv->cmd_dma == &dev_priv->fake_dma)
343 return;
344
345 UPDATE_EVENT_COUNTER();
346 if (dev_priv->status_ptr)
347 event = dev_priv->status_ptr[1] & 0xffff;
348 else
349 event = SAVAGE_READ(SAVAGE_STATUS_WORD1) & 0xffff;
350 wrap = dev_priv->event_wrap;
351 if (event > dev_priv->event_counter)
352 wrap--; /* hardware hasn't passed the last wrap yet */
353
354 if (dev_priv->dma_pages[page].age.wrap > wrap ||
355 (dev_priv->dma_pages[page].age.wrap == wrap &&
356 dev_priv->dma_pages[page].age.event > event)) {
357 if (dev_priv->wait_evnt(dev_priv,
358 dev_priv->dma_pages[page].age.event)
359 < 0)
360 DRM_ERROR("wait_evnt failed!\n");
361 }
362 }
363
364 uint32_t *savage_dma_alloc(drm_savage_private_t *dev_priv, unsigned int n)
365 {
366 unsigned int cur = dev_priv->current_dma_page;
367 unsigned int rest = SAVAGE_DMA_PAGE_SIZE -
368 dev_priv->dma_pages[cur].used;
369 unsigned int nr_pages = (n - rest + SAVAGE_DMA_PAGE_SIZE - 1) /
370 SAVAGE_DMA_PAGE_SIZE;
371 uint32_t *dma_ptr;
372 unsigned int i;
373
374 DRM_DEBUG("cur=%u, cur->used=%u, n=%u, rest=%u, nr_pages=%u\n",
375 cur, dev_priv->dma_pages[cur].used, n, rest, nr_pages);
376
377 if (cur + nr_pages < dev_priv->nr_dma_pages) {
378 dma_ptr = (uint32_t *)dev_priv->cmd_dma->handle +
379 cur * SAVAGE_DMA_PAGE_SIZE + dev_priv->dma_pages[cur].used;
380 if (n < rest)
381 rest = n;
382 dev_priv->dma_pages[cur].used += rest;
383 n -= rest;
384 cur++;
385 } else {
386 dev_priv->dma_flush(dev_priv);
387 nr_pages =
388 (n + SAVAGE_DMA_PAGE_SIZE - 1) / SAVAGE_DMA_PAGE_SIZE;
389 for (i = cur; i < dev_priv->nr_dma_pages; ++i) {
390 dev_priv->dma_pages[i].age = dev_priv->last_dma_age;
391 dev_priv->dma_pages[i].used = 0;
392 dev_priv->dma_pages[i].flushed = 0;
393 }
394 dma_ptr = (uint32_t *)dev_priv->cmd_dma->handle;
395 dev_priv->first_dma_page = cur = 0;
396 }
397 for (i = cur; nr_pages > 0; ++i, --nr_pages) {
398 #if SAVAGE_DMA_DEBUG
399 if (dev_priv->dma_pages[i].used) {
400 DRM_ERROR("unflushed page %u: used=%u\n",
401 i, dev_priv->dma_pages[i].used);
402 }
403 #endif
404 if (n > SAVAGE_DMA_PAGE_SIZE)
405 dev_priv->dma_pages[i].used = SAVAGE_DMA_PAGE_SIZE;
406 else
407 dev_priv->dma_pages[i].used = n;
408 n -= SAVAGE_DMA_PAGE_SIZE;
409 }
410 dev_priv->current_dma_page = --i;
411
412 DRM_DEBUG("cur=%u, cur->used=%u, n=%u\n",
413 i, dev_priv->dma_pages[i].used, n);
414
415 savage_dma_wait(dev_priv, dev_priv->current_dma_page);
416
417 return dma_ptr;
418 }
419
420 static void savage_dma_flush(drm_savage_private_t *dev_priv)
421 {
422 unsigned int first = dev_priv->first_dma_page;
423 unsigned int cur = dev_priv->current_dma_page;
424 uint16_t event;
425 unsigned int wrap, pad, align, len, i;
426 unsigned long phys_addr;
427 BCI_LOCALS;
428
429 if (first == cur &&
430 dev_priv->dma_pages[cur].used == dev_priv->dma_pages[cur].flushed)
431 return;
432
433 /* pad length to multiples of 2 entries
434 * align start of next DMA block to multiles of 8 entries */
435 pad = -dev_priv->dma_pages[cur].used & 1;
436 align = -(dev_priv->dma_pages[cur].used + pad) & 7;
437
438 DRM_DEBUG("first=%u, cur=%u, first->flushed=%u, cur->used=%u, "
439 "pad=%u, align=%u\n",
440 first, cur, dev_priv->dma_pages[first].flushed,
441 dev_priv->dma_pages[cur].used, pad, align);
442
443 /* pad with noops */
444 if (pad) {
445 uint32_t *dma_ptr = (uint32_t *)dev_priv->cmd_dma->handle +
446 cur * SAVAGE_DMA_PAGE_SIZE + dev_priv->dma_pages[cur].used;
447 dev_priv->dma_pages[cur].used += pad;
448 while (pad != 0) {
449 *dma_ptr++ = BCI_CMD_WAIT;
450 pad--;
451 }
452 }
453
454 DRM_MEMORYBARRIER();
455
456 /* do flush ... */
457 phys_addr = dev_priv->cmd_dma->offset +
458 (first * SAVAGE_DMA_PAGE_SIZE +
459 dev_priv->dma_pages[first].flushed) * 4;
460 len = (cur - first) * SAVAGE_DMA_PAGE_SIZE +
461 dev_priv->dma_pages[cur].used - dev_priv->dma_pages[first].flushed;
462
463 DRM_DEBUG("phys_addr=%lx, len=%u\n",
464 phys_addr | dev_priv->dma_type, len);
465
466 BEGIN_BCI(3);
467 BCI_SET_REGISTERS(SAVAGE_DMABUFADDR, 1);
468 BCI_WRITE(phys_addr | dev_priv->dma_type);
469 BCI_DMA(len);
470
471 /* fix alignment of the start of the next block */
472 dev_priv->dma_pages[cur].used += align;
473
474 /* age DMA pages */
475 event = savage_bci_emit_event(dev_priv, 0);
476 wrap = dev_priv->event_wrap;
477 for (i = first; i < cur; ++i) {
478 SET_AGE(&dev_priv->dma_pages[i].age, event, wrap);
479 dev_priv->dma_pages[i].used = 0;
480 dev_priv->dma_pages[i].flushed = 0;
481 }
482 /* age the current page only when it's full */
483 if (dev_priv->dma_pages[cur].used == SAVAGE_DMA_PAGE_SIZE) {
484 SET_AGE(&dev_priv->dma_pages[cur].age, event, wrap);
485 dev_priv->dma_pages[cur].used = 0;
486 dev_priv->dma_pages[cur].flushed = 0;
487 /* advance to next page */
488 cur++;
489 if (cur == dev_priv->nr_dma_pages)
490 cur = 0;
491 dev_priv->first_dma_page = dev_priv->current_dma_page = cur;
492 } else {
493 dev_priv->first_dma_page = cur;
494 dev_priv->dma_pages[cur].flushed = dev_priv->dma_pages[i].used;
495 }
496 SET_AGE(&dev_priv->last_dma_age, event, wrap);
497
498 DRM_DEBUG("first=cur=%u, cur->used=%u, cur->flushed=%u\n", cur,
499 dev_priv->dma_pages[cur].used,
500 dev_priv->dma_pages[cur].flushed);
501 }
502
503 static void savage_fake_dma_flush(drm_savage_private_t *dev_priv)
504 {
505 unsigned int i, j;
506 BCI_LOCALS;
507
508 if (dev_priv->first_dma_page == dev_priv->current_dma_page &&
509 dev_priv->dma_pages[dev_priv->current_dma_page].used == 0)
510 return;
511
512 DRM_DEBUG("first=%u, cur=%u, cur->used=%u\n",
513 dev_priv->first_dma_page, dev_priv->current_dma_page,
514 dev_priv->dma_pages[dev_priv->current_dma_page].used);
515
516 for (i = dev_priv->first_dma_page;
517 i <= dev_priv->current_dma_page && dev_priv->dma_pages[i].used;
518 ++i) {
519 uint32_t *dma_ptr = (uint32_t *)dev_priv->cmd_dma->handle +
520 i * SAVAGE_DMA_PAGE_SIZE;
521 #if SAVAGE_DMA_DEBUG
522 /* Sanity check: all pages except the last one must be full. */
523 if (i < dev_priv->current_dma_page &&
524 dev_priv->dma_pages[i].used != SAVAGE_DMA_PAGE_SIZE) {
525 DRM_ERROR("partial DMA page %u: used=%u",
526 i, dev_priv->dma_pages[i].used);
527 }
528 #endif
529 BEGIN_BCI(dev_priv->dma_pages[i].used);
530 for (j = 0; j < dev_priv->dma_pages[i].used; ++j) {
531 BCI_WRITE(dma_ptr[j]);
532 }
533 dev_priv->dma_pages[i].used = 0;
534 }
535
536 /* reset to first page */
537 dev_priv->first_dma_page = dev_priv->current_dma_page = 0;
538 }
539
540 int savage_driver_load(struct drm_device *dev, unsigned long chipset)
541 {
542 drm_savage_private_t *dev_priv;
543
544 dev_priv = drm_alloc(sizeof(drm_savage_private_t), DRM_MEM_DRIVER);
545 if (dev_priv == NULL)
546 return -ENOMEM;
547
548 memset(dev_priv, 0, sizeof(drm_savage_private_t));
549 dev->dev_private = (void *)dev_priv;
550
551 dev_priv->chipset = (enum savage_family)chipset;
552
553 return 0;
554 }
555
556 /*
557 * Initalize mappings. On Savage4 and SavageIX the alignment
558 * and size of the aperture is not suitable for automatic MTRR setup
559 * in drm_addmap. Therefore we add them manually before the maps are
560 * initialized, and tear them down on last close.
561 */
562 int savage_driver_firstopen(struct drm_device *dev)
563 {
564 drm_savage_private_t *dev_priv = dev->dev_private;
565 unsigned long mmio_base, fb_base, fb_size, aperture_base;
566 /* fb_rsrc and aper_rsrc aren't really used currently, but still exist
567 * in case we decide we need information on the BAR for BSD in the
568 * future.
569 */
570 unsigned int fb_rsrc, aper_rsrc;
571 int ret = 0;
572
573 dev_priv->mtrr[0].handle = -1;
574 dev_priv->mtrr[1].handle = -1;
575 dev_priv->mtrr[2].handle = -1;
576 if (S3_SAVAGE3D_SERIES(dev_priv->chipset)) {
577 fb_rsrc = 0;
578 fb_base = drm_get_resource_start(dev, 0);
579 fb_size = SAVAGE_FB_SIZE_S3;
580 mmio_base = fb_base + SAVAGE_FB_SIZE_S3;
581 aper_rsrc = 0;
582 aperture_base = fb_base + SAVAGE_APERTURE_OFFSET;
583 /* this should always be true */
584 if (drm_get_resource_len(dev, 0) == 0x08000000) {
585 /* Don't make MMIO write-cobining! We need 3
586 * MTRRs. */
587 dev_priv->mtrr[0].base = fb_base;
588 dev_priv->mtrr[0].size = 0x01000000;
589 dev_priv->mtrr[0].handle =
590 drm_mtrr_add(dev_priv->mtrr[0].base,
591 dev_priv->mtrr[0].size, DRM_MTRR_WC);
592 dev_priv->mtrr[1].base = fb_base + 0x02000000;
593 dev_priv->mtrr[1].size = 0x02000000;
594 dev_priv->mtrr[1].handle =
595 drm_mtrr_add(dev_priv->mtrr[1].base,
596 dev_priv->mtrr[1].size, DRM_MTRR_WC);
597 dev_priv->mtrr[2].base = fb_base + 0x04000000;
598 dev_priv->mtrr[2].size = 0x04000000;
599 dev_priv->mtrr[2].handle =
600 drm_mtrr_add(dev_priv->mtrr[2].base,
601 dev_priv->mtrr[2].size, DRM_MTRR_WC);
602 } else {
603 DRM_ERROR("strange pci_resource_len %08lx\n",
604 drm_get_resource_len(dev, 0));
605 }
606 } else if (dev_priv->chipset != S3_SUPERSAVAGE &&
607 dev_priv->chipset != S3_SAVAGE2000) {
608 mmio_base = drm_get_resource_start(dev, 0);
609 fb_rsrc = 1;
610 fb_base = drm_get_resource_start(dev, 1);
611 fb_size = SAVAGE_FB_SIZE_S4;
612 aper_rsrc = 1;
613 aperture_base = fb_base + SAVAGE_APERTURE_OFFSET;
614 /* this should always be true */
615 if (drm_get_resource_len(dev, 1) == 0x08000000) {
616 /* Can use one MTRR to cover both fb and
617 * aperture. */
618 dev_priv->mtrr[0].base = fb_base;
619 dev_priv->mtrr[0].size = 0x08000000;
620 dev_priv->mtrr[0].handle =
621 drm_mtrr_add(dev_priv->mtrr[0].base,
622 dev_priv->mtrr[0].size, DRM_MTRR_WC);
623 } else {
624 DRM_ERROR("strange pci_resource_len %08lx\n",
625 drm_get_resource_len(dev, 1));
626 }
627 } else {
628 mmio_base = drm_get_resource_start(dev, 0);
629 fb_rsrc = 1;
630 fb_base = drm_get_resource_start(dev, 1);
631 fb_size = drm_get_resource_len(dev, 1);
632 aper_rsrc = 2;
633 aperture_base = drm_get_resource_start(dev, 2);
634 /* Automatic MTRR setup will do the right thing. */
635 }
636
637 ret = drm_addmap(dev, mmio_base, SAVAGE_MMIO_SIZE, _DRM_REGISTERS,
638 _DRM_READ_ONLY, &dev_priv->mmio);
639 if (ret)
640 return ret;
641
642 ret = drm_addmap(dev, fb_base, fb_size, _DRM_FRAME_BUFFER,
643 _DRM_WRITE_COMBINING, &dev_priv->fb);
644 if (ret)
645 return ret;
646
647 ret = drm_addmap(dev, aperture_base, SAVAGE_APERTURE_SIZE,
648 _DRM_FRAME_BUFFER, _DRM_WRITE_COMBINING,
649 &dev_priv->aperture);
650 if (ret)
651 return ret;
652
653 return ret;
654 }
655
656 /*
657 * Delete MTRRs and free device-private data.
658 */
659 void savage_driver_lastclose(struct drm_device *dev)
660 {
661 drm_savage_private_t *dev_priv = dev->dev_private;
662 int i;
663
664 for (i = 0; i < 3; ++i)
665 if (dev_priv->mtrr[i].handle >= 0)
666 drm_mtrr_del(dev_priv->mtrr[i].handle,
667 dev_priv->mtrr[i].base,
668 dev_priv->mtrr[i].size, DRM_MTRR_WC);
669 }
670
671 int savage_driver_unload(struct drm_device *dev)
672 {
673 drm_savage_private_t *dev_priv = dev->dev_private;
674
675 drm_free(dev_priv, sizeof(drm_savage_private_t), DRM_MEM_DRIVER);
676
677 return 0;
678 }
679
680 static int savage_do_init_bci(struct drm_device *dev, drm_savage_init_t *init)
681 {
682 drm_savage_private_t *dev_priv = dev->dev_private;
683
684 if (init->fb_bpp != 16 && init->fb_bpp != 32) {
685 DRM_ERROR("invalid frame buffer bpp %d!\n", init->fb_bpp);
686 return -EINVAL;
687 }
688 if (init->depth_bpp != 16 && init->depth_bpp != 32) {
689 DRM_ERROR("invalid depth buffer bpp %d!\n", init->fb_bpp);
690 return -EINVAL;
691 }
692 if (init->dma_type != SAVAGE_DMA_AGP &&
693 init->dma_type != SAVAGE_DMA_PCI) {
694 DRM_ERROR("invalid dma memory type %d!\n", init->dma_type);
695 return -EINVAL;
696 }
697
698 dev_priv->cob_size = init->cob_size;
699 dev_priv->bci_threshold_lo = init->bci_threshold_lo;
700 dev_priv->bci_threshold_hi = init->bci_threshold_hi;
701 dev_priv->dma_type = init->dma_type;
702
703 dev_priv->fb_bpp = init->fb_bpp;
704 dev_priv->front_offset = init->front_offset;
705 dev_priv->front_pitch = init->front_pitch;
706 dev_priv->back_offset = init->back_offset;
707 dev_priv->back_pitch = init->back_pitch;
708 dev_priv->depth_bpp = init->depth_bpp;
709 dev_priv->depth_offset = init->depth_offset;
710 dev_priv->depth_pitch = init->depth_pitch;
711
712 dev_priv->texture_offset = init->texture_offset;
713 dev_priv->texture_size = init->texture_size;
714
715 dev_priv->sarea = drm_getsarea(dev);
716 if (!dev_priv->sarea) {
717 DRM_ERROR("could not find sarea!\n");
718 savage_do_cleanup_bci(dev);
719 return -EINVAL;
720 }
721 if (init->status_offset != 0) {
722 dev_priv->status = drm_core_findmap(dev, init->status_offset);
723 if (!dev_priv->status) {
724 DRM_ERROR("could not find shadow status region!\n");
725 savage_do_cleanup_bci(dev);
726 return -EINVAL;
727 }
728 } else {
729 dev_priv->status = NULL;
730 }
731 if (dev_priv->dma_type == SAVAGE_DMA_AGP && init->buffers_offset) {
732 dev->agp_buffer_token = init->buffers_offset;
733 dev->agp_buffer_map = drm_core_findmap(dev,
734 init->buffers_offset);
735 if (!dev->agp_buffer_map) {
736 DRM_ERROR("could not find DMA buffer region!\n");
737 savage_do_cleanup_bci(dev);
738 return -EINVAL;
739 }
740 drm_core_ioremap(dev->agp_buffer_map, dev);
741 if (!dev->agp_buffer_map) {
742 DRM_ERROR("failed to ioremap DMA buffer region!\n");
743 savage_do_cleanup_bci(dev);
744 return -ENOMEM;
745 }
746 }
747 if (init->agp_textures_offset) {
748 dev_priv->agp_textures =
749 drm_core_findmap(dev, init->agp_textures_offset);
750 if (!dev_priv->agp_textures) {
751 DRM_ERROR("could not find agp texture region!\n");
752 savage_do_cleanup_bci(dev);
753 return -EINVAL;
754 }
755 } else {
756 dev_priv->agp_textures = NULL;
757 }
758
759 if (init->cmd_dma_offset) {
760 if (S3_SAVAGE3D_SERIES(dev_priv->chipset)) {
761 DRM_ERROR("command DMA not supported on "
762 "Savage3D/MX/IX.\n");
763 savage_do_cleanup_bci(dev);
764 return -EINVAL;
765 }
766 if (dev->dma && dev->dma->buflist) {
767 DRM_ERROR("command and vertex DMA not supported "
768 "at the same time.\n");
769 savage_do_cleanup_bci(dev);
770 return -EINVAL;
771 }
772 dev_priv->cmd_dma = drm_core_findmap(dev, init->cmd_dma_offset);
773 if (!dev_priv->cmd_dma) {
774 DRM_ERROR("could not find command DMA region!\n");
775 savage_do_cleanup_bci(dev);
776 return -EINVAL;
777 }
778 if (dev_priv->dma_type == SAVAGE_DMA_AGP) {
779 if (dev_priv->cmd_dma->type != _DRM_AGP) {
780 DRM_ERROR("AGP command DMA region is not a "
781 "_DRM_AGP map!\n");
782 savage_do_cleanup_bci(dev);
783 return -EINVAL;
784 }
785 drm_core_ioremap(dev_priv->cmd_dma, dev);
786 if (!dev_priv->cmd_dma->handle) {
787 DRM_ERROR("failed to ioremap command "
788 "DMA region!\n");
789 savage_do_cleanup_bci(dev);
790 return -ENOMEM;
791 }
792 } else if (dev_priv->cmd_dma->type != _DRM_CONSISTENT) {
793 DRM_ERROR("PCI command DMA region is not a "
794 "_DRM_CONSISTENT map!\n");
795 savage_do_cleanup_bci(dev);
796 return -EINVAL;
797 }
798 } else {
799 dev_priv->cmd_dma = NULL;
800 }
801
802 dev_priv->dma_flush = savage_dma_flush;
803 if (!dev_priv->cmd_dma) {
804 DRM_DEBUG("falling back to faked command DMA.\n");
805 dev_priv->fake_dma.offset = 0;
806 dev_priv->fake_dma.size = SAVAGE_FAKE_DMA_SIZE;
807 dev_priv->fake_dma.type = _DRM_SHM;
808 dev_priv->fake_dma.handle = drm_alloc(SAVAGE_FAKE_DMA_SIZE,
809 DRM_MEM_DRIVER);
810 if (!dev_priv->fake_dma.handle) {
811 DRM_ERROR("could not allocate faked DMA buffer!\n");
812 savage_do_cleanup_bci(dev);
813 return -ENOMEM;
814 }
815 dev_priv->cmd_dma = &dev_priv->fake_dma;
816 dev_priv->dma_flush = savage_fake_dma_flush;
817 }
818
819 dev_priv->sarea_priv =
820 (drm_savage_sarea_t *)((uint8_t *)dev_priv->sarea->handle +
821 init->sarea_priv_offset);
822
823 /* setup bitmap descriptors */
824 {
825 unsigned int color_tile_format;
826 unsigned int depth_tile_format;
827 unsigned int front_stride, back_stride, depth_stride;
828 if (dev_priv->chipset <= S3_SAVAGE4) {
829 color_tile_format = dev_priv->fb_bpp == 16 ?
830 SAVAGE_BD_TILE_16BPP : SAVAGE_BD_TILE_32BPP;
831 depth_tile_format = dev_priv->depth_bpp == 16 ?
832 SAVAGE_BD_TILE_16BPP : SAVAGE_BD_TILE_32BPP;
833 } else {
834 color_tile_format = SAVAGE_BD_TILE_DEST;
835 depth_tile_format = SAVAGE_BD_TILE_DEST;
836 }
837 front_stride = dev_priv->front_pitch / (dev_priv->fb_bpp / 8);
838 back_stride = dev_priv->back_pitch / (dev_priv->fb_bpp / 8);
839 depth_stride =
840 dev_priv->depth_pitch / (dev_priv->depth_bpp / 8);
841
842 dev_priv->front_bd = front_stride | SAVAGE_BD_BW_DISABLE |
843 (dev_priv->fb_bpp << SAVAGE_BD_BPP_SHIFT) |
844 (color_tile_format << SAVAGE_BD_TILE_SHIFT);
845
846 dev_priv-> back_bd = back_stride | SAVAGE_BD_BW_DISABLE |
847 (dev_priv->fb_bpp << SAVAGE_BD_BPP_SHIFT) |
848 (color_tile_format << SAVAGE_BD_TILE_SHIFT);
849
850 dev_priv->depth_bd = depth_stride | SAVAGE_BD_BW_DISABLE |
851 (dev_priv->depth_bpp << SAVAGE_BD_BPP_SHIFT) |
852 (depth_tile_format << SAVAGE_BD_TILE_SHIFT);
853 }
854
855 /* setup status and bci ptr */
856 dev_priv->event_counter = 0;
857 dev_priv->event_wrap = 0;
858 dev_priv->bci_ptr = (volatile uint32_t *)
859 ((uint8_t *)dev_priv->mmio->handle + SAVAGE_BCI_OFFSET);
860 if (S3_SAVAGE3D_SERIES(dev_priv->chipset)) {
861 dev_priv->status_used_mask = SAVAGE_FIFO_USED_MASK_S3D;
862 } else {
863 dev_priv->status_used_mask = SAVAGE_FIFO_USED_MASK_S4;
864 }
865 if (dev_priv->status != NULL) {
866 dev_priv->status_ptr =
867 (volatile uint32_t *)dev_priv->status->handle;
868 dev_priv->wait_fifo = savage_bci_wait_fifo_shadow;
869 dev_priv->wait_evnt = savage_bci_wait_event_shadow;
870 dev_priv->status_ptr[1023] = dev_priv->event_counter;
871 } else {
872 dev_priv->status_ptr = NULL;
873 if (S3_SAVAGE3D_SERIES(dev_priv->chipset)) {
874 dev_priv->wait_fifo = savage_bci_wait_fifo_s3d;
875 } else {
876 dev_priv->wait_fifo = savage_bci_wait_fifo_s4;
877 }
878 dev_priv->wait_evnt = savage_bci_wait_event_reg;
879 }
880
881 /* cliprect functions */
882 if (S3_SAVAGE3D_SERIES(dev_priv->chipset))
883 dev_priv->emit_clip_rect = savage_emit_clip_rect_s3d;
884 else
885 dev_priv->emit_clip_rect = savage_emit_clip_rect_s4;
886
887 if (savage_freelist_init(dev) < 0) {
888 DRM_ERROR("could not initialize freelist\n");
889 savage_do_cleanup_bci(dev);
890 return -ENOMEM;
891 }
892
893 if (savage_dma_init(dev_priv) < 0) {
894 DRM_ERROR("could not initialize command DMA\n");
895 savage_do_cleanup_bci(dev);
896 return -ENOMEM;
897 }
898
899 return 0;
900 }
901
902 static int savage_do_cleanup_bci(struct drm_device *dev)
903 {
904 drm_savage_private_t *dev_priv = dev->dev_private;
905
906 if (dev_priv->cmd_dma == &dev_priv->fake_dma) {
907 if (dev_priv->fake_dma.handle)
908 drm_free(dev_priv->fake_dma.handle,
909 SAVAGE_FAKE_DMA_SIZE, DRM_MEM_DRIVER);
910 } else if (dev_priv->cmd_dma && dev_priv->cmd_dma->handle &&
911 dev_priv->cmd_dma->type == _DRM_AGP &&
912 dev_priv->dma_type == SAVAGE_DMA_AGP)
913 drm_core_ioremapfree(dev_priv->cmd_dma, dev);
914
915 if (dev_priv->dma_type == SAVAGE_DMA_AGP &&
916 dev->agp_buffer_map && dev->agp_buffer_map->handle) {
917 drm_core_ioremapfree(dev->agp_buffer_map, dev);
918 /* make sure the next instance (which may be running
919 * in PCI mode) doesn't try to use an old
920 * agp_buffer_map. */
921 dev->agp_buffer_map = NULL;
922 }
923
924 if (dev_priv->dma_pages)
925 drm_free(dev_priv->dma_pages,
926 sizeof(drm_savage_dma_page_t)*dev_priv->nr_dma_pages,
927 DRM_MEM_DRIVER);
928
929 return 0;
930 }
931
932 static int savage_bci_init(struct drm_device *dev, void *data, struct drm_file *file_priv)
933 {
934 drm_savage_init_t *init = data;
935
936 LOCK_TEST_WITH_RETURN(dev, file_priv);
937
938 switch (init->func) {
939 case SAVAGE_INIT_BCI:
940 return savage_do_init_bci(dev, init);
941 case SAVAGE_CLEANUP_BCI:
942 return savage_do_cleanup_bci(dev);
943 }
944
945 return -EINVAL;
946 }
947
948 static int savage_bci_event_emit(struct drm_device *dev, void *data, struct drm_file *file_priv)
949 {
950 drm_savage_private_t *dev_priv = dev->dev_private;
951 drm_savage_event_emit_t *event = data;
952
953 DRM_DEBUG("\n");
954
955 LOCK_TEST_WITH_RETURN(dev, file_priv);
956
957 event->count = savage_bci_emit_event(dev_priv, event->flags);
958 event->count |= dev_priv->event_wrap << 16;
959
960 return 0;
961 }
962
963 static int savage_bci_event_wait(struct drm_device *dev, void *data, struct drm_file *file_priv)
964 {
965 drm_savage_private_t *dev_priv = dev->dev_private;
966 drm_savage_event_wait_t *event = data;
967 unsigned int event_e, hw_e;
968 unsigned int event_w, hw_w;
969
970 DRM_DEBUG("\n");
971
972 UPDATE_EVENT_COUNTER();
973 if (dev_priv->status_ptr)
974 hw_e = dev_priv->status_ptr[1] & 0xffff;
975 else
976 hw_e = SAVAGE_READ(SAVAGE_STATUS_WORD1) & 0xffff;
977 hw_w = dev_priv->event_wrap;
978 if (hw_e > dev_priv->event_counter)
979 hw_w--; /* hardware hasn't passed the last wrap yet */
980
981 event_e = event->count & 0xffff;
982 event_w = event->count >> 16;
983
984 /* Don't need to wait if
985 * - event counter wrapped since the event was emitted or
986 * - the hardware has advanced up to or over the event to wait for.
987 */
988 if (event_w < hw_w || (event_w == hw_w && event_e <= hw_e))
989 return 0;
990 else
991 return dev_priv->wait_evnt(dev_priv, event_e);
992 }
993
994 /*
995 * DMA buffer management
996 */
997
998 static int savage_bci_get_buffers(struct drm_device *dev,
999 struct drm_file *file_priv,
1000 struct drm_dma *d)
1001 {
1002 struct drm_buf *buf;
1003 int i;
1004
1005 for (i = d->granted_count; i < d->request_count; i++) {
1006 buf = savage_freelist_get(dev);
1007 if (!buf)
1008 return -EAGAIN;
1009
1010 buf->file_priv = file_priv;
1011
1012 if (DRM_COPY_TO_USER(&d->request_indices[i],
1013 &buf->idx, sizeof(buf->idx)))
1014 return -EFAULT;
1015 if (DRM_COPY_TO_USER(&d->request_sizes[i],
1016 &buf->total, sizeof(buf->total)))
1017 return -EFAULT;
1018
1019 d->granted_count++;
1020 }
1021 return 0;
1022 }
1023
1024 int savage_bci_buffers(struct drm_device *dev, void *data, struct drm_file *file_priv)
1025 {
1026 struct drm_device_dma *dma = dev->dma;
1027 struct drm_dma *d = data;
1028 int ret = 0;
1029
1030 LOCK_TEST_WITH_RETURN(dev, file_priv);
1031
1032 /* Please don't send us buffers.
1033 */
1034 if (d->send_count != 0) {
1035 DRM_ERROR("Process %d trying to send %d buffers via drmDMA\n",
1036 DRM_CURRENTPID, d->send_count);
1037 return -EINVAL;
1038 }
1039
1040 /* We'll send you buffers.
1041 */
1042 if (d->request_count < 0 || d->request_count > dma->buf_count) {
1043 DRM_ERROR("Process %d trying to get %d buffers (of %d max)\n",
1044 DRM_CURRENTPID, d->request_count, dma->buf_count);
1045 return -EINVAL;
1046 }
1047
1048 d->granted_count = 0;
1049
1050 if (d->request_count) {
1051 ret = savage_bci_get_buffers(dev, file_priv, d);
1052 }
1053
1054 return ret;
1055 }
1056
1057 void savage_reclaim_buffers(struct drm_device *dev, struct drm_file *file_priv)
1058 {
1059 struct drm_device_dma *dma = dev->dma;
1060 drm_savage_private_t *dev_priv = dev->dev_private;
1061 int i;
1062
1063 if (!dma)
1064 return;
1065 if (!dev_priv)
1066 return;
1067 if (!dma->buflist)
1068 return;
1069
1070 for (i = 0; i < dma->buf_count; i++) {
1071 struct drm_buf *buf = dma->buflist[i];
1072 drm_savage_buf_priv_t *buf_priv = buf->dev_private;
1073
1074 if (buf->file_priv == file_priv && buf_priv &&
1075 buf_priv->next == NULL && buf_priv->prev == NULL) {
1076 uint16_t event;
1077 DRM_DEBUG("reclaimed from client\n");
1078 event = savage_bci_emit_event(dev_priv, SAVAGE_WAIT_3D);
1079 SET_AGE(&buf_priv->age, event, dev_priv->event_wrap);
1080 savage_freelist_put(dev, buf);
1081 }
1082 }
1083
1084 drm_core_reclaim_buffers(dev, file_priv);
1085 }
1086
1087 struct drm_ioctl_desc savage_ioctls[] = {
1088 DRM_IOCTL_DEF(DRM_SAVAGE_BCI_INIT, savage_bci_init, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
1089 DRM_IOCTL_DEF(DRM_SAVAGE_BCI_CMDBUF, savage_bci_cmdbuf, DRM_AUTH),
1090 DRM_IOCTL_DEF(DRM_SAVAGE_BCI_EVENT_EMIT, savage_bci_event_emit, DRM_AUTH),
1091 DRM_IOCTL_DEF(DRM_SAVAGE_BCI_EVENT_WAIT, savage_bci_event_wait, DRM_AUTH),
1092 };
1093
1094 int savage_max_ioctl = DRM_ARRAY_SIZE(savage_ioctls);
DragonFly BSD