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[dragonfly.git] / sys / dev / drm / mga_state.c
blob35508c57ae5405c18ddc8bccbb9c57c837b69b29
1 /* mga_state.c -- State support for MGA G200/G400 -*- linux-c -*-
2 * Created: Thu Jan 27 02:53:43 2000 by jhartmann@precisioninsight.com
3 */
4 /*
5 * Copyright 1999 Precision Insight, Inc., Cedar Park, Texas.
6 * Copyright 2000 VA Linux Systems, Inc., Sunnyvale, California.
7 * All Rights Reserved.
8 *
9 * Permission is hereby granted, free of charge, to any person obtaining a
10 * copy of this software and associated documentation files (the "Software"),
11 * to deal in the Software without restriction, including without limitation
12 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
13 * and/or sell copies of the Software, and to permit persons to whom the
14 * Software is furnished to do so, subject to the following conditions:
15 *
16 * The above copyright notice and this permission notice (including the next
17 * paragraph) shall be included in all copies or substantial portions of the
18 * Software.
19 *
20 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
21 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
22 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
23 * VA LINUX SYSTEMS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
24 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
25 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
26 * OTHER DEALINGS IN THE SOFTWARE.
27 *
28 * Authors:
29 * Jeff Hartmann <jhartmann@valinux.com>
30 * Keith Whitwell <keith@tungstengraphics.com>
31 *
32 * Rewritten by:
33 * Gareth Hughes <gareth@valinux.com>
34 *
35 * $DragonFly: src/sys/dev/drm/mga_state.c,v 1.1 2008/04/05 18:12:29 hasso Exp $
36 */
37
38 #include "drmP.h"
39 #include "drm.h"
40 #include "mga_drm.h"
41 #include "mga_drv.h"
42
43 /* ================================================================
44 * DMA hardware state programming functions
45 */
46
47 static void mga_emit_clip_rect(drm_mga_private_t * dev_priv,
48 struct drm_clip_rect * box)
49 {
50 drm_mga_sarea_t *sarea_priv = dev_priv->sarea_priv;
51 drm_mga_context_regs_t *ctx = &sarea_priv->context_state;
52 unsigned int pitch = dev_priv->front_pitch;
53 DMA_LOCALS;
54
55 BEGIN_DMA(2);
56
57 /* Force reset of DWGCTL on G400 (eliminates clip disable bit).
58 */
59 if (dev_priv->chipset >= MGA_CARD_TYPE_G400) {
60 DMA_BLOCK(MGA_DWGCTL, ctx->dwgctl,
61 MGA_LEN + MGA_EXEC, 0x80000000,
62 MGA_DWGCTL, ctx->dwgctl,
63 MGA_LEN + MGA_EXEC, 0x80000000);
64 }
65 DMA_BLOCK(MGA_DMAPAD, 0x00000000,
66 MGA_CXBNDRY, ((box->x2 - 1) << 16) | box->x1,
67 MGA_YTOP, box->y1 * pitch, MGA_YBOT, (box->y2 - 1) * pitch);
68
69 ADVANCE_DMA();
70 }
71
72 static __inline__ void mga_g200_emit_context(drm_mga_private_t * dev_priv)
73 {
74 drm_mga_sarea_t *sarea_priv = dev_priv->sarea_priv;
75 drm_mga_context_regs_t *ctx = &sarea_priv->context_state;
76 DMA_LOCALS;
77
78 BEGIN_DMA(3);
79
80 DMA_BLOCK(MGA_DSTORG, ctx->dstorg,
81 MGA_MACCESS, ctx->maccess,
82 MGA_PLNWT, ctx->plnwt, MGA_DWGCTL, ctx->dwgctl);
83
84 DMA_BLOCK(MGA_ALPHACTRL, ctx->alphactrl,
85 MGA_FOGCOL, ctx->fogcolor,
86 MGA_WFLAG, ctx->wflag, MGA_ZORG, dev_priv->depth_offset);
87
88 DMA_BLOCK(MGA_FCOL, ctx->fcol,
89 MGA_DMAPAD, 0x00000000,
90 MGA_DMAPAD, 0x00000000, MGA_DMAPAD, 0x00000000);
91
92 ADVANCE_DMA();
93 }
94
95 static __inline__ void mga_g400_emit_context(drm_mga_private_t * dev_priv)
96 {
97 drm_mga_sarea_t *sarea_priv = dev_priv->sarea_priv;
98 drm_mga_context_regs_t *ctx = &sarea_priv->context_state;
99 DMA_LOCALS;
100
101 BEGIN_DMA(4);
102
103 DMA_BLOCK(MGA_DSTORG, ctx->dstorg,
104 MGA_MACCESS, ctx->maccess,
105 MGA_PLNWT, ctx->plnwt,
106 MGA_DWGCTL, ctx->dwgctl);
107
108 DMA_BLOCK(MGA_ALPHACTRL, ctx->alphactrl,
109 MGA_FOGCOL, ctx->fogcolor,
110 MGA_WFLAG, ctx->wflag,
111 MGA_ZORG, dev_priv->depth_offset);
112
113 DMA_BLOCK(MGA_WFLAG1, ctx->wflag,
114 MGA_TDUALSTAGE0, ctx->tdualstage0,
115 MGA_TDUALSTAGE1, ctx->tdualstage1,
116 MGA_FCOL, ctx->fcol);
117
118 DMA_BLOCK(MGA_STENCIL, ctx->stencil,
119 MGA_STENCILCTL, ctx->stencilctl,
120 MGA_DMAPAD, 0x00000000,
121 MGA_DMAPAD, 0x00000000);
122
123 ADVANCE_DMA();
124 }
125
126 static __inline__ void mga_g200_emit_tex0(drm_mga_private_t * dev_priv)
127 {
128 drm_mga_sarea_t *sarea_priv = dev_priv->sarea_priv;
129 drm_mga_texture_regs_t *tex = &sarea_priv->tex_state[0];
130 DMA_LOCALS;
131
132 BEGIN_DMA(4);
133
134 DMA_BLOCK(MGA_TEXCTL2, tex->texctl2,
135 MGA_TEXCTL, tex->texctl,
136 MGA_TEXFILTER, tex->texfilter,
137 MGA_TEXBORDERCOL, tex->texbordercol);
138
139 DMA_BLOCK(MGA_TEXORG, tex->texorg,
140 MGA_TEXORG1, tex->texorg1,
141 MGA_TEXORG2, tex->texorg2,
142 MGA_TEXORG3, tex->texorg3);
143
144 DMA_BLOCK(MGA_TEXORG4, tex->texorg4,
145 MGA_TEXWIDTH, tex->texwidth,
146 MGA_TEXHEIGHT, tex->texheight,
147 MGA_WR24, tex->texwidth);
148
149 DMA_BLOCK(MGA_WR34, tex->texheight,
150 MGA_TEXTRANS, 0x0000ffff,
151 MGA_TEXTRANSHIGH, 0x0000ffff,
152 MGA_DMAPAD, 0x00000000);
153
154 ADVANCE_DMA();
155 }
156
157 static __inline__ void mga_g400_emit_tex0(drm_mga_private_t * dev_priv)
158 {
159 drm_mga_sarea_t *sarea_priv = dev_priv->sarea_priv;
160 drm_mga_texture_regs_t *tex = &sarea_priv->tex_state[0];
161 DMA_LOCALS;
162
163 /* printk("mga_g400_emit_tex0 %x %x %x\n", tex->texorg, */
164 /* tex->texctl, tex->texctl2); */
165
166 BEGIN_DMA(6);
167
168 DMA_BLOCK(MGA_TEXCTL2, tex->texctl2 | MGA_G400_TC2_MAGIC,
169 MGA_TEXCTL, tex->texctl,
170 MGA_TEXFILTER, tex->texfilter,
171 MGA_TEXBORDERCOL, tex->texbordercol);
172
173 DMA_BLOCK(MGA_TEXORG, tex->texorg,
174 MGA_TEXORG1, tex->texorg1,
175 MGA_TEXORG2, tex->texorg2,
176 MGA_TEXORG3, tex->texorg3);
177
178 DMA_BLOCK(MGA_TEXORG4, tex->texorg4,
179 MGA_TEXWIDTH, tex->texwidth,
180 MGA_TEXHEIGHT, tex->texheight,
181 MGA_WR49, 0x00000000);
182
183 DMA_BLOCK(MGA_WR57, 0x00000000,
184 MGA_WR53, 0x00000000,
185 MGA_WR61, 0x00000000,
186 MGA_WR52, MGA_G400_WR_MAGIC);
187
188 DMA_BLOCK(MGA_WR60, MGA_G400_WR_MAGIC,
189 MGA_WR54, tex->texwidth | MGA_G400_WR_MAGIC,
190 MGA_WR62, tex->texheight | MGA_G400_WR_MAGIC,
191 MGA_DMAPAD, 0x00000000);
192
193 DMA_BLOCK(MGA_DMAPAD, 0x00000000,
194 MGA_DMAPAD, 0x00000000,
195 MGA_TEXTRANS, 0x0000ffff,
196 MGA_TEXTRANSHIGH, 0x0000ffff);
197
198 ADVANCE_DMA();
199 }
200
201 static __inline__ void mga_g400_emit_tex1(drm_mga_private_t * dev_priv)
202 {
203 drm_mga_sarea_t *sarea_priv = dev_priv->sarea_priv;
204 drm_mga_texture_regs_t *tex = &sarea_priv->tex_state[1];
205 DMA_LOCALS;
206
207 /* printk("mga_g400_emit_tex1 %x %x %x\n", tex->texorg, */
208 /* tex->texctl, tex->texctl2); */
209
210 BEGIN_DMA(5);
211
212 DMA_BLOCK(MGA_TEXCTL2, (tex->texctl2 |
213 MGA_MAP1_ENABLE |
214 MGA_G400_TC2_MAGIC),
215 MGA_TEXCTL, tex->texctl,
216 MGA_TEXFILTER, tex->texfilter,
217 MGA_TEXBORDERCOL, tex->texbordercol);
218
219 DMA_BLOCK(MGA_TEXORG, tex->texorg,
220 MGA_TEXORG1, tex->texorg1,
221 MGA_TEXORG2, tex->texorg2,
222 MGA_TEXORG3, tex->texorg3);
223
224 DMA_BLOCK(MGA_TEXORG4, tex->texorg4,
225 MGA_TEXWIDTH, tex->texwidth,
226 MGA_TEXHEIGHT, tex->texheight,
227 MGA_WR49, 0x00000000);
228
229 DMA_BLOCK(MGA_WR57, 0x00000000,
230 MGA_WR53, 0x00000000,
231 MGA_WR61, 0x00000000,
232 MGA_WR52, tex->texwidth | MGA_G400_WR_MAGIC);
233
234 DMA_BLOCK(MGA_WR60, tex->texheight | MGA_G400_WR_MAGIC,
235 MGA_TEXTRANS, 0x0000ffff,
236 MGA_TEXTRANSHIGH, 0x0000ffff,
237 MGA_TEXCTL2, tex->texctl2 | MGA_G400_TC2_MAGIC);
238
239 ADVANCE_DMA();
240 }
241
242 static __inline__ void mga_g200_emit_pipe(drm_mga_private_t * dev_priv)
243 {
244 drm_mga_sarea_t *sarea_priv = dev_priv->sarea_priv;
245 unsigned int pipe = sarea_priv->warp_pipe;
246 DMA_LOCALS;
247
248 BEGIN_DMA(3);
249
250 DMA_BLOCK(MGA_WIADDR, MGA_WMODE_SUSPEND,
251 MGA_WVRTXSZ, 0x00000007,
252 MGA_WFLAG, 0x00000000,
253 MGA_WR24, 0x00000000);
254
255 DMA_BLOCK(MGA_WR25, 0x00000100,
256 MGA_WR34, 0x00000000,
257 MGA_WR42, 0x0000ffff,
258 MGA_WR60, 0x0000ffff);
259
260 /* Padding required to to hardware bug.
261 */
262 DMA_BLOCK(MGA_DMAPAD, 0xffffffff,
263 MGA_DMAPAD, 0xffffffff,
264 MGA_DMAPAD, 0xffffffff,
265 MGA_WIADDR, (dev_priv->warp_pipe_phys[pipe] |
266 MGA_WMODE_START | dev_priv->wagp_enable));
267
268 ADVANCE_DMA();
269 }
270
271 static __inline__ void mga_g400_emit_pipe(drm_mga_private_t * dev_priv)
272 {
273 drm_mga_sarea_t *sarea_priv = dev_priv->sarea_priv;
274 unsigned int pipe = sarea_priv->warp_pipe;
275 DMA_LOCALS;
276
277 /* printk("mga_g400_emit_pipe %x\n", pipe); */
278
279 BEGIN_DMA(10);
280
281 DMA_BLOCK(MGA_WIADDR2, MGA_WMODE_SUSPEND,
282 MGA_DMAPAD, 0x00000000,
283 MGA_DMAPAD, 0x00000000,
284 MGA_DMAPAD, 0x00000000);
285
286 if (pipe & MGA_T2) {
287 DMA_BLOCK(MGA_WVRTXSZ, 0x00001e09,
288 MGA_DMAPAD, 0x00000000,
289 MGA_DMAPAD, 0x00000000,
290 MGA_DMAPAD, 0x00000000);
291
292 DMA_BLOCK(MGA_WACCEPTSEQ, 0x00000000,
293 MGA_WACCEPTSEQ, 0x00000000,
294 MGA_WACCEPTSEQ, 0x00000000,
295 MGA_WACCEPTSEQ, 0x1e000000);
296 } else {
297 if (dev_priv->warp_pipe & MGA_T2) {
298 /* Flush the WARP pipe */
299 DMA_BLOCK(MGA_YDST, 0x00000000,
300 MGA_FXLEFT, 0x00000000,
301 MGA_FXRIGHT, 0x00000001,
302 MGA_DWGCTL, MGA_DWGCTL_FLUSH);
303
304 DMA_BLOCK(MGA_LEN + MGA_EXEC, 0x00000001,
305 MGA_DWGSYNC, 0x00007000,
306 MGA_TEXCTL2, MGA_G400_TC2_MAGIC,
307 MGA_LEN + MGA_EXEC, 0x00000000);
308
309 DMA_BLOCK(MGA_TEXCTL2, (MGA_DUALTEX |
310 MGA_G400_TC2_MAGIC),
311 MGA_LEN + MGA_EXEC, 0x00000000,
312 MGA_TEXCTL2, MGA_G400_TC2_MAGIC,
313 MGA_DMAPAD, 0x00000000);
314 }
315
316 DMA_BLOCK(MGA_WVRTXSZ, 0x00001807,
317 MGA_DMAPAD, 0x00000000,
318 MGA_DMAPAD, 0x00000000,
319 MGA_DMAPAD, 0x00000000);
320
321 DMA_BLOCK(MGA_WACCEPTSEQ, 0x00000000,
322 MGA_WACCEPTSEQ, 0x00000000,
323 MGA_WACCEPTSEQ, 0x00000000,
324 MGA_WACCEPTSEQ, 0x18000000);
325 }
326
327 DMA_BLOCK(MGA_WFLAG, 0x00000000,
328 MGA_WFLAG1, 0x00000000,
329 MGA_WR56, MGA_G400_WR56_MAGIC,
330 MGA_DMAPAD, 0x00000000);
331
332 DMA_BLOCK(MGA_WR49, 0x00000000, /* tex0 */
333 MGA_WR57, 0x00000000, /* tex0 */
334 MGA_WR53, 0x00000000, /* tex1 */
335 MGA_WR61, 0x00000000); /* tex1 */
336
337 DMA_BLOCK(MGA_WR54, MGA_G400_WR_MAGIC, /* tex0 width */
338 MGA_WR62, MGA_G400_WR_MAGIC, /* tex0 height */
339 MGA_WR52, MGA_G400_WR_MAGIC, /* tex1 width */
340 MGA_WR60, MGA_G400_WR_MAGIC); /* tex1 height */
341
342 /* Padding required to to hardware bug */
343 DMA_BLOCK(MGA_DMAPAD, 0xffffffff,
344 MGA_DMAPAD, 0xffffffff,
345 MGA_DMAPAD, 0xffffffff,
346 MGA_WIADDR2, (dev_priv->warp_pipe_phys[pipe] |
347 MGA_WMODE_START | dev_priv->wagp_enable));
348
349 ADVANCE_DMA();
350 }
351
352 static void mga_g200_emit_state(drm_mga_private_t * dev_priv)
353 {
354 drm_mga_sarea_t *sarea_priv = dev_priv->sarea_priv;
355 unsigned int dirty = sarea_priv->dirty;
356
357 if (sarea_priv->warp_pipe != dev_priv->warp_pipe) {
358 mga_g200_emit_pipe(dev_priv);
359 dev_priv->warp_pipe = sarea_priv->warp_pipe;
360 }
361
362 if (dirty & MGA_UPLOAD_CONTEXT) {
363 mga_g200_emit_context(dev_priv);
364 sarea_priv->dirty &= ~MGA_UPLOAD_CONTEXT;
365 }
366
367 if (dirty & MGA_UPLOAD_TEX0) {
368 mga_g200_emit_tex0(dev_priv);
369 sarea_priv->dirty &= ~MGA_UPLOAD_TEX0;
370 }
371 }
372
373 static void mga_g400_emit_state(drm_mga_private_t * dev_priv)
374 {
375 drm_mga_sarea_t *sarea_priv = dev_priv->sarea_priv;
376 unsigned int dirty = sarea_priv->dirty;
377 int multitex = sarea_priv->warp_pipe & MGA_T2;
378
379 if (sarea_priv->warp_pipe != dev_priv->warp_pipe) {
380 mga_g400_emit_pipe(dev_priv);
381 dev_priv->warp_pipe = sarea_priv->warp_pipe;
382 }
383
384 if (dirty & MGA_UPLOAD_CONTEXT) {
385 mga_g400_emit_context(dev_priv);
386 sarea_priv->dirty &= ~MGA_UPLOAD_CONTEXT;
387 }
388
389 if (dirty & MGA_UPLOAD_TEX0) {
390 mga_g400_emit_tex0(dev_priv);
391 sarea_priv->dirty &= ~MGA_UPLOAD_TEX0;
392 }
393
394 if ((dirty & MGA_UPLOAD_TEX1) && multitex) {
395 mga_g400_emit_tex1(dev_priv);
396 sarea_priv->dirty &= ~MGA_UPLOAD_TEX1;
397 }
398 }
399
400 /* ================================================================
401 * SAREA state verification
402 */
403
404 /* Disallow all write destinations except the front and backbuffer.
405 */
406 static int mga_verify_context(drm_mga_private_t * dev_priv)
407 {
408 drm_mga_sarea_t *sarea_priv = dev_priv->sarea_priv;
409 drm_mga_context_regs_t *ctx = &sarea_priv->context_state;
410
411 if (ctx->dstorg != dev_priv->front_offset &&
412 ctx->dstorg != dev_priv->back_offset) {
413 DRM_ERROR("*** bad DSTORG: %x (front %x, back %x)\n\n",
414 ctx->dstorg, dev_priv->front_offset,
415 dev_priv->back_offset);
416 ctx->dstorg = 0;
417 return -EINVAL;
418 }
419
420 return 0;
421 }
422
423 /* Disallow texture reads from PCI space.
424 */
425 static int mga_verify_tex(drm_mga_private_t * dev_priv, int unit)
426 {
427 drm_mga_sarea_t *sarea_priv = dev_priv->sarea_priv;
428 drm_mga_texture_regs_t *tex = &sarea_priv->tex_state[unit];
429 unsigned int org;
430
431 org = tex->texorg & (MGA_TEXORGMAP_MASK | MGA_TEXORGACC_MASK);
432
433 if (org == (MGA_TEXORGMAP_SYSMEM | MGA_TEXORGACC_PCI)) {
434 DRM_ERROR("*** bad TEXORG: 0x%x, unit %d\n", tex->texorg, unit);
435 tex->texorg = 0;
436 return -EINVAL;
437 }
438
439 return 0;
440 }
441
442 static int mga_verify_state(drm_mga_private_t * dev_priv)
443 {
444 drm_mga_sarea_t *sarea_priv = dev_priv->sarea_priv;
445 unsigned int dirty = sarea_priv->dirty;
446 int ret = 0;
447
448 if (sarea_priv->nbox > MGA_NR_SAREA_CLIPRECTS)
449 sarea_priv->nbox = MGA_NR_SAREA_CLIPRECTS;
450
451 if (dirty & MGA_UPLOAD_CONTEXT)
452 ret |= mga_verify_context(dev_priv);
453
454 if (dirty & MGA_UPLOAD_TEX0)
455 ret |= mga_verify_tex(dev_priv, 0);
456
457 if (dev_priv->chipset >= MGA_CARD_TYPE_G400) {
458 if (dirty & MGA_UPLOAD_TEX1)
459 ret |= mga_verify_tex(dev_priv, 1);
460
461 if (dirty & MGA_UPLOAD_PIPE)
462 ret |= (sarea_priv->warp_pipe > MGA_MAX_G400_PIPES);
463 } else {
464 if (dirty & MGA_UPLOAD_PIPE)
465 ret |= (sarea_priv->warp_pipe > MGA_MAX_G200_PIPES);
466 }
467
468 return (ret == 0);
469 }
470
471 static int mga_verify_iload(drm_mga_private_t * dev_priv,
472 unsigned int dstorg, unsigned int length)
473 {
474 if (dstorg < dev_priv->texture_offset ||
475 dstorg + length > (dev_priv->texture_offset +
476 dev_priv->texture_size)) {
477 DRM_ERROR("*** bad iload DSTORG: 0x%x\n", dstorg);
478 return -EINVAL;
479 }
480
481 if (length & MGA_ILOAD_MASK) {
482 DRM_ERROR("*** bad iload length: 0x%x\n",
483 length & MGA_ILOAD_MASK);
484 return -EINVAL;
485 }
486
487 return 0;
488 }
489
490 static int mga_verify_blit(drm_mga_private_t * dev_priv,
491 unsigned int srcorg, unsigned int dstorg)
492 {
493 if ((srcorg & 0x3) == (MGA_SRCACC_PCI | MGA_SRCMAP_SYSMEM) ||
494 (dstorg & 0x3) == (MGA_SRCACC_PCI | MGA_SRCMAP_SYSMEM)) {
495 DRM_ERROR("*** bad blit: src=0x%x dst=0x%x\n", srcorg, dstorg);
496 return -EINVAL;
497 }
498 return 0;
499 }
500
501 /* ================================================================
502 *
503 */
504
505 static void mga_dma_dispatch_clear(struct drm_device * dev, drm_mga_clear_t * clear)
506 {
507 drm_mga_private_t *dev_priv = dev->dev_private;
508 drm_mga_sarea_t *sarea_priv = dev_priv->sarea_priv;
509 drm_mga_context_regs_t *ctx = &sarea_priv->context_state;
510 struct drm_clip_rect *pbox = sarea_priv->boxes;
511 int nbox = sarea_priv->nbox;
512 int i;
513 DMA_LOCALS;
514 DRM_DEBUG("\n");
515
516 BEGIN_DMA(1);
517
518 DMA_BLOCK(MGA_DMAPAD, 0x00000000,
519 MGA_DMAPAD, 0x00000000,
520 MGA_DWGSYNC, 0x00007100,
521 MGA_DWGSYNC, 0x00007000);
522
523 ADVANCE_DMA();
524
525 for (i = 0; i < nbox; i++) {
526 struct drm_clip_rect *box = &pbox[i];
527 u32 height = box->y2 - box->y1;
528
529 DRM_DEBUG(" from=%d,%d to=%d,%d\n",
530 box->x1, box->y1, box->x2, box->y2);
531
532 if (clear->flags & MGA_FRONT) {
533 BEGIN_DMA(2);
534
535 DMA_BLOCK(MGA_DMAPAD, 0x00000000,
536 MGA_PLNWT, clear->color_mask,
537 MGA_YDSTLEN, (box->y1 << 16) | height,
538 MGA_FXBNDRY, (box->x2 << 16) | box->x1);
539
540 DMA_BLOCK(MGA_DMAPAD, 0x00000000,
541 MGA_FCOL, clear->clear_color,
542 MGA_DSTORG, dev_priv->front_offset,
543 MGA_DWGCTL + MGA_EXEC, dev_priv->clear_cmd);
544
545 ADVANCE_DMA();
546 }
547
548 if (clear->flags & MGA_BACK) {
549 BEGIN_DMA(2);
550
551 DMA_BLOCK(MGA_DMAPAD, 0x00000000,
552 MGA_PLNWT, clear->color_mask,
553 MGA_YDSTLEN, (box->y1 << 16) | height,
554 MGA_FXBNDRY, (box->x2 << 16) | box->x1);
555
556 DMA_BLOCK(MGA_DMAPAD, 0x00000000,
557 MGA_FCOL, clear->clear_color,
558 MGA_DSTORG, dev_priv->back_offset,
559 MGA_DWGCTL + MGA_EXEC, dev_priv->clear_cmd);
560
561 ADVANCE_DMA();
562 }
563
564 if (clear->flags & MGA_DEPTH) {
565 BEGIN_DMA(2);
566
567 DMA_BLOCK(MGA_DMAPAD, 0x00000000,
568 MGA_PLNWT, clear->depth_mask,
569 MGA_YDSTLEN, (box->y1 << 16) | height,
570 MGA_FXBNDRY, (box->x2 << 16) | box->x1);
571
572 DMA_BLOCK(MGA_DMAPAD, 0x00000000,
573 MGA_FCOL, clear->clear_depth,
574 MGA_DSTORG, dev_priv->depth_offset,
575 MGA_DWGCTL + MGA_EXEC, dev_priv->clear_cmd);
576
577 ADVANCE_DMA();
578 }
579
580 }
581
582 BEGIN_DMA(1);
583
584 /* Force reset of DWGCTL */
585 DMA_BLOCK(MGA_DMAPAD, 0x00000000,
586 MGA_DMAPAD, 0x00000000,
587 MGA_PLNWT, ctx->plnwt,
588 MGA_DWGCTL, ctx->dwgctl);
589
590 ADVANCE_DMA();
591
592 FLUSH_DMA();
593 }
594
595 static void mga_dma_dispatch_swap(struct drm_device * dev)
596 {
597 drm_mga_private_t *dev_priv = dev->dev_private;
598 drm_mga_sarea_t *sarea_priv = dev_priv->sarea_priv;
599 drm_mga_context_regs_t *ctx = &sarea_priv->context_state;
600 struct drm_clip_rect *pbox = sarea_priv->boxes;
601 int nbox = sarea_priv->nbox;
602 int i;
603 DMA_LOCALS;
604 DRM_DEBUG("\n");
605
606 sarea_priv->last_frame.head = dev_priv->prim.tail;
607 sarea_priv->last_frame.wrap = dev_priv->prim.last_wrap;
608
609 BEGIN_DMA(4 + nbox);
610
611 DMA_BLOCK(MGA_DMAPAD, 0x00000000,
612 MGA_DMAPAD, 0x00000000,
613 MGA_DWGSYNC, 0x00007100,
614 MGA_DWGSYNC, 0x00007000);
615
616 DMA_BLOCK(MGA_DSTORG, dev_priv->front_offset,
617 MGA_MACCESS, dev_priv->maccess,
618 MGA_SRCORG, dev_priv->back_offset,
619 MGA_AR5, dev_priv->front_pitch);
620
621 DMA_BLOCK(MGA_DMAPAD, 0x00000000,
622 MGA_DMAPAD, 0x00000000,
623 MGA_PLNWT, 0xffffffff,
624 MGA_DWGCTL, MGA_DWGCTL_COPY);
625
626 for (i = 0; i < nbox; i++) {
627 struct drm_clip_rect *box = &pbox[i];
628 u32 height = box->y2 - box->y1;
629 u32 start = box->y1 * dev_priv->front_pitch;
630
631 DRM_DEBUG(" from=%d,%d to=%d,%d\n",
632 box->x1, box->y1, box->x2, box->y2);
633
634 DMA_BLOCK(MGA_AR0, start + box->x2 - 1,
635 MGA_AR3, start + box->x1,
636 MGA_FXBNDRY, ((box->x2 - 1) << 16) | box->x1,
637 MGA_YDSTLEN + MGA_EXEC, (box->y1 << 16) | height);
638 }
639
640 DMA_BLOCK(MGA_DMAPAD, 0x00000000,
641 MGA_PLNWT, ctx->plnwt,
642 MGA_SRCORG, dev_priv->front_offset,
643 MGA_DWGCTL, ctx->dwgctl);
644
645 ADVANCE_DMA();
646
647 FLUSH_DMA();
648
649 DRM_DEBUG("... done.\n");
650 }
651
652 static void mga_dma_dispatch_vertex(struct drm_device * dev, struct drm_buf * buf)
653 {
654 drm_mga_private_t *dev_priv = dev->dev_private;
655 drm_mga_buf_priv_t *buf_priv = buf->dev_private;
656 drm_mga_sarea_t *sarea_priv = dev_priv->sarea_priv;
657 u32 address = (u32) buf->bus_address;
658 u32 length = (u32) buf->used;
659 int i = 0;
660 DMA_LOCALS;
661 DRM_DEBUG("buf=%d used=%d\n", buf->idx, buf->used);
662
663 if (buf->used) {
664 buf_priv->dispatched = 1;
665
666 MGA_EMIT_STATE(dev_priv, sarea_priv->dirty);
667
668 do {
669 if (i < sarea_priv->nbox) {
670 mga_emit_clip_rect(dev_priv,
671 &sarea_priv->boxes[i]);
672 }
673
674 BEGIN_DMA(1);
675
676 DMA_BLOCK(MGA_DMAPAD, 0x00000000,
677 MGA_DMAPAD, 0x00000000,
678 MGA_SECADDRESS, (address |
679 MGA_DMA_VERTEX),
680 MGA_SECEND, ((address + length) |
681 dev_priv->dma_access));
682
683 ADVANCE_DMA();
684 } while (++i < sarea_priv->nbox);
685 }
686
687 if (buf_priv->discard) {
688 AGE_BUFFER(buf_priv);
689 buf->pending = 0;
690 buf->used = 0;
691 buf_priv->dispatched = 0;
692
693 mga_freelist_put(dev, buf);
694 }
695
696 FLUSH_DMA();
697 }
698
699 static void mga_dma_dispatch_indices(struct drm_device * dev, struct drm_buf * buf,
700 unsigned int start, unsigned int end)
701 {
702 drm_mga_private_t *dev_priv = dev->dev_private;
703 drm_mga_buf_priv_t *buf_priv = buf->dev_private;
704 drm_mga_sarea_t *sarea_priv = dev_priv->sarea_priv;
705 u32 address = (u32) buf->bus_address;
706 int i = 0;
707 DMA_LOCALS;
708 DRM_DEBUG("buf=%d start=%d end=%d\n", buf->idx, start, end);
709
710 if (start != end) {
711 buf_priv->dispatched = 1;
712
713 MGA_EMIT_STATE(dev_priv, sarea_priv->dirty);
714
715 do {
716 if (i < sarea_priv->nbox) {
717 mga_emit_clip_rect(dev_priv,
718 &sarea_priv->boxes[i]);
719 }
720
721 BEGIN_DMA(1);
722
723 DMA_BLOCK(MGA_DMAPAD, 0x00000000,
724 MGA_DMAPAD, 0x00000000,
725 MGA_SETUPADDRESS, address + start,
726 MGA_SETUPEND, ((address + end) |
727 dev_priv->dma_access));
728
729 ADVANCE_DMA();
730 } while (++i < sarea_priv->nbox);
731 }
732
733 if (buf_priv->discard) {
734 AGE_BUFFER(buf_priv);
735 buf->pending = 0;
736 buf->used = 0;
737 buf_priv->dispatched = 0;
738
739 mga_freelist_put(dev, buf);
740 }
741
742 FLUSH_DMA();
743 }
744
745 /* This copies a 64 byte aligned agp region to the frambuffer with a
746 * standard blit, the ioctl needs to do checking.
747 */
748 static void mga_dma_dispatch_iload(struct drm_device * dev, struct drm_buf * buf,
749 unsigned int dstorg, unsigned int length)
750 {
751 drm_mga_private_t *dev_priv = dev->dev_private;
752 drm_mga_buf_priv_t *buf_priv = buf->dev_private;
753 drm_mga_context_regs_t *ctx = &dev_priv->sarea_priv->context_state;
754 u32 srcorg = buf->bus_address | dev_priv->dma_access | MGA_SRCMAP_SYSMEM;
755 u32 y2;
756 DMA_LOCALS;
757 DRM_DEBUG("buf=%d used=%d\n", buf->idx, buf->used);
758
759 y2 = length / 64;
760
761 BEGIN_DMA(5);
762
763 DMA_BLOCK(MGA_DMAPAD, 0x00000000,
764 MGA_DMAPAD, 0x00000000,
765 MGA_DWGSYNC, 0x00007100,
766 MGA_DWGSYNC, 0x00007000);
767
768 DMA_BLOCK(MGA_DSTORG, dstorg,
769 MGA_MACCESS, 0x00000000,
770 MGA_SRCORG, srcorg,
771 MGA_AR5, 64);
772
773 DMA_BLOCK(MGA_PITCH, 64,
774 MGA_PLNWT, 0xffffffff,
775 MGA_DMAPAD, 0x00000000,
776 MGA_DWGCTL, MGA_DWGCTL_COPY);
777
778 DMA_BLOCK(MGA_AR0, 63,
779 MGA_AR3, 0,
780 MGA_FXBNDRY, (63 << 16) | 0,
781 MGA_YDSTLEN + MGA_EXEC, y2);
782
783 DMA_BLOCK(MGA_PLNWT, ctx->plnwt,
784 MGA_SRCORG, dev_priv->front_offset,
785 MGA_PITCH, dev_priv->front_pitch,
786 MGA_DWGSYNC, 0x00007000);
787
788 ADVANCE_DMA();
789
790 AGE_BUFFER(buf_priv);
791
792 buf->pending = 0;
793 buf->used = 0;
794 buf_priv->dispatched = 0;
795
796 mga_freelist_put(dev, buf);
797
798 FLUSH_DMA();
799 }
800
801 static void mga_dma_dispatch_blit(struct drm_device * dev, drm_mga_blit_t * blit)
802 {
803 drm_mga_private_t *dev_priv = dev->dev_private;
804 drm_mga_sarea_t *sarea_priv = dev_priv->sarea_priv;
805 drm_mga_context_regs_t *ctx = &sarea_priv->context_state;
806 struct drm_clip_rect *pbox = sarea_priv->boxes;
807 int nbox = sarea_priv->nbox;
808 u32 scandir = 0, i;
809 DMA_LOCALS;
810 DRM_DEBUG("\n");
811
812 BEGIN_DMA(4 + nbox);
813
814 DMA_BLOCK(MGA_DMAPAD, 0x00000000,
815 MGA_DMAPAD, 0x00000000,
816 MGA_DWGSYNC, 0x00007100,
817 MGA_DWGSYNC, 0x00007000);
818
819 DMA_BLOCK(MGA_DWGCTL, MGA_DWGCTL_COPY,
820 MGA_PLNWT, blit->planemask,
821 MGA_SRCORG, blit->srcorg,
822 MGA_DSTORG, blit->dstorg);
823
824 DMA_BLOCK(MGA_SGN, scandir,
825 MGA_MACCESS, dev_priv->maccess,
826 MGA_AR5, blit->ydir * blit->src_pitch,
827 MGA_PITCH, blit->dst_pitch);
828
829 for (i = 0; i < nbox; i++) {
830 int srcx = pbox[i].x1 + blit->delta_sx;
831 int srcy = pbox[i].y1 + blit->delta_sy;
832 int dstx = pbox[i].x1 + blit->delta_dx;
833 int dsty = pbox[i].y1 + blit->delta_dy;
834 int h = pbox[i].y2 - pbox[i].y1;
835 int w = pbox[i].x2 - pbox[i].x1 - 1;
836 int start;
837
838 if (blit->ydir == -1) {
839 srcy = blit->height - srcy - 1;
840 }
841
842 start = srcy * blit->src_pitch + srcx;
843
844 DMA_BLOCK(MGA_AR0, start + w,
845 MGA_AR3, start,
846 MGA_FXBNDRY, ((dstx + w) << 16) | (dstx & 0xffff),
847 MGA_YDSTLEN + MGA_EXEC, (dsty << 16) | h);
848 }
849
850 /* Do something to flush AGP?
851 */
852
853 /* Force reset of DWGCTL */
854 DMA_BLOCK(MGA_DMAPAD, 0x00000000,
855 MGA_PLNWT, ctx->plnwt,
856 MGA_PITCH, dev_priv->front_pitch,
857 MGA_DWGCTL, ctx->dwgctl);
858
859 ADVANCE_DMA();
860 }
861
862 /* ================================================================
863 *
864 */
865
866 static int mga_dma_clear(struct drm_device *dev, void *data, struct drm_file *file_priv)
867 {
868 drm_mga_private_t *dev_priv = dev->dev_private;
869 drm_mga_sarea_t *sarea_priv = dev_priv->sarea_priv;
870 drm_mga_clear_t *clear = data;
871
872 LOCK_TEST_WITH_RETURN(dev, file_priv);
873
874 if (sarea_priv->nbox > MGA_NR_SAREA_CLIPRECTS)
875 sarea_priv->nbox = MGA_NR_SAREA_CLIPRECTS;
876
877 WRAP_TEST_WITH_RETURN(dev_priv);
878
879 mga_dma_dispatch_clear(dev, clear);
880
881 /* Make sure we restore the 3D state next time.
882 */
883 dev_priv->sarea_priv->dirty |= MGA_UPLOAD_CONTEXT;
884
885 return 0;
886 }
887
888 static int mga_dma_swap(struct drm_device *dev, void *data, struct drm_file *file_priv)
889 {
890 drm_mga_private_t *dev_priv = dev->dev_private;
891 drm_mga_sarea_t *sarea_priv = dev_priv->sarea_priv;
892
893 LOCK_TEST_WITH_RETURN(dev, file_priv);
894
895 if (sarea_priv->nbox > MGA_NR_SAREA_CLIPRECTS)
896 sarea_priv->nbox = MGA_NR_SAREA_CLIPRECTS;
897
898 WRAP_TEST_WITH_RETURN(dev_priv);
899
900 mga_dma_dispatch_swap(dev);
901
902 /* Make sure we restore the 3D state next time.
903 */
904 dev_priv->sarea_priv->dirty |= MGA_UPLOAD_CONTEXT;
905
906 return 0;
907 }
908
909 static int mga_dma_vertex(struct drm_device *dev, void *data, struct drm_file *file_priv)
910 {
911 drm_mga_private_t *dev_priv = dev->dev_private;
912 struct drm_device_dma *dma = dev->dma;
913 struct drm_buf *buf;
914 drm_mga_buf_priv_t *buf_priv;
915 drm_mga_vertex_t *vertex = data;
916
917 LOCK_TEST_WITH_RETURN(dev, file_priv);
918
919 if (vertex->idx < 0 || vertex->idx > dma->buf_count)
920 return -EINVAL;
921 buf = dma->buflist[vertex->idx];
922 buf_priv = buf->dev_private;
923
924 buf->used = vertex->used;
925 buf_priv->discard = vertex->discard;
926
927 if (!mga_verify_state(dev_priv)) {
928 if (vertex->discard) {
929 if (buf_priv->dispatched == 1)
930 AGE_BUFFER(buf_priv);
931 buf_priv->dispatched = 0;
932 mga_freelist_put(dev, buf);
933 }
934 return -EINVAL;
935 }
936
937 WRAP_TEST_WITH_RETURN(dev_priv);
938
939 mga_dma_dispatch_vertex(dev, buf);
940
941 return 0;
942 }
943
944 static int mga_dma_indices(struct drm_device *dev, void *data, struct drm_file *file_priv)
945 {
946 drm_mga_private_t *dev_priv = dev->dev_private;
947 struct drm_device_dma *dma = dev->dma;
948 struct drm_buf *buf;
949 drm_mga_buf_priv_t *buf_priv;
950 drm_mga_indices_t *indices = data;
951
952 LOCK_TEST_WITH_RETURN(dev, file_priv);
953
954 if (indices->idx < 0 || indices->idx > dma->buf_count)
955 return -EINVAL;
956
957 buf = dma->buflist[indices->idx];
958 buf_priv = buf->dev_private;
959
960 buf_priv->discard = indices->discard;
961
962 if (!mga_verify_state(dev_priv)) {
963 if (indices->discard) {
964 if (buf_priv->dispatched == 1)
965 AGE_BUFFER(buf_priv);
966 buf_priv->dispatched = 0;
967 mga_freelist_put(dev, buf);
968 }
969 return -EINVAL;
970 }
971
972 WRAP_TEST_WITH_RETURN(dev_priv);
973
974 mga_dma_dispatch_indices(dev, buf, indices->start, indices->end);
975
976 return 0;
977 }
978
979 static int mga_dma_iload(struct drm_device *dev, void *data, struct drm_file *file_priv)
980 {
981 struct drm_device_dma *dma = dev->dma;
982 drm_mga_private_t *dev_priv = dev->dev_private;
983 struct drm_buf *buf;
984 drm_mga_buf_priv_t *buf_priv;
985 drm_mga_iload_t *iload = data;
986 DRM_DEBUG("\n");
987
988 LOCK_TEST_WITH_RETURN(dev, file_priv);
989
990 #if 0
991 if (mga_do_wait_for_idle(dev_priv) < 0) {
992 if (MGA_DMA_DEBUG)
993 DRM_INFO("-EBUSY\n");
994 return -EBUSY;
995 }
996 #endif
997 if (iload->idx < 0 || iload->idx > dma->buf_count)
998 return -EINVAL;
999
1000 buf = dma->buflist[iload->idx];
1001 buf_priv = buf->dev_private;
1002
1003 if (mga_verify_iload(dev_priv, iload->dstorg, iload->length)) {
1004 mga_freelist_put(dev, buf);
1005 return -EINVAL;
1006 }
1007
1008 WRAP_TEST_WITH_RETURN(dev_priv);
1009
1010 mga_dma_dispatch_iload(dev, buf, iload->dstorg, iload->length);
1011
1012 /* Make sure we restore the 3D state next time.
1013 */
1014 dev_priv->sarea_priv->dirty |= MGA_UPLOAD_CONTEXT;
1015
1016 return 0;
1017 }
1018
1019 static int mga_dma_blit(struct drm_device *dev, void *data, struct drm_file *file_priv)
1020 {
1021 drm_mga_private_t *dev_priv = dev->dev_private;
1022 drm_mga_sarea_t *sarea_priv = dev_priv->sarea_priv;
1023 drm_mga_blit_t *blit = data;
1024 DRM_DEBUG("\n");
1025
1026 LOCK_TEST_WITH_RETURN(dev, file_priv);
1027
1028 if (sarea_priv->nbox > MGA_NR_SAREA_CLIPRECTS)
1029 sarea_priv->nbox = MGA_NR_SAREA_CLIPRECTS;
1030
1031 if (mga_verify_blit(dev_priv, blit->srcorg, blit->dstorg))
1032 return -EINVAL;
1033
1034 WRAP_TEST_WITH_RETURN(dev_priv);
1035
1036 mga_dma_dispatch_blit(dev, blit);
1037
1038 /* Make sure we restore the 3D state next time.
1039 */
1040 dev_priv->sarea_priv->dirty |= MGA_UPLOAD_CONTEXT;
1041
1042 return 0;
1043 }
1044
1045 static int mga_getparam(struct drm_device *dev, void *data, struct drm_file *file_priv)
1046 {
1047 drm_mga_private_t *dev_priv = dev->dev_private;
1048 drm_mga_getparam_t *param = data;
1049 int value;
1050
1051 if (!dev_priv) {
1052 DRM_ERROR("called with no initialization\n");
1053 return -EINVAL;
1054 }
1055
1056 DRM_DEBUG("pid=%d\n", DRM_CURRENTPID);
1057
1058 switch (param->param) {
1059 case MGA_PARAM_IRQ_NR:
1060 value = dev->irq;
1061 break;
1062 case MGA_PARAM_CARD_TYPE:
1063 value = dev_priv->chipset;
1064 break;
1065 default:
1066 return -EINVAL;
1067 }
1068
1069 if (DRM_COPY_TO_USER(param->value, &value, sizeof(int))) {
1070 DRM_ERROR("copy_to_user\n");
1071 return -EFAULT;
1072 }
1073
1074 return 0;
1075 }
1076
1077 static int mga_set_fence(struct drm_device *dev, void *data, struct drm_file *file_priv)
1078 {
1079 drm_mga_private_t *dev_priv = dev->dev_private;
1080 u32 *fence = data;
1081 DMA_LOCALS;
1082
1083 if (!dev_priv) {
1084 DRM_ERROR("called with no initialization\n");
1085 return -EINVAL;
1086 }
1087
1088 DRM_DEBUG("pid=%d\n", DRM_CURRENTPID);
1089
1090 /* I would normal do this assignment in the declaration of fence,
1091 * but dev_priv may be NULL.
1092 */
1093
1094 *fence = dev_priv->next_fence_to_post;
1095 dev_priv->next_fence_to_post++;
1096
1097 BEGIN_DMA(1);
1098 DMA_BLOCK(MGA_DMAPAD, 0x00000000,
1099 MGA_DMAPAD, 0x00000000,
1100 MGA_DMAPAD, 0x00000000,
1101 MGA_SOFTRAP, 0x00000000);
1102 ADVANCE_DMA();
1103
1104 return 0;
1105 }
1106
1107 static int mga_wait_fence(struct drm_device *dev, void *data, struct drm_file *file_priv)
1108 {
1109 drm_mga_private_t *dev_priv = dev->dev_private;
1110 u32 *fence = data;
1111
1112 if (!dev_priv) {
1113 DRM_ERROR("called with no initialization\n");
1114 return -EINVAL;
1115 }
1116
1117 DRM_DEBUG("pid=%d\n", DRM_CURRENTPID);
1118
1119 mga_driver_fence_wait(dev, fence);
1120
1121 return 0;
1122 }
1123
1124 struct drm_ioctl_desc mga_ioctls[] = {
1125 DRM_IOCTL_DEF(DRM_MGA_INIT, mga_dma_init, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
1126 DRM_IOCTL_DEF(DRM_MGA_FLUSH, mga_dma_flush, DRM_AUTH),
1127 DRM_IOCTL_DEF(DRM_MGA_RESET, mga_dma_reset, DRM_AUTH),
1128 DRM_IOCTL_DEF(DRM_MGA_SWAP, mga_dma_swap, DRM_AUTH),
1129 DRM_IOCTL_DEF(DRM_MGA_CLEAR, mga_dma_clear, DRM_AUTH),
1130 DRM_IOCTL_DEF(DRM_MGA_VERTEX, mga_dma_vertex, DRM_AUTH),
1131 DRM_IOCTL_DEF(DRM_MGA_INDICES, mga_dma_indices, DRM_AUTH),
1132 DRM_IOCTL_DEF(DRM_MGA_ILOAD, mga_dma_iload, DRM_AUTH),
1133 DRM_IOCTL_DEF(DRM_MGA_BLIT, mga_dma_blit, DRM_AUTH),
1134 DRM_IOCTL_DEF(DRM_MGA_GETPARAM, mga_getparam, DRM_AUTH),
1135 DRM_IOCTL_DEF(DRM_MGA_SET_FENCE, mga_set_fence, DRM_AUTH),
1136 DRM_IOCTL_DEF(DRM_MGA_WAIT_FENCE, mga_wait_fence, DRM_AUTH),
1137 DRM_IOCTL_DEF(DRM_MGA_DMA_BOOTSTRAP, mga_dma_bootstrap, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
1138
1139 };
1140
1141 int mga_max_ioctl = DRM_ARRAY_SIZE(mga_ioctls);
DragonFly BSD