sys/dev/drm/mach64_drm.h

   1 /* mach64_drm.h -- Public header for the mach64 driver -*- linux-c -*-
   2  * Created: Thu Nov 30 20:04:32 2000 by gareth@valinux.com
   3  */
   4 /*
   5  * Copyright 2000 Gareth Hughes
   6  * Copyright 2002 Frank C. Earl
   7  * Copyright 2002-2003 Leif Delgass
   8  * All Rights Reserved.
   9  *
  10  * Permission is hereby granted, free of charge, to any person obtaining a
  11  * copy of this software and associated documentation files (the "Software"),
  12  * to deal in the Software without restriction, including without limitation
  13  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
  14  * and/or sell copies of the Software, and to permit persons to whom the
  15  * Software is furnished to do so, subject to the following conditions:
  16  *
  17  * The above copyright notice and this permission notice (including the next
  18  * paragraph) shall be included in all copies or substantial portions of the
  19  * Software.
  20  *
  21  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  22  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  23  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  24  * THE COPYRIGHT OWNER(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
  25  * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
  26  * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
  27  *
  28  * Authors:
  29  *    Gareth Hughes <gareth@valinux.com>
  30  *    Frank C. Earl <fearl@airmail.net>
  31  *    Leif Delgass <ldelgass@retinalburn.net>
  32  *
  33  * $DragonFly: src/sys/dev/drm/mach64_drm.h,v 1.1 2008/04/05 18:12:29 hasso Exp $
  34  */
  35
  36 #ifndef __MACH64_DRM_H__
  37 #define __MACH64_DRM_H__
  38
  39 /* WARNING: If you change any of these defines, make sure to change the
  40  * defines in the Xserver file (mach64_sarea.h)
  41  */
  42 #ifndef __MACH64_SAREA_DEFINES__
  43 #define __MACH64_SAREA_DEFINES__
  44
  45 /* What needs to be changed for the current vertex buffer?
  46  * GH: We're going to be pedantic about this.  We want the card to do as
  47  * little as possible, so let's avoid having it fetch a whole bunch of
  48  * register values that don't change all that often, if at all.
  49  */
  50 #define MACH64_UPLOAD_DST_OFF_PITCH     0x0001
  51 #define MACH64_UPLOAD_Z_OFF_PITCH       0x0002
  52 #define MACH64_UPLOAD_Z_ALPHA_CNTL      0x0004
  53 #define MACH64_UPLOAD_SCALE_3D_CNTL     0x0008
  54 #define MACH64_UPLOAD_DP_FOG_CLR        0x0010
  55 #define MACH64_UPLOAD_DP_WRITE_MASK     0x0020
  56 #define MACH64_UPLOAD_DP_PIX_WIDTH      0x0040
  57 #define MACH64_UPLOAD_SETUP_CNTL        0x0080
  58 #define MACH64_UPLOAD_MISC              0x0100
  59 #define MACH64_UPLOAD_TEXTURE           0x0200
  60 #define MACH64_UPLOAD_TEX0IMAGE         0x0400
  61 #define MACH64_UPLOAD_TEX1IMAGE         0x0800
  62 #define MACH64_UPLOAD_CLIPRECTS         0x1000  /* handled client-side */
  63 #define MACH64_UPLOAD_CONTEXT           0x00ff
  64 #define MACH64_UPLOAD_ALL               0x1fff
  65
  66 /* DMA buffer size
  67  */
  68 #define MACH64_BUFFER_SIZE              16384
  69
  70 /* Max number of swaps allowed on the ring
  71  * before the client must wait
  72  */
  73 #define MACH64_MAX_QUEUED_FRAMES        3U
  74
  75 /* Byte offsets for host blit buffer data
  76  */
  77 #define MACH64_HOSTDATA_BLIT_OFFSET     104
  78
  79 /* Keep these small for testing.
  80  */
  81 #define MACH64_NR_SAREA_CLIPRECTS       8
  82
  83 #define MACH64_CARD_HEAP                0
  84 #define MACH64_AGP_HEAP                 1
  85 #define MACH64_NR_TEX_HEAPS             2
  86 #define MACH64_NR_TEX_REGIONS           64
  87 #define MACH64_LOG_TEX_GRANULARITY      16
  88
  89 #define MACH64_TEX_MAXLEVELS            1
  90
  91 #define MACH64_NR_CONTEXT_REGS          15
  92 #define MACH64_NR_TEXTURE_REGS          4
  93
  94 #endif                          /* __MACH64_SAREA_DEFINES__ */
  95
  96 typedef struct {
  97         unsigned int dst_off_pitch;
  98
  99         unsigned int z_off_pitch;
 100         unsigned int z_cntl;
 101         unsigned int alpha_tst_cntl;
 102
 103         unsigned int scale_3d_cntl;
 104
 105         unsigned int sc_left_right;
 106         unsigned int sc_top_bottom;
 107
 108         unsigned int dp_fog_clr;
 109         unsigned int dp_write_mask;
 110         unsigned int dp_pix_width;
 111         unsigned int dp_mix;
 112         unsigned int dp_src;
 113
 114         unsigned int clr_cmp_cntl;
 115         unsigned int gui_traj_cntl;
 116
 117         unsigned int setup_cntl;
 118
 119         unsigned int tex_size_pitch;
 120         unsigned int tex_cntl;
 121         unsigned int secondary_tex_off;
 122         unsigned int tex_offset;
 123 } drm_mach64_context_regs_t;
 124
 125 typedef struct drm_mach64_sarea {
 126         /* The channel for communication of state information to the kernel
 127          * on firing a vertex dma buffer.
 128          */
 129         drm_mach64_context_regs_t context_state;
 130         unsigned int dirty;
 131         unsigned int vertsize;
 132
 133         /* The current cliprects, or a subset thereof.
 134          */
 135         struct drm_clip_rect boxes[MACH64_NR_SAREA_CLIPRECTS];
 136         unsigned int nbox;
 137
 138         /* Counters for client-side throttling of rendering clients.
 139          */
 140         unsigned int frames_queued;
 141
 142         /* Texture memory LRU.
 143          */
 144         struct drm_tex_region tex_list[MACH64_NR_TEX_HEAPS][MACH64_NR_TEX_REGIONS +
 145                                                        1];
 146         unsigned int tex_age[MACH64_NR_TEX_HEAPS];
 147         int ctx_owner;
 148 } drm_mach64_sarea_t;
 149
 150 /* WARNING: If you change any of these defines, make sure to change the
 151  * defines in the Xserver file (mach64_common.h)
 152  */
 153
 154 /* Mach64 specific ioctls
 155  * The device specific ioctl range is 0x40 to 0x79.
 156  */
 157
 158 #define DRM_MACH64_INIT           0x00
 159 #define DRM_MACH64_IDLE           0x01
 160 #define DRM_MACH64_RESET          0x02
 161 #define DRM_MACH64_SWAP           0x03
 162 #define DRM_MACH64_CLEAR          0x04
 163 #define DRM_MACH64_VERTEX         0x05
 164 #define DRM_MACH64_BLIT           0x06
 165 #define DRM_MACH64_FLUSH          0x07
 166 #define DRM_MACH64_GETPARAM       0x08
 167
 168 #define DRM_IOCTL_MACH64_INIT           DRM_IOW( DRM_COMMAND_BASE + DRM_MACH64_INIT, drm_mach64_init_t)
 169 #define DRM_IOCTL_MACH64_IDLE           DRM_IO(  DRM_COMMAND_BASE + DRM_MACH64_IDLE )
 170 #define DRM_IOCTL_MACH64_RESET          DRM_IO(  DRM_COMMAND_BASE + DRM_MACH64_RESET )
 171 #define DRM_IOCTL_MACH64_SWAP           DRM_IO(  DRM_COMMAND_BASE + DRM_MACH64_SWAP )
 172 #define DRM_IOCTL_MACH64_CLEAR          DRM_IOW( DRM_COMMAND_BASE + DRM_MACH64_CLEAR, drm_mach64_clear_t)
 173 #define DRM_IOCTL_MACH64_VERTEX         DRM_IOW( DRM_COMMAND_BASE + DRM_MACH64_VERTEX, drm_mach64_vertex_t)
 174 #define DRM_IOCTL_MACH64_BLIT           DRM_IOW( DRM_COMMAND_BASE + DRM_MACH64_BLIT, drm_mach64_blit_t)
 175 #define DRM_IOCTL_MACH64_FLUSH          DRM_IO(  DRM_COMMAND_BASE + DRM_MACH64_FLUSH )
 176 #define DRM_IOCTL_MACH64_GETPARAM       DRM_IOWR( DRM_COMMAND_BASE + DRM_MACH64_GETPARAM, drm_mach64_getparam_t)
 177
 178 /* Buffer flags for clears
 179  */
 180 #define MACH64_FRONT                    0x1
 181 #define MACH64_BACK                     0x2
 182 #define MACH64_DEPTH                    0x4
 183
 184 /* Primitive types for vertex buffers
 185  */
 186 #define MACH64_PRIM_POINTS              0x00000000
 187 #define MACH64_PRIM_LINES               0x00000001
 188 #define MACH64_PRIM_LINE_LOOP           0x00000002
 189 #define MACH64_PRIM_LINE_STRIP          0x00000003
 190 #define MACH64_PRIM_TRIANGLES           0x00000004
 191 #define MACH64_PRIM_TRIANGLE_STRIP      0x00000005
 192 #define MACH64_PRIM_TRIANGLE_FAN        0x00000006
 193 #define MACH64_PRIM_QUADS               0x00000007
 194 #define MACH64_PRIM_QUAD_STRIP          0x00000008
 195 #define MACH64_PRIM_POLYGON             0x00000009
 196
 197 typedef enum _drm_mach64_dma_mode_t {
 198         MACH64_MODE_DMA_ASYNC,
 199         MACH64_MODE_DMA_SYNC,
 200         MACH64_MODE_MMIO
 201 } drm_mach64_dma_mode_t;
 202
 203 typedef struct drm_mach64_init {
 204         enum {
 205                 DRM_MACH64_INIT_DMA = 0x01,
 206                 DRM_MACH64_CLEANUP_DMA = 0x02
 207         } func;
 208
 209         unsigned long sarea_priv_offset;
 210         int is_pci;
 211         drm_mach64_dma_mode_t dma_mode;
 212
 213         unsigned int fb_bpp;
 214         unsigned int front_offset, front_pitch;
 215         unsigned int back_offset, back_pitch;
 216
 217         unsigned int depth_bpp;
 218         unsigned int depth_offset, depth_pitch;
 219
 220         unsigned long fb_offset;
 221         unsigned long mmio_offset;
 222         unsigned long ring_offset;
 223         unsigned long buffers_offset;
 224         unsigned long agp_textures_offset;
 225 } drm_mach64_init_t;
 226
 227 typedef struct drm_mach64_clear {
 228         unsigned int flags;
 229         int x, y, w, h;
 230         unsigned int clear_color;
 231         unsigned int clear_depth;
 232 } drm_mach64_clear_t;
 233
 234 typedef struct drm_mach64_vertex {
 235         int prim;
 236         void *buf;              /* Address of vertex buffer */
 237         unsigned long used;     /* Number of bytes in buffer */
 238         int discard;            /* Client finished with buffer? */
 239 } drm_mach64_vertex_t;
 240
 241 typedef struct drm_mach64_blit {
 242         void *buf;
 243         int pitch;
 244         int offset;
 245         int format;
 246         unsigned short x, y;
 247         unsigned short width, height;
 248 } drm_mach64_blit_t;
 249
 250 typedef struct drm_mach64_getparam {
 251         enum {
 252                 MACH64_PARAM_FRAMES_QUEUED = 0x01,
 253                 MACH64_PARAM_IRQ_NR = 0x02
 254         } param;
 255         void *value;
 256 } drm_mach64_getparam_t;
 257
 258 #endif