sys/dev/drm/i915_drm.h

   1 /*
   2  * Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas.
   3  * All Rights Reserved.
   4  *
   5  * Permission is hereby granted, free of charge, to any person obtaining a
   6  * copy of this software and associated documentation files (the
   7  * "Software"), to deal in the Software without restriction, including
   8  * without limitation the rights to use, copy, modify, merge, publish,
   9  * distribute, sub license, and/or sell copies of the Software, and to
  10  * permit persons to whom the Software is furnished to do so, subject to
  11  * the following conditions:
  12  *
  13  * The above copyright notice and this permission notice (including the
  14  * next paragraph) shall be included in all copies or substantial portions
  15  * of the Software.
  16  *
  17  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
  18  * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  19  * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
  20  * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR
  21  * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
  22  * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
  23  * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
  24  *
  25  * $DragonFly: src/sys/dev/drm/i915_drm.h,v 1.1 2008/04/05 18:12:29 hasso Exp $
  26  */
  27
  28 #ifndef _I915_DRM_H_
  29 #define _I915_DRM_H_
  30
  31 /* Please note that modifications to all structs defined here are
  32  * subject to backwards-compatibility constraints.
  33  */
  34
  35 #include "drm.h"
  36
  37 /* Each region is a minimum of 16k, and there are at most 255 of them.
  38  */
  39 #define I915_NR_TEX_REGIONS 255 /* table size 2k - maximum due to use
  40                                  * of chars for next/prev indices */
  41 #define I915_LOG_MIN_TEX_REGION_SIZE 14
  42
  43 typedef struct _drm_i915_init {
  44         enum {
  45                 I915_INIT_DMA = 0x01,
  46                 I915_CLEANUP_DMA = 0x02,
  47                 I915_RESUME_DMA = 0x03
  48         } func;
  49         unsigned int mmio_offset;
  50         int sarea_priv_offset;
  51         unsigned int ring_start;
  52         unsigned int ring_end;
  53         unsigned int ring_size;
  54         unsigned int front_offset;
  55         unsigned int back_offset;
  56         unsigned int depth_offset;
  57         unsigned int w;
  58         unsigned int h;
  59         unsigned int pitch;
  60         unsigned int pitch_bits;
  61         unsigned int back_pitch;
  62         unsigned int depth_pitch;
  63         unsigned int cpp;
  64         unsigned int chipset;
  65 } drm_i915_init_t;
  66
  67 typedef struct _drm_i915_sarea {
  68         struct drm_tex_region texList[I915_NR_TEX_REGIONS + 1];
  69         int last_upload;        /* last time texture was uploaded */
  70         int last_enqueue;       /* last time a buffer was enqueued */
  71         int last_dispatch;      /* age of the most recently dispatched buffer */
  72         int ctxOwner;           /* last context to upload state */
  73         int texAge;
  74         int pf_enabled;         /* is pageflipping allowed? */
  75         int pf_active;
  76         int pf_current_page;    /* which buffer is being displayed? */
  77         int perf_boxes;         /* performance boxes to be displayed */
  78         int width, height;      /* screen size in pixels */
  79
  80         drm_handle_t front_handle;
  81         int front_offset;
  82         int front_size;
  83
  84         drm_handle_t back_handle;
  85         int back_offset;
  86         int back_size;
  87
  88         drm_handle_t depth_handle;
  89         int depth_offset;
  90         int depth_size;
  91
  92         drm_handle_t tex_handle;
  93         int tex_offset;
  94         int tex_size;
  95         int log_tex_granularity;
  96         int pitch;
  97         int rotation;           /* 0, 90, 180 or 270 */
  98         int rotated_offset;
  99         int rotated_size;
 100         int rotated_pitch;
 101         int virtualX, virtualY;
 102
 103         unsigned int front_tiled;
 104         unsigned int back_tiled;
 105         unsigned int depth_tiled;
 106         unsigned int rotated_tiled;
 107         unsigned int rotated2_tiled;
 108
 109         int planeA_x;
 110         int planeA_y;
 111         int planeA_w;
 112         int planeA_h;
 113         int planeB_x;
 114         int planeB_y;
 115         int planeB_w;
 116         int planeB_h;
 117
 118         /* Triple buffering */
 119         drm_handle_t third_handle;
 120         int third_offset;
 121         int third_size;
 122         unsigned int third_tiled;
 123 } drm_i915_sarea_t;
 124
 125 /* Driver specific fence types and classes.
 126  */
 127
 128 /* The only fence class we support */
 129 #define DRM_I915_FENCE_CLASS_ACCEL 0
 130 /* Fence type that guarantees read-write flush */
 131 #define DRM_I915_FENCE_TYPE_RW 2
 132 /* MI_FLUSH programmed just before the fence */
 133 #define DRM_I915_FENCE_FLAG_FLUSHED 0x01000000
 134
 135 /* Flags for perf_boxes
 136  */
 137 #define I915_BOX_RING_EMPTY    0x1
 138 #define I915_BOX_FLIP          0x2
 139 #define I915_BOX_WAIT          0x4
 140 #define I915_BOX_TEXTURE_LOAD  0x8
 141 #define I915_BOX_LOST_CONTEXT  0x10
 142
 143 /* I915 specific ioctls
 144  * The device specific ioctl range is 0x40 to 0x79.
 145  */
 146 #define DRM_I915_INIT           0x00
 147 #define DRM_I915_FLUSH          0x01
 148 #define DRM_I915_FLIP           0x02
 149 #define DRM_I915_BATCHBUFFER    0x03
 150 #define DRM_I915_IRQ_EMIT       0x04
 151 #define DRM_I915_IRQ_WAIT       0x05
 152 #define DRM_I915_GETPARAM       0x06
 153 #define DRM_I915_SETPARAM       0x07
 154 #define DRM_I915_ALLOC          0x08
 155 #define DRM_I915_FREE           0x09
 156 #define DRM_I915_INIT_HEAP      0x0a
 157 #define DRM_I915_CMDBUFFER      0x0b
 158 #define DRM_I915_DESTROY_HEAP   0x0c
 159 #define DRM_I915_SET_VBLANK_PIPE        0x0d
 160 #define DRM_I915_GET_VBLANK_PIPE        0x0e
 161 #define DRM_I915_VBLANK_SWAP    0x0f
 162 #define DRM_I915_MMIO           0x10
 163 #define DRM_I915_HWS_ADDR       0x11
 164 #define DRM_I915_EXECBUFFER     0x12
 165
 166 #define DRM_IOCTL_I915_INIT             DRM_IOW( DRM_COMMAND_BASE + DRM_I915_INIT, drm_i915_init_t)
 167 #define DRM_IOCTL_I915_FLUSH            DRM_IO ( DRM_COMMAND_BASE + DRM_I915_FLUSH)
 168 #define DRM_IOCTL_I915_FLIP             DRM_IOW( DRM_COMMAND_BASE + DRM_I915_FLIP, drm_i915_flip_t)
 169 #define DRM_IOCTL_I915_BATCHBUFFER      DRM_IOW( DRM_COMMAND_BASE + DRM_I915_BATCHBUFFER, drm_i915_batchbuffer_t)
 170 #define DRM_IOCTL_I915_IRQ_EMIT         DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_IRQ_EMIT, drm_i915_irq_emit_t)
 171 #define DRM_IOCTL_I915_IRQ_WAIT         DRM_IOW( DRM_COMMAND_BASE + DRM_I915_IRQ_WAIT, drm_i915_irq_wait_t)
 172 #define DRM_IOCTL_I915_GETPARAM         DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_GETPARAM, drm_i915_getparam_t)
 173 #define DRM_IOCTL_I915_SETPARAM         DRM_IOW( DRM_COMMAND_BASE + DRM_I915_SETPARAM, drm_i915_setparam_t)
 174 #define DRM_IOCTL_I915_ALLOC            DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_ALLOC, drm_i915_mem_alloc_t)
 175 #define DRM_IOCTL_I915_FREE             DRM_IOW( DRM_COMMAND_BASE + DRM_I915_FREE, drm_i915_mem_free_t)
 176 #define DRM_IOCTL_I915_INIT_HEAP        DRM_IOW( DRM_COMMAND_BASE + DRM_I915_INIT_HEAP, drm_i915_mem_init_heap_t)
 177 #define DRM_IOCTL_I915_CMDBUFFER        DRM_IOW( DRM_COMMAND_BASE + DRM_I915_CMDBUFFER, drm_i915_cmdbuffer_t)
 178 #define DRM_IOCTL_I915_DESTROY_HEAP     DRM_IOW( DRM_COMMAND_BASE + DRM_I915_DESTROY_HEAP, drm_i915_mem_destroy_heap_t)
 179 #define DRM_IOCTL_I915_SET_VBLANK_PIPE  DRM_IOW( DRM_COMMAND_BASE + DRM_I915_SET_VBLANK_PIPE, drm_i915_vblank_pipe_t)
 180 #define DRM_IOCTL_I915_GET_VBLANK_PIPE  DRM_IOR( DRM_COMMAND_BASE + DRM_I915_GET_VBLANK_PIPE, drm_i915_vblank_pipe_t)
 181 #define DRM_IOCTL_I915_VBLANK_SWAP      DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_VBLANK_SWAP, drm_i915_vblank_swap_t)
 182 #define DRM_IOCTL_I915_MMIO             DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_MMIO, drm_i915_mmio)
 183 #define DRM_IOCTL_I915_EXECBUFFER       DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_EXECBUFFER, struct drm_i915_execbuffer)
 184
 185 /* Asynchronous page flipping:
 186  */
 187 typedef struct drm_i915_flip {
 188         /*
 189          * This is really talking about planes, and we could rename it
 190          * except for the fact that some of the duplicated i915_drm.h files
 191          * out there check for HAVE_I915_FLIP and so might pick up this
 192          * version.
 193          */
 194         int pipes;
 195 } drm_i915_flip_t;
 196
 197 /* Allow drivers to submit batchbuffers directly to hardware, relying
 198  * on the security mechanisms provided by hardware.
 199  */
 200 typedef struct _drm_i915_batchbuffer {
 201         int start;              /* agp offset */
 202         int used;               /* nr bytes in use */
 203         int DR1;                /* hw flags for GFX_OP_DRAWRECT_INFO */
 204         int DR4;                /* window origin for GFX_OP_DRAWRECT_INFO */
 205         int num_cliprects;      /* mulitpass with multiple cliprects? */
 206         struct drm_clip_rect __user *cliprects; /* pointer to userspace cliprects */
 207 } drm_i915_batchbuffer_t;
 208
 209 /* As above, but pass a pointer to userspace buffer which can be
 210  * validated by the kernel prior to sending to hardware.
 211  */
 212 typedef struct _drm_i915_cmdbuffer {
 213         char __user *buf;       /* pointer to userspace command buffer */
 214         int sz;                 /* nr bytes in buf */
 215         int DR1;                /* hw flags for GFX_OP_DRAWRECT_INFO */
 216         int DR4;                /* window origin for GFX_OP_DRAWRECT_INFO */
 217         int num_cliprects;      /* mulitpass with multiple cliprects? */
 218         struct drm_clip_rect __user *cliprects; /* pointer to userspace cliprects */
 219 } drm_i915_cmdbuffer_t;
 220
 221 /* Userspace can request & wait on irq's:
 222  */
 223 typedef struct drm_i915_irq_emit {
 224         int __user *irq_seq;
 225 } drm_i915_irq_emit_t;
 226
 227 typedef struct drm_i915_irq_wait {
 228         int irq_seq;
 229 } drm_i915_irq_wait_t;
 230
 231 /* Ioctl to query kernel params:
 232  */
 233 #define I915_PARAM_IRQ_ACTIVE            1
 234 #define I915_PARAM_ALLOW_BATCHBUFFER     2
 235 #define I915_PARAM_LAST_DISPATCH         3
 236
 237 typedef struct drm_i915_getparam {
 238         int param;
 239         int __user *value;
 240 } drm_i915_getparam_t;
 241
 242 /* Ioctl to set kernel params:
 243  */
 244 #define I915_SETPARAM_USE_MI_BATCHBUFFER_START            1
 245 #define I915_SETPARAM_TEX_LRU_LOG_GRANULARITY             2
 246 #define I915_SETPARAM_ALLOW_BATCHBUFFER                   3
 247
 248 typedef struct drm_i915_setparam {
 249         int param;
 250         int value;
 251 } drm_i915_setparam_t;
 252
 253 /* A memory manager for regions of shared memory:
 254  */
 255 #define I915_MEM_REGION_AGP 1
 256
 257 typedef struct drm_i915_mem_alloc {
 258         int region;
 259         int alignment;
 260         int size;
 261         int __user *region_offset;      /* offset from start of fb or agp */
 262 } drm_i915_mem_alloc_t;
 263
 264 typedef struct drm_i915_mem_free {
 265         int region;
 266         int region_offset;
 267 } drm_i915_mem_free_t;
 268
 269 typedef struct drm_i915_mem_init_heap {
 270         int region;
 271         int size;
 272         int start;
 273 } drm_i915_mem_init_heap_t;
 274
 275 /* Allow memory manager to be torn down and re-initialized (eg on
 276  * rotate):
 277  */
 278 typedef struct drm_i915_mem_destroy_heap {
 279         int region;
 280 } drm_i915_mem_destroy_heap_t;
 281
 282 /* Allow X server to configure which pipes to monitor for vblank signals
 283  */
 284 #define DRM_I915_VBLANK_PIPE_A  1
 285 #define DRM_I915_VBLANK_PIPE_B  2
 286
 287 typedef struct drm_i915_vblank_pipe {
 288         int pipe;
 289 } drm_i915_vblank_pipe_t;
 290
 291 /* Schedule buffer swap at given vertical blank:
 292  */
 293 typedef struct drm_i915_vblank_swap {
 294         drm_drawable_t drawable;
 295         enum drm_vblank_seq_type seqtype;
 296         unsigned int sequence;
 297 } drm_i915_vblank_swap_t;
 298
 299 #define I915_MMIO_READ  0
 300 #define I915_MMIO_WRITE 1
 301
 302 #define I915_MMIO_MAY_READ      0x1
 303 #define I915_MMIO_MAY_WRITE     0x2
 304
 305 #define MMIO_REGS_IA_PRIMATIVES_COUNT           0
 306 #define MMIO_REGS_IA_VERTICES_COUNT             1
 307 #define MMIO_REGS_VS_INVOCATION_COUNT           2
 308 #define MMIO_REGS_GS_PRIMITIVES_COUNT           3
 309 #define MMIO_REGS_GS_INVOCATION_COUNT           4
 310 #define MMIO_REGS_CL_PRIMITIVES_COUNT           5
 311 #define MMIO_REGS_CL_INVOCATION_COUNT           6
 312 #define MMIO_REGS_PS_INVOCATION_COUNT           7
 313 #define MMIO_REGS_PS_DEPTH_COUNT                8
 314
 315 typedef struct drm_i915_mmio_entry {
 316         unsigned int flag;
 317         unsigned int offset;
 318         unsigned int size;
 319 } drm_i915_mmio_entry_t;
 320
 321 typedef struct drm_i915_mmio {
 322         unsigned int read_write:1;
 323         unsigned int reg:31;
 324         void __user *data;
 325 } drm_i915_mmio_t;
 326
 327 typedef struct drm_i915_hws_addr {
 328         uint64_t addr;
 329 } drm_i915_hws_addr_t;
 330
 331 /*
 332  * Relocation header is 4 uint32_ts
 333  * 0 - (16-bit relocation type << 16)| 16 bit reloc count
 334  * 1 - buffer handle for another list of relocs
 335  * 2-3 - spare.
 336  */
 337 #define I915_RELOC_HEADER 4
 338
 339 /*
 340  * type 0 relocation has 4-uint32_t stride
 341  * 0 - offset into buffer
 342  * 1 - delta to add in
 343  * 2 - index into buffer list
 344  * 3 - reserved (for optimisations later).
 345  */
 346 #define I915_RELOC_TYPE_0 0
 347 #define I915_RELOC0_STRIDE 4
 348
 349 struct drm_i915_op_arg {
 350         uint64_t next;
 351         uint32_t reloc_handle;
 352         int handled;
 353         union {
 354                 struct drm_bo_op_req req;
 355                 struct drm_bo_arg_rep rep;
 356         } d;
 357
 358 };
 359
 360 struct drm_i915_execbuffer {
 361         uint64_t ops_list;
 362         uint32_t num_buffers;
 363         struct _drm_i915_batchbuffer batch;
 364         drm_context_t context; /* for lockless use in the future */
 365         struct drm_fence_arg fence_arg;
 366 };
 367
 368 #endif                          /* _I915_DRM_H_ */