2 .\" Copyright (c) 1995, 1996, 1997, 1998, 2000
3 .\" Justin T. Gibbs. All rights reserved.
5 .\" Redistribution and use in source and binary forms, with or without
6 .\" modification, are permitted provided that the following conditions
8 .\" 1. Redistributions of source code must retain the above copyright
9 .\" notice, this list of conditions and the following disclaimer.
10 .\" 2. Redistributions in binary form must reproduce the above copyright
11 .\" notice, this list of conditions and the following disclaimer in the
12 .\" documentation and/or other materials provided with the distribution.
13 .\" 3. The name of the author may not be used to endorse or promote products
14 .\" derived from this software without specific prior written permission.
16 .\" THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
17 .\" IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
18 .\" OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
19 .\" IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
20 .\" INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
21 .\" NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
22 .\" DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
23 .\" THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
24 .\" (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
25 .\" THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27 .\" $FreeBSD: src/share/man/man4/ahc.4,v 1.38.2.1 2006/06/05 19:30:28 brueffer Exp $
29 .Dd September 26, 2007
34 .Nd Adaptec PCI SCSI host adapter driver
36 To compile this driver into the kernel,
37 place the following lines in your
38 kernel configuration file:
39 .Bd -ragged -offset indent
44 To allow PCI adapters to use memory mapped I/O if enabled:
45 .Cd options AHC_ALLOW_MEMIO
47 To compile in debugging code:
49 .Cd options AHC_DEBUG_OPTS=<bitmask of options>
50 .Cd options AHC_REG_PRETTY_PRINT
52 To configure one or more controllers to assume the target role:
53 .Cd options AHC_TMODE_ENABLE <bitmask of units>
56 Alternatively, to load the driver as a
57 module at boot time, place the following lines in
59 .Bd -literal -offset indent
64 This driver provides access to the
66 bus(es) connected to the Adaptec AIC77xx and AIC78xx
69 Driver features include support for twin and wide busses,
70 fast, ultra or ultra2 synchronous transfers depending on controller type,
71 tagged queueing, SCB paging, and target mode.
73 Memory mapped I/O can be enabled for PCI devices with the
74 .Dq Dv AHC_ALLOW_MEMIO
76 Memory mapped I/O is more efficient than the alternative, programmed I/O.
77 Most PCI BIOSes will map devices so that either technique for communicating
78 with the card is available.
80 usually when the PCI device is sitting behind a PCI->PCI bridge,
81 the BIOS may fail to properly initialize the chip for memory mapped I/O.
82 The typical symptom of this problem is a system hang if memory mapped I/O
84 Most modern motherboards perform the initialization correctly and work fine
85 with this option enabled.
89 option is used to control which diagnostic messages are printed to the
93 Logically OR the following bits together:
94 .Bl -column -offset indent ".Em Value" ".Em Function"
95 .It Em Value Ta Em Function
96 .It 0x0001 Ta Show miscellaneous information
97 .It 0x0002 Ta Show sense data
98 .It 0x0004 Ta Show Serial EEPROM contents
99 .It 0x0008 Ta Show bus termination settings
100 .It 0x0010 Ta Show host memory usage
101 .It 0x0020 Ta Show SCSI protocol messages
102 .\".It 0x0040 XXX: AHC_SHOW_DV
103 .It 0x0080 Ta Show selection timeouts
104 .It 0x0200 Ta Show Queue Full status
105 .It 0x0400 Ta Show SCB queue status
106 .It 0x0800 Ta Show inbound packet information
107 .\".It 0x1000 XXX: AHC_SHOW_MASKED_ERRORS
108 .It 0x2000 Ta Enable extra diagnostic code in the firmware
112 .Dv AHC_REG_PRETTY_PRINT
113 option compiles in support for human-readable bit definitions for each register
114 that is printed by the debugging code.
116 Individual controllers may be configured to operate in the target role
118 .Dq Dv AHC_TMODE_ENABLE
119 configuration option.
120 The value assigned to this option should be a bitmap
121 of all units where target mode is desired.
122 For example, a value of 0x25, would enable target mode on units 0, 2, and 5.
123 A value of 0x8a enables it for units 1, 3, and 7.
125 Per target configuration performed in the
127 menu, accessible at boot, is honored by this driver.
128 This includes synchronous/asynchronous transfers,
129 maximum synchronous negotiation rate,
132 and the host adapter's SCSI ID.
133 For systems that store non-volatile settings in a system specific manner
134 rather than a serial eeprom directly connected to the aic7xxx controller,
137 must be enabled for the driver to access this information.
138 This restriction applies to many motherboard configurations.
140 Note that I/O addresses are determined automatically by the probe routines.
142 Performance and feature sets vary throughout the aic7xxx product line.
143 The following table provides a comparison of the different chips supported
147 Note that wide and twin channel features, although always supported
148 by a particular chip, may be disabled in a particular motherboard or card
151 .Bl -column "aic7850 " "MIPS " "PCI/32 " "MaxSync " "MaxWidth " "SCBs " "1 2 3 4 5 6 7 8 "
152 .It Em Chip Ta Em MIPS Ta Em Bus Ta Em MaxSync Ta Em MaxWidth Ta Em SCBs Ta Em Features
153 .It aic7850 Ta 10 Ta PCI/32 Ta 10MHz Ta 8Bit Ta 3 Ta ""
154 .It aic7860 Ta 10 Ta PCI/32 Ta 20MHz Ta 8Bit Ta 3 Ta ""
155 .It aic7870 Ta 10 Ta PCI/32 Ta 10MHz Ta 16Bit Ta 16 Ta ""
156 .It aic7880 Ta 10 Ta PCI/32 Ta 20MHz Ta 16Bit Ta 16 Ta ""
157 .It aic7890 Ta 20 Ta PCI/32 Ta 40MHz Ta 16Bit Ta 16 Ta " 3 4 5 6 7 8"
158 .It aic7891 Ta 20 Ta PCI/64 Ta 40MHz Ta 16Bit Ta 16 Ta " 3 4 5 6 7 8"
159 .It aic7892 Ta 20 Ta PCI/64 Ta 80MHz Ta 16Bit Ta 16 Ta " 3 4 5 6 7 8"
160 .It aic7895 Ta 15 Ta PCI/32 Ta 20MHz Ta 16Bit Ta 16 Ta " 2 3 4 5"
161 .It aic7895C Ta 15 Ta PCI/32 Ta 20MHz Ta 16Bit Ta 16 Ta " 2 3 4 5 8"
162 .It aic7896 Ta 20 Ta PCI/32 Ta 40MHz Ta 16Bit Ta 16 Ta " 2 3 4 5 6 7 8"
163 .It aic7897 Ta 20 Ta PCI/64 Ta 40MHz Ta 16Bit Ta 16 Ta " 2 3 4 5 6 7 8"
164 .It aic7899 Ta 20 Ta PCI/64 Ta 80MHz Ta 16Bit Ta 16 Ta " 2 3 4 5 6 7 8"
169 Multiplexed Twin Channel Device - One controller servicing two busses.
171 Multi-function Twin Channel Device - Two controllers on one chip.
173 Command Channel Secondary DMA Engine - Allows scatter gather list and
176 64 Byte SCB Support - SCSI CDB is embedded in the SCB to eliminate an extra DMA.
178 Block Move Instruction Support - Doubles the speed of certain sequencer
182 style Scatter Gather Engine - Improves S/G prefetch performance.
184 Queuing Registers - Allows queueing of new transactions without pausing the
187 Multiple Target IDs - Allows the controller to respond to selection as a
188 target on multiple SCSI IDs.
194 driver supports the following
196 host adapter chips and
352 NEC PC-9821Xt13 (PC-98)
356 NEC PC-9821X-B02L/B09 (PC-98)
358 NEC SV-98/2-B03 (PC-98)
360 Many motherboards with on-board
364 .Sh SCSI CONTROL BLOCKS (SCBs)
365 Every transaction sent to a device on the SCSI bus is assigned a
366 .Sq SCSI Control Block
368 The SCB contains all of the information required by the
369 controller to process a transaction.
370 The chip feature table lists
371 the number of SCBs that can be stored in on-chip memory.
373 with model numbers greater than or equal to 7870 allow for the on chip
374 SCB space to be augmented with external SRAM up to a maximum of 255 SCBs.
375 Very few Adaptec controller configurations have external SRAM.
377 If external SRAM is not available, SCBs are a limited resource.
378 Using the SCBs in a straight forward manner would only allow the driver to
379 handle as many concurrent transactions as there are physical SCBs.
380 To fully utilize the SCSI bus and the devices on it,
381 requires much more concurrency.
382 The solution to this problem is
384 a concept similar to memory paging.
385 SCB paging takes advantage of
386 the fact that devices usually disconnect from the SCSI bus for long
387 periods of time without talking to the controller.
388 The SCBs for disconnected transactions are only of use to the controller
389 when the transfer is resumed.
390 When the host queues another transaction
391 for the controller to execute, the controller firmware will use a
392 free SCB if one is available.
393 Otherwise, the state of the most recently
394 disconnected (and therefore most likely to stay disconnected) SCB is
395 saved, via dma, to host memory, and the local SCB reused to start
397 This allows the controller to queue up to
398 255 transactions regardless of the amount of SCB space.
400 local SCB space serves as a cache for disconnected transactions, the
401 more SCB space available, the less host bus traffic consumed saving
402 and restoring SCB data.
418 sequencer-code assembler,
419 and the firmware running on the aic7xxx chips were written by
420 .An Justin T. Gibbs .
422 Some Quantum drives (at least the Empire 2100 and 1080s) will not run on an
424 Rev B in synchronous mode at 10MHz.
425 Controllers with this problem have a
426 42 MHz clock crystal on them and run slightly above 10MHz.
427 This confuses the drive and hangs the bus.
428 Setting a maximum synchronous negotiation rate of 8MHz in the
430 utility will allow normal operation.
432 Although the Ultra2 and Ultra160 products have sufficient instruction
433 ram space to support both the initiator and target roles concurrently,
434 this configuration is disabled in favor of allowing the target role
435 to respond on multiple target ids.
436 A method for configuring dual role mode should be provided.
438 Tagged Queuing is not supported in target mode.
440 Reselection in target mode fails to function correctly on all high
441 voltage differential boards as shipped by Adaptec.
443 how to modify HVD board to work correctly in target mode is available