?  search:
summary | log | graphiclog1 | graphiclog2 | commit | commitdiff | tree | refs | edit | fork
blame | history | raw | HEAD
e1000 - Literally import e1000 driver from FreeBSD
[dragonfly.git] / sys / dev / netif / e1000 / if_em.h
blobfe5a99b3b99f77a85a93a892005db67e0c8b7889
1 /******************************************************************************
2
3 Copyright (c) 2001-2010, Intel Corporation
4 All rights reserved.
5
6 Redistribution and use in source and binary forms, with or without
7 modification, are permitted provided that the following conditions are met:
8
9 1. Redistributions of source code must retain the above copyright notice,
10 this list of conditions and the following disclaimer.
11
12 2. Redistributions in binary form must reproduce the above copyright
13 notice, this list of conditions and the following disclaimer in the
14 documentation and/or other materials provided with the distribution.
15
16 3. Neither the name of the Intel Corporation nor the names of its
17 contributors may be used to endorse or promote products derived from
18 this software without specific prior written permission.
19
20 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
21 AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
22 IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
23 ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
24 LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
25 CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
26 SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
27 INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
28 CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
29 ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
30 POSSIBILITY OF SUCH DAMAGE.
31
32 ******************************************************************************/
33 /*$FreeBSD$*/
34
35
36 #ifndef _EM_H_DEFINED_
37 #define _EM_H_DEFINED_
38
39
40 /* Tunables */
41
42 /*
43 * EM_TXD: Maximum number of Transmit Descriptors
44 * Valid Range: 80-256 for 82542 and 82543-based adapters
45 * 80-4096 for others
46 * Default Value: 256
47 * This value is the number of transmit descriptors allocated by the driver.
48 * Increasing this value allows the driver to queue more transmits. Each
49 * descriptor is 16 bytes.
50 * Since TDLEN should be multiple of 128bytes, the number of transmit
51 * desscriptors should meet the following condition.
52 * (num_tx_desc * sizeof(struct e1000_tx_desc)) % 128 == 0
53 */
54 #define EM_MIN_TXD 80
55 #define EM_MAX_TXD_82543 256
56 #define EM_MAX_TXD 4096
57 #define EM_DEFAULT_TXD 1024
58
59 /*
60 * EM_RXD - Maximum number of receive Descriptors
61 * Valid Range: 80-256 for 82542 and 82543-based adapters
62 * 80-4096 for others
63 * Default Value: 256
64 * This value is the number of receive descriptors allocated by the driver.
65 * Increasing this value allows the driver to buffer more incoming packets.
66 * Each descriptor is 16 bytes. A receive buffer is also allocated for each
67 * descriptor. The maximum MTU size is 16110.
68 * Since TDLEN should be multiple of 128bytes, the number of transmit
69 * desscriptors should meet the following condition.
70 * (num_tx_desc * sizeof(struct e1000_tx_desc)) % 128 == 0
71 */
72 #define EM_MIN_RXD 80
73 #define EM_MAX_RXD_82543 256
74 #define EM_MAX_RXD 4096
75 #define EM_DEFAULT_RXD 1024
76
77 /*
78 * EM_TIDV - Transmit Interrupt Delay Value
79 * Valid Range: 0-65535 (0=off)
80 * Default Value: 64
81 * This value delays the generation of transmit interrupts in units of
82 * 1.024 microseconds. Transmit interrupt reduction can improve CPU
83 * efficiency if properly tuned for specific network traffic. If the
84 * system is reporting dropped transmits, this value may be set too high
85 * causing the driver to run out of available transmit descriptors.
86 */
87 #define EM_TIDV 64
88
89 /*
90 * EM_TADV - Transmit Absolute Interrupt Delay Value
91 * (Not valid for 82542/82543/82544)
92 * Valid Range: 0-65535 (0=off)
93 * Default Value: 64
94 * This value, in units of 1.024 microseconds, limits the delay in which a
95 * transmit interrupt is generated. Useful only if EM_TIDV is non-zero,
96 * this value ensures that an interrupt is generated after the initial
97 * packet is sent on the wire within the set amount of time. Proper tuning,
98 * along with EM_TIDV, may improve traffic throughput in specific
99 * network conditions.
100 */
101 #define EM_TADV 64
102
103 /*
104 * EM_RDTR - Receive Interrupt Delay Timer (Packet Timer)
105 * Valid Range: 0-65535 (0=off)
106 * Default Value: 0
107 * This value delays the generation of receive interrupts in units of 1.024
108 * microseconds. Receive interrupt reduction can improve CPU efficiency if
109 * properly tuned for specific network traffic. Increasing this value adds
110 * extra latency to frame reception and can end up decreasing the throughput
111 * of TCP traffic. If the system is reporting dropped receives, this value
112 * may be set too high, causing the driver to run out of available receive
113 * descriptors.
114 *
115 * CAUTION: When setting EM_RDTR to a value other than 0, adapters
116 * may hang (stop transmitting) under certain network conditions.
117 * If this occurs a WATCHDOG message is logged in the system
118 * event log. In addition, the controller is automatically reset,
119 * restoring the network connection. To eliminate the potential
120 * for the hang ensure that EM_RDTR is set to 0.
121 */
122 #define EM_RDTR 0
123
124 /*
125 * Receive Interrupt Absolute Delay Timer (Not valid for 82542/82543/82544)
126 * Valid Range: 0-65535 (0=off)
127 * Default Value: 64
128 * This value, in units of 1.024 microseconds, limits the delay in which a
129 * receive interrupt is generated. Useful only if EM_RDTR is non-zero,
130 * this value ensures that an interrupt is generated after the initial
131 * packet is received within the set amount of time. Proper tuning,
132 * along with EM_RDTR, may improve traffic throughput in specific network
133 * conditions.
134 */
135 #define EM_RADV 64
136
137 /*
138 * This parameter controls the max duration of transmit watchdog.
139 */
140 #define EM_WATCHDOG (10 * hz)
141
142 /*
143 * This parameter controls when the driver calls the routine to reclaim
144 * transmit descriptors.
145 */
146 #define EM_TX_CLEANUP_THRESHOLD (adapter->num_tx_desc / 8)
147 #define EM_TX_OP_THRESHOLD (adapter->num_tx_desc / 32)
148
149 /*
150 * This parameter controls whether or not autonegotation is enabled.
151 * 0 - Disable autonegotiation
152 * 1 - Enable autonegotiation
153 */
154 #define DO_AUTO_NEG 1
155
156 /*
157 * This parameter control whether or not the driver will wait for
158 * autonegotiation to complete.
159 * 1 - Wait for autonegotiation to complete
160 * 0 - Don't wait for autonegotiation to complete
161 */
162 #define WAIT_FOR_AUTO_NEG_DEFAULT 0
163
164 /* Tunables -- End */
165
166 #define AUTONEG_ADV_DEFAULT (ADVERTISE_10_HALF | ADVERTISE_10_FULL | \
167 ADVERTISE_100_HALF | ADVERTISE_100_FULL | \
168 ADVERTISE_1000_FULL)
169
170 #define AUTO_ALL_MODES 0
171
172 /* PHY master/slave setting */
173 #define EM_MASTER_SLAVE e1000_ms_hw_default
174
175 /*
176 * Micellaneous constants
177 */
178 #define EM_VENDOR_ID 0x8086
179 #define EM_FLASH 0x0014
180
181 #define EM_JUMBO_PBA 0x00000028
182 #define EM_DEFAULT_PBA 0x00000030
183 #define EM_SMARTSPEED_DOWNSHIFT 3
184 #define EM_SMARTSPEED_MAX 15
185 #define EM_MAX_INTR 10
186
187 #define MAX_NUM_MULTICAST_ADDRESSES 128
188 #define PCI_ANY_ID (~0U)
189 #define ETHER_ALIGN 2
190 #define EM_FC_PAUSE_TIME 0x0680
191 #define EM_EEPROM_APME 0x400;
192 #define EM_82544_APME 0x0004;
193
194 /* Code compatilbility between 6 and 7 */
195 #ifndef ETHER_BPF_MTAP
196 #define ETHER_BPF_MTAP BPF_MTAP
197 #endif
198
199 /*
200 * TDBA/RDBA should be aligned on 16 byte boundary. But TDLEN/RDLEN should be
201 * multiple of 128 bytes. So we align TDBA/RDBA on 128 byte boundary. This will
202 * also optimize cache line size effect. H/W supports up to cache line size 128.
203 */
204 #define EM_DBA_ALIGN 128
205
206 #define SPEED_MODE_BIT (1<<21) /* On PCI-E MACs only */
207
208 /* PCI Config defines */
209 #define EM_BAR_TYPE(v) ((v) & EM_BAR_TYPE_MASK)
210 #define EM_BAR_TYPE_MASK 0x00000001
211 #define EM_BAR_TYPE_MMEM 0x00000000
212 #define EM_BAR_TYPE_IO 0x00000001
213 #define EM_BAR_TYPE_FLASH 0x0014
214 #define EM_BAR_MEM_TYPE(v) ((v) & EM_BAR_MEM_TYPE_MASK)
215 #define EM_BAR_MEM_TYPE_MASK 0x00000006
216 #define EM_BAR_MEM_TYPE_32BIT 0x00000000
217 #define EM_BAR_MEM_TYPE_64BIT 0x00000004
218 #define EM_MSIX_BAR 3 /* On 82575 */
219
220 /* Defines for printing debug information */
221 #define DEBUG_INIT 0
222 #define DEBUG_IOCTL 0
223 #define DEBUG_HW 0
224
225 #define INIT_DEBUGOUT(S) if (DEBUG_INIT) printf(S "\n")
226 #define INIT_DEBUGOUT1(S, A) if (DEBUG_INIT) printf(S "\n", A)
227 #define INIT_DEBUGOUT2(S, A, B) if (DEBUG_INIT) printf(S "\n", A, B)
228 #define IOCTL_DEBUGOUT(S) if (DEBUG_IOCTL) printf(S "\n")
229 #define IOCTL_DEBUGOUT1(S, A) if (DEBUG_IOCTL) printf(S "\n", A)
230 #define IOCTL_DEBUGOUT2(S, A, B) if (DEBUG_IOCTL) printf(S "\n", A, B)
231 #define HW_DEBUGOUT(S) if (DEBUG_HW) printf(S "\n")
232 #define HW_DEBUGOUT1(S, A) if (DEBUG_HW) printf(S "\n", A)
233 #define HW_DEBUGOUT2(S, A, B) if (DEBUG_HW) printf(S "\n", A, B)
234
235 #define EM_MAX_SCATTER 64
236 #define EM_VFTA_SIZE 128
237 #define EM_TSO_SIZE (65535 + sizeof(struct ether_vlan_header))
238 #define EM_TSO_SEG_SIZE 4096 /* Max dma segment size */
239 #define EM_MSIX_MASK 0x01F00000 /* For 82574 use */
240 #define ETH_ZLEN 60
241 #define ETH_ADDR_LEN 6
242 #define CSUM_OFFLOAD 7 /* Offload bits in mbuf flag */
243
244 /*
245 * 82574 has a nonstandard address for EIAC
246 * and since its only used in MSIX, and in
247 * the em driver only 82574 uses MSIX we can
248 * solve it just using this define.
249 */
250 #define EM_EIAC 0x000DC
251
252 /* Used in for 82547 10Mb Half workaround */
253 #define EM_PBA_BYTES_SHIFT 0xA
254 #define EM_TX_HEAD_ADDR_SHIFT 7
255 #define EM_PBA_TX_MASK 0xFFFF0000
256 #define EM_FIFO_HDR 0x10
257 #define EM_82547_PKT_THRESH 0x3e0
258
259 /* Precision Time Sync (IEEE 1588) defines */
260 #define ETHERTYPE_IEEE1588 0x88F7
261 #define PICOSECS_PER_TICK 20833
262 #define TSYNC_PORT 319 /* UDP port for the protocol */
263
264 /*
265 * Bus dma allocation structure used by
266 * e1000_dma_malloc and e1000_dma_free.
267 */
268 struct em_dma_alloc {
269 bus_addr_t dma_paddr;
270 caddr_t dma_vaddr;
271 bus_dma_tag_t dma_tag;
272 bus_dmamap_t dma_map;
273 bus_dma_segment_t dma_seg;
274 int dma_nseg;
275 };
276
277 struct adapter;
278
279 struct em_int_delay_info {
280 struct adapter *adapter; /* Back-pointer to the adapter struct */
281 int offset; /* Register offset to read/write */
282 int value; /* Current value in usecs */
283 };
284
285 /* Our adapter structure */
286 struct adapter {
287 struct ifnet *ifp;
288 #if __FreeBSD_version >= 800000
289 struct buf_ring *br;
290 #endif
291 struct e1000_hw hw;
292
293 /* FreeBSD operating-system-specific structures. */
294 struct e1000_osdep osdep;
295 struct device *dev;
296
297 struct resource *memory;
298 struct resource *flash;
299 struct resource *msix;
300
301 struct resource *ioport;
302 int io_rid;
303
304 /* 82574 may use 3 int vectors */
305 struct resource *res[3];
306 void *tag[3];
307 int rid[3];
308
309 struct ifmedia media;
310 struct callout timer;
311 struct callout tx_fifo_timer;
312 bool watchdog_check;
313 int watchdog_time;
314 int msi;
315 int if_flags;
316 int max_frame_size;
317 int min_frame_size;
318 struct mtx core_mtx;
319 struct mtx tx_mtx;
320 struct mtx rx_mtx;
321 int em_insert_vlan_header;
322
323 /* Task for FAST handling */
324 struct task link_task;
325 struct task rxtx_task;
326 struct task rx_task;
327 struct task tx_task;
328 struct taskqueue *tq; /* private task queue */
329
330 #if __FreeBSD_version >= 700029
331 eventhandler_tag vlan_attach;
332 eventhandler_tag vlan_detach;
333 u32 num_vlans;
334 #endif
335
336 /* Management and WOL features */
337 u32 wol;
338 bool has_manage;
339 bool has_amt;
340
341 /* Info about the board itself */
342 uint8_t link_active;
343 uint16_t link_speed;
344 uint16_t link_duplex;
345 uint32_t smartspeed;
346 struct em_int_delay_info tx_int_delay;
347 struct em_int_delay_info tx_abs_int_delay;
348 struct em_int_delay_info rx_int_delay;
349 struct em_int_delay_info rx_abs_int_delay;
350
351 /*
352 * Transmit definitions
353 *
354 * We have an array of num_tx_desc descriptors (handled
355 * by the controller) paired with an array of tx_buffers
356 * (at tx_buffer_area).
357 * The index of the next available descriptor is next_avail_tx_desc.
358 * The number of remaining tx_desc is num_tx_desc_avail.
359 */
360 struct em_dma_alloc txdma; /* bus_dma glue for tx desc */
361 struct e1000_tx_desc *tx_desc_base;
362 uint32_t next_avail_tx_desc;
363 uint32_t next_tx_to_clean;
364 volatile uint16_t num_tx_desc_avail;
365 uint16_t num_tx_desc;
366 uint16_t last_hw_offload;
367 uint32_t txd_cmd;
368 struct em_buffer *tx_buffer_area;
369 bus_dma_tag_t txtag; /* dma tag for tx */
370 uint32_t tx_tso; /* last tx was tso */
371
372 /*
373 * Receive definitions
374 *
375 * we have an array of num_rx_desc rx_desc (handled by the
376 * controller), and paired with an array of rx_buffers
377 * (at rx_buffer_area).
378 * The next pair to check on receive is at offset next_rx_desc_to_check
379 */
380 struct em_dma_alloc rxdma; /* bus_dma glue for rx desc */
381 struct e1000_rx_desc *rx_desc_base;
382 uint32_t next_rx_desc_to_check;
383 uint32_t rx_buffer_len;
384 uint16_t num_rx_desc;
385 int rx_process_limit;
386 struct em_buffer *rx_buffer_area;
387 bus_dma_tag_t rxtag;
388 bus_dmamap_t rx_sparemap;
389
390 /*
391 * First/last mbuf pointers, for
392 * collecting multisegment RX packets.
393 */
394 struct mbuf *fmp;
395 struct mbuf *lmp;
396
397 /* Misc stats maintained by the driver */
398 unsigned long dropped_pkts;
399 unsigned long mbuf_alloc_failed;
400 unsigned long mbuf_cluster_failed;
401 unsigned long no_tx_desc_avail1;
402 unsigned long no_tx_desc_avail2;
403 unsigned long no_tx_map_avail;
404 unsigned long no_tx_dma_setup;
405 unsigned long watchdog_events;
406 unsigned long rx_overruns;
407 unsigned long rx_irq;
408 unsigned long tx_irq;
409 unsigned long link_irq;
410
411 /* 82547 workaround */
412 uint32_t tx_fifo_size;
413 uint32_t tx_fifo_head;
414 uint32_t tx_fifo_head_addr;
415 uint64_t tx_fifo_reset_cnt;
416 uint64_t tx_fifo_wrk_cnt;
417 uint32_t tx_head_addr;
418
419 /* For 82544 PCIX Workaround */
420 boolean_t pcix_82544;
421 boolean_t in_detach;
422
423 #ifdef EM_IEEE1588
424 /* IEEE 1588 precision time support */
425 struct cyclecounter cycles;
426 struct nettimer clock;
427 struct nettime_compare compare;
428 struct hwtstamp_ctrl hwtstamp;
429 #endif
430
431 struct e1000_hw_stats stats;
432 };
433
434 /* ******************************************************************************
435 * vendor_info_array
436 *
437 * This array contains the list of Subvendor/Subdevice IDs on which the driver
438 * should load.
439 *
440 * ******************************************************************************/
441 typedef struct _em_vendor_info_t {
442 unsigned int vendor_id;
443 unsigned int device_id;
444 unsigned int subvendor_id;
445 unsigned int subdevice_id;
446 unsigned int index;
447 } em_vendor_info_t;
448
449 struct em_buffer {
450 int next_eop; /* Index of the desc to watch */
451 struct mbuf *m_head;
452 bus_dmamap_t map; /* bus_dma map for packet */
453 };
454
455 /* For 82544 PCIX Workaround */
456 typedef struct _ADDRESS_LENGTH_PAIR
457 {
458 uint64_t address;
459 uint32_t length;
460 } ADDRESS_LENGTH_PAIR, *PADDRESS_LENGTH_PAIR;
461
462 typedef struct _DESCRIPTOR_PAIR
463 {
464 ADDRESS_LENGTH_PAIR descriptor[4];
465 uint32_t elements;
466 } DESC_ARRAY, *PDESC_ARRAY;
467
468 #define EM_CORE_LOCK_INIT(_sc, _name) \
469 mtx_init(&(_sc)->core_mtx, _name, "EM Core Lock", MTX_DEF)
470 #define EM_TX_LOCK_INIT(_sc, _name) \
471 mtx_init(&(_sc)->tx_mtx, _name, "EM TX Lock", MTX_DEF)
472 #define EM_RX_LOCK_INIT(_sc, _name) \
473 mtx_init(&(_sc)->rx_mtx, _name, "EM RX Lock", MTX_DEF)
474 #define EM_CORE_LOCK_DESTROY(_sc) mtx_destroy(&(_sc)->core_mtx)
475 #define EM_TX_LOCK_DESTROY(_sc) mtx_destroy(&(_sc)->tx_mtx)
476 #define EM_RX_LOCK_DESTROY(_sc) mtx_destroy(&(_sc)->rx_mtx)
477 #define EM_CORE_LOCK(_sc) mtx_lock(&(_sc)->core_mtx)
478 #define EM_TX_LOCK(_sc) mtx_lock(&(_sc)->tx_mtx)
479 #define EM_TX_TRYLOCK(_sc) mtx_trylock(&(_sc)->tx_mtx)
480 #define EM_RX_LOCK(_sc) mtx_lock(&(_sc)->rx_mtx)
481 #define EM_CORE_UNLOCK(_sc) mtx_unlock(&(_sc)->core_mtx)
482 #define EM_TX_UNLOCK(_sc) mtx_unlock(&(_sc)->tx_mtx)
483 #define EM_RX_UNLOCK(_sc) mtx_unlock(&(_sc)->rx_mtx)
484 #define EM_CORE_LOCK_ASSERT(_sc) mtx_assert(&(_sc)->core_mtx, MA_OWNED)
485 #define EM_TX_LOCK_ASSERT(_sc) mtx_assert(&(_sc)->tx_mtx, MA_OWNED)
486
487 #endif /* _EM_H_DEFINED_ */
DragonFly BSD