sys/dev/netif/e1000/e1000_phy.h

   1 /******************************************************************************
   2
   3   Copyright (c) 2001-2010, Intel Corporation
   4   All rights reserved.
   5
   6   Redistribution and use in source and binary forms, with or without
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  10       this list of conditions and the following disclaimer.
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  13       notice, this list of conditions and the following disclaimer in the
  14       documentation and/or other materials provided with the distribution.
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  18       this software without specific prior written permission.
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  20   THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
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  22   IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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  29   ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
  30   POSSIBILITY OF SUCH DAMAGE.
  31
  32 ******************************************************************************/
  33 /*$FreeBSD$*/
  34
  35 #ifndef _E1000_PHY_H_
  36 #define _E1000_PHY_H_
  37
  38 void e1000_init_phy_ops_generic(struct e1000_hw *hw);
  39 s32  e1000_null_read_reg(struct e1000_hw *hw, u32 offset, u16 *data);
  40 void e1000_null_phy_generic(struct e1000_hw *hw);
  41 s32  e1000_null_lplu_state(struct e1000_hw *hw, bool active);
  42 s32  e1000_null_write_reg(struct e1000_hw *hw, u32 offset, u16 data);
  43 s32  e1000_check_downshift_generic(struct e1000_hw *hw);
  44 s32  e1000_check_polarity_m88(struct e1000_hw *hw);
  45 s32  e1000_check_polarity_igp(struct e1000_hw *hw);
  46 s32  e1000_check_polarity_ife(struct e1000_hw *hw);
  47 s32  e1000_check_reset_block_generic(struct e1000_hw *hw);
  48 s32  e1000_phy_setup_autoneg(struct e1000_hw *hw);
  49 s32  e1000_copper_link_autoneg(struct e1000_hw *hw);
  50 s32  e1000_copper_link_setup_igp(struct e1000_hw *hw);
  51 s32  e1000_copper_link_setup_m88(struct e1000_hw *hw);
  52 s32  e1000_phy_force_speed_duplex_igp(struct e1000_hw *hw);
  53 s32  e1000_phy_force_speed_duplex_m88(struct e1000_hw *hw);
  54 s32  e1000_phy_force_speed_duplex_ife(struct e1000_hw *hw);
  55 s32  e1000_get_cable_length_m88(struct e1000_hw *hw);
  56 s32  e1000_get_cable_length_igp_2(struct e1000_hw *hw);
  57 s32  e1000_get_cfg_done_generic(struct e1000_hw *hw);
  58 s32  e1000_get_phy_id(struct e1000_hw *hw);
  59 s32  e1000_get_phy_info_igp(struct e1000_hw *hw);
  60 s32  e1000_get_phy_info_m88(struct e1000_hw *hw);
  61 s32  e1000_get_phy_info_ife(struct e1000_hw *hw);
  62 s32  e1000_phy_sw_reset_generic(struct e1000_hw *hw);
  63 void e1000_phy_force_speed_duplex_setup(struct e1000_hw *hw, u16 *phy_ctrl);
  64 s32  e1000_phy_hw_reset_generic(struct e1000_hw *hw);
  65 s32  e1000_phy_reset_dsp_generic(struct e1000_hw *hw);
  66 s32  e1000_read_kmrn_reg_generic(struct e1000_hw *hw, u32 offset, u16 *data);
  67 s32  e1000_read_kmrn_reg_locked(struct e1000_hw *hw, u32 offset, u16 *data);
  68 s32  e1000_read_phy_reg_igp(struct e1000_hw *hw, u32 offset, u16 *data);
  69 s32  e1000_read_phy_reg_igp_locked(struct e1000_hw *hw, u32 offset, u16 *data);
  70 s32  e1000_read_phy_reg_m88(struct e1000_hw *hw, u32 offset, u16 *data);
  71 s32  e1000_set_d3_lplu_state_generic(struct e1000_hw *hw, bool active);
  72 s32  e1000_setup_copper_link_generic(struct e1000_hw *hw);
  73 s32  e1000_wait_autoneg_generic(struct e1000_hw *hw);
  74 s32  e1000_write_kmrn_reg_generic(struct e1000_hw *hw, u32 offset, u16 data);
  75 s32  e1000_write_kmrn_reg_locked(struct e1000_hw *hw, u32 offset, u16 data);
  76 s32  e1000_write_phy_reg_igp(struct e1000_hw *hw, u32 offset, u16 data);
  77 s32  e1000_write_phy_reg_igp_locked(struct e1000_hw *hw, u32 offset, u16 data);
  78 s32  e1000_write_phy_reg_m88(struct e1000_hw *hw, u32 offset, u16 data);
  79 s32  e1000_phy_reset_dsp(struct e1000_hw *hw);
  80 s32  e1000_phy_has_link_generic(struct e1000_hw *hw, u32 iterations,
  81                                 u32 usec_interval, bool *success);
  82 s32  e1000_phy_init_script_igp3(struct e1000_hw *hw);
  83 enum e1000_phy_type e1000_get_phy_type_from_id(u32 phy_id);
  84 s32  e1000_determine_phy_address(struct e1000_hw *hw);
  85 s32  e1000_write_phy_reg_bm(struct e1000_hw *hw, u32 offset, u16 data);
  86 s32  e1000_read_phy_reg_bm(struct e1000_hw *hw, u32 offset, u16 *data);
  87 s32  e1000_read_phy_reg_bm2(struct e1000_hw *hw, u32 offset, u16 *data);
  88 s32  e1000_write_phy_reg_bm2(struct e1000_hw *hw, u32 offset, u16 data);
  89 void e1000_power_up_phy_copper(struct e1000_hw *hw);
  90 void e1000_power_down_phy_copper(struct e1000_hw *hw);
  91 s32  e1000_read_phy_reg_mdic(struct e1000_hw *hw, u32 offset, u16 *data);
  92 s32  e1000_write_phy_reg_mdic(struct e1000_hw *hw, u32 offset, u16 data);
  93 s32  e1000_read_phy_reg_i2c(struct e1000_hw *hw, u32 offset, u16 *data);
  94 s32  e1000_write_phy_reg_i2c(struct e1000_hw *hw, u32 offset, u16 data);
  95 s32  e1000_read_phy_reg_hv(struct e1000_hw *hw, u32 offset, u16 *data);
  96 s32  e1000_read_phy_reg_hv_locked(struct e1000_hw *hw, u32 offset, u16 *data);
  97 s32  e1000_write_phy_reg_hv(struct e1000_hw *hw, u32 offset, u16 data);
  98 s32  e1000_write_phy_reg_hv_locked(struct e1000_hw *hw, u32 offset, u16 data);
  99 s32  e1000_link_stall_workaround_hv(struct e1000_hw *hw);
 100 s32  e1000_copper_link_setup_82577(struct e1000_hw *hw);
 101 s32  e1000_check_polarity_82577(struct e1000_hw *hw);
 102 s32  e1000_get_phy_info_82577(struct e1000_hw *hw);
 103 s32  e1000_phy_force_speed_duplex_82577(struct e1000_hw *hw);
 104 s32  e1000_get_cable_length_82577(struct e1000_hw *hw);
 105
 106 #define E1000_MAX_PHY_ADDR                4
 107
 108 /* IGP01E1000 Specific Registers */
 109 #define IGP01E1000_PHY_PORT_CONFIG        0x10 /* Port Config */
 110 #define IGP01E1000_PHY_PORT_STATUS        0x11 /* Status */
 111 #define IGP01E1000_PHY_PORT_CTRL          0x12 /* Control */
 112 #define IGP01E1000_PHY_LINK_HEALTH        0x13 /* PHY Link Health */
 113 #define IGP01E1000_GMII_FIFO              0x14 /* GMII FIFO */
 114 #define IGP01E1000_PHY_CHANNEL_QUALITY    0x15 /* PHY Channel Quality */
 115 #define IGP02E1000_PHY_POWER_MGMT         0x19 /* Power Management */
 116 #define IGP01E1000_PHY_PAGE_SELECT        0x1F /* Page Select */
 117 #define BM_PHY_PAGE_SELECT                22   /* Page Select for BM */
 118 #define IGP_PAGE_SHIFT                    5
 119 #define PHY_REG_MASK                      0x1F
 120
 121 /* BM/HV Specific Registers */
 122 #define BM_PORT_CTRL_PAGE                 769
 123 #define BM_PCIE_PAGE                      770
 124 #define BM_WUC_PAGE                       800
 125 #define BM_WUC_ADDRESS_OPCODE             0x11
 126 #define BM_WUC_DATA_OPCODE                0x12
 127 #define BM_WUC_ENABLE_PAGE                BM_PORT_CTRL_PAGE
 128 #define BM_WUC_ENABLE_REG                 17
 129 #define BM_WUC_ENABLE_BIT                 (1 << 2)
 130 #define BM_WUC_HOST_WU_BIT                (1 << 4)
 131
 132 #define PHY_UPPER_SHIFT                   21
 133 #define BM_PHY_REG(page, reg) \
 134         (((reg) & MAX_PHY_REG_ADDRESS) |\
 135          (((page) & 0xFFFF) << PHY_PAGE_SHIFT) |\
 136          (((reg) & ~MAX_PHY_REG_ADDRESS) << (PHY_UPPER_SHIFT - PHY_PAGE_SHIFT)))
 137 #define BM_PHY_REG_PAGE(offset) \
 138         ((u16)(((offset) >> PHY_PAGE_SHIFT) & 0xFFFF))
 139 #define BM_PHY_REG_NUM(offset) \
 140         ((u16)(((offset) & MAX_PHY_REG_ADDRESS) |\
 141          (((offset) >> (PHY_UPPER_SHIFT - PHY_PAGE_SHIFT)) &\
 142                 ~MAX_PHY_REG_ADDRESS)))
 143
 144 #define HV_INTC_FC_PAGE_START             768
 145 #define I82578_ADDR_REG                   29
 146 #define I82577_ADDR_REG                   16
 147 #define I82577_CFG_REG                    22
 148 #define I82577_CFG_ASSERT_CRS_ON_TX       (1 << 15)
 149 #define I82577_CFG_ENABLE_DOWNSHIFT       (3 << 10) /* auto downshift 100/10 */
 150 #define I82577_CTRL_REG                   23
 151
 152 /* 82577 specific PHY registers */
 153 #define I82577_PHY_CTRL_2            18
 154 #define I82577_PHY_LBK_CTRL          19
 155 #define I82577_PHY_STATUS_2          26
 156 #define I82577_PHY_DIAG_STATUS       31
 157
 158 /* I82577 PHY Status 2 */
 159 #define I82577_PHY_STATUS2_REV_POLARITY   0x0400
 160 #define I82577_PHY_STATUS2_MDIX           0x0800
 161 #define I82577_PHY_STATUS2_SPEED_MASK     0x0300
 162 #define I82577_PHY_STATUS2_SPEED_1000MBPS 0x0200
 163 #define I82577_PHY_STATUS2_SPEED_100MBPS  0x0100
 164
 165 /* I82577 PHY Control 2 */
 166 #define I82577_PHY_CTRL2_AUTO_MDIX        0x0400
 167 #define I82577_PHY_CTRL2_FORCE_MDI_MDIX   0x0200
 168
 169 /* I82577 PHY Diagnostics Status */
 170 #define I82577_DSTATUS_CABLE_LENGTH       0x03FC
 171 #define I82577_DSTATUS_CABLE_LENGTH_SHIFT 2
 172
 173 /* BM PHY Copper Specific Control 1 */
 174 #define BM_CS_CTRL1                       16
 175 #define BM_CS_CTRL1_ENERGY_DETECT         0x0300 /* Enable Energy Detect */
 176
 177 /* BM PHY Copper Specific Status */
 178 #define BM_CS_STATUS                      17
 179 #define BM_CS_STATUS_ENERGY_DETECT        0x0010 /* Energy Detect Status */
 180 #define BM_CS_STATUS_LINK_UP              0x0400
 181 #define BM_CS_STATUS_RESOLVED             0x0800
 182 #define BM_CS_STATUS_SPEED_MASK           0xC000
 183 #define BM_CS_STATUS_SPEED_1000           0x8000
 184
 185 /* 82577 Mobile Phy Status Register */
 186 #define HV_M_STATUS                       26
 187 #define HV_M_STATUS_AUTONEG_COMPLETE      0x1000
 188 #define HV_M_STATUS_SPEED_MASK            0x0300
 189 #define HV_M_STATUS_SPEED_1000            0x0200
 190 #define HV_M_STATUS_LINK_UP               0x0040
 191
 192 #define IGP01E1000_PHY_PCS_INIT_REG       0x00B4
 193 #define IGP01E1000_PHY_POLARITY_MASK      0x0078
 194
 195 #define IGP01E1000_PSCR_AUTO_MDIX         0x1000
 196 #define IGP01E1000_PSCR_FORCE_MDI_MDIX    0x2000 /* 0=MDI, 1=MDIX */
 197
 198 #define IGP01E1000_PSCFR_SMART_SPEED      0x0080
 199
 200 /* Enable flexible speed on link-up */
 201 #define IGP01E1000_GMII_FLEX_SPD          0x0010
 202 #define IGP01E1000_GMII_SPD               0x0020 /* Enable SPD */
 203
 204 #define IGP02E1000_PM_SPD                 0x0001 /* Smart Power Down */
 205 #define IGP02E1000_PM_D0_LPLU             0x0002 /* For D0a states */
 206 #define IGP02E1000_PM_D3_LPLU             0x0004 /* For all other states */
 207
 208 #define IGP01E1000_PLHR_SS_DOWNGRADE      0x8000
 209
 210 #define IGP01E1000_PSSR_POLARITY_REVERSED 0x0002
 211 #define IGP01E1000_PSSR_MDIX              0x0800
 212 #define IGP01E1000_PSSR_SPEED_MASK        0xC000
 213 #define IGP01E1000_PSSR_SPEED_1000MBPS    0xC000
 214
 215 #define IGP02E1000_PHY_CHANNEL_NUM        4
 216 #define IGP02E1000_PHY_AGC_A              0x11B1
 217 #define IGP02E1000_PHY_AGC_B              0x12B1
 218 #define IGP02E1000_PHY_AGC_C              0x14B1
 219 #define IGP02E1000_PHY_AGC_D              0x18B1
 220
 221 #define IGP02E1000_AGC_LENGTH_SHIFT       9   /* Course - 15:13, Fine - 12:9 */
 222 #define IGP02E1000_AGC_LENGTH_MASK        0x7F
 223 #define IGP02E1000_AGC_RANGE              15
 224
 225 #define IGP03E1000_PHY_MISC_CTRL          0x1B
 226 #define IGP03E1000_PHY_MISC_DUPLEX_MANUAL_SET  0x1000 /* Manually Set Duplex */
 227
 228 #define E1000_CABLE_LENGTH_UNDEFINED      0xFF
 229
 230 #define E1000_KMRNCTRLSTA_OFFSET          0x001F0000
 231 #define E1000_KMRNCTRLSTA_OFFSET_SHIFT    16
 232 #define E1000_KMRNCTRLSTA_REN             0x00200000
 233 #define E1000_KMRNCTRLSTA_DIAG_OFFSET     0x3    /* Kumeran Diagnostic */
 234 #define E1000_KMRNCTRLSTA_TIMEOUTS        0x4    /* Kumeran Timeouts */
 235 #define E1000_KMRNCTRLSTA_INBAND_PARAM    0x9    /* Kumeran InBand Parameters */
 236 #define E1000_KMRNCTRLSTA_DIAG_NELPBK     0x1000 /* Nearend Loopback mode */
 237 #define E1000_KMRNCTRLSTA_K1_CONFIG        0x7
 238 #define E1000_KMRNCTRLSTA_K1_ENABLE        0x0002
 239
 240 #define IFE_PHY_EXTENDED_STATUS_CONTROL 0x10
 241 #define IFE_PHY_SPECIAL_CONTROL     0x11 /* 100BaseTx PHY Special Control */
 242 #define IFE_PHY_SPECIAL_CONTROL_LED 0x1B /* PHY Special and LED Control */
 243 #define IFE_PHY_MDIX_CONTROL        0x1C /* MDI/MDI-X Control */
 244
 245 /* IFE PHY Extended Status Control */
 246 #define IFE_PESC_POLARITY_REVERSED    0x0100
 247
 248 /* IFE PHY Special Control */
 249 #define IFE_PSC_AUTO_POLARITY_DISABLE      0x0010
 250 #define IFE_PSC_FORCE_POLARITY             0x0020
 251 #define IFE_PSC_DISABLE_DYNAMIC_POWER_DOWN 0x0100
 252
 253 /* IFE PHY Special Control and LED Control */
 254 #define IFE_PSCL_PROBE_MODE            0x0020
 255 #define IFE_PSCL_PROBE_LEDS_OFF        0x0006 /* Force LEDs 0 and 2 off */
 256 #define IFE_PSCL_PROBE_LEDS_ON         0x0007 /* Force LEDs 0 and 2 on */
 257
 258 /* IFE PHY MDIX Control */
 259 #define IFE_PMC_MDIX_STATUS      0x0020 /* 1=MDI-X, 0=MDI */
 260 #define IFE_PMC_FORCE_MDIX       0x0040 /* 1=force MDI-X, 0=force MDI */
 261 #define IFE_PMC_AUTO_MDIX        0x0080 /* 1=enable auto MDI/MDI-X, 0=disable */
 262
 263 #endif