sys/dev/netif/e1000/e1000_hw.h

   1 /******************************************************************************
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   3   Copyright (c) 2001-2010, Intel Corporation
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  10       this list of conditions and the following disclaimer.
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  18       this software without specific prior written permission.
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  20   THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
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  31
  32 ******************************************************************************/
  33 /*$FreeBSD$*/
  34
  35 #ifndef _E1000_HW_H_
  36 #define _E1000_HW_H_
  37
  38 #include "e1000_osdep.h"
  39 #include "e1000_regs.h"
  40 #include "e1000_defines.h"
  41
  42 struct e1000_hw;
  43
  44 #define E1000_DEV_ID_82542                    0x1000
  45 #define E1000_DEV_ID_82543GC_FIBER            0x1001
  46 #define E1000_DEV_ID_82543GC_COPPER           0x1004
  47 #define E1000_DEV_ID_82544EI_COPPER           0x1008
  48 #define E1000_DEV_ID_82544EI_FIBER            0x1009
  49 #define E1000_DEV_ID_82544GC_COPPER           0x100C
  50 #define E1000_DEV_ID_82544GC_LOM              0x100D
  51 #define E1000_DEV_ID_82540EM                  0x100E
  52 #define E1000_DEV_ID_82540EM_LOM              0x1015
  53 #define E1000_DEV_ID_82540EP_LOM              0x1016
  54 #define E1000_DEV_ID_82540EP                  0x1017
  55 #define E1000_DEV_ID_82540EP_LP               0x101E
  56 #define E1000_DEV_ID_82545EM_COPPER           0x100F
  57 #define E1000_DEV_ID_82545EM_FIBER            0x1011
  58 #define E1000_DEV_ID_82545GM_COPPER           0x1026
  59 #define E1000_DEV_ID_82545GM_FIBER            0x1027
  60 #define E1000_DEV_ID_82545GM_SERDES           0x1028
  61 #define E1000_DEV_ID_82546EB_COPPER           0x1010
  62 #define E1000_DEV_ID_82546EB_FIBER            0x1012
  63 #define E1000_DEV_ID_82546EB_QUAD_COPPER      0x101D
  64 #define E1000_DEV_ID_82546GB_COPPER           0x1079
  65 #define E1000_DEV_ID_82546GB_FIBER            0x107A
  66 #define E1000_DEV_ID_82546GB_SERDES           0x107B
  67 #define E1000_DEV_ID_82546GB_PCIE             0x108A
  68 #define E1000_DEV_ID_82546GB_QUAD_COPPER      0x1099
  69 #define E1000_DEV_ID_82546GB_QUAD_COPPER_KSP3 0x10B5
  70 #define E1000_DEV_ID_82541EI                  0x1013
  71 #define E1000_DEV_ID_82541EI_MOBILE           0x1018
  72 #define E1000_DEV_ID_82541ER_LOM              0x1014
  73 #define E1000_DEV_ID_82541ER                  0x1078
  74 #define E1000_DEV_ID_82541GI                  0x1076
  75 #define E1000_DEV_ID_82541GI_LF               0x107C
  76 #define E1000_DEV_ID_82541GI_MOBILE           0x1077
  77 #define E1000_DEV_ID_82547EI                  0x1019
  78 #define E1000_DEV_ID_82547EI_MOBILE           0x101A
  79 #define E1000_DEV_ID_82547GI                  0x1075
  80 #define E1000_DEV_ID_82571EB_COPPER           0x105E
  81 #define E1000_DEV_ID_82571EB_FIBER            0x105F
  82 #define E1000_DEV_ID_82571EB_SERDES           0x1060
  83 #define E1000_DEV_ID_82571EB_SERDES_DUAL      0x10D9
  84 #define E1000_DEV_ID_82571EB_SERDES_QUAD      0x10DA
  85 #define E1000_DEV_ID_82571EB_QUAD_COPPER      0x10A4
  86 #define E1000_DEV_ID_82571PT_QUAD_COPPER      0x10D5
  87 #define E1000_DEV_ID_82571EB_QUAD_FIBER       0x10A5
  88 #define E1000_DEV_ID_82571EB_QUAD_COPPER_LP   0x10BC
  89 #define E1000_DEV_ID_82572EI_COPPER           0x107D
  90 #define E1000_DEV_ID_82572EI_FIBER            0x107E
  91 #define E1000_DEV_ID_82572EI_SERDES           0x107F
  92 #define E1000_DEV_ID_82572EI                  0x10B9
  93 #define E1000_DEV_ID_82573E                   0x108B
  94 #define E1000_DEV_ID_82573E_IAMT              0x108C
  95 #define E1000_DEV_ID_82573L                   0x109A
  96 #define E1000_DEV_ID_82574L                   0x10D3
  97 #define E1000_DEV_ID_82574LA                  0x10F6
  98 #define E1000_DEV_ID_82583V                   0x150C
  99 #define E1000_DEV_ID_80003ES2LAN_COPPER_DPT   0x1096
 100 #define E1000_DEV_ID_80003ES2LAN_SERDES_DPT   0x1098
 101 #define E1000_DEV_ID_80003ES2LAN_COPPER_SPT   0x10BA
 102 #define E1000_DEV_ID_80003ES2LAN_SERDES_SPT   0x10BB
 103 #define E1000_DEV_ID_ICH8_82567V_3            0x1501
 104 #define E1000_DEV_ID_ICH8_IGP_M_AMT           0x1049
 105 #define E1000_DEV_ID_ICH8_IGP_AMT             0x104A
 106 #define E1000_DEV_ID_ICH8_IGP_C               0x104B
 107 #define E1000_DEV_ID_ICH8_IFE                 0x104C
 108 #define E1000_DEV_ID_ICH8_IFE_GT              0x10C4
 109 #define E1000_DEV_ID_ICH8_IFE_G               0x10C5
 110 #define E1000_DEV_ID_ICH8_IGP_M               0x104D
 111 #define E1000_DEV_ID_ICH9_IGP_M               0x10BF
 112 #define E1000_DEV_ID_ICH9_IGP_M_AMT           0x10F5
 113 #define E1000_DEV_ID_ICH9_IGP_M_V             0x10CB
 114 #define E1000_DEV_ID_ICH9_IGP_AMT             0x10BD
 115 #define E1000_DEV_ID_ICH9_BM                  0x10E5
 116 #define E1000_DEV_ID_ICH9_IGP_C               0x294C
 117 #define E1000_DEV_ID_ICH9_IFE                 0x10C0
 118 #define E1000_DEV_ID_ICH9_IFE_GT              0x10C3
 119 #define E1000_DEV_ID_ICH9_IFE_G               0x10C2
 120 #define E1000_DEV_ID_ICH10_R_BM_LM            0x10CC
 121 #define E1000_DEV_ID_ICH10_R_BM_LF            0x10CD
 122 #define E1000_DEV_ID_ICH10_R_BM_V             0x10CE
 123 #define E1000_DEV_ID_ICH10_D_BM_LM            0x10DE
 124 #define E1000_DEV_ID_ICH10_D_BM_LF            0x10DF
 125 #define E1000_DEV_ID_PCH_M_HV_LM              0x10EA
 126 #define E1000_DEV_ID_PCH_M_HV_LC              0x10EB
 127 #define E1000_DEV_ID_PCH_D_HV_DM              0x10EF
 128 #define E1000_DEV_ID_PCH_D_HV_DC              0x10F0
 129 #define E1000_DEV_ID_82576                    0x10C9
 130 #define E1000_DEV_ID_82576_FIBER              0x10E6
 131 #define E1000_DEV_ID_82576_SERDES             0x10E7
 132 #define E1000_DEV_ID_82576_QUAD_COPPER        0x10E8
 133 #define E1000_DEV_ID_82576_NS                 0x150A
 134 #define E1000_DEV_ID_82576_NS_SERDES          0x1518
 135 #define E1000_DEV_ID_82576_SERDES_QUAD        0x150D
 136 #define E1000_DEV_ID_82575EB_COPPER           0x10A7
 137 #define E1000_DEV_ID_82575EB_FIBER_SERDES     0x10A9
 138 #define E1000_DEV_ID_82575GB_QUAD_COPPER      0x10D6
 139 #define E1000_DEV_ID_82575GB_QUAD_COPPER_PM   0x10E2
 140 #define E1000_DEV_ID_82580_COPPER             0x150E
 141 #define E1000_DEV_ID_82580_FIBER              0x150F
 142 #define E1000_DEV_ID_82580_SERDES             0x1510
 143 #define E1000_DEV_ID_82580_SGMII              0x1511
 144 #define E1000_DEV_ID_82580_COPPER_DUAL        0x1516
 145 #define E1000_REVISION_0 0
 146 #define E1000_REVISION_1 1
 147 #define E1000_REVISION_2 2
 148 #define E1000_REVISION_3 3
 149 #define E1000_REVISION_4 4
 150
 151 #define E1000_FUNC_0     0
 152 #define E1000_FUNC_1     1
 153 #define E1000_FUNC_2     2
 154 #define E1000_FUNC_3     3
 155
 156 #define E1000_ALT_MAC_ADDRESS_OFFSET_LAN0   0
 157 #define E1000_ALT_MAC_ADDRESS_OFFSET_LAN1   3
 158 #define E1000_ALT_MAC_ADDRESS_OFFSET_LAN2   6
 159 #define E1000_ALT_MAC_ADDRESS_OFFSET_LAN3   9
 160
 161 enum e1000_mac_type {
 162         e1000_undefined = 0,
 163         e1000_82542,
 164         e1000_82543,
 165         e1000_82544,
 166         e1000_82540,
 167         e1000_82545,
 168         e1000_82545_rev_3,
 169         e1000_82546,
 170         e1000_82546_rev_3,
 171         e1000_82541,
 172         e1000_82541_rev_2,
 173         e1000_82547,
 174         e1000_82547_rev_2,
 175         e1000_82571,
 176         e1000_82572,
 177         e1000_82573,
 178         e1000_82574,
 179         e1000_82583,
 180         e1000_80003es2lan,
 181         e1000_ich8lan,
 182         e1000_ich9lan,
 183         e1000_ich10lan,
 184         e1000_pchlan,
 185         e1000_82575,
 186         e1000_82576,
 187         e1000_82580,
 188         e1000_num_macs  /* List is 1-based, so subtract 1 for TRUE count. */
 189 };
 190
 191 enum e1000_media_type {
 192         e1000_media_type_unknown = 0,
 193         e1000_media_type_copper = 1,
 194         e1000_media_type_fiber = 2,
 195         e1000_media_type_internal_serdes = 3,
 196         e1000_num_media_types
 197 };
 198
 199 enum e1000_nvm_type {
 200         e1000_nvm_unknown = 0,
 201         e1000_nvm_none,
 202         e1000_nvm_eeprom_spi,
 203         e1000_nvm_eeprom_microwire,
 204         e1000_nvm_flash_hw,
 205         e1000_nvm_flash_sw
 206 };
 207
 208 enum e1000_nvm_override {
 209         e1000_nvm_override_none = 0,
 210         e1000_nvm_override_spi_small,
 211         e1000_nvm_override_spi_large,
 212         e1000_nvm_override_microwire_small,
 213         e1000_nvm_override_microwire_large
 214 };
 215
 216 enum e1000_phy_type {
 217         e1000_phy_unknown = 0,
 218         e1000_phy_none,
 219         e1000_phy_m88,
 220         e1000_phy_igp,
 221         e1000_phy_igp_2,
 222         e1000_phy_gg82563,
 223         e1000_phy_igp_3,
 224         e1000_phy_ife,
 225         e1000_phy_bm,
 226         e1000_phy_82578,
 227         e1000_phy_82577,
 228         e1000_phy_82580,
 229         e1000_phy_vf,
 230 };
 231
 232 enum e1000_bus_type {
 233         e1000_bus_type_unknown = 0,
 234         e1000_bus_type_pci,
 235         e1000_bus_type_pcix,
 236         e1000_bus_type_pci_express,
 237         e1000_bus_type_reserved
 238 };
 239
 240 enum e1000_bus_speed {
 241         e1000_bus_speed_unknown = 0,
 242         e1000_bus_speed_33,
 243         e1000_bus_speed_66,
 244         e1000_bus_speed_100,
 245         e1000_bus_speed_120,
 246         e1000_bus_speed_133,
 247         e1000_bus_speed_2500,
 248         e1000_bus_speed_5000,
 249         e1000_bus_speed_reserved
 250 };
 251
 252 enum e1000_bus_width {
 253         e1000_bus_width_unknown = 0,
 254         e1000_bus_width_pcie_x1,
 255         e1000_bus_width_pcie_x2,
 256         e1000_bus_width_pcie_x4 = 4,
 257         e1000_bus_width_pcie_x8 = 8,
 258         e1000_bus_width_32,
 259         e1000_bus_width_64,
 260         e1000_bus_width_reserved
 261 };
 262
 263 enum e1000_1000t_rx_status {
 264         e1000_1000t_rx_status_not_ok = 0,
 265         e1000_1000t_rx_status_ok,
 266         e1000_1000t_rx_status_undefined = 0xFF
 267 };
 268
 269 enum e1000_rev_polarity {
 270         e1000_rev_polarity_normal = 0,
 271         e1000_rev_polarity_reversed,
 272         e1000_rev_polarity_undefined = 0xFF
 273 };
 274
 275 enum e1000_fc_mode {
 276         e1000_fc_none = 0,
 277         e1000_fc_rx_pause,
 278         e1000_fc_tx_pause,
 279         e1000_fc_full,
 280         e1000_fc_default = 0xFF
 281 };
 282
 283 enum e1000_ffe_config {
 284         e1000_ffe_config_enabled = 0,
 285         e1000_ffe_config_active,
 286         e1000_ffe_config_blocked
 287 };
 288
 289 enum e1000_dsp_config {
 290         e1000_dsp_config_disabled = 0,
 291         e1000_dsp_config_enabled,
 292         e1000_dsp_config_activated,
 293         e1000_dsp_config_undefined = 0xFF
 294 };
 295
 296 enum e1000_ms_type {
 297         e1000_ms_hw_default = 0,
 298         e1000_ms_force_master,
 299         e1000_ms_force_slave,
 300         e1000_ms_auto
 301 };
 302
 303 enum e1000_smart_speed {
 304         e1000_smart_speed_default = 0,
 305         e1000_smart_speed_on,
 306         e1000_smart_speed_off
 307 };
 308
 309 enum e1000_serdes_link_state {
 310         e1000_serdes_link_down = 0,
 311         e1000_serdes_link_autoneg_progress,
 312         e1000_serdes_link_autoneg_complete,
 313         e1000_serdes_link_forced_up
 314 };
 315
 316 /* Receive Descriptor */
 317 struct e1000_rx_desc {
 318         __le64 buffer_addr; /* Address of the descriptor's data buffer */
 319         __le16 length;      /* Length of data DMAed into data buffer */
 320         __le16 csum;        /* Packet checksum */
 321         u8  status;         /* Descriptor status */
 322         u8  errors;         /* Descriptor Errors */
 323         __le16 special;
 324 };
 325
 326 /* Receive Descriptor - Extended */
 327 union e1000_rx_desc_extended {
 328         struct {
 329                 __le64 buffer_addr;
 330                 __le64 reserved;
 331         } read;
 332         struct {
 333                 struct {
 334                         __le32 mrq;           /* Multiple Rx Queues */
 335                         union {
 336                                 __le32 rss;         /* RSS Hash */
 337                                 struct {
 338                                         __le16 ip_id;  /* IP id */
 339                                         __le16 csum;   /* Packet Checksum */
 340                                 } csum_ip;
 341                         } hi_dword;
 342                 } lower;
 343                 struct {
 344                         __le32 status_error;  /* ext status/error */
 345                         __le16 length;
 346                         __le16 vlan;          /* VLAN tag */
 347                 } upper;
 348         } wb;  /* writeback */
 349 };
 350
 351 #define MAX_PS_BUFFERS 4
 352 /* Receive Descriptor - Packet Split */
 353 union e1000_rx_desc_packet_split {
 354         struct {
 355                 /* one buffer for protocol header(s), three data buffers */
 356                 __le64 buffer_addr[MAX_PS_BUFFERS];
 357         } read;
 358         struct {
 359                 struct {
 360                         __le32 mrq;           /* Multiple Rx Queues */
 361                         union {
 362                                 __le32 rss;           /* RSS Hash */
 363                                 struct {
 364                                         __le16 ip_id;    /* IP id */
 365                                         __le16 csum;     /* Packet Checksum */
 366                                 } csum_ip;
 367                         } hi_dword;
 368                 } lower;
 369                 struct {
 370                         __le32 status_error;  /* ext status/error */
 371                         __le16 length0;       /* length of buffer 0 */
 372                         __le16 vlan;          /* VLAN tag */
 373                 } middle;
 374                 struct {
 375                         __le16 header_status;
 376                         __le16 length[3];     /* length of buffers 1-3 */
 377                 } upper;
 378                 __le64 reserved;
 379         } wb; /* writeback */
 380 };
 381
 382 /* Transmit Descriptor */
 383 struct e1000_tx_desc {
 384         __le64 buffer_addr;   /* Address of the descriptor's data buffer */
 385         union {
 386                 __le32 data;
 387                 struct {
 388                         __le16 length;    /* Data buffer length */
 389                         u8 cso;           /* Checksum offset */
 390                         u8 cmd;           /* Descriptor control */
 391                 } flags;
 392         } lower;
 393         union {
 394                 __le32 data;
 395                 struct {
 396                         u8 status;        /* Descriptor status */
 397                         u8 css;           /* Checksum start */
 398                         __le16 special;
 399                 } fields;
 400         } upper;
 401 };
 402
 403 /* Offload Context Descriptor */
 404 struct e1000_context_desc {
 405         union {
 406                 __le32 ip_config;
 407                 struct {
 408                         u8 ipcss;         /* IP checksum start */
 409                         u8 ipcso;         /* IP checksum offset */
 410                         __le16 ipcse;     /* IP checksum end */
 411                 } ip_fields;
 412         } lower_setup;
 413         union {
 414                 __le32 tcp_config;
 415                 struct {
 416                         u8 tucss;         /* TCP checksum start */
 417                         u8 tucso;         /* TCP checksum offset */
 418                         __le16 tucse;     /* TCP checksum end */
 419                 } tcp_fields;
 420         } upper_setup;
 421         __le32 cmd_and_length;
 422         union {
 423                 __le32 data;
 424                 struct {
 425                         u8 status;        /* Descriptor status */
 426                         u8 hdr_len;       /* Header length */
 427                         __le16 mss;       /* Maximum segment size */
 428                 } fields;
 429         } tcp_seg_setup;
 430 };
 431
 432 /* Offload data descriptor */
 433 struct e1000_data_desc {
 434         __le64 buffer_addr;   /* Address of the descriptor's buffer address */
 435         union {
 436                 __le32 data;
 437                 struct {
 438                         __le16 length;    /* Data buffer length */
 439                         u8 typ_len_ext;
 440                         u8 cmd;
 441                 } flags;
 442         } lower;
 443         union {
 444                 __le32 data;
 445                 struct {
 446                         u8 status;        /* Descriptor status */
 447                         u8 popts;         /* Packet Options */
 448                         __le16 special;
 449                 } fields;
 450         } upper;
 451 };
 452
 453 /* Statistics counters collected by the MAC */
 454 struct e1000_hw_stats {
 455         u64 crcerrs;
 456         u64 algnerrc;
 457         u64 symerrs;
 458         u64 rxerrc;
 459         u64 mpc;
 460         u64 scc;
 461         u64 ecol;
 462         u64 mcc;
 463         u64 latecol;
 464         u64 colc;
 465         u64 dc;
 466         u64 tncrs;
 467         u64 sec;
 468         u64 cexterr;
 469         u64 rlec;
 470         u64 xonrxc;
 471         u64 xontxc;
 472         u64 xoffrxc;
 473         u64 xofftxc;
 474         u64 fcruc;
 475         u64 prc64;
 476         u64 prc127;
 477         u64 prc255;
 478         u64 prc511;
 479         u64 prc1023;
 480         u64 prc1522;
 481         u64 gprc;
 482         u64 bprc;
 483         u64 mprc;
 484         u64 gptc;
 485         u64 gorc;
 486         u64 gotc;
 487         u64 rnbc;
 488         u64 ruc;
 489         u64 rfc;
 490         u64 roc;
 491         u64 rjc;
 492         u64 mgprc;
 493         u64 mgpdc;
 494         u64 mgptc;
 495         u64 tor;
 496         u64 tot;
 497         u64 tpr;
 498         u64 tpt;
 499         u64 ptc64;
 500         u64 ptc127;
 501         u64 ptc255;
 502         u64 ptc511;
 503         u64 ptc1023;
 504         u64 ptc1522;
 505         u64 mptc;
 506         u64 bptc;
 507         u64 tsctc;
 508         u64 tsctfc;
 509         u64 iac;
 510         u64 icrxptc;
 511         u64 icrxatc;
 512         u64 ictxptc;
 513         u64 ictxatc;
 514         u64 ictxqec;
 515         u64 ictxqmtc;
 516         u64 icrxdmtc;
 517         u64 icrxoc;
 518         u64 cbtmpc;
 519         u64 htdpmc;
 520         u64 cbrdpc;
 521         u64 cbrmpc;
 522         u64 rpthc;
 523         u64 hgptc;
 524         u64 htcbdpc;
 525         u64 hgorc;
 526         u64 hgotc;
 527         u64 lenerrs;
 528         u64 scvpc;
 529         u64 hrmpc;
 530         u64 doosync;
 531 };
 532
 533
 534 struct e1000_phy_stats {
 535         u32 idle_errors;
 536         u32 receive_errors;
 537 };
 538
 539 struct e1000_host_mng_dhcp_cookie {
 540         u32 signature;
 541         u8  status;
 542         u8  reserved0;
 543         u16 vlan_id;
 544         u32 reserved1;
 545         u16 reserved2;
 546         u8  reserved3;
 547         u8  checksum;
 548 };
 549
 550 /* Host Interface "Rev 1" */
 551 struct e1000_host_command_header {
 552         u8 command_id;
 553         u8 command_length;
 554         u8 command_options;
 555         u8 checksum;
 556 };
 557
 558 #define E1000_HI_MAX_DATA_LENGTH     252
 559 struct e1000_host_command_info {
 560         struct e1000_host_command_header command_header;
 561         u8 command_data[E1000_HI_MAX_DATA_LENGTH];
 562 };
 563
 564 /* Host Interface "Rev 2" */
 565 struct e1000_host_mng_command_header {
 566         u8  command_id;
 567         u8  checksum;
 568         u16 reserved1;
 569         u16 reserved2;
 570         u16 command_length;
 571 };
 572
 573 #define E1000_HI_MAX_MNG_DATA_LENGTH 0x6F8
 574 struct e1000_host_mng_command_info {
 575         struct e1000_host_mng_command_header command_header;
 576         u8 command_data[E1000_HI_MAX_MNG_DATA_LENGTH];
 577 };
 578
 579 #include "e1000_mac.h"
 580 #include "e1000_phy.h"
 581 #include "e1000_nvm.h"
 582 #include "e1000_manage.h"
 583
 584 struct e1000_mac_operations {
 585         /* Function pointers for the MAC. */
 586         s32  (*init_params)(struct e1000_hw *);
 587         s32  (*id_led_init)(struct e1000_hw *);
 588         s32  (*blink_led)(struct e1000_hw *);
 589         s32  (*check_for_link)(struct e1000_hw *);
 590         bool (*check_mng_mode)(struct e1000_hw *hw);
 591         s32  (*cleanup_led)(struct e1000_hw *);
 592         void (*clear_hw_cntrs)(struct e1000_hw *);
 593         void (*clear_vfta)(struct e1000_hw *);
 594         s32  (*get_bus_info)(struct e1000_hw *);
 595         void (*set_lan_id)(struct e1000_hw *);
 596         s32  (*get_link_up_info)(struct e1000_hw *, u16 *, u16 *);
 597         s32  (*led_on)(struct e1000_hw *);
 598         s32  (*led_off)(struct e1000_hw *);
 599         void (*update_mc_addr_list)(struct e1000_hw *, u8 *, u32);
 600         s32  (*reset_hw)(struct e1000_hw *);
 601         s32  (*init_hw)(struct e1000_hw *);
 602         void (*shutdown_serdes)(struct e1000_hw *);
 603         void (*power_up_serdes)(struct e1000_hw *);
 604         s32  (*setup_link)(struct e1000_hw *);
 605         s32  (*setup_physical_interface)(struct e1000_hw *);
 606         s32  (*setup_led)(struct e1000_hw *);
 607         void (*write_vfta)(struct e1000_hw *, u32, u32);
 608         void (*config_collision_dist)(struct e1000_hw *);
 609         void (*rar_set)(struct e1000_hw *, u8*, u32);
 610         s32  (*read_mac_addr)(struct e1000_hw *);
 611         s32  (*validate_mdi_setting)(struct e1000_hw *);
 612         s32  (*mng_host_if_write)(struct e1000_hw *, u8*, u16, u16, u8*);
 613         s32  (*mng_write_cmd_header)(struct e1000_hw *hw,
 614                       struct e1000_host_mng_command_header*);
 615         s32  (*mng_enable_host_if)(struct e1000_hw *);
 616         s32  (*wait_autoneg)(struct e1000_hw *);
 617 };
 618
 619 struct e1000_phy_operations {
 620         s32  (*init_params)(struct e1000_hw *);
 621         s32  (*acquire)(struct e1000_hw *);
 622         s32  (*cfg_on_link_up)(struct e1000_hw *);
 623         s32  (*check_polarity)(struct e1000_hw *);
 624         s32  (*check_reset_block)(struct e1000_hw *);
 625         s32  (*commit)(struct e1000_hw *);
 626         s32  (*force_speed_duplex)(struct e1000_hw *);
 627         s32  (*get_cfg_done)(struct e1000_hw *hw);
 628         s32  (*get_cable_length)(struct e1000_hw *);
 629         s32  (*get_info)(struct e1000_hw *);
 630         s32  (*read_reg)(struct e1000_hw *, u32, u16 *);
 631         s32  (*read_reg_locked)(struct e1000_hw *, u32, u16 *);
 632         void (*release)(struct e1000_hw *);
 633         s32  (*reset)(struct e1000_hw *);
 634         s32  (*set_d0_lplu_state)(struct e1000_hw *, bool);
 635         s32  (*set_d3_lplu_state)(struct e1000_hw *, bool);
 636         s32  (*write_reg)(struct e1000_hw *, u32, u16);
 637         s32  (*write_reg_locked)(struct e1000_hw *, u32, u16);
 638         void (*power_up)(struct e1000_hw *);
 639         void (*power_down)(struct e1000_hw *);
 640 };
 641
 642 struct e1000_nvm_operations {
 643         s32  (*init_params)(struct e1000_hw *);
 644         s32  (*acquire)(struct e1000_hw *);
 645         s32  (*read)(struct e1000_hw *, u16, u16, u16 *);
 646         void (*release)(struct e1000_hw *);
 647         void (*reload)(struct e1000_hw *);
 648         s32  (*update)(struct e1000_hw *);
 649         s32  (*valid_led_default)(struct e1000_hw *, u16 *);
 650         s32  (*validate)(struct e1000_hw *);
 651         s32  (*write)(struct e1000_hw *, u16, u16, u16 *);
 652 };
 653
 654 struct e1000_mac_info {
 655         struct e1000_mac_operations ops;
 656         u8 addr[6];
 657         u8 perm_addr[6];
 658
 659         enum e1000_mac_type type;
 660
 661         u32 collision_delta;
 662         u32 ledctl_default;
 663         u32 ledctl_mode1;
 664         u32 ledctl_mode2;
 665         u32 mc_filter_type;
 666         u32 tx_packet_delta;
 667         u32 txcw;
 668
 669         u16 current_ifs_val;
 670         u16 ifs_max_val;
 671         u16 ifs_min_val;
 672         u16 ifs_ratio;
 673         u16 ifs_step_size;
 674         u16 mta_reg_count;
 675         u16 uta_reg_count;
 676
 677         /* Maximum size of the MTA register table in all supported adapters */
 678         #define MAX_MTA_REG 128
 679         u32 mta_shadow[MAX_MTA_REG];
 680         u16 rar_entry_count;
 681
 682         u8  forced_speed_duplex;
 683
 684         bool adaptive_ifs;
 685         bool arc_subsystem_valid;
 686         bool asf_firmware_present;
 687         bool autoneg;
 688         bool autoneg_failed;
 689         bool get_link_status;
 690         bool in_ifs_mode;
 691         bool report_tx_early;
 692         enum e1000_serdes_link_state serdes_link_state;
 693         bool serdes_has_link;
 694         bool tx_pkt_filtering;
 695 };
 696
 697 struct e1000_phy_info {
 698         struct e1000_phy_operations ops;
 699         enum e1000_phy_type type;
 700
 701         enum e1000_1000t_rx_status local_rx;
 702         enum e1000_1000t_rx_status remote_rx;
 703         enum e1000_ms_type ms_type;
 704         enum e1000_ms_type original_ms_type;
 705         enum e1000_rev_polarity cable_polarity;
 706         enum e1000_smart_speed smart_speed;
 707
 708         u32 addr;
 709         u32 id;
 710         u32 reset_delay_us; /* in usec */
 711         u32 revision;
 712
 713         enum e1000_media_type media_type;
 714
 715         u16 autoneg_advertised;
 716         u16 autoneg_mask;
 717         u16 cable_length;
 718         u16 max_cable_length;
 719         u16 min_cable_length;
 720
 721         u8 mdix;
 722
 723         bool disable_polarity_correction;
 724         bool is_mdix;
 725         bool polarity_correction;
 726         bool reset_disable;
 727         bool speed_downgraded;
 728         bool autoneg_wait_to_complete;
 729 };
 730
 731 struct e1000_nvm_info {
 732         struct e1000_nvm_operations ops;
 733         enum e1000_nvm_type type;
 734         enum e1000_nvm_override override;
 735
 736         u32 flash_bank_size;
 737         u32 flash_base_addr;
 738
 739         u16 word_size;
 740         u16 delay_usec;
 741         u16 address_bits;
 742         u16 opcode_bits;
 743         u16 page_size;
 744 };
 745
 746 struct e1000_bus_info {
 747         enum e1000_bus_type type;
 748         enum e1000_bus_speed speed;
 749         enum e1000_bus_width width;
 750
 751         u16 func;
 752         u16 pci_cmd_word;
 753 };
 754
 755 struct e1000_fc_info {
 756         u32 high_water;          /* Flow control high-water mark */
 757         u32 low_water;           /* Flow control low-water mark */
 758         u16 pause_time;          /* Flow control pause timer */
 759         bool send_xon;           /* Flow control send XON */
 760         bool strict_ieee;        /* Strict IEEE mode */
 761         enum e1000_fc_mode current_mode; /* FC mode in effect */
 762         enum e1000_fc_mode requested_mode; /* FC mode requested by caller */
 763 };
 764
 765 struct e1000_dev_spec_82541 {
 766         enum e1000_dsp_config dsp_config;
 767         enum e1000_ffe_config ffe_config;
 768         u16 spd_default;
 769         bool phy_init_script;
 770 };
 771
 772 struct e1000_dev_spec_82542 {
 773         bool dma_fairness;
 774 };
 775
 776 struct e1000_dev_spec_82543 {
 777         u32  tbi_compatibility;
 778         bool dma_fairness;
 779         bool init_phy_disabled;
 780 };
 781
 782 struct e1000_dev_spec_82571 {
 783         bool laa_is_present;
 784         u32 smb_counter;
 785 };
 786
 787 struct e1000_dev_spec_80003es2lan {
 788         bool  mdic_wa_enable;
 789 };
 790
 791 struct e1000_shadow_ram {
 792         u16  value;
 793         bool modified;
 794 };
 795
 796 #define E1000_SHADOW_RAM_WORDS          2048
 797
 798 struct e1000_dev_spec_ich8lan {
 799         bool kmrn_lock_loss_workaround_enabled;
 800         struct e1000_shadow_ram shadow_ram[E1000_SHADOW_RAM_WORDS];
 801         E1000_MUTEX nvm_mutex;
 802         E1000_MUTEX swflag_mutex;
 803         bool nvm_k1_enabled;
 804 };
 805
 806 struct e1000_dev_spec_82575 {
 807         bool sgmii_active;
 808         bool global_device_reset;
 809 };
 810
 811 struct e1000_dev_spec_vf {
 812         u32     vf_number;
 813         u32     v2p_mailbox;
 814 };
 815
 816
 817 struct e1000_hw {
 818         void *back;
 819
 820         u8 *hw_addr;
 821         u8 *flash_address;
 822         unsigned long io_base;
 823
 824         struct e1000_mac_info  mac;
 825         struct e1000_fc_info   fc;
 826         struct e1000_phy_info  phy;
 827         struct e1000_nvm_info  nvm;
 828         struct e1000_bus_info  bus;
 829         struct e1000_host_mng_dhcp_cookie mng_cookie;
 830
 831         union {
 832                 struct e1000_dev_spec_82541     _82541;
 833                 struct e1000_dev_spec_82542     _82542;
 834                 struct e1000_dev_spec_82543     _82543;
 835                 struct e1000_dev_spec_82571     _82571;
 836                 struct e1000_dev_spec_80003es2lan _80003es2lan;
 837                 struct e1000_dev_spec_ich8lan   ich8lan;
 838                 struct e1000_dev_spec_82575     _82575;
 839                 struct e1000_dev_spec_vf        vf;
 840         } dev_spec;
 841
 842         u16 device_id;
 843         u16 subsystem_vendor_id;
 844         u16 subsystem_device_id;
 845         u16 vendor_id;
 846
 847         u8  revision_id;
 848 };
 849
 850 #include "e1000_82541.h"
 851 #include "e1000_82543.h"
 852 #include "e1000_82571.h"
 853 #include "e1000_80003es2lan.h"
 854 #include "e1000_ich8lan.h"
 855 #include "e1000_82575.h"
 856
 857 /* These functions must be implemented by drivers */
 858 void e1000_pci_clear_mwi(struct e1000_hw *hw);
 859 void e1000_pci_set_mwi(struct e1000_hw *hw);
 860 s32  e1000_read_pcie_cap_reg(struct e1000_hw *hw, u32 reg, u16 *value);
 861 s32  e1000_write_pcie_cap_reg(struct e1000_hw *hw, u32 reg, u16 *value);
 862 void e1000_read_pci_cfg(struct e1000_hw *hw, u32 reg, u16 *value);
 863 void e1000_write_pci_cfg(struct e1000_hw *hw, u32 reg, u16 *value);
 864
 865 #endif