sys/dev/netif/e1000/e1000_82575.h

   1 /******************************************************************************
   2
   3   Copyright (c) 2001-2010, Intel Corporation
   4   All rights reserved.
   5
   6   Redistribution and use in source and binary forms, with or without
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  10       this list of conditions and the following disclaimer.
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  13       notice, this list of conditions and the following disclaimer in the
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  18       this software without specific prior written permission.
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  20   THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
  21   AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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  31
  32 ******************************************************************************/
  33 /*$FreeBSD$*/
  34
  35 #ifndef _E1000_82575_H_
  36 #define _E1000_82575_H_
  37
  38 #define ID_LED_DEFAULT_82575_SERDES ((ID_LED_DEF1_DEF2 << 12) | \
  39                                      (ID_LED_DEF1_DEF2 <<  8) | \
  40                                      (ID_LED_DEF1_DEF2 <<  4) | \
  41                                      (ID_LED_OFF1_ON2))
  42 /*
  43  * Receive Address Register Count
  44  * Number of high/low register pairs in the RAR.  The RAR (Receive Address
  45  * Registers) holds the directed and multicast addresses that we monitor.
  46  * These entries are also used for MAC-based filtering.
  47  */
  48 /*
  49  * For 82576, there are an additional set of RARs that begin at an offset
  50  * separate from the first set of RARs.
  51  */
  52 #define E1000_RAR_ENTRIES_82575   16
  53 #define E1000_RAR_ENTRIES_82576   24
  54 #define E1000_RAR_ENTRIES_82580        24
  55 #define E1000_SW_SYNCH_MB              0x00000100
  56 #define E1000_STAT_DEV_RST_SET         0x00100000
  57 #define E1000_CTRL_DEV_RST             0x20000000
  58
  59 #ifdef E1000_BIT_FIELDS
  60 struct e1000_adv_data_desc {
  61         __le64 buffer_addr;    /* Address of the descriptor's data buffer */
  62         union {
  63                 u32 data;
  64                 struct {
  65                         u32 datalen :16; /* Data buffer length */
  66                         u32 rsvd    :4;
  67                         u32 dtyp    :4;  /* Descriptor type */
  68                         u32 dcmd    :8;  /* Descriptor command */
  69                 } config;
  70         } lower;
  71         union {
  72                 u32 data;
  73                 struct {
  74                         u32 status  :4;  /* Descriptor status */
  75                         u32 idx     :4;
  76                         u32 popts   :6;  /* Packet Options */
  77                         u32 paylen  :18; /* Payload length */
  78                 } options;
  79         } upper;
  80 };
  81
  82 #define E1000_TXD_DTYP_ADV_C    0x2  /* Advanced Context Descriptor */
  83 #define E1000_TXD_DTYP_ADV_D    0x3  /* Advanced Data Descriptor */
  84 #define E1000_ADV_TXD_CMD_DEXT  0x20 /* Descriptor extension (0 = legacy) */
  85 #define E1000_ADV_TUCMD_IPV4    0x2  /* IP Packet Type: 1=IPv4 */
  86 #define E1000_ADV_TUCMD_IPV6    0x0  /* IP Packet Type: 0=IPv6 */
  87 #define E1000_ADV_TUCMD_L4T_UDP 0x0  /* L4 Packet TYPE of UDP */
  88 #define E1000_ADV_TUCMD_L4T_TCP 0x4  /* L4 Packet TYPE of TCP */
  89 #define E1000_ADV_TUCMD_MKRREQ  0x10 /* Indicates markers are required */
  90 #define E1000_ADV_DCMD_EOP      0x1  /* End of Packet */
  91 #define E1000_ADV_DCMD_IFCS     0x2  /* Insert FCS (Ethernet CRC) */
  92 #define E1000_ADV_DCMD_RS       0x8  /* Report Status */
  93 #define E1000_ADV_DCMD_VLE      0x40 /* Add VLAN tag */
  94 #define E1000_ADV_DCMD_TSE      0x80 /* TCP Seg enable */
  95 /* Extended Device Control */
  96 #define E1000_CTRL_EXT_NSICR    0x00000001 /* Disable Intr Clear all on read */
  97
  98 struct e1000_adv_context_desc {
  99         union {
 100                 u32 ip_config;
 101                 struct {
 102                         u32 iplen    :9;
 103                         u32 maclen   :7;
 104                         u32 vlan_tag :16;
 105                 } fields;
 106         } ip_setup;
 107         u32 seq_num;
 108         union {
 109                 u64 l4_config;
 110                 struct {
 111                         u32 mkrloc :9;
 112                         u32 tucmd  :11;
 113                         u32 dtyp   :4;
 114                         u32 adv    :8;
 115                         u32 rsvd   :4;
 116                         u32 idx    :4;
 117                         u32 l4len  :8;
 118                         u32 mss    :16;
 119                 } fields;
 120         } l4_setup;
 121 };
 122 #endif
 123
 124 /* SRRCTL bit definitions */
 125 #define E1000_SRRCTL_BSIZEPKT_SHIFT                     10 /* Shift _right_ */
 126 #define E1000_SRRCTL_BSIZEHDRSIZE_MASK                  0x00000F00
 127 #define E1000_SRRCTL_BSIZEHDRSIZE_SHIFT                 2  /* Shift _left_ */
 128 #define E1000_SRRCTL_DESCTYPE_LEGACY                    0x00000000
 129 #define E1000_SRRCTL_DESCTYPE_ADV_ONEBUF                0x02000000
 130 #define E1000_SRRCTL_DESCTYPE_HDR_SPLIT                 0x04000000
 131 #define E1000_SRRCTL_DESCTYPE_HDR_SPLIT_ALWAYS          0x0A000000
 132 #define E1000_SRRCTL_DESCTYPE_HDR_REPLICATION           0x06000000
 133 #define E1000_SRRCTL_DESCTYPE_HDR_REPLICATION_LARGE_PKT 0x08000000
 134 #define E1000_SRRCTL_DESCTYPE_MASK                      0x0E000000
 135 #define E1000_SRRCTL_TIMESTAMP                          0x40000000
 136 #define E1000_SRRCTL_DROP_EN                            0x80000000
 137
 138 #define E1000_SRRCTL_BSIZEPKT_MASK      0x0000007F
 139 #define E1000_SRRCTL_BSIZEHDR_MASK      0x00003F00
 140
 141 #define E1000_TX_HEAD_WB_ENABLE   0x1
 142 #define E1000_TX_SEQNUM_WB_ENABLE 0x2
 143
 144 #define E1000_MRQC_ENABLE_RSS_4Q            0x00000002
 145 #define E1000_MRQC_ENABLE_VMDQ              0x00000003
 146 #define E1000_MRQC_ENABLE_VMDQ_RSS_2Q       0x00000005
 147 #define E1000_MRQC_RSS_FIELD_IPV4_UDP       0x00400000
 148 #define E1000_MRQC_RSS_FIELD_IPV6_UDP       0x00800000
 149 #define E1000_MRQC_RSS_FIELD_IPV6_UDP_EX    0x01000000
 150 #define E1000_MRQC_ENABLE_RSS_8Q            0x00000002
 151
 152 #define E1000_VMRCTL_MIRROR_PORT_SHIFT      8
 153 #define E1000_VMRCTL_MIRROR_DSTPORT_MASK    (7 << E1000_VMRCTL_MIRROR_PORT_SHIFT)
 154 #define E1000_VMRCTL_POOL_MIRROR_ENABLE     (1 << 0)
 155 #define E1000_VMRCTL_UPLINK_MIRROR_ENABLE   (1 << 1)
 156 #define E1000_VMRCTL_DOWNLINK_MIRROR_ENABLE (1 << 2)
 157
 158 #define E1000_EICR_TX_QUEUE ( \
 159     E1000_EICR_TX_QUEUE0 |    \
 160     E1000_EICR_TX_QUEUE1 |    \
 161     E1000_EICR_TX_QUEUE2 |    \
 162     E1000_EICR_TX_QUEUE3)
 163
 164 #define E1000_EICR_RX_QUEUE ( \
 165     E1000_EICR_RX_QUEUE0 |    \
 166     E1000_EICR_RX_QUEUE1 |    \
 167     E1000_EICR_RX_QUEUE2 |    \
 168     E1000_EICR_RX_QUEUE3)
 169
 170 #define E1000_EIMS_RX_QUEUE E1000_EICR_RX_QUEUE
 171 #define E1000_EIMS_TX_QUEUE E1000_EICR_TX_QUEUE
 172
 173 #define EIMS_ENABLE_MASK ( \
 174     E1000_EIMS_RX_QUEUE  | \
 175     E1000_EIMS_TX_QUEUE  | \
 176     E1000_EIMS_TCP_TIMER | \
 177     E1000_EIMS_OTHER)
 178
 179 /* Immediate Interrupt Rx (A.K.A. Low Latency Interrupt) */
 180 #define E1000_IMIR_PORT_IM_EN     0x00010000  /* TCP port enable */
 181 #define E1000_IMIR_PORT_BP        0x00020000  /* TCP port check bypass */
 182 #define E1000_IMIREXT_SIZE_BP     0x00001000  /* Packet size bypass */
 183 #define E1000_IMIREXT_CTRL_URG    0x00002000  /* Check URG bit in header */
 184 #define E1000_IMIREXT_CTRL_ACK    0x00004000  /* Check ACK bit in header */
 185 #define E1000_IMIREXT_CTRL_PSH    0x00008000  /* Check PSH bit in header */
 186 #define E1000_IMIREXT_CTRL_RST    0x00010000  /* Check RST bit in header */
 187 #define E1000_IMIREXT_CTRL_SYN    0x00020000  /* Check SYN bit in header */
 188 #define E1000_IMIREXT_CTRL_FIN    0x00040000  /* Check FIN bit in header */
 189 #define E1000_IMIREXT_CTRL_BP     0x00080000  /* Bypass check of ctrl bits */
 190
 191 /* Receive Descriptor - Advanced */
 192 union e1000_adv_rx_desc {
 193         struct {
 194                 __le64 pkt_addr;             /* Packet buffer address */
 195                 __le64 hdr_addr;             /* Header buffer address */
 196         } read;
 197         struct {
 198                 struct {
 199                         union {
 200                                 __le32 data;
 201                                 struct {
 202                                         __le16 pkt_info; /*RSS type, Pkt type*/
 203                                         __le16 hdr_info; /* Split Header,
 204                                                           * header buffer len*/
 205                                 } hs_rss;
 206                         } lo_dword;
 207                         union {
 208                                 __le32 rss;          /* RSS Hash */
 209                                 struct {
 210                                         __le16 ip_id;    /* IP id */
 211                                         __le16 csum;     /* Packet Checksum */
 212                                 } csum_ip;
 213                         } hi_dword;
 214                 } lower;
 215                 struct {
 216                         __le32 status_error;     /* ext status/error */
 217                         __le16 length;           /* Packet length */
 218                         __le16 vlan;             /* VLAN tag */
 219                 } upper;
 220         } wb;  /* writeback */
 221 };
 222
 223 #define E1000_RXDADV_RSSTYPE_MASK        0x0000000F
 224 #define E1000_RXDADV_RSSTYPE_SHIFT       12
 225 #define E1000_RXDADV_HDRBUFLEN_MASK      0x7FE0
 226 #define E1000_RXDADV_HDRBUFLEN_SHIFT     5
 227 #define E1000_RXDADV_SPLITHEADER_EN      0x00001000
 228 #define E1000_RXDADV_SPH                 0x8000
 229 #define E1000_RXDADV_STAT_TS             0x10000 /* Pkt was time stamped */
 230 #define E1000_RXDADV_STAT_TSIP           0x08000 /* timestamp in packet */
 231 #define E1000_RXDADV_ERR_HBO             0x00800000
 232
 233 /* RSS Hash results */
 234 #define E1000_RXDADV_RSSTYPE_NONE        0x00000000
 235 #define E1000_RXDADV_RSSTYPE_IPV4_TCP    0x00000001
 236 #define E1000_RXDADV_RSSTYPE_IPV4        0x00000002
 237 #define E1000_RXDADV_RSSTYPE_IPV6_TCP    0x00000003
 238 #define E1000_RXDADV_RSSTYPE_IPV6_EX     0x00000004
 239 #define E1000_RXDADV_RSSTYPE_IPV6        0x00000005
 240 #define E1000_RXDADV_RSSTYPE_IPV6_TCP_EX 0x00000006
 241 #define E1000_RXDADV_RSSTYPE_IPV4_UDP    0x00000007
 242 #define E1000_RXDADV_RSSTYPE_IPV6_UDP    0x00000008
 243 #define E1000_RXDADV_RSSTYPE_IPV6_UDP_EX 0x00000009
 244
 245 /* RSS Packet Types as indicated in the receive descriptor */
 246 #define E1000_RXDADV_PKTTYPE_NONE        0x00000000
 247 #define E1000_RXDADV_PKTTYPE_IPV4        0x00000010 /* IPV4 hdr present */
 248 #define E1000_RXDADV_PKTTYPE_IPV4_EX     0x00000020 /* IPV4 hdr + extensions */
 249 #define E1000_RXDADV_PKTTYPE_IPV6        0x00000040 /* IPV6 hdr present */
 250 #define E1000_RXDADV_PKTTYPE_IPV6_EX     0x00000080 /* IPV6 hdr + extensions */
 251 #define E1000_RXDADV_PKTTYPE_TCP         0x00000100 /* TCP hdr present */
 252 #define E1000_RXDADV_PKTTYPE_UDP         0x00000200 /* UDP hdr present */
 253 #define E1000_RXDADV_PKTTYPE_SCTP        0x00000400 /* SCTP hdr present */
 254 #define E1000_RXDADV_PKTTYPE_NFS         0x00000800 /* NFS hdr present */
 255
 256 #define E1000_RXDADV_PKTTYPE_IPSEC_ESP   0x00001000 /* IPSec ESP */
 257 #define E1000_RXDADV_PKTTYPE_IPSEC_AH    0x00002000 /* IPSec AH */
 258 #define E1000_RXDADV_PKTTYPE_LINKSEC     0x00004000 /* LinkSec Encap */
 259 #define E1000_RXDADV_PKTTYPE_ETQF        0x00008000 /* PKTTYPE is ETQF index */
 260 #define E1000_RXDADV_PKTTYPE_ETQF_MASK   0x00000070 /* ETQF has 8 indices */
 261 #define E1000_RXDADV_PKTTYPE_ETQF_SHIFT  4          /* Right-shift 4 bits */
 262
 263 /* LinkSec results */
 264 /* Security Processing bit Indication */
 265 #define E1000_RXDADV_LNKSEC_STATUS_SECP         0x00020000
 266 #define E1000_RXDADV_LNKSEC_ERROR_BIT_MASK      0x18000000
 267 #define E1000_RXDADV_LNKSEC_ERROR_NO_SA_MATCH   0x08000000
 268 #define E1000_RXDADV_LNKSEC_ERROR_REPLAY_ERROR  0x10000000
 269 #define E1000_RXDADV_LNKSEC_ERROR_BAD_SIG       0x18000000
 270
 271 #define E1000_RXDADV_IPSEC_STATUS_SECP          0x00020000
 272 #define E1000_RXDADV_IPSEC_ERROR_BIT_MASK       0x18000000
 273 #define E1000_RXDADV_IPSEC_ERROR_INVALID_PROTOCOL       0x08000000
 274 #define E1000_RXDADV_IPSEC_ERROR_INVALID_LENGTH         0x10000000
 275 #define E1000_RXDADV_IPSEC_ERROR_AUTHENTICATION_FAILED  0x18000000
 276
 277 /* Transmit Descriptor - Advanced */
 278 union e1000_adv_tx_desc {
 279         struct {
 280                 __le64 buffer_addr;    /* Address of descriptor's data buf */
 281                 __le32 cmd_type_len;
 282                 __le32 olinfo_status;
 283         } read;
 284         struct {
 285                 __le64 rsvd;       /* Reserved */
 286                 __le32 nxtseq_seed;
 287                 __le32 status;
 288         } wb;
 289 };
 290
 291 /* Adv Transmit Descriptor Config Masks */
 292 #define E1000_ADVTXD_DTYP_CTXT    0x00200000 /* Advanced Context Descriptor */
 293 #define E1000_ADVTXD_DTYP_DATA    0x00300000 /* Advanced Data Descriptor */
 294 #define E1000_ADVTXD_DCMD_EOP     0x01000000 /* End of Packet */
 295 #define E1000_ADVTXD_DCMD_IFCS    0x02000000 /* Insert FCS (Ethernet CRC) */
 296 #define E1000_ADVTXD_DCMD_RS      0x08000000 /* Report Status */
 297 #define E1000_ADVTXD_DCMD_DDTYP_ISCSI  0x10000000 /* DDP hdr type or iSCSI */
 298 #define E1000_ADVTXD_DCMD_DEXT    0x20000000 /* Descriptor extension (1=Adv) */
 299 #define E1000_ADVTXD_DCMD_VLE     0x40000000 /* VLAN pkt enable */
 300 #define E1000_ADVTXD_DCMD_TSE     0x80000000 /* TCP Seg enable */
 301 #define E1000_ADVTXD_MAC_LINKSEC  0x00040000 /* Apply LinkSec on packet */
 302 #define E1000_ADVTXD_MAC_TSTAMP   0x00080000 /* IEEE1588 Timestamp packet */
 303 #define E1000_ADVTXD_STAT_SN_CRC  0x00000002 /* NXTSEQ/SEED present in WB */
 304 #define E1000_ADVTXD_IDX_SHIFT    4  /* Adv desc Index shift */
 305 #define E1000_ADVTXD_POPTS_ISCO_1ST  0x00000000 /* 1st TSO of iSCSI PDU */
 306 #define E1000_ADVTXD_POPTS_ISCO_MDL  0x00000800 /* Middle TSO of iSCSI PDU */
 307 #define E1000_ADVTXD_POPTS_ISCO_LAST 0x00001000 /* Last TSO of iSCSI PDU */
 308 #define E1000_ADVTXD_POPTS_ISCO_FULL 0x00001800 /* 1st&Last TSO-full iSCSI PDU*/
 309 #define E1000_ADVTXD_POPTS_IPSEC     0x00000400 /* IPSec offload request */
 310 #define E1000_ADVTXD_PAYLEN_SHIFT    14 /* Adv desc PAYLEN shift */
 311
 312 /* Context descriptors */
 313 struct e1000_adv_tx_context_desc {
 314         __le32 vlan_macip_lens;
 315         __le32 seqnum_seed;
 316         __le32 type_tucmd_mlhl;
 317         __le32 mss_l4len_idx;
 318 };
 319
 320 #define E1000_ADVTXD_MACLEN_SHIFT    9  /* Adv ctxt desc mac len shift */
 321 #define E1000_ADVTXD_VLAN_SHIFT     16  /* Adv ctxt vlan tag shift */
 322 #define E1000_ADVTXD_TUCMD_IPV4    0x00000400  /* IP Packet Type: 1=IPv4 */
 323 #define E1000_ADVTXD_TUCMD_IPV6    0x00000000  /* IP Packet Type: 0=IPv6 */
 324 #define E1000_ADVTXD_TUCMD_L4T_UDP 0x00000000  /* L4 Packet TYPE of UDP */
 325 #define E1000_ADVTXD_TUCMD_L4T_TCP 0x00000800  /* L4 Packet TYPE of TCP */
 326 #define E1000_ADVTXD_TUCMD_L4T_SCTP 0x00001000  /* L4 Packet TYPE of SCTP */
 327 #define E1000_ADVTXD_TUCMD_IPSEC_TYPE_ESP    0x00002000 /* IPSec Type ESP */
 328 /* IPSec Encrypt Enable for ESP */
 329 #define E1000_ADVTXD_TUCMD_IPSEC_ENCRYPT_EN  0x00004000
 330 #define E1000_ADVTXD_TUCMD_MKRREQ  0x00002000 /* Req requires Markers and CRC */
 331 #define E1000_ADVTXD_L4LEN_SHIFT     8  /* Adv ctxt L4LEN shift */
 332 #define E1000_ADVTXD_MSS_SHIFT      16  /* Adv ctxt MSS shift */
 333 /* Adv ctxt IPSec SA IDX mask */
 334 #define E1000_ADVTXD_IPSEC_SA_INDEX_MASK     0x000000FF
 335 /* Adv ctxt IPSec ESP len mask */
 336 #define E1000_ADVTXD_IPSEC_ESP_LEN_MASK      0x000000FF
 337
 338 /* Additional Transmit Descriptor Control definitions */
 339 #define E1000_TXDCTL_QUEUE_ENABLE  0x02000000 /* Enable specific Tx Queue */
 340 #define E1000_TXDCTL_SWFLSH        0x04000000 /* Tx Desc. write-back flushing */
 341 /* Tx Queue Arbitration Priority 0=low, 1=high */
 342 #define E1000_TXDCTL_PRIORITY      0x08000000
 343
 344 /* Additional Receive Descriptor Control definitions */
 345 #define E1000_RXDCTL_QUEUE_ENABLE  0x02000000 /* Enable specific Rx Queue */
 346 #define E1000_RXDCTL_SWFLSH        0x04000000 /* Rx Desc. write-back flushing */
 347
 348 /* Direct Cache Access (DCA) definitions */
 349 #define E1000_DCA_CTRL_DCA_ENABLE  0x00000000 /* DCA Enable */
 350 #define E1000_DCA_CTRL_DCA_DISABLE 0x00000001 /* DCA Disable */
 351
 352 #define E1000_DCA_CTRL_DCA_MODE_CB1 0x00 /* DCA Mode CB1 */
 353 #define E1000_DCA_CTRL_DCA_MODE_CB2 0x02 /* DCA Mode CB2 */
 354
 355 #define E1000_DCA_RXCTRL_CPUID_MASK 0x0000001F /* Rx CPUID Mask */
 356 #define E1000_DCA_RXCTRL_DESC_DCA_EN (1 << 5) /* DCA Rx Desc enable */
 357 #define E1000_DCA_RXCTRL_HEAD_DCA_EN (1 << 6) /* DCA Rx Desc header enable */
 358 #define E1000_DCA_RXCTRL_DATA_DCA_EN (1 << 7) /* DCA Rx Desc payload enable */
 359
 360 #define E1000_DCA_TXCTRL_CPUID_MASK 0x0000001F /* Tx CPUID Mask */
 361 #define E1000_DCA_TXCTRL_DESC_DCA_EN (1 << 5) /* DCA Tx Desc enable */
 362 #define E1000_DCA_TXCTRL_TX_WB_RO_EN (1 << 11) /* Tx Desc writeback RO bit */
 363
 364 #define E1000_DCA_TXCTRL_CPUID_MASK_82576 0xFF000000 /* Tx CPUID Mask */
 365 #define E1000_DCA_RXCTRL_CPUID_MASK_82576 0xFF000000 /* Rx CPUID Mask */
 366 #define E1000_DCA_TXCTRL_CPUID_SHIFT_82576 24 /* Tx CPUID */
 367 #define E1000_DCA_RXCTRL_CPUID_SHIFT_82576 24 /* Rx CPUID */
 368
 369 /* Additional interrupt register bit definitions */
 370 #define E1000_ICR_LSECPNS       0x00000020          /* PN threshold - server */
 371 #define E1000_IMS_LSECPNS       E1000_ICR_LSECPNS   /* PN threshold - server */
 372 #define E1000_ICS_LSECPNS       E1000_ICR_LSECPNS   /* PN threshold - server */
 373
 374 /* ETQF register bit definitions */
 375 #define E1000_ETQF_FILTER_ENABLE   (1 << 26)
 376 #define E1000_ETQF_IMM_INT         (1 << 29)
 377 #define E1000_ETQF_1588            (1 << 30)
 378 #define E1000_ETQF_QUEUE_ENABLE    (1 << 31)
 379 /*
 380  * ETQF filter list: one static filter per filter consumer. This is
 381  *                   to avoid filter collisions later. Add new filters
 382  *                   here!!
 383  *
 384  * Current filters:
 385  *    EAPOL 802.1x (0x888e): Filter 0
 386  */
 387 #define E1000_ETQF_FILTER_EAPOL          0
 388
 389 #define E1000_FTQF_VF_BP               0x00008000
 390 #define E1000_FTQF_1588_TIME_STAMP     0x08000000
 391 #define E1000_FTQF_MASK                0xF0000000
 392 #define E1000_FTQF_MASK_PROTO_BP       0x10000000
 393 #define E1000_FTQF_MASK_SOURCE_ADDR_BP 0x20000000
 394 #define E1000_FTQF_MASK_DEST_ADDR_BP   0x40000000
 395 #define E1000_FTQF_MASK_SOURCE_PORT_BP 0x80000000
 396
 397 #define E1000_NVM_APME_82575          0x0400
 398 #define MAX_NUM_VFS                   8
 399
 400 #define E1000_DTXSWC_MAC_SPOOF_MASK   0x000000FF /* Per VF MAC spoof control */
 401 #define E1000_DTXSWC_VLAN_SPOOF_MASK  0x0000FF00 /* Per VF VLAN spoof control */
 402 #define E1000_DTXSWC_LLE_MASK         0x00FF0000 /* Per VF Local LB enables */
 403 #define E1000_DTXSWC_VLAN_SPOOF_SHIFT 8
 404 #define E1000_DTXSWC_LLE_SHIFT        16
 405 #define E1000_DTXSWC_VMDQ_LOOPBACK_EN (1 << 31)  /* global VF LB enable */
 406
 407 /* Easy defines for setting default pool, would normally be left a zero */
 408 #define E1000_VT_CTL_DEFAULT_POOL_SHIFT 7
 409 #define E1000_VT_CTL_DEFAULT_POOL_MASK  (0x7 << E1000_VT_CTL_DEFAULT_POOL_SHIFT)
 410
 411 /* Other useful VMD_CTL register defines */
 412 #define E1000_VT_CTL_IGNORE_MAC         (1 << 28)
 413 #define E1000_VT_CTL_DISABLE_DEF_POOL   (1 << 29)
 414 #define E1000_VT_CTL_VM_REPL_EN         (1 << 30)
 415
 416 /* Per VM Offload register setup */
 417 #define E1000_VMOLR_RLPML_MASK 0x00003FFF /* Long Packet Maximum Length mask */
 418 #define E1000_VMOLR_LPE        0x00010000 /* Accept Long packet */
 419 #define E1000_VMOLR_RSSE       0x00020000 /* Enable RSS */
 420 #define E1000_VMOLR_AUPE       0x01000000 /* Accept untagged packets */
 421 #define E1000_VMOLR_ROMPE      0x02000000 /* Accept overflow multicast */
 422 #define E1000_VMOLR_ROPE       0x04000000 /* Accept overflow unicast */
 423 #define E1000_VMOLR_BAM        0x08000000 /* Accept Broadcast packets */
 424 #define E1000_VMOLR_MPME       0x10000000 /* Multicast promiscuous mode */
 425 #define E1000_VMOLR_STRVLAN    0x40000000 /* Vlan stripping enable */
 426 #define E1000_VMOLR_STRCRC     0x80000000 /* CRC stripping enable */
 427
 428 #define E1000_VLVF_ARRAY_SIZE     32
 429 #define E1000_VLVF_VLANID_MASK    0x00000FFF
 430 #define E1000_VLVF_POOLSEL_SHIFT  12
 431 #define E1000_VLVF_POOLSEL_MASK   (0xFF << E1000_VLVF_POOLSEL_SHIFT)
 432 #define E1000_VLVF_LVLAN          0x00100000
 433 #define E1000_VLVF_VLANID_ENABLE  0x80000000
 434
 435 #define E1000_VMVIR_VLANA_DEFAULT 0x40000000 /* Always use default VLAN */
 436 #define E1000_VMVIR_VLANA_NEVER   0x80000000 /* Never insert VLAN tag */
 437
 438 #define E1000_VF_INIT_TIMEOUT 200 /* Number of retries to clear RSTI */
 439
 440 #define E1000_IOVCTL 0x05BBC
 441 #define E1000_IOVCTL_REUSE_VFQ 0x00000001
 442
 443 #define E1000_RPLOLR_STRVLAN   0x40000000
 444 #define E1000_RPLOLR_STRCRC    0x80000000
 445
 446 #define E1000_TCTL_EXT_COLD       0x000FFC00
 447 #define E1000_TCTL_EXT_COLD_SHIFT 10
 448
 449 #define E1000_DTXCTL_8023LL     0x0004
 450 #define E1000_DTXCTL_VLAN_ADDED 0x0008
 451 #define E1000_DTXCTL_OOS_ENABLE 0x0010
 452 #define E1000_DTXCTL_MDP_EN     0x0020
 453 #define E1000_DTXCTL_SPOOF_INT  0x0040
 454
 455 #define ALL_QUEUES   0xFFFF
 456
 457 /* RX packet buffer size defines */
 458 #define E1000_RXPBS_SIZE_MASK_82576  0x0000007F
 459 void e1000_vmdq_set_loopback_pf(struct e1000_hw *hw, bool enable);
 460 void e1000_vmdq_set_replication_pf(struct e1000_hw *hw, bool enable);
 461 u16 e1000_rxpbs_adjust_82580(u32 data);
 462 #endif /* _E1000_82575_H_ */