sys/dev/drm/radeon_irq.c

   1 /* radeon_irq.c -- IRQ handling for radeon -*- linux-c -*- */
   2 /*-
   3  * Copyright (C) The Weather Channel, Inc.  2002.  All Rights Reserved.
   4  *
   5  * The Weather Channel (TM) funded Tungsten Graphics to develop the
   6  * initial release of the Radeon 8500 driver under the XFree86 license.
   7  * This notice must be preserved.
   8  *
   9  * Permission is hereby granted, free of charge, to any person obtaining a
  10  * copy of this software and associated documentation files (the "Software"),
  11  * to deal in the Software without restriction, including without limitation
  12  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
  13  * and/or sell copies of the Software, and to permit persons to whom the
  14  * Software is furnished to do so, subject to the following conditions:
  15  *
  16  * The above copyright notice and this permission notice (including the next
  17  * paragraph) shall be included in all copies or substantial portions of the
  18  * Software.
  19  *
  20  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  21  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  22  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  23  * PRECISION INSIGHT AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
  24  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  25  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
  26  * DEALINGS IN THE SOFTWARE.
  27  *
  28  * Authors:
  29  *    Keith Whitwell <keith@tungstengraphics.com>
  30  *    Michel D�zer <michel@daenzer.net>
  31  */
  32
  33 #include "dev/drm/drmP.h"
  34 #include "dev/drm/drm.h"
  35 #include "dev/drm/radeon_drm.h"
  36 #include "dev/drm/radeon_drv.h"
  37
  38 void radeon_irq_set_state(struct drm_device *dev, u32 mask, int state)
  39 {
  40         drm_radeon_private_t *dev_priv = dev->dev_private;
  41
  42         if (state)
  43                 dev_priv->irq_enable_reg |= mask;
  44         else
  45                 dev_priv->irq_enable_reg &= ~mask;
  46
  47         if (dev->irq_enabled)
  48                 RADEON_WRITE(RADEON_GEN_INT_CNTL, dev_priv->irq_enable_reg);
  49 }
  50
  51 static void r500_vbl_irq_set_state(struct drm_device *dev, u32 mask, int state)
  52 {
  53         drm_radeon_private_t *dev_priv = dev->dev_private;
  54
  55         if (state)
  56                 dev_priv->r500_disp_irq_reg |= mask;
  57         else
  58                 dev_priv->r500_disp_irq_reg &= ~mask;
  59
  60         if (dev->irq_enabled)
  61                 RADEON_WRITE(R500_DxMODE_INT_MASK, dev_priv->r500_disp_irq_reg);
  62 }
  63
  64 int radeon_enable_vblank(struct drm_device *dev, int crtc)
  65 {
  66         drm_radeon_private_t *dev_priv = dev->dev_private;
  67
  68         if ((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_RS600) {
  69                 switch (crtc) {
  70                 case 0:
  71                         r500_vbl_irq_set_state(dev, R500_D1MODE_INT_MASK, 1);
  72                         break;
  73                 case 1:
  74                         r500_vbl_irq_set_state(dev, R500_D2MODE_INT_MASK, 1);
  75                         break;
  76                 default:
  77                         DRM_ERROR("tried to enable vblank on non-existent crtc %d\n",
  78                                   crtc);
  79                         return EINVAL;
  80                 }
  81         } else {
  82                 switch (crtc) {
  83                 case 0:
  84                         radeon_irq_set_state(dev, RADEON_CRTC_VBLANK_MASK, 1);
  85                         break;
  86                 case 1:
  87                         radeon_irq_set_state(dev, RADEON_CRTC2_VBLANK_MASK, 1);
  88                         break;
  89                 default:
  90                         DRM_ERROR("tried to enable vblank on non-existent crtc %d\n",
  91                                   crtc);
  92                         return EINVAL;
  93                 }
  94         }
  95
  96         return 0;
  97 }
  98
  99 void radeon_disable_vblank(struct drm_device *dev, int crtc)
 100 {
 101         drm_radeon_private_t *dev_priv = dev->dev_private;
 102
 103         if ((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_RS600) {
 104                 switch (crtc) {
 105                 case 0:
 106                         r500_vbl_irq_set_state(dev, R500_D1MODE_INT_MASK, 0);
 107                         break;
 108                 case 1:
 109                         r500_vbl_irq_set_state(dev, R500_D2MODE_INT_MASK, 0);
 110                         break;
 111                 default:
 112                         DRM_ERROR("tried to enable vblank on non-existent crtc %d\n",
 113                                   crtc);
 114                         break;
 115                 }
 116         } else {
 117                 switch (crtc) {
 118                 case 0:
 119                         radeon_irq_set_state(dev, RADEON_CRTC_VBLANK_MASK, 0);
 120                         break;
 121                 case 1:
 122                         radeon_irq_set_state(dev, RADEON_CRTC2_VBLANK_MASK, 0);
 123                         break;
 124                 default:
 125                         DRM_ERROR("tried to enable vblank on non-existent crtc %d\n",
 126                                   crtc);
 127                         break;
 128                 }
 129         }
 130 }
 131
 132 static __inline__ u32 radeon_acknowledge_irqs(drm_radeon_private_t * dev_priv, u32 *r500_disp_int)
 133 {
 134         u32 irqs = RADEON_READ(RADEON_GEN_INT_STATUS);
 135         u32 irq_mask = RADEON_SW_INT_TEST;
 136
 137         *r500_disp_int = 0;
 138         if ((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_RS600) {
 139                 /* vbl interrupts in a different place */
 140
 141                 if (irqs & R500_DISPLAY_INT_STATUS) {
 142                         /* if a display interrupt */
 143                         u32 disp_irq;
 144
 145                         disp_irq = RADEON_READ(R500_DISP_INTERRUPT_STATUS);
 146
 147                         *r500_disp_int = disp_irq;
 148                         if (disp_irq & R500_D1_VBLANK_INTERRUPT) {
 149                                 RADEON_WRITE(R500_D1MODE_VBLANK_STATUS, R500_VBLANK_ACK);
 150                         }
 151                         if (disp_irq & R500_D2_VBLANK_INTERRUPT) {
 152                                 RADEON_WRITE(R500_D2MODE_VBLANK_STATUS, R500_VBLANK_ACK);
 153                         }
 154                 }
 155                 irq_mask |= R500_DISPLAY_INT_STATUS;
 156         } else
 157                 irq_mask |= RADEON_CRTC_VBLANK_STAT | RADEON_CRTC2_VBLANK_STAT;
 158
 159         irqs &= irq_mask;
 160
 161         if (irqs)
 162                 RADEON_WRITE(RADEON_GEN_INT_STATUS, irqs);
 163
 164         return irqs;
 165 }
 166
 167 /* Interrupts - Used for device synchronization and flushing in the
 168  * following circumstances:
 169  *
 170  * - Exclusive FB access with hw idle:
 171  *    - Wait for GUI Idle (?) interrupt, then do normal flush.
 172  *
 173  * - Frame throttling, NV_fence:
 174  *    - Drop marker irq's into command stream ahead of time.
 175  *    - Wait on irq's with lock *not held*
 176  *    - Check each for termination condition
 177  *
 178  * - Internally in cp_getbuffer, etc:
 179  *    - as above, but wait with lock held???
 180  *
 181  * NOTE: These functions are misleadingly named -- the irq's aren't
 182  * tied to dma at all, this is just a hangover from dri prehistory.
 183  */
 184
 185 irqreturn_t radeon_driver_irq_handler(DRM_IRQ_ARGS)
 186 {
 187         struct drm_device *dev = (struct drm_device *) arg;
 188         drm_radeon_private_t *dev_priv =
 189             (drm_radeon_private_t *) dev->dev_private;
 190         u32 stat;
 191         u32 r500_disp_int;
 192         u32 tmp;
 193
 194         /* Only consider the bits we're interested in - others could be used
 195          * outside the DRM
 196          */
 197         stat = radeon_acknowledge_irqs(dev_priv, &r500_disp_int);
 198         if (!stat)
 199                 return IRQ_NONE;
 200
 201         stat &= dev_priv->irq_enable_reg;
 202
 203         /* SW interrupt */
 204         if (stat & RADEON_SW_INT_TEST)
 205                 DRM_WAKEUP(&dev_priv->swi_queue);
 206
 207         /* VBLANK interrupt */
 208         if ((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_RS600) {
 209                 if (r500_disp_int & R500_D1_VBLANK_INTERRUPT)
 210                         drm_handle_vblank(dev, 0);
 211                 if (r500_disp_int & R500_D2_VBLANK_INTERRUPT)
 212                         drm_handle_vblank(dev, 1);
 213         } else {
 214                 if (stat & RADEON_CRTC_VBLANK_STAT)
 215                         drm_handle_vblank(dev, 0);
 216                 if (stat & RADEON_CRTC2_VBLANK_STAT)
 217                         drm_handle_vblank(dev, 1);
 218         }
 219         if (dev->msi_enabled) {
 220                 switch(dev_priv->flags & RADEON_FAMILY_MASK) {
 221                         case CHIP_RS400:
 222                         case CHIP_RS480:
 223                                 tmp = RADEON_READ(RADEON_AIC_CNTL) &
 224                                     ~RS400_MSI_REARM;
 225                                 RADEON_WRITE(RADEON_AIC_CNTL, tmp);
 226                                 RADEON_WRITE(RADEON_AIC_CNTL,
 227                                     tmp | RS400_MSI_REARM);
 228                                 break;
 229                         case CHIP_RS600:
 230                         case CHIP_RS690:
 231                         case CHIP_RS740:
 232                                 tmp = RADEON_READ(RADEON_BUS_CNTL) &
 233                                     ~RS600_MSI_REARM;
 234                                 RADEON_WRITE(RADEON_BUS_CNTL, tmp);
 235                                 RADEON_WRITE(RADEON_BUS_CNTL, tmp |
 236                                     RS600_MSI_REARM);
 237                                 break;
 238                          default:
 239                                 tmp = RADEON_READ(RADEON_MSI_REARM_EN) &
 240                                     ~RV370_MSI_REARM_EN;
 241                                 RADEON_WRITE(RADEON_MSI_REARM_EN, tmp);
 242                                 RADEON_WRITE(RADEON_MSI_REARM_EN,
 243                                     tmp | RV370_MSI_REARM_EN);
 244                                 break;
 245                 }
 246         }
 247         return IRQ_HANDLED;
 248 }
 249
 250 static int radeon_emit_irq(struct drm_device * dev)
 251 {
 252         drm_radeon_private_t *dev_priv = dev->dev_private;
 253         unsigned int ret;
 254         RING_LOCALS;
 255
 256         atomic_inc(&dev_priv->swi_emitted);
 257         ret = atomic_read(&dev_priv->swi_emitted);
 258
 259         BEGIN_RING(4);
 260         OUT_RING_REG(RADEON_LAST_SWI_REG, ret);
 261         OUT_RING_REG(RADEON_GEN_INT_STATUS, RADEON_SW_INT_FIRE);
 262         ADVANCE_RING();
 263         COMMIT_RING();
 264
 265         return ret;
 266 }
 267
 268 static int radeon_wait_irq(struct drm_device * dev, int swi_nr)
 269 {
 270         drm_radeon_private_t *dev_priv =
 271             (drm_radeon_private_t *) dev->dev_private;
 272         int ret = 0;
 273
 274         if (RADEON_READ(RADEON_LAST_SWI_REG) >= swi_nr)
 275                 return 0;
 276
 277         dev_priv->stats.boxes |= RADEON_BOX_WAIT_IDLE;
 278
 279         DRM_WAIT_ON(ret, dev_priv->swi_queue, 3 * DRM_HZ,
 280                     RADEON_READ(RADEON_LAST_SWI_REG) >= swi_nr);
 281
 282         if (ret == -ERESTART)
 283                 DRM_DEBUG("restarting syscall");
 284
 285         return ret;
 286 }
 287
 288 u32 radeon_get_vblank_counter(struct drm_device *dev, int crtc)
 289 {
 290         drm_radeon_private_t *dev_priv = dev->dev_private;
 291
 292         if (!dev_priv) {
 293                 DRM_ERROR("called with no initialization\n");
 294                 return -EINVAL;
 295         }
 296
 297         if (crtc < 0 || crtc > 1) {
 298                 DRM_ERROR("Invalid crtc %d\n", crtc);
 299                 return -EINVAL;
 300         }
 301
 302         if ((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_RS600) {
 303                 if (crtc == 0)
 304                         return RADEON_READ(R500_D1CRTC_FRAME_COUNT);
 305                 else
 306                         return RADEON_READ(R500_D2CRTC_FRAME_COUNT);
 307         } else {
 308                 if (crtc == 0)
 309                         return RADEON_READ(RADEON_CRTC_CRNT_FRAME);
 310                 else
 311                         return RADEON_READ(RADEON_CRTC2_CRNT_FRAME);
 312         }
 313 }
 314
 315 /* Needs the lock as it touches the ring.
 316  */
 317 int radeon_irq_emit(struct drm_device *dev, void *data, struct drm_file *file_priv)
 318 {
 319         drm_radeon_private_t *dev_priv = dev->dev_private;
 320         drm_radeon_irq_emit_t *emit = data;
 321         int result;
 322
 323         LOCK_TEST_WITH_RETURN(dev, file_priv);
 324
 325         if (!dev_priv) {
 326                 DRM_ERROR("called with no initialization\n");
 327                 return -EINVAL;
 328         }
 329
 330         result = radeon_emit_irq(dev);
 331
 332         if (DRM_COPY_TO_USER(emit->irq_seq, &result, sizeof(int))) {
 333                 DRM_ERROR("copy_to_user\n");
 334                 return -EFAULT;
 335         }
 336
 337         return 0;
 338 }
 339
 340 /* Doesn't need the hardware lock.
 341  */
 342 int radeon_irq_wait(struct drm_device *dev, void *data, struct drm_file *file_priv)
 343 {
 344         drm_radeon_private_t *dev_priv = dev->dev_private;
 345         drm_radeon_irq_wait_t *irqwait = data;
 346
 347         if (!dev_priv) {
 348                 DRM_ERROR("called with no initialization\n");
 349                 return -EINVAL;
 350         }
 351
 352         return radeon_wait_irq(dev, irqwait->irq_seq);
 353 }
 354
 355 /* drm_dma.h hooks
 356 */
 357 void radeon_driver_irq_preinstall(struct drm_device * dev)
 358 {
 359         drm_radeon_private_t *dev_priv =
 360             (drm_radeon_private_t *) dev->dev_private;
 361         u32 dummy;
 362
 363         /* Disable *all* interrupts */
 364         if ((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_RS600)
 365                 RADEON_WRITE(R500_DxMODE_INT_MASK, 0);
 366         RADEON_WRITE(RADEON_GEN_INT_CNTL, 0);
 367
 368         /* Clear bits if they're already high */
 369         radeon_acknowledge_irqs(dev_priv, &dummy);
 370 }
 371
 372 int radeon_driver_irq_postinstall(struct drm_device * dev)
 373 {
 374         drm_radeon_private_t *dev_priv =
 375             (drm_radeon_private_t *) dev->dev_private;
 376
 377         atomic_set(&dev_priv->swi_emitted, 0);
 378         DRM_INIT_WAITQUEUE(&dev_priv->swi_queue);
 379
 380         radeon_irq_set_state(dev, RADEON_SW_INT_ENABLE, 1);
 381
 382         return 0;
 383 }
 384
 385 void radeon_driver_irq_uninstall(struct drm_device * dev)
 386 {
 387         drm_radeon_private_t *dev_priv =
 388             (drm_radeon_private_t *) dev->dev_private;
 389         if (!dev_priv)
 390                 return;
 391
 392         dev_priv->irq_enabled = 0;
 393
 394         if ((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_RS600)
 395                 RADEON_WRITE(R500_DxMODE_INT_MASK, 0);
 396         /* Disable *all* interrupts */
 397         RADEON_WRITE(RADEON_GEN_INT_CNTL, 0);
 398 }
 399
 400
 401 int radeon_vblank_crtc_get(struct drm_device *dev)
 402 {
 403         drm_radeon_private_t *dev_priv = (drm_radeon_private_t *) dev->dev_private;
 404
 405         return dev_priv->vblank_crtc;
 406 }
 407
 408 int radeon_vblank_crtc_set(struct drm_device *dev, int64_t value)
 409 {
 410         drm_radeon_private_t *dev_priv = (drm_radeon_private_t *) dev->dev_private;
 411         if (value & ~(DRM_RADEON_VBLANK_CRTC1 | DRM_RADEON_VBLANK_CRTC2)) {
 412                 DRM_ERROR("called with invalid crtc 0x%x\n", (unsigned int)value);
 413                 return -EINVAL;
 414         }
 415         dev_priv->vblank_crtc = (unsigned int)value;
 416         return 0;
 417 }