2 * Copyright (c) 1997, Stefan Esser <se@freebsd.org>
3 * Copyright (c) 2000, Michael Smith <msmith@freebsd.org>
4 * Copyright (c) 2000, BSDi
7 * Redistribution and use in source and binary forms, with or without
8 * modification, are permitted provided that the following conditions
10 * 1. Redistributions of source code must retain the above copyright
11 * notice unmodified, this list of conditions, and the following
13 * 2. Redistributions in binary form must reproduce the above copyright
14 * notice, this list of conditions and the following disclaimer in the
15 * documentation and/or other materials provided with the distribution.
17 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
18 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
19 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
20 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
21 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
22 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
26 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
28 * $FreeBSD: src/sys/i386/isa/pci_cfgreg.c,v 1.1.2.7 2001/11/28 05:47:03 imp Exp $
29 * $DragonFly: src/sys/bus/pci/i386/pci_cfgreg.c,v 1.15 2008/08/02 05:22:20 dillon Exp $
33 #include <sys/param.h> /* XXX trim includes */
34 #include <sys/systm.h>
36 #include <sys/kernel.h>
37 #include <sys/module.h>
38 #include <sys/malloc.h>
39 #include <sys/sysctl.h>
42 #include <machine/md_var.h>
43 #include <machine/clock.h>
44 #include <bus/pci/pcivar.h>
45 #include <bus/pci/pcireg.h>
46 #include <bus/isa/isavar.h>
47 #include "pci_cfgreg.h"
48 #include <machine/segments.h>
49 #include <machine/pc/bios.h>
50 #include <machine/smp.h>
52 #define PRVERB(a) do { \
57 static int pci_disable_bios_route
= 0;
58 SYSCTL_INT(_hw
, OID_AUTO
, pci_disable_bios_route
, CTLFLAG_RD
,
59 &pci_disable_bios_route
, 0, "disable interrupt routing via PCI-BIOS");
60 TUNABLE_INT("hw.pci_disable_bios_route", &pci_disable_bios_route
);
65 static int pci_cfgintr_valid(struct PIR_entry
*pe
, int pin
, int irq
);
66 static int pci_cfgintr_unique(struct PIR_entry
*pe
, int pin
);
67 static int pci_cfgintr_linked(struct PIR_entry
*pe
, int pin
);
68 static int pci_cfgintr_search(struct PIR_entry
*pe
, int bus
, int device
, int matchpin
, int pin
);
69 static int pci_cfgintr_virgin(struct PIR_entry
*pe
, int pin
);
71 static void pci_print_irqmask(u_int16_t irqs
);
72 static void pci_print_route_table(struct PIR_table
*prt
, int size
);
73 static int pcireg_cfgread(int bus
, int slot
, int func
, int reg
, int bytes
);
74 static void pcireg_cfgwrite(int bus
, int slot
, int func
, int reg
, int data
, int bytes
);
75 static int pcireg_cfgopen(void);
77 static struct PIR_table
*pci_route_table
;
78 static int pci_route_count
;
81 * Some BIOS writers seem to want to ignore the spec and put
82 * 0 in the intline rather than 255 to indicate none. Some use
83 * numbers in the range 128-254 to indicate something strange and
84 * apparently undocumented anywhere. Assume these are completely bogus
85 * and map them to 255, which means "none".
88 pci_map_intline(int line
)
90 if (line
== 0 || line
>= 128)
91 return (PCI_INVALID_IRQ
);
96 pcibios_get_version(void)
98 struct bios_regs args
;
100 if (PCIbios
.ventry
== 0) {
101 PRVERB(("pcibios: No call entry point\n"));
104 args
.eax
= PCIBIOS_BIOS_PRESENT
;
105 if (bios32(&args
, PCIbios
.ventry
, GSEL(GCODE_SEL
, SEL_KPL
))) {
106 PRVERB(("pcibios: BIOS_PRESENT call failed\n"));
109 if (args
.edx
!= 0x20494350) {
110 PRVERB(("pcibios: BIOS_PRESENT didn't return 'PCI ' in edx\n"));
113 return (args
.ebx
& 0xffff);
117 * Initialise access to PCI configuration space
122 static int opened
= 0;
124 static struct PIR_table
*pt
;
132 if (pcireg_cfgopen() == 0)
135 v
= pcibios_get_version();
137 kprintf("pcibios: BIOS version %x.%02x\n", (v
& 0xff00) >> 8,
141 * Look for the interrupt routing table.
143 * We use PCI BIOS's PIR table if it's available $PIR is the
144 * standard way to do this. Sadly some machines are not
145 * standards conforming and have _PIR instead. We shrug and cope
146 * by looking for both.
148 if (pcibios_get_version() >= 0x0210 && pt
== NULL
) {
149 sigaddr
= bios_sigsearch(0, "$PIR", 4, 16, 0);
151 sigaddr
= bios_sigsearch(0, "_PIR", 4, 16, 0);
153 pt
= (struct PIR_table
*)(uintptr_t)
154 BIOS_PADDRTOVADDR(sigaddr
);
155 for (cv
= (u_int8_t
*)pt
, ck
= 0, i
= 0;
156 i
< (pt
->pt_header
.ph_length
); i
++)
158 if (ck
== 0 && pt
->pt_header
.ph_length
>
159 sizeof(struct PIR_header
)) {
160 pci_route_table
= pt
;
161 pci_route_count
= (pt
->pt_header
.ph_length
-
162 sizeof(struct PIR_header
)) /
163 sizeof(struct PIR_entry
);
164 kprintf("Using $PIR table, %d entries at %p\n",
165 pci_route_count
, pci_route_table
);
167 pci_print_route_table(pci_route_table
,
177 * Read configuration space register
180 pci_cfgregread(int bus
, int slot
, int func
, int reg
, int bytes
)
187 * If we are using the APIC, the contents of the intline
188 * register will probably be wrong (since they are set up for
189 * use with the PIC. Rather than rewrite these registers
190 * (maybe that would be smarter) we trap attempts to read them
191 * and translate to our private vector numbers.
193 if ((reg
== PCIR_INTLINE
) && (bytes
== 1)) {
195 pin
= pcireg_cfgread(bus
, slot
, func
, PCIR_INTPIN
, 1);
196 line
= pcireg_cfgread(bus
, slot
, func
, PCIR_INTLINE
, 1);
201 airq
= pci_apic_irq(bus
, slot
, pin
);
203 /* PCI specific entry found in MP table */
205 undirect_pci_irq(line
);
209 * PCI interrupts might be redirected to the
210 * ISA bus according to some MP tables. Use the
211 * same methods as used by the ISA devices
212 * devices to find the proper IOAPIC int pin.
214 airq
= isa_apic_irq(line
);
215 if ((airq
>= 0) && (airq
!= line
)) {
216 /* XXX: undirect_pci_irq() ? */
217 undirect_isa_irq(line
);
226 * Some BIOS writers seem to want to ignore the spec and put
227 * 0 in the intline rather than 255 to indicate none. The rest of
228 * the code uses 255 as an invalid IRQ.
230 if (reg
== PCIR_INTLINE
&& bytes
== 1) {
231 line
= pcireg_cfgread(bus
, slot
, func
, PCIR_INTLINE
, 1);
232 return pci_map_intline(line
);
235 return (pcireg_cfgread(bus
, slot
, func
, reg
, bytes
));
239 * Write configuration space register
242 pci_cfgregwrite(int bus
, int slot
, int func
, int reg
, u_int32_t data
, int bytes
)
244 pcireg_cfgwrite(bus
, slot
, func
, reg
, data
, bytes
);
248 pci_cfgread(pcicfgregs
*cfg
, int reg
, int bytes
)
250 return (pci_cfgregread(cfg
->bus
, cfg
->slot
, cfg
->func
, reg
, bytes
));
254 pci_cfgwrite(pcicfgregs
*cfg
, int reg
, int data
, int bytes
)
256 pci_cfgregwrite(cfg
->bus
, cfg
->slot
, cfg
->func
, reg
, data
, bytes
);
261 * Route a PCI interrupt
264 pci_cfgintr(int bus
, int device
, int pin
, int oldirq
)
266 struct PIR_entry
*pe
;
268 struct bios_regs args
;
274 v
= pcibios_get_version();
277 "pci_cfgintr: BIOS %x.%02x doesn't support interrupt routing\n",
278 (v
& 0xff00) >> 8, v
& 0xff));
279 return (PCI_INVALID_IRQ
);
281 if ((bus
< 0) || (bus
> 255) || (device
< 0) || (device
> 255) ||
282 (pin
< 1) || (pin
> 4))
283 return (PCI_INVALID_IRQ
);
286 * Scan the entry table for a contender
288 for (i
= 0, pe
= &pci_route_table
->pt_entry
[0]; i
< pci_route_count
;
290 if ((bus
!= pe
->pe_bus
) || (device
!= pe
->pe_device
))
294 * A link of 0 means that this intpin is not connected to
295 * any other device's interrupt pins and is not connected to
296 * any of the Interrupt Router's interrupt pins, so we can't
299 if (pe
->pe_intpin
[pin
- 1].link
== 0)
302 if (pci_cfgintr_valid(pe
, pin
, oldirq
)) {
303 kprintf("pci_cfgintr: %d:%d INT%c BIOS irq %d\n", bus
,
304 device
, 'A' + pin
- 1, oldirq
);
309 * We try to find a linked interrupt, then we look to see
310 * if the interrupt is uniquely routed, then we look for
311 * a virgin interrupt. The virgin interrupt should return
312 * an interrupt we can route, but if that fails, maybe we
313 * should try harder to route a different interrupt.
314 * However, experience has shown that that's rarely the
315 * failure mode we see.
317 irq
= pci_cfgintr_linked(pe
, pin
);
318 if (irq
!= PCI_INVALID_IRQ
)
320 if (irq
== PCI_INVALID_IRQ
) {
321 irq
= pci_cfgintr_unique(pe
, pin
);
322 if (irq
!= PCI_INVALID_IRQ
)
325 if (irq
== PCI_INVALID_IRQ
)
326 irq
= pci_cfgintr_virgin(pe
, pin
);
328 if (irq
== PCI_INVALID_IRQ
)
331 if (pci_disable_bios_route
!= 0)
334 * Ask the BIOS to route the interrupt. If we picked an
335 * interrupt that failed, we should really try other
336 * choices that the BIOS offers us.
338 * For uniquely routed interrupts, we need to try
339 * to route them on some machines. Yet other machines
340 * fail to route, so we have to pretend that in that
341 * case it worked. Isn't PC hardware fun?
343 * NOTE: if we want to whack hardware to do this, then
344 * I think the right way to do that would be to have
345 * bridge drivers that do this. I'm not sure that the
346 * $PIR table would be valid for those interrupt
349 args
.eax
= PCIBIOS_ROUTE_INTERRUPT
;
350 args
.ebx
= (bus
<< 8) | (device
<< 3);
351 /* pin value is 0xa - 0xd */
352 args
.ecx
= (irq
<< 8) | (0xa + pin
-1);
354 bios32(&args
, PCIbios
.ventry
, GSEL(GCODE_SEL
, SEL_KPL
)) &&
356 PRVERB(("pci_cfgintr: ROUTE_INTERRUPT failed.\n"));
357 return (PCI_INVALID_IRQ
);
359 kprintf("pci_cfgintr: %d:%d INT%c routed to irq %d\n", bus
,
360 device
, 'A' + pin
- 1, irq
);
364 PRVERB(("pci_cfgintr: can't route an interrupt to %d:%d INT%c oldirq=%d\n", bus
,
365 device
, 'A' + pin
- 1, oldirq
));
366 return (PCI_INVALID_IRQ
);
370 * Check to see if an existing IRQ setting is valid.
373 pci_cfgintr_valid(struct PIR_entry
*pe
, int pin
, int irq
)
377 if (!PCI_INTERRUPT_VALID(irq
))
379 irqmask
= pe
->pe_intpin
[pin
- 1].irqs
;
380 if (irqmask
& (1 << irq
)) {
381 PRVERB(("pci_cfgintr_valid: BIOS irq %d is valid\n", irq
));
388 * Look to see if the routing table claims this pin is uniquely routed.
391 pci_cfgintr_unique(struct PIR_entry
*pe
, int pin
)
396 irqmask
= pe
->pe_intpin
[pin
- 1].irqs
;
397 if(irqmask
!= 0 && powerof2(irqmask
)) {
398 irq
= ffs(irqmask
) - 1;
399 PRVERB(("pci_cfgintr_unique: hard-routed to irq %d\n", irq
));
402 return (PCI_INVALID_IRQ
);
406 * Look for another device which shares the same link byte and
407 * already has a unique IRQ, or which has had one routed already.
410 pci_cfgintr_linked(struct PIR_entry
*pe
, int pin
)
412 struct PIR_entry
*oe
;
413 struct PIR_intpin
*pi
;
419 for (i
= 0, oe
= &pci_route_table
->pt_entry
[0]; i
< pci_route_count
;
421 /* scan interrupt pins */
422 for (j
= 0, pi
= &oe
->pe_intpin
[0]; j
< 4; j
++, pi
++) {
424 /* don't look at the entry we're trying to match */
425 if ((pe
== oe
) && (i
== (pin
- 1)))
427 /* compare link bytes */
428 if (pi
->link
!= pe
->pe_intpin
[pin
- 1].link
)
430 /* link destination mapped to a unique interrupt? */
431 if (pi
->irqs
!= 0 && powerof2(pi
->irqs
)) {
432 irq
= ffs(pi
->irqs
) - 1;
433 PRVERB(("pci_cfgintr_linked: linked (%x) to hard-routed irq %d\n",
439 * look for the real PCI device that matches this
442 irq
= pci_cfgintr_search(pe
, oe
->pe_bus
, oe
->pe_device
,
444 if (irq
!= PCI_INVALID_IRQ
)
448 return (PCI_INVALID_IRQ
);
452 * Scan for the real PCI device at (bus)/(device) using intpin (matchpin) and
453 * see if it has already been assigned an interrupt.
456 pci_cfgintr_search(struct PIR_entry
*pe
, int bus
, int device
, int matchpin
, int pin
)
458 devclass_t pci_devclass
;
459 device_t
*pci_devices
;
461 device_t
*pci_children
;
463 device_t
*busp
, *childp
;
467 * Find all the PCI busses.
470 if ((pci_devclass
= devclass_find("pci")) != NULL
)
471 devclass_get_devices(pci_devclass
, &pci_devices
, &pci_count
);
474 * Scan all the PCI busses/devices looking for this one.
476 irq
= PCI_INVALID_IRQ
;
477 for (i
= 0, busp
= pci_devices
; (i
< pci_count
) && (irq
== PCI_INVALID_IRQ
);
480 device_get_children(*busp
, &pci_children
, &pci_childcount
);
482 for (j
= 0, childp
= pci_children
; j
< pci_childcount
; j
++,
484 if ((pci_get_bus(*childp
) == bus
) &&
485 (pci_get_slot(*childp
) == device
) &&
486 (pci_get_intpin(*childp
) == matchpin
)) {
487 irq
= pci_map_intline(pci_get_irq(*childp
));
488 if (irq
!= PCI_INVALID_IRQ
)
489 PRVERB(("pci_cfgintr_search: linked (%x) to configured irq %d at %d:%d:%d\n",
490 pe
->pe_intpin
[pin
- 1].link
, irq
,
491 pci_get_bus(*childp
),
492 pci_get_slot(*childp
),
493 pci_get_function(*childp
)));
497 if (pci_children
!= NULL
)
498 kfree(pci_children
, M_TEMP
);
500 if (pci_devices
!= NULL
)
501 kfree(pci_devices
, M_TEMP
);
506 * Pick a suitable IRQ from those listed as routable to this device.
509 pci_cfgintr_virgin(struct PIR_entry
*pe
, int pin
)
514 * first scan the set of PCI-only interrupts and see if any of these
517 for (irq
= 0; irq
< 16; irq
++) {
520 /* can we use this interrupt? */
521 if ((pci_route_table
->pt_header
.ph_pci_irqs
& ibit
) &&
522 (pe
->pe_intpin
[pin
- 1].irqs
& ibit
)) {
523 PRVERB(("pci_cfgintr_virgin: using routable PCI-only interrupt %d\n", irq
));
528 /* life is tough, so just pick an interrupt */
529 for (irq
= 0; irq
< 16; irq
++) {
532 if (pe
->pe_intpin
[pin
- 1].irqs
& ibit
) {
533 PRVERB(("pci_cfgintr_virgin: using routable interrupt %d\n", irq
));
537 return (PCI_INVALID_IRQ
);
541 pci_print_irqmask(u_int16_t irqs
)
550 for (i
= 0; i
< 16; i
++, irqs
>>= 1)
561 * Dump the contents of a PCI BIOS Interrupt Routing Table to the console.
564 pci_print_route_table(struct PIR_table
*ptr
, int size
)
566 struct PIR_entry
*entry
;
567 struct PIR_intpin
*intpin
;
570 kprintf("PCI-Only Interrupts: ");
571 pci_print_irqmask(ptr
->pt_header
.ph_pci_irqs
);
572 kprintf("\nLocation Bus Device Pin Link IRQs\n");
573 entry
= &ptr
->pt_entry
[0];
574 for (i
= 0; i
< size
; i
++, entry
++) {
575 intpin
= &entry
->pe_intpin
[0];
576 for (pin
= 0; pin
< 4; pin
++, intpin
++)
577 if (intpin
->link
!= 0) {
578 if (entry
->pe_slot
== 0)
579 kprintf("embedded ");
581 kprintf("slot %-3d ", entry
->pe_slot
);
582 kprintf(" %3d %3d %c 0x%02x ",
583 entry
->pe_bus
, entry
->pe_device
,
584 'A' + pin
, intpin
->link
);
585 pci_print_irqmask(intpin
->irqs
);
592 * See if any interrupts for a given PCI bus are routed in the PIR. Don't
593 * even bother looking if the BIOS doesn't support routing anyways.
596 pci_probe_route_table(int bus
)
601 v
= pcibios_get_version();
604 for (i
= 0; i
< pci_route_count
; i
++)
605 if (pci_route_table
->pt_entry
[i
].pe_bus
== bus
)
611 * Configuration space access using direct register operations
614 /* enable configuration space accesses and return data port address */
616 pci_cfgenable(unsigned bus
, unsigned slot
, unsigned func
, int reg
, int bytes
)
620 if (bus
<= PCI_BUSMAX
622 && func
<= PCI_FUNCMAX
625 && (unsigned) bytes
<= 4
626 && (reg
& (bytes
- 1)) == 0) {
629 outl(CONF1_ADDR_PORT
, (1 << 31)
630 | (bus
<< 16) | (slot
<< 11)
631 | (func
<< 8) | (reg
& ~0x03));
632 dataport
= CONF1_DATA_PORT
+ (reg
& 0x03);
635 outb(CONF2_ENABLE_PORT
, 0xf0 | (func
<< 1));
636 outb(CONF2_FORWARD_PORT
, bus
);
637 dataport
= 0xc000 | (slot
<< 8) | reg
;
644 /* disable configuration space accesses */
650 outl(CONF1_ADDR_PORT
, 0);
653 outb(CONF2_ENABLE_PORT
, 0);
654 outb(CONF2_FORWARD_PORT
, 0);
660 pcireg_cfgread(int bus
, int slot
, int func
, int reg
, int bytes
)
665 port
= pci_cfgenable(bus
, slot
, func
, reg
, bytes
);
684 pcireg_cfgwrite(int bus
, int slot
, int func
, int reg
, int data
, int bytes
)
688 port
= pci_cfgenable(bus
, slot
, func
, reg
, bytes
);
705 /* check whether the configuration mechanism has been correctly identified */
707 pci_cfgcheck(int maxdev
)
715 kprintf("pci_cfgcheck:\tdevice ");
717 for (device
= 0; device
< maxdev
; device
++) {
719 kprintf("%d ", device
);
721 port
= pci_cfgenable(0, device
, 0, 0, 4);
723 if (id
== 0 || id
== 0xffffffff)
726 port
= pci_cfgenable(0, device
, 0, 8, 4);
727 class = inl(port
) >> 8;
729 kprintf("[class=%06x] ", class);
730 if (class == 0 || (class & 0xf870ff) != 0)
733 port
= pci_cfgenable(0, device
, 0, 14, 1);
736 kprintf("[hdr=%02x] ", header
);
737 if ((header
& 0x7e) != 0)
741 kprintf("is there (id=%08x)\n", id
);
747 kprintf("-- nothing found\n");
756 uint32_t mode1res
,oldval1
;
757 uint8_t mode2res
,oldval2
;
759 oldval1
= inl(CONF1_ADDR_PORT
);
762 kprintf("pci_open(1):\tmode 1 addr port (0x0cf8) is 0x%08x\n",
766 if ((oldval1
& CONF1_ENABLE_MSK
) == 0) {
771 outl(CONF1_ADDR_PORT
, CONF1_ENABLE_CHK
);
773 mode1res
= inl(CONF1_ADDR_PORT
);
774 outl(CONF1_ADDR_PORT
, oldval1
);
777 kprintf("pci_open(1a):\tmode1res=0x%08x (0x%08lx)\n",
778 mode1res
, CONF1_ENABLE_CHK
);
781 if (pci_cfgcheck(32))
785 outl(CONF1_ADDR_PORT
, CONF1_ENABLE_CHK1
);
786 mode1res
= inl(CONF1_ADDR_PORT
);
787 outl(CONF1_ADDR_PORT
, oldval1
);
790 kprintf("pci_open(1b):\tmode1res=0x%08x (0x%08lx)\n",
791 mode1res
, CONF1_ENABLE_CHK1
);
793 if ((mode1res
& CONF1_ENABLE_MSK1
) == CONF1_ENABLE_RES1
) {
794 if (pci_cfgcheck(32))
799 oldval2
= inb(CONF2_ENABLE_PORT
);
802 kprintf("pci_open(2):\tmode 2 enable port (0x0cf8) is 0x%02x\n",
806 if ((oldval2
& 0xf0) == 0) {
811 outb(CONF2_ENABLE_PORT
, CONF2_ENABLE_CHK
);
812 mode2res
= inb(CONF2_ENABLE_PORT
);
813 outb(CONF2_ENABLE_PORT
, oldval2
);
816 kprintf("pci_open(2a):\tmode2res=0x%02x (0x%02x)\n",
817 mode2res
, CONF2_ENABLE_CHK
);
819 if (mode2res
== CONF2_ENABLE_RES
) {
821 kprintf("pci_open(2a):\tnow trying mechanism 2\n");
823 if (pci_cfgcheck(16))