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kernel: Remove <sys/mutex.h> from all files that don't need it (2/2).
[dragonfly.git] / sys / dev / netif / ral / rt2860.c
blob4e16695a3f75ae9688ec4a9cff4e461dcbd3d424
1 /*-
2 * Copyright (c) 2007-2010 Damien Bergamini <damien.bergamini@free.fr>
3 * Copyright (c) 2012 Bernhard Schmidt <bschmidt@FreeBSD.org>
4 *
5 * Permission to use, copy, modify, and distribute this software for any
6 * purpose with or without fee is hereby granted, provided that the above
7 * copyright notice and this permission notice appear in all copies.
8 *
9 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
10 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
11 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
12 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
13 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
14 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
15 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
16 *
17 * $OpenBSD: rt2860.c,v 1.65 2010/10/23 14:24:54 damien Exp $
18 */
19
20 #include <sys/cdefs.h>
21 __FBSDID("$FreeBSD$");
22
23 /*-
24 * Ralink Technology RT2860/RT3090/RT3390/RT3562/RT5390/RT5392 chipset driver
25 * http://www.ralinktech.com/
26 */
27
28 #include <sys/param.h>
29 #include <sys/sysctl.h>
30 #include <sys/sockio.h>
31 #include <sys/mbuf.h>
32 #include <sys/kernel.h>
33 #include <sys/socket.h>
34 #include <sys/systm.h>
35 #include <sys/malloc.h>
36 #include <sys/lock.h>
37 #include <sys/module.h>
38 #include <sys/bus.h>
39 #include <sys/endian.h>
40 #include <sys/firmware.h>
41
42 #if defined(__DragonFly__)
43 /* empty */
44 #else
45 #include <machine/bus.h>
46 #include <machine/resource.h>
47 #endif
48 #include <sys/rman.h>
49
50 #include <net/bpf.h>
51 #include <net/if.h>
52 #include <net/if_var.h>
53 #include <net/if_arp.h>
54 #include <net/ethernet.h>
55 #include <net/if_dl.h>
56 #include <net/if_media.h>
57 #include <net/if_types.h>
58
59 #include <netproto/802_11/ieee80211_var.h>
60 #include <netproto/802_11/ieee80211_radiotap.h>
61 #include <netproto/802_11/ieee80211_regdomain.h>
62 #include <netproto/802_11/ieee80211_ratectl.h>
63
64 #include <netinet/in.h>
65 #include <netinet/in_systm.h>
66 #include <netinet/in_var.h>
67 #include <netinet/ip.h>
68 #include <netinet/if_ether.h>
69
70 #include <dev/netif/ral/rt2860reg.h>
71 #include <dev/netif/ral/rt2860var.h>
72
73 #define RAL_DEBUG
74 #ifdef RAL_DEBUG
75 #define DPRINTF(x) do { if (sc->sc_debug > 0) kprintf x; } while (0)
76 #define DPRINTFN(n, x) do { if (sc->sc_debug >= (n)) kprintf x; } while (0)
77 #else
78 #define DPRINTF(x)
79 #define DPRINTFN(n, x)
80 #endif
81
82 static struct ieee80211vap *rt2860_vap_create(struct ieee80211com *,
83 const char [IFNAMSIZ], int, enum ieee80211_opmode,
84 int, const uint8_t [IEEE80211_ADDR_LEN],
85 const uint8_t [IEEE80211_ADDR_LEN]);
86 static void rt2860_vap_delete(struct ieee80211vap *);
87 static void rt2860_dma_map_addr(void *, bus_dma_segment_t *, int, int);
88 static int rt2860_alloc_tx_ring(struct rt2860_softc *,
89 struct rt2860_tx_ring *);
90 static void rt2860_reset_tx_ring(struct rt2860_softc *,
91 struct rt2860_tx_ring *);
92 static void rt2860_free_tx_ring(struct rt2860_softc *,
93 struct rt2860_tx_ring *);
94 static int rt2860_alloc_tx_pool(struct rt2860_softc *);
95 static void rt2860_free_tx_pool(struct rt2860_softc *);
96 static int rt2860_alloc_rx_ring(struct rt2860_softc *,
97 struct rt2860_rx_ring *);
98 static void rt2860_reset_rx_ring(struct rt2860_softc *,
99 struct rt2860_rx_ring *);
100 static void rt2860_free_rx_ring(struct rt2860_softc *,
101 struct rt2860_rx_ring *);
102 static void rt2860_updatestats(struct rt2860_softc *);
103 static void rt2860_newassoc(struct ieee80211_node *, int);
104 static void rt2860_node_free(struct ieee80211_node *);
105 #ifdef IEEE80211_HT
106 static int rt2860_ampdu_rx_start(struct ieee80211com *,
107 struct ieee80211_node *, uint8_t);
108 static void rt2860_ampdu_rx_stop(struct ieee80211com *,
109 struct ieee80211_node *, uint8_t);
110 #endif
111 static int rt2860_newstate(struct ieee80211vap *, enum ieee80211_state,
112 int);
113 static uint16_t rt3090_efuse_read_2(struct rt2860_softc *, uint16_t);
114 static uint16_t rt2860_eeprom_read_2(struct rt2860_softc *, uint16_t);
115 static void rt2860_intr_coherent(struct rt2860_softc *);
116 static void rt2860_drain_stats_fifo(struct rt2860_softc *);
117 static void rt2860_tx_intr(struct rt2860_softc *, int);
118 static void rt2860_rx_intr(struct rt2860_softc *);
119 static void rt2860_tbtt_intr(struct rt2860_softc *);
120 static void rt2860_gp_intr(struct rt2860_softc *);
121 static int rt2860_tx(struct rt2860_softc *, struct mbuf *,
122 struct ieee80211_node *);
123 static int rt2860_raw_xmit(struct ieee80211_node *, struct mbuf *,
124 const struct ieee80211_bpf_params *);
125 static int rt2860_tx_raw(struct rt2860_softc *, struct mbuf *,
126 struct ieee80211_node *,
127 const struct ieee80211_bpf_params *params);
128 static int rt2860_transmit(struct ieee80211com *, struct mbuf *);
129 static void rt2860_start(struct rt2860_softc *);
130 static void rt2860_watchdog(void *);
131 static void rt2860_parent(struct ieee80211com *);
132 static void rt2860_mcu_bbp_write(struct rt2860_softc *, uint8_t, uint8_t);
133 static uint8_t rt2860_mcu_bbp_read(struct rt2860_softc *, uint8_t);
134 static void rt2860_rf_write(struct rt2860_softc *, uint8_t, uint32_t);
135 static uint8_t rt3090_rf_read(struct rt2860_softc *, uint8_t);
136 static void rt3090_rf_write(struct rt2860_softc *, uint8_t, uint8_t);
137 static int rt2860_mcu_cmd(struct rt2860_softc *, uint8_t, uint16_t, int);
138 static void rt2860_enable_mrr(struct rt2860_softc *);
139 static void rt2860_set_txpreamble(struct rt2860_softc *);
140 static void rt2860_set_basicrates(struct rt2860_softc *,
141 const struct ieee80211_rateset *);
142 static void rt2860_scan_start(struct ieee80211com *);
143 static void rt2860_scan_end(struct ieee80211com *);
144 static void rt2860_set_channel(struct ieee80211com *);
145 static void rt2860_select_chan_group(struct rt2860_softc *, int);
146 static void rt2860_set_chan(struct rt2860_softc *, u_int);
147 static void rt3090_set_chan(struct rt2860_softc *, u_int);
148 static void rt5390_set_chan(struct rt2860_softc *, u_int);
149 static int rt3090_rf_init(struct rt2860_softc *);
150 static void rt5390_rf_init(struct rt2860_softc *);
151 static void rt3090_rf_wakeup(struct rt2860_softc *);
152 static void rt5390_rf_wakeup(struct rt2860_softc *);
153 static int rt3090_filter_calib(struct rt2860_softc *, uint8_t, uint8_t,
154 uint8_t *);
155 static void rt3090_rf_setup(struct rt2860_softc *);
156 static void rt2860_set_leds(struct rt2860_softc *, uint16_t);
157 static void rt2860_set_gp_timer(struct rt2860_softc *, int);
158 static void rt2860_set_bssid(struct rt2860_softc *, const uint8_t *);
159 static void rt2860_set_macaddr(struct rt2860_softc *, const uint8_t *);
160 static void rt2860_update_promisc(struct ieee80211com *);
161 static void rt2860_updateslot(struct ieee80211com *);
162 static void rt2860_updateprot(struct rt2860_softc *);
163 static int rt2860_updateedca(struct ieee80211com *);
164 #ifdef HW_CRYPTO
165 static int rt2860_set_key(struct ieee80211com *, struct ieee80211_node *,
166 struct ieee80211_key *);
167 static void rt2860_delete_key(struct ieee80211com *,
168 struct ieee80211_node *, struct ieee80211_key *);
169 #endif
170 static int8_t rt2860_rssi2dbm(struct rt2860_softc *, uint8_t, uint8_t);
171 static const char *rt2860_get_rf(uint16_t);
172 static int rt2860_read_eeprom(struct rt2860_softc *,
173 uint8_t macaddr[IEEE80211_ADDR_LEN]);
174 static int rt2860_bbp_init(struct rt2860_softc *);
175 static void rt5390_bbp_init(struct rt2860_softc *);
176 static int rt2860_txrx_enable(struct rt2860_softc *);
177 static void rt2860_init(void *);
178 static void rt2860_init_locked(struct rt2860_softc *);
179 static void rt2860_stop(void *);
180 static void rt2860_stop_locked(struct rt2860_softc *);
181 static int rt2860_load_microcode(struct rt2860_softc *);
182 #ifdef NOT_YET
183 static void rt2860_calib(struct rt2860_softc *);
184 #endif
185 static void rt3090_set_rx_antenna(struct rt2860_softc *, int);
186 static void rt2860_switch_chan(struct rt2860_softc *,
187 struct ieee80211_channel *);
188 static int rt2860_setup_beacon(struct rt2860_softc *,
189 struct ieee80211vap *);
190 static void rt2860_enable_tsf_sync(struct rt2860_softc *);
191
192 static const struct {
193 uint32_t reg;
194 uint32_t val;
195 } rt2860_def_mac[] = {
196 RT2860_DEF_MAC
197 };
198
199 static const struct {
200 uint8_t reg;
201 uint8_t val;
202 } rt2860_def_bbp[] = {
203 RT2860_DEF_BBP
204 }, rt5390_def_bbp[] = {
205 RT5390_DEF_BBP
206 };
207
208 static const struct rfprog {
209 uint8_t chan;
210 uint32_t r1, r2, r3, r4;
211 } rt2860_rf2850[] = {
212 RT2860_RF2850
213 };
214
215 struct {
216 uint8_t n, r, k;
217 } rt3090_freqs[] = {
218 RT3070_RF3052
219 };
220
221 static const struct {
222 uint8_t reg;
223 uint8_t val;
224 } rt3090_def_rf[] = {
225 RT3070_DEF_RF
226 }, rt5390_def_rf[] = {
227 RT5390_DEF_RF
228 }, rt5392_def_rf[] = {
229 RT5392_DEF_RF
230 };
231
232 int
233 rt2860_attach(device_t dev, int id)
234 {
235 struct rt2860_softc *sc = device_get_softc(dev);
236 struct ieee80211com *ic = &sc->sc_ic;
237 uint32_t tmp;
238 uint8_t bands[IEEE80211_MODE_BYTES];
239 int error, ntries, qid;
240
241 sc->sc_dev = dev;
242 sc->sc_debug = 0;
243
244 #if defined(__DragonFly__)
245 lockinit(&sc->sc_mtx, device_get_nameunit(dev), 0, LK_CANRECURSE);
246 #else
247 mtx_init(&sc->sc_mtx, device_get_nameunit(dev), MTX_NETWORK_LOCK,
248 MTX_DEF | MTX_RECURSE);
249 #endif
250
251 callout_init_mtx(&sc->watchdog_ch, &sc->sc_mtx, 0);
252 mbufq_init(&sc->sc_snd, ifqmaxlen);
253
254 /* wait for NIC to initialize */
255 for (ntries = 0; ntries < 100; ntries++) {
256 tmp = RAL_READ(sc, RT2860_ASIC_VER_ID);
257 if (tmp != 0 && tmp != 0xffffffff)
258 break;
259 DELAY(10);
260 }
261 if (ntries == 100) {
262 device_printf(sc->sc_dev,
263 "timeout waiting for NIC to initialize\n");
264 error = EIO;
265 goto fail1;
266 }
267 sc->mac_ver = tmp >> 16;
268 sc->mac_rev = tmp & 0xffff;
269
270 if (sc->mac_ver != 0x2860 &&
271 (id == 0x0681 || id == 0x0781 || id == 0x1059))
272 sc->sc_flags |= RT2860_ADVANCED_PS;
273
274 /* retrieve RF rev. no and various other things from EEPROM */
275 rt2860_read_eeprom(sc, ic->ic_macaddr);
276 #if defined(__DragonFly__)
277 device_printf(sc->sc_dev, "MAC/BBP RT%X (rev 0x%04X), "
278 "RF %s (MIMO %dT%dR), address %s\n",
279 sc->mac_ver, sc->mac_rev, rt2860_get_rf(sc->rf_rev),
280 sc->ntxchains, sc->nrxchains, ether_sprintf(ic->ic_macaddr));
281 #else
282 device_printf(sc->sc_dev, "MAC/BBP RT%X (rev 0x%04X), "
283 "RF %s (MIMO %dT%dR), address %6D\n",
284 sc->mac_ver, sc->mac_rev, rt2860_get_rf(sc->rf_rev),
285 sc->ntxchains, sc->nrxchains, ic->ic_macaddr, ":");
286 #endif
287
288 /*
289 * Allocate Tx (4 EDCAs + HCCA + Mgt) and Rx rings.
290 */
291 for (qid = 0; qid < 6; qid++) {
292 if ((error = rt2860_alloc_tx_ring(sc, &sc->txq[qid])) != 0) {
293 device_printf(sc->sc_dev,
294 "could not allocate Tx ring %d\n", qid);
295 goto fail2;
296 }
297 }
298
299 if ((error = rt2860_alloc_rx_ring(sc, &sc->rxq)) != 0) {
300 device_printf(sc->sc_dev, "could not allocate Rx ring\n");
301 goto fail2;
302 }
303
304 if ((error = rt2860_alloc_tx_pool(sc)) != 0) {
305 device_printf(sc->sc_dev, "could not allocate Tx pool\n");
306 goto fail3;
307 }
308
309 /* mgmt ring is broken on RT2860C, use EDCA AC VO ring instead */
310 sc->mgtqid = (sc->mac_ver == 0x2860 && sc->mac_rev == 0x0100) ?
311 WME_AC_VO : 5;
312
313 ic->ic_softc = sc;
314 ic->ic_name = device_get_nameunit(dev);
315 ic->ic_opmode = IEEE80211_M_STA;
316 ic->ic_phytype = IEEE80211_T_OFDM; /* not only, but not used */
317
318 /* set device capabilities */
319 ic->ic_caps =
320 IEEE80211_C_STA /* station mode */
321 | IEEE80211_C_IBSS /* ibss, nee adhoc, mode */
322 | IEEE80211_C_HOSTAP /* hostap mode */
323 | IEEE80211_C_MONITOR /* monitor mode */
324 | IEEE80211_C_AHDEMO /* adhoc demo mode */
325 | IEEE80211_C_WDS /* 4-address traffic works */
326 | IEEE80211_C_MBSS /* mesh point link mode */
327 | IEEE80211_C_SHPREAMBLE /* short preamble supported */
328 | IEEE80211_C_SHSLOT /* short slot time supported */
329 | IEEE80211_C_WPA /* capable of WPA1+WPA2 */
330 #if 0
331 | IEEE80211_C_BGSCAN /* capable of bg scanning */
332 #endif
333 | IEEE80211_C_WME /* 802.11e */
334 ;
335
336 memset(bands, 0, sizeof(bands));
337 setbit(bands, IEEE80211_MODE_11B);
338 setbit(bands, IEEE80211_MODE_11G);
339 if (sc->rf_rev == RT2860_RF_2750 || sc->rf_rev == RT2860_RF_2850)
340 setbit(bands, IEEE80211_MODE_11A);
341 ieee80211_init_channels(ic, NULL, bands);
342
343 ieee80211_ifattach(ic);
344
345 ic->ic_wme.wme_update = rt2860_updateedca;
346 ic->ic_scan_start = rt2860_scan_start;
347 ic->ic_scan_end = rt2860_scan_end;
348 ic->ic_set_channel = rt2860_set_channel;
349 ic->ic_updateslot = rt2860_updateslot;
350 ic->ic_update_promisc = rt2860_update_promisc;
351 ic->ic_raw_xmit = rt2860_raw_xmit;
352 sc->sc_node_free = ic->ic_node_free;
353 ic->ic_node_free = rt2860_node_free;
354 ic->ic_newassoc = rt2860_newassoc;
355 ic->ic_transmit = rt2860_transmit;
356 ic->ic_parent = rt2860_parent;
357 ic->ic_vap_create = rt2860_vap_create;
358 ic->ic_vap_delete = rt2860_vap_delete;
359
360 ieee80211_radiotap_attach(ic,
361 &sc->sc_txtap.wt_ihdr, sizeof(sc->sc_txtap),
362 RT2860_TX_RADIOTAP_PRESENT,
363 &sc->sc_rxtap.wr_ihdr, sizeof(sc->sc_rxtap),
364 RT2860_RX_RADIOTAP_PRESENT);
365
366 #ifdef RAL_DEBUG
367 SYSCTL_ADD_INT(device_get_sysctl_ctx(dev),
368 SYSCTL_CHILDREN(device_get_sysctl_tree(dev)), OID_AUTO,
369 "debug", CTLFLAG_RW, &sc->sc_debug, 0, "debug msgs");
370 #endif
371 if (bootverbose)
372 ieee80211_announce(ic);
373
374 return 0;
375
376 fail3: rt2860_free_rx_ring(sc, &sc->rxq);
377 fail2: while (--qid >= 0)
378 rt2860_free_tx_ring(sc, &sc->txq[qid]);
379 #if defined(__DragonFly__)
380 fail1: lockuninit(&sc->sc_mtx);
381 #else
382 fail1: mtx_destroy(&sc->sc_mtx);
383 #endif
384 return error;
385 }
386
387 int
388 rt2860_detach(void *xsc)
389 {
390 struct rt2860_softc *sc = xsc;
391 struct ieee80211com *ic = &sc->sc_ic;
392 int qid;
393
394 RAL_LOCK(sc);
395 rt2860_stop_locked(sc);
396 RAL_UNLOCK(sc);
397
398 ieee80211_ifdetach(ic);
399 mbufq_drain(&sc->sc_snd);
400 for (qid = 0; qid < 6; qid++)
401 rt2860_free_tx_ring(sc, &sc->txq[qid]);
402 rt2860_free_rx_ring(sc, &sc->rxq);
403 rt2860_free_tx_pool(sc);
404
405 #if defined(__DragonFly__)
406 lockuninit(&sc->sc_mtx);
407 #else
408 mtx_destroy(&sc->sc_mtx);
409 #endif
410
411 return 0;
412 }
413
414 void
415 rt2860_shutdown(void *xsc)
416 {
417 struct rt2860_softc *sc = xsc;
418
419 rt2860_stop(sc);
420 }
421
422 void
423 rt2860_suspend(void *xsc)
424 {
425 struct rt2860_softc *sc = xsc;
426
427 rt2860_stop(sc);
428 }
429
430 void
431 rt2860_resume(void *xsc)
432 {
433 struct rt2860_softc *sc = xsc;
434
435 if (sc->sc_ic.ic_nrunning > 0)
436 rt2860_init(sc);
437 }
438
439 static struct ieee80211vap *
440 rt2860_vap_create(struct ieee80211com *ic, const char name[IFNAMSIZ], int unit,
441 enum ieee80211_opmode opmode, int flags,
442 const uint8_t bssid[IEEE80211_ADDR_LEN],
443 const uint8_t mac[IEEE80211_ADDR_LEN])
444 {
445 struct rt2860_softc *sc = ic->ic_softc;
446 struct rt2860_vap *rvp;
447 struct ieee80211vap *vap;
448
449 switch (opmode) {
450 case IEEE80211_M_STA:
451 case IEEE80211_M_IBSS:
452 case IEEE80211_M_AHDEMO:
453 case IEEE80211_M_MONITOR:
454 case IEEE80211_M_HOSTAP:
455 case IEEE80211_M_MBSS:
456 /* XXXRP: TBD */
457 if (!TAILQ_EMPTY(&ic->ic_vaps)) {
458 device_printf(sc->sc_dev, "only 1 vap supported\n");
459 return NULL;
460 }
461 if (opmode == IEEE80211_M_STA)
462 flags |= IEEE80211_CLONE_NOBEACONS;
463 break;
464 case IEEE80211_M_WDS:
465 if (TAILQ_EMPTY(&ic->ic_vaps) ||
466 ic->ic_opmode != IEEE80211_M_HOSTAP) {
467 device_printf(sc->sc_dev,
468 "wds only supported in ap mode\n");
469 return NULL;
470 }
471 /*
472 * Silently remove any request for a unique
473 * bssid; WDS vap's always share the local
474 * mac address.
475 */
476 flags &= ~IEEE80211_CLONE_BSSID;
477 break;
478 default:
479 device_printf(sc->sc_dev, "unknown opmode %d\n", opmode);
480 return NULL;
481 }
482 rvp = kmalloc(sizeof(struct rt2860_vap), M_80211_VAP, M_WAITOK | M_ZERO);
483 vap = &rvp->ral_vap;
484 ieee80211_vap_setup(ic, vap, name, unit, opmode, flags, bssid);
485
486 /* override state transition machine */
487 rvp->ral_newstate = vap->iv_newstate;
488 vap->iv_newstate = rt2860_newstate;
489 #if 0
490 vap->iv_update_beacon = rt2860_beacon_update;
491 #endif
492
493 /* HW supports up to 255 STAs (0-254) in HostAP and IBSS modes */
494 vap->iv_max_aid = min(IEEE80211_AID_MAX, RT2860_WCID_MAX);
495
496 ieee80211_ratectl_init(vap);
497 /* complete setup */
498 ieee80211_vap_attach(vap, ieee80211_media_change,
499 ieee80211_media_status, mac);
500 if (TAILQ_FIRST(&ic->ic_vaps) == vap)
501 ic->ic_opmode = opmode;
502 return vap;
503 }
504
505 static void
506 rt2860_vap_delete(struct ieee80211vap *vap)
507 {
508 struct rt2860_vap *rvp = RT2860_VAP(vap);
509
510 ieee80211_ratectl_deinit(vap);
511 ieee80211_vap_detach(vap);
512 kfree(rvp, M_80211_VAP);
513 }
514
515 static void
516 rt2860_dma_map_addr(void *arg, bus_dma_segment_t *segs, int nseg, int error)
517 {
518 if (error != 0)
519 return;
520
521 KASSERT(nseg == 1, ("too many DMA segments, %d should be 1", nseg));
522
523 *(bus_addr_t *)arg = segs[0].ds_addr;
524 }
525
526
527 static int
528 rt2860_alloc_tx_ring(struct rt2860_softc *sc, struct rt2860_tx_ring *ring)
529 {
530 int size, error;
531
532 size = RT2860_TX_RING_COUNT * sizeof (struct rt2860_txd);
533
534 #if defined(__DragonFly__)
535 error = bus_dma_tag_create(bus_get_dma_tag(sc->sc_dev), 16, 0,
536 BUS_SPACE_MAXADDR_32BIT, BUS_SPACE_MAXADDR, NULL, NULL,
537 size, 1, size, 0, &ring->desc_dmat);
538 #else
539 error = bus_dma_tag_create(bus_get_dma_tag(sc->sc_dev), 16, 0,
540 BUS_SPACE_MAXADDR_32BIT, BUS_SPACE_MAXADDR, NULL, NULL,
541 size, 1, size, 0, NULL, NULL, &ring->desc_dmat);
542 #endif
543 if (error != 0) {
544 device_printf(sc->sc_dev, "could not create desc DMA tag\n");
545 goto fail;
546 }
547
548 error = bus_dmamem_alloc(ring->desc_dmat, (void **)&ring->txd,
549 BUS_DMA_NOWAIT | BUS_DMA_ZERO, &ring->desc_map);
550 if (error != 0) {
551 device_printf(sc->sc_dev, "could not allocate DMA memory\n");
552 goto fail;
553 }
554
555 error = bus_dmamap_load(ring->desc_dmat, ring->desc_map, ring->txd,
556 size, rt2860_dma_map_addr, &ring->paddr, 0);
557 if (error != 0) {
558 device_printf(sc->sc_dev, "could not load desc DMA map\n");
559 goto fail;
560 }
561
562 bus_dmamap_sync(ring->desc_dmat, ring->desc_map, BUS_DMASYNC_PREWRITE);
563
564 return 0;
565
566 fail: rt2860_free_tx_ring(sc, ring);
567 return error;
568 }
569
570 void
571 rt2860_reset_tx_ring(struct rt2860_softc *sc, struct rt2860_tx_ring *ring)
572 {
573 struct rt2860_tx_data *data;
574 int i;
575
576 for (i = 0; i < RT2860_TX_RING_COUNT; i++) {
577 if ((data = ring->data[i]) == NULL)
578 continue; /* nothing mapped in this slot */
579
580 if (data->m != NULL) {
581 bus_dmamap_sync(sc->txwi_dmat, data->map,
582 BUS_DMASYNC_POSTWRITE);
583 bus_dmamap_unload(sc->txwi_dmat, data->map);
584 m_freem(data->m);
585 data->m = NULL;
586 }
587 if (data->ni != NULL) {
588 ieee80211_free_node(data->ni);
589 data->ni = NULL;
590 }
591
592 SLIST_INSERT_HEAD(&sc->data_pool, data, next);
593 ring->data[i] = NULL;
594 }
595
596 ring->queued = 0;
597 ring->cur = ring->next = 0;
598 }
599
600 void
601 rt2860_free_tx_ring(struct rt2860_softc *sc, struct rt2860_tx_ring *ring)
602 {
603 struct rt2860_tx_data *data;
604 int i;
605
606 if (ring->txd != NULL) {
607 bus_dmamap_sync(ring->desc_dmat, ring->desc_map,
608 BUS_DMASYNC_POSTWRITE);
609 bus_dmamap_unload(ring->desc_dmat, ring->desc_map);
610 bus_dmamem_free(ring->desc_dmat, ring->txd, ring->desc_map);
611 }
612 if (ring->desc_dmat != NULL)
613 bus_dma_tag_destroy(ring->desc_dmat);
614
615 for (i = 0; i < RT2860_TX_RING_COUNT; i++) {
616 if ((data = ring->data[i]) == NULL)
617 continue; /* nothing mapped in this slot */
618
619 if (data->m != NULL) {
620 bus_dmamap_sync(sc->txwi_dmat, data->map,
621 BUS_DMASYNC_POSTWRITE);
622 bus_dmamap_unload(sc->txwi_dmat, data->map);
623 m_freem(data->m);
624 }
625 if (data->ni != NULL)
626 ieee80211_free_node(data->ni);
627
628 SLIST_INSERT_HEAD(&sc->data_pool, data, next);
629 }
630 }
631
632 /*
633 * Allocate a pool of TX Wireless Information blocks.
634 */
635 int
636 rt2860_alloc_tx_pool(struct rt2860_softc *sc)
637 {
638 caddr_t vaddr;
639 bus_addr_t paddr;
640 int i, size, error;
641
642 size = RT2860_TX_POOL_COUNT * RT2860_TXWI_DMASZ;
643
644 /* init data_pool early in case of failure.. */
645 SLIST_INIT(&sc->data_pool);
646
647 #if defined(__DragonFly__)
648 error = bus_dma_tag_create(bus_get_dma_tag(sc->sc_dev), 4, 0,
649 BUS_SPACE_MAXADDR_32BIT, BUS_SPACE_MAXADDR, NULL, NULL,
650 size, 1, size, 0, &sc->txwi_dmat);
651 #else
652 error = bus_dma_tag_create(bus_get_dma_tag(sc->sc_dev), 1, 0,
653 BUS_SPACE_MAXADDR_32BIT, BUS_SPACE_MAXADDR, NULL, NULL,
654 size, 1, size, 0, NULL, NULL, &sc->txwi_dmat);
655 #endif
656 if (error != 0) {
657 device_printf(sc->sc_dev, "could not create txwi DMA tag\n");
658 goto fail;
659 }
660
661 error = bus_dmamem_alloc(sc->txwi_dmat, (void **)&sc->txwi_vaddr,
662 BUS_DMA_NOWAIT | BUS_DMA_ZERO, &sc->txwi_map);
663 if (error != 0) {
664 device_printf(sc->sc_dev, "could not allocate DMA memory\n");
665 goto fail;
666 }
667
668 error = bus_dmamap_load(sc->txwi_dmat, sc->txwi_map,
669 sc->txwi_vaddr, size, rt2860_dma_map_addr, &paddr, 0);
670 if (error != 0) {
671 device_printf(sc->sc_dev, "could not load txwi DMA map\n");
672 goto fail;
673 }
674
675 bus_dmamap_sync(sc->txwi_dmat, sc->txwi_map, BUS_DMASYNC_PREWRITE);
676
677 vaddr = sc->txwi_vaddr;
678 for (i = 0; i < RT2860_TX_POOL_COUNT; i++) {
679 struct rt2860_tx_data *data = &sc->data[i];
680
681 error = bus_dmamap_create(sc->txwi_dmat, 0, &data->map);
682 if (error != 0) {
683 device_printf(sc->sc_dev, "could not create DMA map\n");
684 goto fail;
685 }
686 data->txwi = (struct rt2860_txwi *)vaddr;
687 data->paddr = paddr;
688 vaddr += RT2860_TXWI_DMASZ;
689 paddr += RT2860_TXWI_DMASZ;
690
691 SLIST_INSERT_HEAD(&sc->data_pool, data, next);
692 }
693
694 return 0;
695
696 fail: rt2860_free_tx_pool(sc);
697 return error;
698 }
699
700 void
701 rt2860_free_tx_pool(struct rt2860_softc *sc)
702 {
703 if (sc->txwi_vaddr != NULL) {
704 bus_dmamap_sync(sc->txwi_dmat, sc->txwi_map,
705 BUS_DMASYNC_POSTWRITE);
706 bus_dmamap_unload(sc->txwi_dmat, sc->txwi_map);
707 bus_dmamem_free(sc->txwi_dmat, sc->txwi_vaddr, sc->txwi_map);
708 }
709 if (sc->txwi_dmat != NULL)
710 bus_dma_tag_destroy(sc->txwi_dmat);
711
712 while (!SLIST_EMPTY(&sc->data_pool)) {
713 struct rt2860_tx_data *data;
714 data = SLIST_FIRST(&sc->data_pool);
715 bus_dmamap_destroy(sc->txwi_dmat, data->map);
716 SLIST_REMOVE_HEAD(&sc->data_pool, next);
717 }
718 }
719
720 int
721 rt2860_alloc_rx_ring(struct rt2860_softc *sc, struct rt2860_rx_ring *ring)
722 {
723 bus_addr_t physaddr;
724 int i, size, error;
725
726 size = RT2860_RX_RING_COUNT * sizeof (struct rt2860_rxd);
727
728 #if defined(__DragonFly__)
729 error = bus_dma_tag_create(bus_get_dma_tag(sc->sc_dev), 16, 0,
730 BUS_SPACE_MAXADDR_32BIT, BUS_SPACE_MAXADDR, NULL, NULL,
731 size, 1, size, 0, &ring->desc_dmat);
732 #else
733 error = bus_dma_tag_create(bus_get_dma_tag(sc->sc_dev), 16, 0,
734 BUS_SPACE_MAXADDR_32BIT, BUS_SPACE_MAXADDR, NULL, NULL,
735 size, 1, size, 0, NULL, NULL, &ring->desc_dmat);
736 #endif
737 if (error != 0) {
738 device_printf(sc->sc_dev, "could not create desc DMA tag\n");
739 goto fail;
740 }
741
742 error = bus_dmamem_alloc(ring->desc_dmat, (void **)&ring->rxd,
743 BUS_DMA_NOWAIT | BUS_DMA_ZERO, &ring->desc_map);
744 if (error != 0) {
745 device_printf(sc->sc_dev, "could not allocate DMA memory\n");
746 goto fail;
747 }
748
749 error = bus_dmamap_load(ring->desc_dmat, ring->desc_map, ring->rxd,
750 size, rt2860_dma_map_addr, &ring->paddr, 0);
751 if (error != 0) {
752 device_printf(sc->sc_dev, "could not load desc DMA map\n");
753 goto fail;
754 }
755
756 #if defined(__DragonFly__)
757 error = bus_dma_tag_create(bus_get_dma_tag(sc->sc_dev), 4, 0,
758 BUS_SPACE_MAXADDR_32BIT, BUS_SPACE_MAXADDR, NULL, NULL, MCLBYTES,
759 1, MCLBYTES, 0, &ring->data_dmat);
760 #else
761 error = bus_dma_tag_create(bus_get_dma_tag(sc->sc_dev), 1, 0,
762 BUS_SPACE_MAXADDR_32BIT, BUS_SPACE_MAXADDR, NULL, NULL, MCLBYTES,
763 1, MCLBYTES, 0, NULL, NULL, &ring->data_dmat);
764 #endif
765 if (error != 0) {
766 device_printf(sc->sc_dev, "could not create data DMA tag\n");
767 goto fail;
768 }
769
770 for (i = 0; i < RT2860_RX_RING_COUNT; i++) {
771 struct rt2860_rx_data *data = &ring->data[i];
772 struct rt2860_rxd *rxd = &ring->rxd[i];
773
774 error = bus_dmamap_create(ring->data_dmat, 0, &data->map);
775 if (error != 0) {
776 device_printf(sc->sc_dev, "could not create DMA map\n");
777 goto fail;
778 }
779
780 data->m = m_getcl(M_NOWAIT, MT_DATA, M_PKTHDR);
781 if (data->m == NULL) {
782 device_printf(sc->sc_dev,
783 "could not allocate rx mbuf\n");
784 error = ENOMEM;
785 goto fail;
786 }
787
788 error = bus_dmamap_load(ring->data_dmat, data->map,
789 mtod(data->m, void *), MCLBYTES, rt2860_dma_map_addr,
790 &physaddr, 0);
791 if (error != 0) {
792 device_printf(sc->sc_dev,
793 "could not load rx buf DMA map");
794 goto fail;
795 }
796
797 rxd->sdp0 = htole32(physaddr);
798 rxd->sdl0 = htole16(MCLBYTES);
799 }
800
801 bus_dmamap_sync(ring->desc_dmat, ring->desc_map, BUS_DMASYNC_PREWRITE);
802
803 return 0;
804
805 fail: rt2860_free_rx_ring(sc, ring);
806 return error;
807 }
808
809 void
810 rt2860_reset_rx_ring(struct rt2860_softc *sc, struct rt2860_rx_ring *ring)
811 {
812 int i;
813
814 for (i = 0; i < RT2860_RX_RING_COUNT; i++)
815 ring->rxd[i].sdl0 &= ~htole16(RT2860_RX_DDONE);
816
817 bus_dmamap_sync(ring->desc_dmat, ring->desc_map, BUS_DMASYNC_PREWRITE);
818
819 ring->cur = 0;
820 }
821
822 void
823 rt2860_free_rx_ring(struct rt2860_softc *sc, struct rt2860_rx_ring *ring)
824 {
825 int i;
826
827 if (ring->rxd != NULL) {
828 bus_dmamap_sync(ring->desc_dmat, ring->desc_map,
829 BUS_DMASYNC_POSTWRITE);
830 bus_dmamap_unload(ring->desc_dmat, ring->desc_map);
831 bus_dmamem_free(ring->desc_dmat, ring->rxd, ring->desc_map);
832 }
833 if (ring->desc_dmat != NULL)
834 bus_dma_tag_destroy(ring->desc_dmat);
835
836 for (i = 0; i < RT2860_RX_RING_COUNT; i++) {
837 struct rt2860_rx_data *data = &ring->data[i];
838
839 if (data->m != NULL) {
840 bus_dmamap_sync(ring->data_dmat, data->map,
841 BUS_DMASYNC_POSTREAD);
842 bus_dmamap_unload(ring->data_dmat, data->map);
843 m_freem(data->m);
844 }
845 if (data->map != NULL)
846 bus_dmamap_destroy(ring->data_dmat, data->map);
847 }
848 if (ring->data_dmat != NULL)
849 bus_dma_tag_destroy(ring->data_dmat);
850 }
851
852 static void
853 rt2860_updatestats(struct rt2860_softc *sc)
854 {
855 struct ieee80211com *ic = &sc->sc_ic;
856
857 /*
858 * In IBSS or HostAP modes (when the hardware sends beacons), the
859 * MAC can run into a livelock and start sending CTS-to-self frames
860 * like crazy if protection is enabled. Fortunately, we can detect
861 * when such a situation occurs and reset the MAC.
862 */
863 if (ic->ic_curmode != IEEE80211_M_STA) {
864 /* check if we're in a livelock situation.. */
865 uint32_t tmp = RAL_READ(sc, RT2860_DEBUG);
866 if ((tmp & (1 << 29)) && (tmp & (1 << 7 | 1 << 5))) {
867 /* ..and reset MAC/BBP for a while.. */
868 DPRINTF(("CTS-to-self livelock detected\n"));
869 RAL_WRITE(sc, RT2860_MAC_SYS_CTRL, RT2860_MAC_SRST);
870 RAL_BARRIER_WRITE(sc);
871 DELAY(1);
872 RAL_WRITE(sc, RT2860_MAC_SYS_CTRL,
873 RT2860_MAC_RX_EN | RT2860_MAC_TX_EN);
874 }
875 }
876 }
877
878 static void
879 rt2860_newassoc(struct ieee80211_node *ni, int isnew)
880 {
881 struct ieee80211com *ic = ni->ni_ic;
882 struct rt2860_softc *sc = ic->ic_softc;
883 uint8_t wcid;
884
885 wcid = IEEE80211_AID(ni->ni_associd);
886 if (isnew && ni->ni_associd != 0) {
887 sc->wcid2ni[wcid] = ni;
888
889 /* init WCID table entry */
890 RAL_WRITE_REGION_1(sc, RT2860_WCID_ENTRY(wcid),
891 ni->ni_macaddr, IEEE80211_ADDR_LEN);
892 }
893 DPRINTF(("new assoc isnew=%d addr=%s WCID=%d\n",
894 isnew, ether_sprintf(ni->ni_macaddr), wcid));
895 }
896
897 static void
898 rt2860_node_free(struct ieee80211_node *ni)
899 {
900 struct ieee80211com *ic = ni->ni_ic;
901 struct rt2860_softc *sc = ic->ic_softc;
902 uint8_t wcid;
903
904 if (ni->ni_associd != 0) {
905 wcid = IEEE80211_AID(ni->ni_associd);
906
907 /* clear Rx WCID search table entry */
908 RAL_SET_REGION_4(sc, RT2860_WCID_ENTRY(wcid), 0, 2);
909 }
910 sc->sc_node_free(ni);
911 }
912
913 #ifdef IEEE80211_HT
914 static int
915 rt2860_ampdu_rx_start(struct ieee80211com *ic, struct ieee80211_node *ni,
916 uint8_t tid)
917 {
918 struct rt2860_softc *sc = ic->ic_softc;
919 uint8_t wcid = ((struct rt2860_node *)ni)->wcid;
920 uint32_t tmp;
921
922 /* update BA session mask */
923 tmp = RAL_READ(sc, RT2860_WCID_ENTRY(wcid) + 4);
924 tmp |= (1 << tid) << 16;
925 RAL_WRITE(sc, RT2860_WCID_ENTRY(wcid) + 4, tmp);
926 return 0;
927 }
928
929 static void
930 rt2860_ampdu_rx_stop(struct ieee80211com *ic, struct ieee80211_node *ni,
931 uint8_t tid)
932 {
933 struct rt2860_softc *sc = ic->ic_softc;
934 uint8_t wcid = ((struct rt2860_node *)ni)->wcid;
935 uint32_t tmp;
936
937 /* update BA session mask */
938 tmp = RAL_READ(sc, RT2860_WCID_ENTRY(wcid) + 4);
939 tmp &= ~((1 << tid) << 16);
940 RAL_WRITE(sc, RT2860_WCID_ENTRY(wcid) + 4, tmp);
941 }
942 #endif
943
944 int
945 rt2860_newstate(struct ieee80211vap *vap, enum ieee80211_state nstate, int arg)
946 {
947 struct rt2860_vap *rvp = RT2860_VAP(vap);
948 struct ieee80211com *ic = vap->iv_ic;
949 struct rt2860_softc *sc = ic->ic_softc;
950 uint32_t tmp;
951 int error;
952
953 if (vap->iv_state == IEEE80211_S_RUN) {
954 /* turn link LED off */
955 rt2860_set_leds(sc, RT2860_LED_RADIO);
956 }
957
958 if (nstate == IEEE80211_S_INIT && vap->iv_state == IEEE80211_S_RUN) {
959 /* abort TSF synchronization */
960 tmp = RAL_READ(sc, RT2860_BCN_TIME_CFG);
961 RAL_WRITE(sc, RT2860_BCN_TIME_CFG,
962 tmp & ~(RT2860_BCN_TX_EN | RT2860_TSF_TIMER_EN |
963 RT2860_TBTT_TIMER_EN));
964 }
965
966 rt2860_set_gp_timer(sc, 0);
967
968 error = rvp->ral_newstate(vap, nstate, arg);
969 if (error != 0)
970 return (error);
971
972 if (nstate == IEEE80211_S_RUN) {
973 struct ieee80211_node *ni = vap->iv_bss;
974
975 if (ic->ic_opmode != IEEE80211_M_MONITOR) {
976 rt2860_enable_mrr(sc);
977 rt2860_set_txpreamble(sc);
978 rt2860_set_basicrates(sc, &ni->ni_rates);
979 rt2860_set_bssid(sc, ni->ni_bssid);
980 }
981
982 if (vap->iv_opmode == IEEE80211_M_HOSTAP ||
983 vap->iv_opmode == IEEE80211_M_IBSS ||
984 vap->iv_opmode == IEEE80211_M_MBSS) {
985 error = rt2860_setup_beacon(sc, vap);
986 if (error != 0)
987 return error;
988 }
989
990 if (ic->ic_opmode != IEEE80211_M_MONITOR) {
991 rt2860_enable_tsf_sync(sc);
992 rt2860_set_gp_timer(sc, 500);
993 }
994
995 /* turn link LED on */
996 rt2860_set_leds(sc, RT2860_LED_RADIO |
997 (IEEE80211_IS_CHAN_2GHZ(ni->ni_chan) ?
998 RT2860_LED_LINK_2GHZ : RT2860_LED_LINK_5GHZ));
999 }
1000 return error;
1001 }
1002
1003 /* Read 16-bit from eFUSE ROM (>=RT3071 only.) */
1004 static uint16_t
1005 rt3090_efuse_read_2(struct rt2860_softc *sc, uint16_t addr)
1006 {
1007 uint32_t tmp;
1008 uint16_t reg;
1009 int ntries;
1010
1011 addr *= 2;
1012 /*-
1013 * Read one 16-byte block into registers EFUSE_DATA[0-3]:
1014 * DATA0: F E D C
1015 * DATA1: B A 9 8
1016 * DATA2: 7 6 5 4
1017 * DATA3: 3 2 1 0
1018 */
1019 tmp = RAL_READ(sc, RT3070_EFUSE_CTRL);
1020 tmp &= ~(RT3070_EFSROM_MODE_MASK | RT3070_EFSROM_AIN_MASK);
1021 tmp |= (addr & ~0xf) << RT3070_EFSROM_AIN_SHIFT | RT3070_EFSROM_KICK;
1022 RAL_WRITE(sc, RT3070_EFUSE_CTRL, tmp);
1023 for (ntries = 0; ntries < 500; ntries++) {
1024 tmp = RAL_READ(sc, RT3070_EFUSE_CTRL);
1025 if (!(tmp & RT3070_EFSROM_KICK))
1026 break;
1027 DELAY(2);
1028 }
1029 if (ntries == 500)
1030 return 0xffff;
1031
1032 if ((tmp & RT3070_EFUSE_AOUT_MASK) == RT3070_EFUSE_AOUT_MASK)
1033 return 0xffff; /* address not found */
1034
1035 /* determine to which 32-bit register our 16-bit word belongs */
1036 reg = RT3070_EFUSE_DATA3 - (addr & 0xc);
1037 tmp = RAL_READ(sc, reg);
1038
1039 return (addr & 2) ? tmp >> 16 : tmp & 0xffff;
1040 }
1041
1042 /*
1043 * Read 16 bits at address 'addr' from the serial EEPROM (either 93C46,
1044 * 93C66 or 93C86).
1045 */
1046 static uint16_t
1047 rt2860_eeprom_read_2(struct rt2860_softc *sc, uint16_t addr)
1048 {
1049 uint32_t tmp;
1050 uint16_t val;
1051 int n;
1052
1053 /* clock C once before the first command */
1054 RT2860_EEPROM_CTL(sc, 0);
1055
1056 RT2860_EEPROM_CTL(sc, RT2860_S);
1057 RT2860_EEPROM_CTL(sc, RT2860_S | RT2860_C);
1058 RT2860_EEPROM_CTL(sc, RT2860_S);
1059
1060 /* write start bit (1) */
1061 RT2860_EEPROM_CTL(sc, RT2860_S | RT2860_D);
1062 RT2860_EEPROM_CTL(sc, RT2860_S | RT2860_D | RT2860_C);
1063
1064 /* write READ opcode (10) */
1065 RT2860_EEPROM_CTL(sc, RT2860_S | RT2860_D);
1066 RT2860_EEPROM_CTL(sc, RT2860_S | RT2860_D | RT2860_C);
1067 RT2860_EEPROM_CTL(sc, RT2860_S);
1068 RT2860_EEPROM_CTL(sc, RT2860_S | RT2860_C);
1069
1070 /* write address (A5-A0 or A7-A0) */
1071 n = ((RAL_READ(sc, RT2860_PCI_EECTRL) & 0x30) == 0) ? 5 : 7;
1072 for (; n >= 0; n--) {
1073 RT2860_EEPROM_CTL(sc, RT2860_S |
1074 (((addr >> n) & 1) << RT2860_SHIFT_D));
1075 RT2860_EEPROM_CTL(sc, RT2860_S |
1076 (((addr >> n) & 1) << RT2860_SHIFT_D) | RT2860_C);
1077 }
1078
1079 RT2860_EEPROM_CTL(sc, RT2860_S);
1080
1081 /* read data Q15-Q0 */
1082 val = 0;
1083 for (n = 15; n >= 0; n--) {
1084 RT2860_EEPROM_CTL(sc, RT2860_S | RT2860_C);
1085 tmp = RAL_READ(sc, RT2860_PCI_EECTRL);
1086 val |= ((tmp & RT2860_Q) >> RT2860_SHIFT_Q) << n;
1087 RT2860_EEPROM_CTL(sc, RT2860_S);
1088 }
1089
1090 RT2860_EEPROM_CTL(sc, 0);
1091
1092 /* clear Chip Select and clock C */
1093 RT2860_EEPROM_CTL(sc, RT2860_S);
1094 RT2860_EEPROM_CTL(sc, 0);
1095 RT2860_EEPROM_CTL(sc, RT2860_C);
1096
1097 return val;
1098 }
1099
1100 static __inline uint16_t
1101 rt2860_srom_read(struct rt2860_softc *sc, uint8_t addr)
1102 {
1103 /* either eFUSE ROM or EEPROM */
1104 return sc->sc_srom_read(sc, addr);
1105 }
1106
1107 static void
1108 rt2860_intr_coherent(struct rt2860_softc *sc)
1109 {
1110 uint32_t tmp;
1111
1112 /* DMA finds data coherent event when checking the DDONE bit */
1113
1114 DPRINTF(("Tx/Rx Coherent interrupt\n"));
1115
1116 /* restart DMA engine */
1117 tmp = RAL_READ(sc, RT2860_WPDMA_GLO_CFG);
1118 tmp &= ~(RT2860_TX_WB_DDONE | RT2860_RX_DMA_EN | RT2860_TX_DMA_EN);
1119 RAL_WRITE(sc, RT2860_WPDMA_GLO_CFG, tmp);
1120
1121 (void)rt2860_txrx_enable(sc);
1122 }
1123
1124 static void
1125 rt2860_drain_stats_fifo(struct rt2860_softc *sc)
1126 {
1127 struct ieee80211_node *ni;
1128 uint32_t stat;
1129 int retrycnt;
1130 uint8_t wcid, mcs, pid;
1131
1132 /* drain Tx status FIFO (maxsize = 16) */
1133 while ((stat = RAL_READ(sc, RT2860_TX_STAT_FIFO)) & RT2860_TXQ_VLD) {
1134 DPRINTFN(4, ("tx stat 0x%08x\n", stat));
1135
1136 wcid = (stat >> RT2860_TXQ_WCID_SHIFT) & 0xff;
1137 ni = sc->wcid2ni[wcid];
1138
1139 /* if no ACK was requested, no feedback is available */
1140 if (!(stat & RT2860_TXQ_ACKREQ) || wcid == 0xff || ni == NULL)
1141 continue;
1142
1143 /* update per-STA AMRR stats */
1144 if (stat & RT2860_TXQ_OK) {
1145 /*
1146 * Check if there were retries, ie if the Tx success
1147 * rate is different from the requested rate. Note
1148 * that it works only because we do not allow rate
1149 * fallback from OFDM to CCK.
1150 */
1151 mcs = (stat >> RT2860_TXQ_MCS_SHIFT) & 0x7f;
1152 pid = (stat >> RT2860_TXQ_PID_SHIFT) & 0xf;
1153 if (mcs + 1 != pid)
1154 retrycnt = 1;
1155 else
1156 retrycnt = 0;
1157 ieee80211_ratectl_tx_complete(ni->ni_vap, ni,
1158 IEEE80211_RATECTL_TX_SUCCESS, &retrycnt, NULL);
1159 } else {
1160 ieee80211_ratectl_tx_complete(ni->ni_vap, ni,
1161 IEEE80211_RATECTL_TX_FAILURE, &retrycnt, NULL);
1162 if_inc_counter(ni->ni_vap->iv_ifp,
1163 IFCOUNTER_OERRORS, 1);
1164 }
1165 }
1166 }
1167
1168 static void
1169 rt2860_tx_intr(struct rt2860_softc *sc, int qid)
1170 {
1171 struct rt2860_tx_ring *ring = &sc->txq[qid];
1172 uint32_t hw;
1173
1174 rt2860_drain_stats_fifo(sc);
1175
1176 hw = RAL_READ(sc, RT2860_TX_DTX_IDX(qid));
1177 while (ring->next != hw) {
1178 struct rt2860_tx_data *data = ring->data[ring->next];
1179
1180 if (data != NULL) {
1181 bus_dmamap_sync(sc->txwi_dmat, data->map,
1182 BUS_DMASYNC_POSTWRITE);
1183 bus_dmamap_unload(sc->txwi_dmat, data->map);
1184 if (data->m->m_flags & M_TXCB) {
1185 ieee80211_process_callback(data->ni, data->m,
1186 0);
1187 }
1188 ieee80211_tx_complete(data->ni, data->m, 0);
1189 data->ni = NULL;
1190 data->m = NULL;
1191 SLIST_INSERT_HEAD(&sc->data_pool, data, next);
1192 ring->data[ring->next] = NULL;
1193 }
1194 ring->queued--;
1195 ring->next = (ring->next + 1) % RT2860_TX_RING_COUNT;
1196 }
1197
1198 sc->sc_tx_timer = 0;
1199 if (ring->queued < RT2860_TX_RING_COUNT)
1200 sc->qfullmsk &= ~(1 << qid);
1201 rt2860_start(sc);
1202 }
1203
1204 /*
1205 * Return the Rx chain with the highest RSSI for a given frame.
1206 */
1207 static __inline uint8_t
1208 rt2860_maxrssi_chain(struct rt2860_softc *sc, const struct rt2860_rxwi *rxwi)
1209 {
1210 uint8_t rxchain = 0;
1211
1212 if (sc->nrxchains > 1) {
1213 if (rxwi->rssi[1] > rxwi->rssi[rxchain])
1214 rxchain = 1;
1215 if (sc->nrxchains > 2)
1216 if (rxwi->rssi[2] > rxwi->rssi[rxchain])
1217 rxchain = 2;
1218 }
1219 return rxchain;
1220 }
1221
1222 static void
1223 rt2860_rx_intr(struct rt2860_softc *sc)
1224 {
1225 struct rt2860_rx_radiotap_header *tap;
1226 struct ieee80211com *ic = &sc->sc_ic;
1227 struct ieee80211_frame *wh;
1228 struct ieee80211_node *ni;
1229 struct mbuf *m, *m1;
1230 bus_addr_t physaddr;
1231 uint32_t hw;
1232 uint16_t phy;
1233 uint8_t ant;
1234 int8_t rssi, nf;
1235 int error;
1236
1237 hw = RAL_READ(sc, RT2860_FS_DRX_IDX) & 0xfff;
1238 while (sc->rxq.cur != hw) {
1239 struct rt2860_rx_data *data = &sc->rxq.data[sc->rxq.cur];
1240 struct rt2860_rxd *rxd = &sc->rxq.rxd[sc->rxq.cur];
1241 struct rt2860_rxwi *rxwi;
1242
1243 bus_dmamap_sync(sc->rxq.desc_dmat, sc->rxq.desc_map,
1244 BUS_DMASYNC_POSTREAD);
1245
1246 if (__predict_false(!(rxd->sdl0 & htole16(RT2860_RX_DDONE)))) {
1247 DPRINTF(("RXD DDONE bit not set!\n"));
1248 break; /* should not happen */
1249 }
1250
1251 if (__predict_false(rxd->flags &
1252 htole32(RT2860_RX_CRCERR | RT2860_RX_ICVERR))) {
1253 #if defined(__DragonFly__)
1254 /* not implemented */
1255 #else
1256 counter_u64_add(ic->ic_ierrors, 1);
1257 #endif
1258 goto skip;
1259 }
1260
1261 #ifdef HW_CRYPTO
1262 if (__predict_false(rxd->flags & htole32(RT2860_RX_MICERR))) {
1263 /* report MIC failures to net80211 for TKIP */
1264 ic->ic_stats.is_rx_locmicfail++;
1265 ieee80211_michael_mic_failure(ic, 0/* XXX */);
1266 #if defined(__DragonFly__)
1267 /* not implemented */
1268 #else
1269 counter_u64_add(ic->ic_ierrors, 1);
1270 #endif
1271 goto skip;
1272 }
1273 #endif
1274
1275 m1 = m_getcl(M_NOWAIT, MT_DATA, M_PKTHDR);
1276 if (__predict_false(m1 == NULL)) {
1277 #if defined(__DragonFly__)
1278 /* not implemented */
1279 #else
1280 counter_u64_add(ic->ic_ierrors, 1);
1281 #endif
1282 goto skip;
1283 }
1284
1285 bus_dmamap_sync(sc->rxq.data_dmat, data->map,
1286 BUS_DMASYNC_POSTREAD);
1287 bus_dmamap_unload(sc->rxq.data_dmat, data->map);
1288
1289 error = bus_dmamap_load(sc->rxq.data_dmat, data->map,
1290 mtod(m1, void *), MCLBYTES, rt2860_dma_map_addr,
1291 &physaddr, 0);
1292 if (__predict_false(error != 0)) {
1293 m_freem(m1);
1294
1295 /* try to reload the old mbuf */
1296 error = bus_dmamap_load(sc->rxq.data_dmat, data->map,
1297 mtod(data->m, void *), MCLBYTES,
1298 rt2860_dma_map_addr, &physaddr, 0);
1299 if (__predict_false(error != 0)) {
1300 panic("%s: could not load old rx mbuf",
1301 device_get_name(sc->sc_dev));
1302 }
1303 /* physical address may have changed */
1304 rxd->sdp0 = htole32(physaddr);
1305 #if defined(__DragonFly__)
1306 /* not implemented */
1307 #else
1308 counter_u64_add(ic->ic_ierrors, 1);
1309 #endif
1310 goto skip;
1311 }
1312
1313 /*
1314 * New mbuf successfully loaded, update Rx ring and continue
1315 * processing.
1316 */
1317 m = data->m;
1318 data->m = m1;
1319 rxd->sdp0 = htole32(physaddr);
1320
1321 rxwi = mtod(m, struct rt2860_rxwi *);
1322
1323 /* finalize mbuf */
1324 m->m_data = (caddr_t)(rxwi + 1);
1325 m->m_pkthdr.len = m->m_len = le16toh(rxwi->len) & 0xfff;
1326
1327 wh = mtod(m, struct ieee80211_frame *);
1328 #ifdef HW_CRYPTO
1329 if (wh->i_fc[1] & IEEE80211_FC1_PROTECTED) {
1330 /* frame is decrypted by hardware */
1331 wh->i_fc[1] &= ~IEEE80211_FC1_PROTECTED;
1332 }
1333 #endif
1334
1335 /* HW may insert 2 padding bytes after 802.11 header */
1336 if (rxd->flags & htole32(RT2860_RX_L2PAD)) {
1337 u_int hdrlen = ieee80211_hdrsize(wh);
1338 bcopy(wh, (caddr_t)wh + 2, hdrlen);
1339 m->m_data += 2;
1340 wh = mtod(m, struct ieee80211_frame *);
1341 }
1342
1343 ant = rt2860_maxrssi_chain(sc, rxwi);
1344 rssi = rt2860_rssi2dbm(sc, rxwi->rssi[ant], ant);
1345 nf = RT2860_NOISE_FLOOR;
1346
1347 if (ieee80211_radiotap_active(ic)) {
1348 tap = &sc->sc_rxtap;
1349 tap->wr_flags = 0;
1350 tap->wr_antenna = ant;
1351 tap->wr_antsignal = nf + rssi;
1352 tap->wr_antnoise = nf;
1353 /* in case it can't be found below */
1354 tap->wr_rate = 2;
1355 phy = le16toh(rxwi->phy);
1356 switch (phy & RT2860_PHY_MODE) {
1357 case RT2860_PHY_CCK:
1358 switch ((phy & RT2860_PHY_MCS) & ~RT2860_PHY_SHPRE) {
1359 case 0: tap->wr_rate = 2; break;
1360 case 1: tap->wr_rate = 4; break;
1361 case 2: tap->wr_rate = 11; break;
1362 case 3: tap->wr_rate = 22; break;
1363 }
1364 if (phy & RT2860_PHY_SHPRE)
1365 tap->wr_flags |= IEEE80211_RADIOTAP_F_SHORTPRE;
1366 break;
1367 case RT2860_PHY_OFDM:
1368 switch (phy & RT2860_PHY_MCS) {
1369 case 0: tap->wr_rate = 12; break;
1370 case 1: tap->wr_rate = 18; break;
1371 case 2: tap->wr_rate = 24; break;
1372 case 3: tap->wr_rate = 36; break;
1373 case 4: tap->wr_rate = 48; break;
1374 case 5: tap->wr_rate = 72; break;
1375 case 6: tap->wr_rate = 96; break;
1376 case 7: tap->wr_rate = 108; break;
1377 }
1378 break;
1379 }
1380 }
1381
1382 RAL_UNLOCK(sc);
1383 wh = mtod(m, struct ieee80211_frame *);
1384
1385 /* send the frame to the 802.11 layer */
1386 ni = ieee80211_find_rxnode(ic,
1387 (struct ieee80211_frame_min *)wh);
1388 if (ni != NULL) {
1389 (void)ieee80211_input(ni, m, rssi - nf, nf);
1390 ieee80211_free_node(ni);
1391 } else
1392 (void)ieee80211_input_all(ic, m, rssi - nf, nf);
1393
1394 RAL_LOCK(sc);
1395
1396 skip: rxd->sdl0 &= ~htole16(RT2860_RX_DDONE);
1397
1398 bus_dmamap_sync(sc->rxq.desc_dmat, sc->rxq.desc_map,
1399 BUS_DMASYNC_PREWRITE);
1400
1401 sc->rxq.cur = (sc->rxq.cur + 1) % RT2860_RX_RING_COUNT;
1402 }
1403
1404 /* tell HW what we have processed */
1405 RAL_WRITE(sc, RT2860_RX_CALC_IDX,
1406 (sc->rxq.cur - 1) % RT2860_RX_RING_COUNT);
1407 }
1408
1409 static void
1410 rt2860_tbtt_intr(struct rt2860_softc *sc)
1411 {
1412 #if 0
1413 struct ieee80211com *ic = &sc->sc_ic;
1414
1415 #ifndef IEEE80211_STA_ONLY
1416 if (ic->ic_opmode == IEEE80211_M_HOSTAP) {
1417 /* one less beacon until next DTIM */
1418 if (ic->ic_dtim_count == 0)
1419 ic->ic_dtim_count = ic->ic_dtim_period - 1;
1420 else
1421 ic->ic_dtim_count--;
1422
1423 /* update dynamic parts of beacon */
1424 rt2860_setup_beacon(sc);
1425
1426 /* flush buffered multicast frames */
1427 if (ic->ic_dtim_count == 0)
1428 ieee80211_notify_dtim(ic);
1429 }
1430 #endif
1431 /* check if protection mode has changed */
1432 if ((sc->sc_ic_flags ^ ic->ic_flags) & IEEE80211_F_USEPROT) {
1433 rt2860_updateprot(sc);
1434 sc->sc_ic_flags = ic->ic_flags;
1435 }
1436 #endif
1437 }
1438
1439 static void
1440 rt2860_gp_intr(struct rt2860_softc *sc)
1441 {
1442 struct ieee80211com *ic = &sc->sc_ic;
1443 struct ieee80211vap *vap = TAILQ_FIRST(&ic->ic_vaps);
1444
1445 DPRINTFN(2, ("GP timeout state=%d\n", vap->iv_state));
1446
1447 if (vap->iv_state == IEEE80211_S_RUN)
1448 rt2860_updatestats(sc);
1449 }
1450
1451 void
1452 rt2860_intr(void *arg)
1453 {
1454 struct rt2860_softc *sc = arg;
1455 uint32_t r;
1456
1457 RAL_LOCK(sc);
1458
1459 r = RAL_READ(sc, RT2860_INT_STATUS);
1460 if (__predict_false(r == 0xffffffff)) {
1461 RAL_UNLOCK(sc);
1462 return; /* device likely went away */
1463 }
1464 if (r == 0) {
1465 RAL_UNLOCK(sc);
1466 return; /* not for us */
1467 }
1468
1469 /* acknowledge interrupts */
1470 RAL_WRITE(sc, RT2860_INT_STATUS, r);
1471
1472 if (r & RT2860_TX_RX_COHERENT)
1473 rt2860_intr_coherent(sc);
1474
1475 if (r & RT2860_MAC_INT_2) /* TX status */
1476 rt2860_drain_stats_fifo(sc);
1477
1478 if (r & RT2860_TX_DONE_INT5)
1479 rt2860_tx_intr(sc, 5);
1480
1481 if (r & RT2860_RX_DONE_INT)
1482 rt2860_rx_intr(sc);
1483
1484 if (r & RT2860_TX_DONE_INT4)
1485 rt2860_tx_intr(sc, 4);
1486
1487 if (r & RT2860_TX_DONE_INT3)
1488 rt2860_tx_intr(sc, 3);
1489
1490 if (r & RT2860_TX_DONE_INT2)
1491 rt2860_tx_intr(sc, 2);
1492
1493 if (r & RT2860_TX_DONE_INT1)
1494 rt2860_tx_intr(sc, 1);
1495
1496 if (r & RT2860_TX_DONE_INT0)
1497 rt2860_tx_intr(sc, 0);
1498
1499 if (r & RT2860_MAC_INT_0) /* TBTT */
1500 rt2860_tbtt_intr(sc);
1501
1502 if (r & RT2860_MAC_INT_3) { /* Auto wakeup */
1503 /* TBD wakeup */;
1504 }
1505
1506 if (r & RT2860_MAC_INT_4) /* GP timer */
1507 rt2860_gp_intr(sc);
1508
1509 RAL_UNLOCK(sc);
1510 }
1511
1512 static int
1513 rt2860_tx(struct rt2860_softc *sc, struct mbuf *m, struct ieee80211_node *ni)
1514 {
1515 struct ieee80211com *ic = &sc->sc_ic;
1516 struct ieee80211vap *vap = ni->ni_vap;
1517 struct rt2860_tx_ring *ring;
1518 struct rt2860_tx_data *data;
1519 struct rt2860_txd *txd;
1520 struct rt2860_txwi *txwi;
1521 struct ieee80211_frame *wh;
1522 const struct ieee80211_txparam *tp;
1523 struct ieee80211_key *k;
1524 struct mbuf *m1;
1525 bus_dma_segment_t segs[RT2860_MAX_SCATTER];
1526 bus_dma_segment_t *seg;
1527 u_int hdrlen;
1528 uint16_t qos, dur;
1529 uint8_t type, qsel, mcs, pid, tid, qid;
1530 int i, nsegs, ntxds, pad, rate, ridx, error;
1531
1532 #if defined(__DragonFly__)
1533 ntxds = 0; /* quiet gcc5 */
1534 #endif
1535 /* the data pool contains at least one element, pick the first */
1536 data = SLIST_FIRST(&sc->data_pool);
1537
1538 wh = mtod(m, struct ieee80211_frame *);
1539
1540 if (wh->i_fc[1] & IEEE80211_FC1_PROTECTED) {
1541 k = ieee80211_crypto_encap(ni, m);
1542 if (k == NULL) {
1543 m_freem(m);
1544 return ENOBUFS;
1545 }
1546
1547 /* packet header may have moved, reset our local pointer */
1548 wh = mtod(m, struct ieee80211_frame *);
1549 }
1550
1551 hdrlen = ieee80211_anyhdrsize(wh);
1552 type = wh->i_fc[0] & IEEE80211_FC0_TYPE_MASK;
1553
1554 tp = &vap->iv_txparms[ieee80211_chan2mode(ni->ni_chan)];
1555 if (IEEE80211_IS_MULTICAST(wh->i_addr1)) {
1556 rate = tp->mcastrate;
1557 } else if (m->m_flags & M_EAPOL) {
1558 rate = tp->mgmtrate;
1559 } else if (tp->ucastrate != IEEE80211_FIXED_RATE_NONE) {
1560 rate = tp->ucastrate;
1561 } else {
1562 (void) ieee80211_ratectl_rate(ni, NULL, 0);
1563 rate = ni->ni_txrate;
1564 }
1565 rate &= IEEE80211_RATE_VAL;
1566
1567 qid = M_WME_GETAC(m);
1568 if (IEEE80211_QOS_HAS_SEQ(wh)) {
1569 qos = ((const struct ieee80211_qosframe *)wh)->i_qos[0];
1570 tid = qos & IEEE80211_QOS_TID;
1571 } else {
1572 qos = 0;
1573 tid = 0;
1574 }
1575 ring = &sc->txq[qid];
1576 ridx = ieee80211_legacy_rate_lookup(ic->ic_rt, rate);
1577
1578 /* get MCS code from rate index */
1579 mcs = rt2860_rates[ridx].mcs;
1580
1581 /* setup TX Wireless Information */
1582 txwi = data->txwi;
1583 txwi->flags = 0;
1584 /* let HW generate seq numbers for non-QoS frames */
1585 txwi->xflags = qos ? 0 : RT2860_TX_NSEQ;
1586 if (type == IEEE80211_FC0_TYPE_DATA)
1587 txwi->wcid = IEEE80211_AID(ni->ni_associd);
1588 else
1589 txwi->wcid = 0xff;
1590 txwi->len = htole16(m->m_pkthdr.len);
1591 if (rt2860_rates[ridx].phy == IEEE80211_T_DS) {
1592 txwi->phy = htole16(RT2860_PHY_CCK);
1593 if (ridx != RT2860_RIDX_CCK1 &&
1594 (ic->ic_flags & IEEE80211_F_SHPREAMBLE))
1595 mcs |= RT2860_PHY_SHPRE;
1596 } else
1597 txwi->phy = htole16(RT2860_PHY_OFDM);
1598 txwi->phy |= htole16(mcs);
1599
1600 /*
1601 * We store the MCS code into the driver-private PacketID field.
1602 * The PacketID is latched into TX_STAT_FIFO when Tx completes so
1603 * that we know at which initial rate the frame was transmitted.
1604 * We add 1 to the MCS code because setting the PacketID field to
1605 * 0 means that we don't want feedback in TX_STAT_FIFO.
1606 */
1607 pid = (mcs + 1) & 0xf;
1608 txwi->len |= htole16(pid << RT2860_TX_PID_SHIFT);
1609
1610 /* check if RTS/CTS or CTS-to-self protection is required */
1611 if (!IEEE80211_IS_MULTICAST(wh->i_addr1) &&
1612 (m->m_pkthdr.len + IEEE80211_CRC_LEN > vap->iv_rtsthreshold ||
1613 ((ic->ic_flags & IEEE80211_F_USEPROT) &&
1614 rt2860_rates[ridx].phy == IEEE80211_T_OFDM)))
1615 txwi->txop = RT2860_TX_TXOP_HT;
1616 else
1617 txwi->txop = RT2860_TX_TXOP_BACKOFF;
1618
1619 if (!IEEE80211_IS_MULTICAST(wh->i_addr1) &&
1620 (!qos || (qos & IEEE80211_QOS_ACKPOLICY) !=
1621 IEEE80211_QOS_ACKPOLICY_NOACK)) {
1622 txwi->xflags |= RT2860_TX_ACK;
1623
1624 if (ic->ic_flags & IEEE80211_F_SHPREAMBLE)
1625 dur = rt2860_rates[ridx].sp_ack_dur;
1626 else
1627 dur = rt2860_rates[ridx].lp_ack_dur;
1628 *(uint16_t *)wh->i_dur = htole16(dur);
1629 }
1630 /* ask MAC to insert timestamp into probe responses */
1631 if ((wh->i_fc[0] &
1632 (IEEE80211_FC0_TYPE_MASK | IEEE80211_FC0_SUBTYPE_MASK)) ==
1633 (IEEE80211_FC0_TYPE_MGT | IEEE80211_FC0_SUBTYPE_PROBE_RESP))
1634 /* NOTE: beacons do not pass through tx_data() */
1635 txwi->flags |= RT2860_TX_TS;
1636
1637 if (ieee80211_radiotap_active_vap(vap)) {
1638 struct rt2860_tx_radiotap_header *tap = &sc->sc_txtap;
1639
1640 tap->wt_flags = 0;
1641 tap->wt_rate = rate;
1642 if (mcs & RT2860_PHY_SHPRE)
1643 tap->wt_flags |= IEEE80211_RADIOTAP_F_SHORTPRE;
1644
1645 ieee80211_radiotap_tx(vap, m);
1646 }
1647
1648 pad = (hdrlen + 3) & ~3;
1649
1650 /* copy and trim 802.11 header */
1651 memcpy(txwi + 1, wh, hdrlen);
1652 m_adj(m, hdrlen);
1653
1654 #if defined(__DragonFly__)
1655 error = bus_dmamap_load_mbuf_segment(sc->txwi_dmat, data->map, m,
1656 segs, 1, &nsegs, BUS_DMA_NOWAIT);
1657 #else
1658 error = bus_dmamap_load_mbuf_sg(sc->txwi_dmat, data->map, m, segs,
1659 &nsegs, 0);
1660 #endif
1661 if (__predict_false(error != 0 && error != EFBIG)) {
1662 device_printf(sc->sc_dev, "can't map mbuf (error %d)\n",
1663 error);
1664 m_freem(m);
1665 return error;
1666 }
1667 if (__predict_true(error == 0)) {
1668 /* determine how many TXDs are required */
1669 ntxds = 1 + (nsegs / 2);
1670
1671 if (ring->queued + ntxds >= RT2860_TX_RING_COUNT) {
1672 /* not enough free TXDs, force mbuf defrag */
1673 bus_dmamap_unload(sc->txwi_dmat, data->map);
1674 error = EFBIG;
1675 }
1676 }
1677 if (__predict_false(error != 0)) {
1678 m1 = m_defrag(m, M_NOWAIT);
1679 if (m1 == NULL) {
1680 device_printf(sc->sc_dev,
1681 "could not defragment mbuf\n");
1682 m_freem(m);
1683 return ENOBUFS;
1684 }
1685 m = m1;
1686
1687 #if defined(__DragonFly__)
1688 error = bus_dmamap_load_mbuf_segment(sc->txwi_dmat, data->map,
1689 m, segs, 1, &nsegs, BUS_DMA_NOWAIT);
1690 #else
1691 error = bus_dmamap_load_mbuf_sg(sc->txwi_dmat, data->map, m,
1692 segs, &nsegs, 0);
1693 #endif
1694 if (__predict_false(error != 0)) {
1695 device_printf(sc->sc_dev, "can't map mbuf (error %d)\n",
1696 error);
1697 m_freem(m);
1698 return error;
1699 }
1700
1701 /* determine how many TXDs are now required */
1702 ntxds = 1 + (nsegs / 2);
1703
1704 if (ring->queued + ntxds >= RT2860_TX_RING_COUNT) {
1705 /* this is a hopeless case, drop the mbuf! */
1706 bus_dmamap_unload(sc->txwi_dmat, data->map);
1707 m_freem(m);
1708 return ENOBUFS;
1709 }
1710 }
1711
1712 qsel = (qid < WME_NUM_AC) ? RT2860_TX_QSEL_EDCA : RT2860_TX_QSEL_MGMT;
1713
1714 /* first segment is TXWI + 802.11 header */
1715 txd = &ring->txd[ring->cur];
1716 txd->sdp0 = htole32(data->paddr);
1717 txd->sdl0 = htole16(sizeof (struct rt2860_txwi) + pad);
1718 txd->flags = qsel;
1719
1720 /* setup payload segments */
1721 seg = &segs[0];
1722 for (i = nsegs; i >= 2; i -= 2) {
1723 txd->sdp1 = htole32(seg->ds_addr);
1724 txd->sdl1 = htole16(seg->ds_len);
1725 seg++;
1726 ring->cur = (ring->cur + 1) % RT2860_TX_RING_COUNT;
1727 /* grab a new Tx descriptor */
1728 txd = &ring->txd[ring->cur];
1729 txd->sdp0 = htole32(seg->ds_addr);
1730 txd->sdl0 = htole16(seg->ds_len);
1731 txd->flags = qsel;
1732 seg++;
1733 }
1734 /* finalize last segment */
1735 if (i > 0) {
1736 txd->sdp1 = htole32(seg->ds_addr);
1737 txd->sdl1 = htole16(seg->ds_len | RT2860_TX_LS1);
1738 } else {
1739 txd->sdl0 |= htole16(RT2860_TX_LS0);
1740 txd->sdl1 = 0;
1741 }
1742
1743 /* remove from the free pool and link it into the SW Tx slot */
1744 SLIST_REMOVE_HEAD(&sc->data_pool, next);
1745 data->m = m;
1746 data->ni = ni;
1747 ring->data[ring->cur] = data;
1748
1749 bus_dmamap_sync(sc->txwi_dmat, sc->txwi_map, BUS_DMASYNC_PREWRITE);
1750 bus_dmamap_sync(sc->txwi_dmat, data->map, BUS_DMASYNC_PREWRITE);
1751 bus_dmamap_sync(ring->desc_dmat, ring->desc_map, BUS_DMASYNC_PREWRITE);
1752
1753 DPRINTFN(4, ("sending frame qid=%d wcid=%d nsegs=%d ridx=%d\n",
1754 qid, txwi->wcid, nsegs, ridx));
1755
1756 ring->cur = (ring->cur + 1) % RT2860_TX_RING_COUNT;
1757 ring->queued += ntxds;
1758 if (ring->queued >= RT2860_TX_RING_COUNT)
1759 sc->qfullmsk |= 1 << qid;
1760
1761 /* kick Tx */
1762 RAL_WRITE(sc, RT2860_TX_CTX_IDX(qid), ring->cur);
1763
1764 return 0;
1765 }
1766
1767 static int
1768 rt2860_raw_xmit(struct ieee80211_node *ni, struct mbuf *m,
1769 const struct ieee80211_bpf_params *params)
1770 {
1771 struct ieee80211com *ic = ni->ni_ic;
1772 struct rt2860_softc *sc = ic->ic_softc;
1773 int error;
1774
1775 RAL_LOCK(sc);
1776
1777 /* prevent management frames from being sent if we're not ready */
1778 if (!(sc->sc_flags & RT2860_RUNNING)) {
1779 RAL_UNLOCK(sc);
1780 m_freem(m);
1781 return ENETDOWN;
1782 }
1783 if (params == NULL) {
1784 /*
1785 * Legacy path; interpret frame contents to decide
1786 * precisely how to send the frame.
1787 */
1788 error = rt2860_tx(sc, m, ni);
1789 } else {
1790 /*
1791 * Caller supplied explicit parameters to use in
1792 * sending the frame.
1793 */
1794 error = rt2860_tx_raw(sc, m, ni, params);
1795 }
1796 sc->sc_tx_timer = 5;
1797 RAL_UNLOCK(sc);
1798 return error;
1799 }
1800
1801 static int
1802 rt2860_tx_raw(struct rt2860_softc *sc, struct mbuf *m,
1803 struct ieee80211_node *ni, const struct ieee80211_bpf_params *params)
1804 {
1805 struct ieee80211com *ic = &sc->sc_ic;
1806 struct ieee80211vap *vap = ni->ni_vap;
1807 struct rt2860_tx_ring *ring;
1808 struct rt2860_tx_data *data;
1809 struct rt2860_txd *txd;
1810 struct rt2860_txwi *txwi;
1811 struct ieee80211_frame *wh;
1812 struct mbuf *m1;
1813 bus_dma_segment_t segs[RT2860_MAX_SCATTER];
1814 bus_dma_segment_t *seg;
1815 u_int hdrlen;
1816 uint16_t dur;
1817 uint8_t type, qsel, mcs, pid, tid, qid;
1818 int i, nsegs, ntxds, pad, rate, ridx, error;
1819
1820 #if defined(__DragonFly__)
1821 ntxds = 0; /* quiet gcc5 */
1822 #endif
1823 /* the data pool contains at least one element, pick the first */
1824 data = SLIST_FIRST(&sc->data_pool);
1825
1826 wh = mtod(m, struct ieee80211_frame *);
1827 hdrlen = ieee80211_hdrsize(wh);
1828 type = wh->i_fc[0] & IEEE80211_FC0_TYPE_MASK;
1829
1830 /* Choose a TX rate index. */
1831 rate = params->ibp_rate0;
1832 ridx = ieee80211_legacy_rate_lookup(ic->ic_rt,
1833 rate & IEEE80211_RATE_VAL);
1834 if (ridx == (uint8_t)-1) {
1835 /* XXX fall back to mcast/mgmt rate? */
1836 m_freem(m);
1837 return EINVAL;
1838 }
1839
1840 qid = params->ibp_pri & 3;
1841 tid = 0;
1842 ring = &sc->txq[qid];
1843
1844 /* get MCS code from rate index */
1845 mcs = rt2860_rates[ridx].mcs;
1846
1847 /* setup TX Wireless Information */
1848 txwi = data->txwi;
1849 txwi->flags = 0;
1850 /* let HW generate seq numbers for non-QoS frames */
1851 txwi->xflags = params->ibp_pri & 3 ? 0 : RT2860_TX_NSEQ;
1852 txwi->wcid = 0xff;
1853 txwi->len = htole16(m->m_pkthdr.len);
1854 if (rt2860_rates[ridx].phy == IEEE80211_T_DS) {
1855 txwi->phy = htole16(RT2860_PHY_CCK);
1856 if (ridx != RT2860_RIDX_CCK1 &&
1857 (ic->ic_flags & IEEE80211_F_SHPREAMBLE))
1858 mcs |= RT2860_PHY_SHPRE;
1859 } else
1860 txwi->phy = htole16(RT2860_PHY_OFDM);
1861 txwi->phy |= htole16(mcs);
1862
1863 /*
1864 * We store the MCS code into the driver-private PacketID field.
1865 * The PacketID is latched into TX_STAT_FIFO when Tx completes so
1866 * that we know at which initial rate the frame was transmitted.
1867 * We add 1 to the MCS code because setting the PacketID field to
1868 * 0 means that we don't want feedback in TX_STAT_FIFO.
1869 */
1870 pid = (mcs + 1) & 0xf;
1871 txwi->len |= htole16(pid << RT2860_TX_PID_SHIFT);
1872
1873 /* check if RTS/CTS or CTS-to-self protection is required */
1874 if (params->ibp_flags & IEEE80211_BPF_RTS ||
1875 params->ibp_flags & IEEE80211_BPF_CTS)
1876 txwi->txop = RT2860_TX_TXOP_HT;
1877 else
1878 txwi->txop = RT2860_TX_TXOP_BACKOFF;
1879 if ((params->ibp_flags & IEEE80211_BPF_NOACK) == 0) {
1880 txwi->xflags |= RT2860_TX_ACK;
1881
1882 if (ic->ic_flags & IEEE80211_F_SHPREAMBLE)
1883 dur = rt2860_rates[ridx].sp_ack_dur;
1884 else
1885 dur = rt2860_rates[ridx].lp_ack_dur;
1886 *(uint16_t *)wh->i_dur = htole16(dur);
1887 }
1888 /* ask MAC to insert timestamp into probe responses */
1889 if ((wh->i_fc[0] &
1890 (IEEE80211_FC0_TYPE_MASK | IEEE80211_FC0_SUBTYPE_MASK)) ==
1891 (IEEE80211_FC0_TYPE_MGT | IEEE80211_FC0_SUBTYPE_PROBE_RESP))
1892 /* NOTE: beacons do not pass through tx_data() */
1893 txwi->flags |= RT2860_TX_TS;
1894
1895 if (ieee80211_radiotap_active_vap(vap)) {
1896 struct rt2860_tx_radiotap_header *tap = &sc->sc_txtap;
1897
1898 tap->wt_flags = 0;
1899 tap->wt_rate = rate;
1900 if (mcs & RT2860_PHY_SHPRE)
1901 tap->wt_flags |= IEEE80211_RADIOTAP_F_SHORTPRE;
1902
1903 ieee80211_radiotap_tx(vap, m);
1904 }
1905
1906 pad = (hdrlen + 3) & ~3;
1907
1908 /* copy and trim 802.11 header */
1909 memcpy(txwi + 1, wh, hdrlen);
1910 m_adj(m, hdrlen);
1911
1912 #if defined(__DragonFly__)
1913 error = bus_dmamap_load_mbuf_segment(sc->txwi_dmat, data->map, m,
1914 segs, 1, &nsegs, BUS_DMA_NOWAIT);
1915 #else
1916 error = bus_dmamap_load_mbuf_sg(sc->txwi_dmat, data->map, m, segs,
1917 &nsegs, 0);
1918 #endif
1919 if (__predict_false(error != 0 && error != EFBIG)) {
1920 device_printf(sc->sc_dev, "can't map mbuf (error %d)\n",
1921 error);
1922 m_freem(m);
1923 return error;
1924 }
1925 if (__predict_true(error == 0)) {
1926 /* determine how many TXDs are required */
1927 ntxds = 1 + (nsegs / 2);
1928
1929 if (ring->queued + ntxds >= RT2860_TX_RING_COUNT) {
1930 /* not enough free TXDs, force mbuf defrag */
1931 bus_dmamap_unload(sc->txwi_dmat, data->map);
1932 error = EFBIG;
1933 }
1934 }
1935 if (__predict_false(error != 0)) {
1936 m1 = m_defrag(m, M_NOWAIT);
1937 if (m1 == NULL) {
1938 device_printf(sc->sc_dev,
1939 "could not defragment mbuf\n");
1940 m_freem(m);
1941 return ENOBUFS;
1942 }
1943 m = m1;
1944
1945 #if defined(__DragonFly__)
1946 error = bus_dmamap_load_mbuf_segment(sc->txwi_dmat, data->map,
1947 m, segs, 1, &nsegs, BUS_DMA_NOWAIT);
1948 #else
1949 error = bus_dmamap_load_mbuf_sg(sc->txwi_dmat, data->map, m,
1950 segs, &nsegs, 0);
1951 #endif
1952 if (__predict_false(error != 0)) {
1953 device_printf(sc->sc_dev, "can't map mbuf (error %d)\n",
1954 error);
1955 m_freem(m);
1956 return error;
1957 }
1958
1959 /* determine how many TXDs are now required */
1960 ntxds = 1 + (nsegs / 2);
1961
1962 if (ring->queued + ntxds >= RT2860_TX_RING_COUNT) {
1963 /* this is a hopeless case, drop the mbuf! */
1964 bus_dmamap_unload(sc->txwi_dmat, data->map);
1965 m_freem(m);
1966 return ENOBUFS;
1967 }
1968 }
1969
1970 qsel = (qid < WME_NUM_AC) ? RT2860_TX_QSEL_EDCA : RT2860_TX_QSEL_MGMT;
1971
1972 /* first segment is TXWI + 802.11 header */
1973 txd = &ring->txd[ring->cur];
1974 txd->sdp0 = htole32(data->paddr);
1975 txd->sdl0 = htole16(sizeof (struct rt2860_txwi) + pad);
1976 txd->flags = qsel;
1977
1978 /* setup payload segments */
1979 seg = &segs[0];
1980 for (i = nsegs; i >= 2; i -= 2) {
1981 txd->sdp1 = htole32(seg->ds_addr);
1982 txd->sdl1 = htole16(seg->ds_len);
1983 seg++;
1984 ring->cur = (ring->cur + 1) % RT2860_TX_RING_COUNT;
1985 /* grab a new Tx descriptor */
1986 txd = &ring->txd[ring->cur];
1987 txd->sdp0 = htole32(seg->ds_addr);
1988 txd->sdl0 = htole16(seg->ds_len);
1989 txd->flags = qsel;
1990 seg++;
1991 }
1992 /* finalize last segment */
1993 if (i > 0) {
1994 txd->sdp1 = htole32(seg->ds_addr);
1995 txd->sdl1 = htole16(seg->ds_len | RT2860_TX_LS1);
1996 } else {
1997 txd->sdl0 |= htole16(RT2860_TX_LS0);
1998 txd->sdl1 = 0;
1999 }
2000
2001 /* remove from the free pool and link it into the SW Tx slot */
2002 SLIST_REMOVE_HEAD(&sc->data_pool, next);
2003 data->m = m;
2004 data->ni = ni;
2005 ring->data[ring->cur] = data;
2006
2007 bus_dmamap_sync(sc->txwi_dmat, sc->txwi_map, BUS_DMASYNC_PREWRITE);
2008 bus_dmamap_sync(sc->txwi_dmat, data->map, BUS_DMASYNC_PREWRITE);
2009 bus_dmamap_sync(ring->desc_dmat, ring->desc_map, BUS_DMASYNC_PREWRITE);
2010
2011 DPRINTFN(4, ("sending frame qid=%d wcid=%d nsegs=%d ridx=%d\n",
2012 qid, txwi->wcid, nsegs, ridx));
2013
2014 ring->cur = (ring->cur + 1) % RT2860_TX_RING_COUNT;
2015 ring->queued += ntxds;
2016 if (ring->queued >= RT2860_TX_RING_COUNT)
2017 sc->qfullmsk |= 1 << qid;
2018
2019 /* kick Tx */
2020 RAL_WRITE(sc, RT2860_TX_CTX_IDX(qid), ring->cur);
2021
2022 return 0;
2023 }
2024
2025 static int
2026 rt2860_transmit(struct ieee80211com *ic, struct mbuf *m)
2027 {
2028 struct rt2860_softc *sc = ic->ic_softc;
2029 int error;
2030
2031 RAL_LOCK(sc);
2032 if ((sc->sc_flags & RT2860_RUNNING) == 0) {
2033 RAL_UNLOCK(sc);
2034 return (ENXIO);
2035 }
2036 error = mbufq_enqueue(&sc->sc_snd, m);
2037 if (error) {
2038 RAL_UNLOCK(sc);
2039 return (error);
2040 }
2041 rt2860_start(sc);
2042 RAL_UNLOCK(sc);
2043
2044 return (0);
2045 }
2046
2047 static void
2048 rt2860_start(struct rt2860_softc *sc)
2049 {
2050 struct ieee80211_node *ni;
2051 struct mbuf *m;
2052
2053 RAL_LOCK_ASSERT(sc);
2054
2055 if ((sc->sc_flags & RT2860_RUNNING) == 0)
2056 return;
2057
2058 while (!SLIST_EMPTY(&sc->data_pool) && sc->qfullmsk == 0 &&
2059 (m = mbufq_dequeue(&sc->sc_snd)) != NULL) {
2060 ni = (struct ieee80211_node *)m->m_pkthdr.rcvif;
2061 if (rt2860_tx(sc, m, ni) != 0) {
2062 if_inc_counter(ni->ni_vap->iv_ifp,
2063 IFCOUNTER_OERRORS, 1);
2064 ieee80211_free_node(ni);
2065 continue;
2066 }
2067 sc->sc_tx_timer = 5;
2068 }
2069 }
2070
2071 static void
2072 rt2860_watchdog(void *arg)
2073 {
2074 struct rt2860_softc *sc = arg;
2075
2076 RAL_LOCK_ASSERT(sc);
2077
2078 KASSERT(sc->sc_flags & RT2860_RUNNING, ("not running"));
2079
2080 if (sc->sc_invalid) /* card ejected */
2081 return;
2082
2083 if (sc->sc_tx_timer > 0 && --sc->sc_tx_timer == 0) {
2084 device_printf(sc->sc_dev, "device timeout\n");
2085 rt2860_stop_locked(sc);
2086 rt2860_init_locked(sc);
2087 #if defined(__DragonFly__)
2088 /* not implemented */
2089 #else
2090 counter_u64_add(sc->sc_ic.ic_oerrors, 1);
2091 #endif
2092 return;
2093 }
2094 callout_reset(&sc->watchdog_ch, hz, rt2860_watchdog, sc);
2095 }
2096
2097 static void
2098 rt2860_parent(struct ieee80211com *ic)
2099 {
2100 struct rt2860_softc *sc = ic->ic_softc;
2101 int startall = 0;
2102
2103 RAL_LOCK(sc);
2104 if (ic->ic_nrunning> 0) {
2105 if (!(sc->sc_flags & RT2860_RUNNING)) {
2106 rt2860_init_locked(sc);
2107 startall = 1;
2108 } else
2109 rt2860_update_promisc(ic);
2110 } else if (sc->sc_flags & RT2860_RUNNING)
2111 rt2860_stop_locked(sc);
2112 RAL_UNLOCK(sc);
2113 if (startall)
2114 ieee80211_start_all(ic);
2115 }
2116
2117 /*
2118 * Reading and writing from/to the BBP is different from RT2560 and RT2661.
2119 * We access the BBP through the 8051 microcontroller unit which means that
2120 * the microcode must be loaded first.
2121 */
2122 void
2123 rt2860_mcu_bbp_write(struct rt2860_softc *sc, uint8_t reg, uint8_t val)
2124 {
2125 int ntries;
2126
2127 for (ntries = 0; ntries < 100; ntries++) {
2128 if (!(RAL_READ(sc, RT2860_H2M_BBPAGENT) & RT2860_BBP_CSR_KICK))
2129 break;
2130 DELAY(1);
2131 }
2132 if (ntries == 100) {
2133 device_printf(sc->sc_dev,
2134 "could not write to BBP through MCU\n");
2135 return;
2136 }
2137
2138 RAL_WRITE(sc, RT2860_H2M_BBPAGENT, RT2860_BBP_RW_PARALLEL |
2139 RT2860_BBP_CSR_KICK | reg << 8 | val);
2140 RAL_BARRIER_WRITE(sc);
2141
2142 rt2860_mcu_cmd(sc, RT2860_MCU_CMD_BBP, 0, 0);
2143 DELAY(1000);
2144 }
2145
2146 uint8_t
2147 rt2860_mcu_bbp_read(struct rt2860_softc *sc, uint8_t reg)
2148 {
2149 uint32_t val;
2150 int ntries;
2151
2152 for (ntries = 0; ntries < 100; ntries++) {
2153 if (!(RAL_READ(sc, RT2860_H2M_BBPAGENT) & RT2860_BBP_CSR_KICK))
2154 break;
2155 DELAY(1);
2156 }
2157 if (ntries == 100) {
2158 device_printf(sc->sc_dev,
2159 "could not read from BBP through MCU\n");
2160 return 0;
2161 }
2162
2163 RAL_WRITE(sc, RT2860_H2M_BBPAGENT, RT2860_BBP_RW_PARALLEL |
2164 RT2860_BBP_CSR_KICK | RT2860_BBP_CSR_READ | reg << 8);
2165 RAL_BARRIER_WRITE(sc);
2166
2167 rt2860_mcu_cmd(sc, RT2860_MCU_CMD_BBP, 0, 0);
2168 DELAY(1000);
2169
2170 for (ntries = 0; ntries < 100; ntries++) {
2171 val = RAL_READ(sc, RT2860_H2M_BBPAGENT);
2172 if (!(val & RT2860_BBP_CSR_KICK))
2173 return val & 0xff;
2174 DELAY(1);
2175 }
2176 device_printf(sc->sc_dev, "could not read from BBP through MCU\n");
2177
2178 return 0;
2179 }
2180
2181 /*
2182 * Write to one of the 4 programmable 24-bit RF registers.
2183 */
2184 static void
2185 rt2860_rf_write(struct rt2860_softc *sc, uint8_t reg, uint32_t val)
2186 {
2187 uint32_t tmp;
2188 int ntries;
2189
2190 for (ntries = 0; ntries < 100; ntries++) {
2191 if (!(RAL_READ(sc, RT2860_RF_CSR_CFG0) & RT2860_RF_REG_CTRL))
2192 break;
2193 DELAY(1);
2194 }
2195 if (ntries == 100) {
2196 device_printf(sc->sc_dev, "could not write to RF\n");
2197 return;
2198 }
2199
2200 /* RF registers are 24-bit on the RT2860 */
2201 tmp = RT2860_RF_REG_CTRL | 24 << RT2860_RF_REG_WIDTH_SHIFT |
2202 (val & 0x3fffff) << 2 | (reg & 3);
2203 RAL_WRITE(sc, RT2860_RF_CSR_CFG0, tmp);
2204 }
2205
2206 static uint8_t
2207 rt3090_rf_read(struct rt2860_softc *sc, uint8_t reg)
2208 {
2209 uint32_t tmp;
2210 int ntries;
2211
2212 for (ntries = 0; ntries < 100; ntries++) {
2213 if (!(RAL_READ(sc, RT3070_RF_CSR_CFG) & RT3070_RF_KICK))
2214 break;
2215 DELAY(1);
2216 }
2217 if (ntries == 100) {
2218 device_printf(sc->sc_dev, "could not read RF register\n");
2219 return 0xff;
2220 }
2221 tmp = RT3070_RF_KICK | reg << 8;
2222 RAL_WRITE(sc, RT3070_RF_CSR_CFG, tmp);
2223
2224 for (ntries = 0; ntries < 100; ntries++) {
2225 tmp = RAL_READ(sc, RT3070_RF_CSR_CFG);
2226 if (!(tmp & RT3070_RF_KICK))
2227 break;
2228 DELAY(1);
2229 }
2230 if (ntries == 100) {
2231 device_printf(sc->sc_dev, "could not read RF register\n");
2232 return 0xff;
2233 }
2234 return tmp & 0xff;
2235 }
2236
2237 void
2238 rt3090_rf_write(struct rt2860_softc *sc, uint8_t reg, uint8_t val)
2239 {
2240 uint32_t tmp;
2241 int ntries;
2242
2243 for (ntries = 0; ntries < 10; ntries++) {
2244 if (!(RAL_READ(sc, RT3070_RF_CSR_CFG) & RT3070_RF_KICK))
2245 break;
2246 DELAY(10);
2247 }
2248 if (ntries == 10) {
2249 device_printf(sc->sc_dev, "could not write to RF\n");
2250 return;
2251 }
2252
2253 tmp = RT3070_RF_WRITE | RT3070_RF_KICK | reg << 8 | val;
2254 RAL_WRITE(sc, RT3070_RF_CSR_CFG, tmp);
2255 }
2256
2257 /*
2258 * Send a command to the 8051 microcontroller unit.
2259 */
2260 int
2261 rt2860_mcu_cmd(struct rt2860_softc *sc, uint8_t cmd, uint16_t arg, int wait)
2262 {
2263 int slot, ntries;
2264 uint32_t tmp;
2265 uint8_t cid;
2266
2267 for (ntries = 0; ntries < 100; ntries++) {
2268 if (!(RAL_READ(sc, RT2860_H2M_MAILBOX) & RT2860_H2M_BUSY))
2269 break;
2270 DELAY(2);
2271 }
2272 if (ntries == 100)
2273 return EIO;
2274
2275 cid = wait ? cmd : RT2860_TOKEN_NO_INTR;
2276 RAL_WRITE(sc, RT2860_H2M_MAILBOX, RT2860_H2M_BUSY | cid << 16 | arg);
2277 RAL_BARRIER_WRITE(sc);
2278 RAL_WRITE(sc, RT2860_HOST_CMD, cmd);
2279
2280 if (!wait)
2281 return 0;
2282 /* wait for the command to complete */
2283 for (ntries = 0; ntries < 200; ntries++) {
2284 tmp = RAL_READ(sc, RT2860_H2M_MAILBOX_CID);
2285 /* find the command slot */
2286 for (slot = 0; slot < 4; slot++, tmp >>= 8)
2287 if ((tmp & 0xff) == cid)
2288 break;
2289 if (slot < 4)
2290 break;
2291 DELAY(100);
2292 }
2293 if (ntries == 200) {
2294 /* clear command and status */
2295 RAL_WRITE(sc, RT2860_H2M_MAILBOX_STATUS, 0xffffffff);
2296 RAL_WRITE(sc, RT2860_H2M_MAILBOX_CID, 0xffffffff);
2297 return ETIMEDOUT;
2298 }
2299 /* get command status (1 means success) */
2300 tmp = RAL_READ(sc, RT2860_H2M_MAILBOX_STATUS);
2301 tmp = (tmp >> (slot * 8)) & 0xff;
2302 DPRINTF(("MCU command=0x%02x slot=%d status=0x%02x\n",
2303 cmd, slot, tmp));
2304 /* clear command and status */
2305 RAL_WRITE(sc, RT2860_H2M_MAILBOX_STATUS, 0xffffffff);
2306 RAL_WRITE(sc, RT2860_H2M_MAILBOX_CID, 0xffffffff);
2307 return (tmp == 1) ? 0 : EIO;
2308 }
2309
2310 static void
2311 rt2860_enable_mrr(struct rt2860_softc *sc)
2312 {
2313 #define CCK(mcs) (mcs)
2314 #define OFDM(mcs) (1 << 3 | (mcs))
2315 RAL_WRITE(sc, RT2860_LG_FBK_CFG0,
2316 OFDM(6) << 28 | /* 54->48 */
2317 OFDM(5) << 24 | /* 48->36 */
2318 OFDM(4) << 20 | /* 36->24 */
2319 OFDM(3) << 16 | /* 24->18 */
2320 OFDM(2) << 12 | /* 18->12 */
2321 OFDM(1) << 8 | /* 12-> 9 */
2322 OFDM(0) << 4 | /* 9-> 6 */
2323 OFDM(0)); /* 6-> 6 */
2324
2325 RAL_WRITE(sc, RT2860_LG_FBK_CFG1,
2326 CCK(2) << 12 | /* 11->5.5 */
2327 CCK(1) << 8 | /* 5.5-> 2 */
2328 CCK(0) << 4 | /* 2-> 1 */
2329 CCK(0)); /* 1-> 1 */
2330 #undef OFDM
2331 #undef CCK
2332 }
2333
2334 static void
2335 rt2860_set_txpreamble(struct rt2860_softc *sc)
2336 {
2337 struct ieee80211com *ic = &sc->sc_ic;
2338 uint32_t tmp;
2339
2340 tmp = RAL_READ(sc, RT2860_AUTO_RSP_CFG);
2341 tmp &= ~RT2860_CCK_SHORT_EN;
2342 if (ic->ic_flags & IEEE80211_F_SHPREAMBLE)
2343 tmp |= RT2860_CCK_SHORT_EN;
2344 RAL_WRITE(sc, RT2860_AUTO_RSP_CFG, tmp);
2345 }
2346
2347 void
2348 rt2860_set_basicrates(struct rt2860_softc *sc,
2349 const struct ieee80211_rateset *rs)
2350 {
2351 struct ieee80211com *ic = &sc->sc_ic;
2352 uint32_t mask = 0;
2353 uint8_t rate;
2354 int i;
2355
2356 for (i = 0; i < rs->rs_nrates; i++) {
2357 rate = rs->rs_rates[i];
2358
2359 if (!(rate & IEEE80211_RATE_BASIC))
2360 continue;
2361
2362 mask |= 1 << ieee80211_legacy_rate_lookup(ic->ic_rt,
2363 IEEE80211_RV(rate));
2364 }
2365
2366 RAL_WRITE(sc, RT2860_LEGACY_BASIC_RATE, mask);
2367 }
2368
2369 static void
2370 rt2860_scan_start(struct ieee80211com *ic)
2371 {
2372 struct rt2860_softc *sc = ic->ic_softc;
2373 uint32_t tmp;
2374
2375 tmp = RAL_READ(sc, RT2860_BCN_TIME_CFG);
2376 RAL_WRITE(sc, RT2860_BCN_TIME_CFG,
2377 tmp & ~(RT2860_BCN_TX_EN | RT2860_TSF_TIMER_EN |
2378 RT2860_TBTT_TIMER_EN));
2379 rt2860_set_gp_timer(sc, 0);
2380 }
2381
2382 static void
2383 rt2860_scan_end(struct ieee80211com *ic)
2384 {
2385 struct rt2860_softc *sc = ic->ic_softc;
2386 struct ieee80211vap *vap = TAILQ_FIRST(&ic->ic_vaps);
2387
2388 if (vap->iv_state == IEEE80211_S_RUN) {
2389 rt2860_enable_tsf_sync(sc);
2390 rt2860_set_gp_timer(sc, 500);
2391 }
2392 }
2393
2394 static void
2395 rt2860_set_channel(struct ieee80211com *ic)
2396 {
2397 struct rt2860_softc *sc = ic->ic_softc;
2398
2399 RAL_LOCK(sc);
2400 rt2860_switch_chan(sc, ic->ic_curchan);
2401 RAL_UNLOCK(sc);
2402 }
2403
2404 static void
2405 rt2860_select_chan_group(struct rt2860_softc *sc, int group)
2406 {
2407 uint32_t tmp;
2408 uint8_t agc;
2409
2410 rt2860_mcu_bbp_write(sc, 62, 0x37 - sc->lna[group]);
2411 rt2860_mcu_bbp_write(sc, 63, 0x37 - sc->lna[group]);
2412 rt2860_mcu_bbp_write(sc, 64, 0x37 - sc->lna[group]);
2413 rt2860_mcu_bbp_write(sc, 86, 0x00);
2414
2415 if (group == 0) {
2416 if (sc->ext_2ghz_lna) {
2417 rt2860_mcu_bbp_write(sc, 82, 0x62);
2418 rt2860_mcu_bbp_write(sc, 75, 0x46);
2419 } else {
2420 rt2860_mcu_bbp_write(sc, 82, 0x84);
2421 rt2860_mcu_bbp_write(sc, 75, 0x50);
2422 }
2423 } else {
2424 if (sc->ext_5ghz_lna) {
2425 rt2860_mcu_bbp_write(sc, 82, 0xf2);
2426 rt2860_mcu_bbp_write(sc, 75, 0x46);
2427 } else {
2428 rt2860_mcu_bbp_write(sc, 82, 0xf2);
2429 rt2860_mcu_bbp_write(sc, 75, 0x50);
2430 }
2431 }
2432
2433 tmp = RAL_READ(sc, RT2860_TX_BAND_CFG);
2434 tmp &= ~(RT2860_5G_BAND_SEL_N | RT2860_5G_BAND_SEL_P);
2435 tmp |= (group == 0) ? RT2860_5G_BAND_SEL_N : RT2860_5G_BAND_SEL_P;
2436 RAL_WRITE(sc, RT2860_TX_BAND_CFG, tmp);
2437
2438 /* enable appropriate Power Amplifiers and Low Noise Amplifiers */
2439 tmp = RT2860_RFTR_EN | RT2860_TRSW_EN | RT2860_LNA_PE0_EN;
2440 if (sc->nrxchains > 1)
2441 tmp |= RT2860_LNA_PE1_EN;
2442 if (sc->mac_ver == 0x3593 && sc->nrxchains > 2)
2443 tmp |= RT3593_LNA_PE2_EN;
2444 if (group == 0) { /* 2GHz */
2445 tmp |= RT2860_PA_PE_G0_EN;
2446 if (sc->ntxchains > 1)
2447 tmp |= RT2860_PA_PE_G1_EN;
2448 if (sc->mac_ver == 0x3593 && sc->ntxchains > 2)
2449 tmp |= RT3593_PA_PE_G2_EN;
2450 } else { /* 5GHz */
2451 tmp |= RT2860_PA_PE_A0_EN;
2452 if (sc->ntxchains > 1)
2453 tmp |= RT2860_PA_PE_A1_EN;
2454 if (sc->mac_ver == 0x3593 && sc->ntxchains > 2)
2455 tmp |= RT3593_PA_PE_A2_EN;
2456 }
2457 RAL_WRITE(sc, RT2860_TX_PIN_CFG, tmp);
2458
2459 if (sc->mac_ver == 0x3593) {
2460 tmp = RAL_READ(sc, RT2860_GPIO_CTRL);
2461 if (sc->sc_flags & RT2860_PCIE) {
2462 tmp &= ~0x01010000;
2463 if (group == 0)
2464 tmp |= 0x00010000;
2465 } else {
2466 tmp &= ~0x00008080;
2467 if (group == 0)
2468 tmp |= 0x00000080;
2469 }
2470 tmp = (tmp & ~0x00001000) | 0x00000010;
2471 RAL_WRITE(sc, RT2860_GPIO_CTRL, tmp);
2472 }
2473
2474 /* set initial AGC value */
2475 if (group == 0) { /* 2GHz band */
2476 if (sc->mac_ver >= 0x3071)
2477 agc = 0x1c + sc->lna[0] * 2;
2478 else
2479 agc = 0x2e + sc->lna[0];
2480 } else { /* 5GHz band */
2481 agc = 0x32 + (sc->lna[group] * 5) / 3;
2482 }
2483 rt2860_mcu_bbp_write(sc, 66, agc);
2484
2485 DELAY(1000);
2486 }
2487
2488 static void
2489 rt2860_set_chan(struct rt2860_softc *sc, u_int chan)
2490 {
2491 const struct rfprog *rfprog = rt2860_rf2850;
2492 uint32_t r2, r3, r4;
2493 int8_t txpow1, txpow2;
2494 u_int i;
2495
2496 /* find the settings for this channel (we know it exists) */
2497 for (i = 0; rfprog[i].chan != chan; i++);
2498
2499 r2 = rfprog[i].r2;
2500 if (sc->ntxchains == 1)
2501 r2 |= 1 << 12; /* 1T: disable Tx chain 2 */
2502 if (sc->nrxchains == 1)
2503 r2 |= 1 << 15 | 1 << 4; /* 1R: disable Rx chains 2 & 3 */
2504 else if (sc->nrxchains == 2)
2505 r2 |= 1 << 4; /* 2R: disable Rx chain 3 */
2506
2507 /* use Tx power values from EEPROM */
2508 txpow1 = sc->txpow1[i];
2509 txpow2 = sc->txpow2[i];
2510 if (chan > 14) {
2511 if (txpow1 >= 0)
2512 txpow1 = txpow1 << 1 | 1;
2513 else
2514 txpow1 = (7 + txpow1) << 1;
2515 if (txpow2 >= 0)
2516 txpow2 = txpow2 << 1 | 1;
2517 else
2518 txpow2 = (7 + txpow2) << 1;
2519 }
2520 r3 = rfprog[i].r3 | txpow1 << 7;
2521 r4 = rfprog[i].r4 | sc->freq << 13 | txpow2 << 4;
2522
2523 rt2860_rf_write(sc, RT2860_RF1, rfprog[i].r1);
2524 rt2860_rf_write(sc, RT2860_RF2, r2);
2525 rt2860_rf_write(sc, RT2860_RF3, r3);
2526 rt2860_rf_write(sc, RT2860_RF4, r4);
2527
2528 DELAY(200);
2529
2530 rt2860_rf_write(sc, RT2860_RF1, rfprog[i].r1);
2531 rt2860_rf_write(sc, RT2860_RF2, r2);
2532 rt2860_rf_write(sc, RT2860_RF3, r3 | 1);
2533 rt2860_rf_write(sc, RT2860_RF4, r4);
2534
2535 DELAY(200);
2536
2537 rt2860_rf_write(sc, RT2860_RF1, rfprog[i].r1);
2538 rt2860_rf_write(sc, RT2860_RF2, r2);
2539 rt2860_rf_write(sc, RT2860_RF3, r3);
2540 rt2860_rf_write(sc, RT2860_RF4, r4);
2541 }
2542
2543 static void
2544 rt3090_set_chan(struct rt2860_softc *sc, u_int chan)
2545 {
2546 int8_t txpow1, txpow2;
2547 uint8_t rf;
2548 int i;
2549
2550 /* RT3090 is 2GHz only */
2551 KASSERT(chan >= 1 && chan <= 14, ("chan %d not support", chan));
2552
2553 /* find the settings for this channel (we know it exists) */
2554 for (i = 0; rt2860_rf2850[i].chan != chan; i++);
2555
2556 /* use Tx power values from EEPROM */
2557 txpow1 = sc->txpow1[i];
2558 txpow2 = sc->txpow2[i];
2559
2560 rt3090_rf_write(sc, 2, rt3090_freqs[i].n);
2561 rf = rt3090_rf_read(sc, 3);
2562 rf = (rf & ~0x0f) | rt3090_freqs[i].k;
2563 rt3090_rf_write(sc, 3, rf);
2564 rf = rt3090_rf_read(sc, 6);
2565 rf = (rf & ~0x03) | rt3090_freqs[i].r;
2566 rt3090_rf_write(sc, 6, rf);
2567
2568 /* set Tx0 power */
2569 rf = rt3090_rf_read(sc, 12);
2570 rf = (rf & ~0x1f) | txpow1;
2571 rt3090_rf_write(sc, 12, rf);
2572
2573 /* set Tx1 power */
2574 rf = rt3090_rf_read(sc, 13);
2575 rf = (rf & ~0x1f) | txpow2;
2576 rt3090_rf_write(sc, 13, rf);
2577
2578 rf = rt3090_rf_read(sc, 1);
2579 rf &= ~0xfc;
2580 if (sc->ntxchains == 1)
2581 rf |= RT3070_TX1_PD | RT3070_TX2_PD;
2582 else if (sc->ntxchains == 2)
2583 rf |= RT3070_TX2_PD;
2584 if (sc->nrxchains == 1)
2585 rf |= RT3070_RX1_PD | RT3070_RX2_PD;
2586 else if (sc->nrxchains == 2)
2587 rf |= RT3070_RX2_PD;
2588 rt3090_rf_write(sc, 1, rf);
2589
2590 /* set RF offset */
2591 rf = rt3090_rf_read(sc, 23);
2592 rf = (rf & ~0x7f) | sc->freq;
2593 rt3090_rf_write(sc, 23, rf);
2594
2595 /* program RF filter */
2596 rf = rt3090_rf_read(sc, 24); /* Tx */
2597 rf = (rf & ~0x3f) | sc->rf24_20mhz;
2598 rt3090_rf_write(sc, 24, rf);
2599 rf = rt3090_rf_read(sc, 31); /* Rx */
2600 rf = (rf & ~0x3f) | sc->rf24_20mhz;
2601 rt3090_rf_write(sc, 31, rf);
2602
2603 /* enable RF tuning */
2604 rf = rt3090_rf_read(sc, 7);
2605 rt3090_rf_write(sc, 7, rf | RT3070_TUNE);
2606 }
2607
2608 static void
2609 rt5390_set_chan(struct rt2860_softc *sc, u_int chan)
2610 {
2611 uint8_t h20mhz, rf, tmp;
2612 int8_t txpow1, txpow2;
2613 int i;
2614
2615 /* RT5390 is 2GHz only */
2616 KASSERT(chan >= 1 && chan <= 14, ("chan %d not support", chan));
2617
2618 /* find the settings for this channel (we know it exists) */
2619 for (i = 0; rt2860_rf2850[i].chan != chan; i++);
2620
2621 /* use Tx power values from EEPROM */
2622 txpow1 = sc->txpow1[i];
2623 txpow2 = sc->txpow2[i];
2624
2625 rt3090_rf_write(sc, 8, rt3090_freqs[i].n);
2626 rt3090_rf_write(sc, 9, rt3090_freqs[i].k & 0x0f);
2627 rf = rt3090_rf_read(sc, 11);
2628 rf = (rf & ~0x03) | (rt3090_freqs[i].r & 0x03);
2629 rt3090_rf_write(sc, 11, rf);
2630
2631 rf = rt3090_rf_read(sc, 49);
2632 rf = (rf & ~0x3f) | (txpow1 & 0x3f);
2633 /* the valid range of the RF R49 is 0x00~0x27 */
2634 if ((rf & 0x3f) > 0x27)
2635 rf = (rf & ~0x3f) | 0x27;
2636 rt3090_rf_write(sc, 49, rf);
2637 if (sc->mac_ver == 0x5392) {
2638 rf = rt3090_rf_read(sc, 50);
2639 rf = (rf & ~0x3f) | (txpow2 & 0x3f);
2640 /* the valid range of the RF R50 is 0x00~0x27 */
2641 if ((rf & 0x3f) > 0x27)
2642 rf = (rf & ~0x3f) | 0x27;
2643 rt3090_rf_write(sc, 50, rf);
2644 }
2645
2646 rf = rt3090_rf_read(sc, 1);
2647 rf |= RT3070_RF_BLOCK | RT3070_PLL_PD | RT3070_RX0_PD | RT3070_TX0_PD;
2648 if (sc->mac_ver == 0x5392)
2649 rf |= RT3070_RX1_PD | RT3070_TX1_PD;
2650 rt3090_rf_write(sc, 1, rf);
2651
2652 rf = rt3090_rf_read(sc, 2);
2653 rt3090_rf_write(sc, 2, rf | RT3593_RESCAL);
2654 DELAY(1000);
2655 rt3090_rf_write(sc, 2, rf & ~RT3593_RESCAL);
2656
2657 rf = rt3090_rf_read(sc, 17);
2658 tmp = rf;
2659 rf = (rf & ~0x7f) | (sc->freq & 0x7f);
2660 rf = MIN(rf, 0x5f);
2661 if (tmp != rf)
2662 rt2860_mcu_cmd(sc, 0x74, (tmp << 8 ) | rf, 0);
2663
2664 if (sc->mac_ver == 0x5390) {
2665 if (chan <= 4)
2666 rf = 0x73;
2667 else if (chan >= 5 && chan <= 6)
2668 rf = 0x63;
2669 else if (chan >= 7 && chan <= 10)
2670 rf = 0x53;
2671 else
2672 rf = 43;
2673 rt3090_rf_write(sc, 55, rf);
2674
2675 if (chan == 1)
2676 rf = 0x0c;
2677 else if (chan == 2)
2678 rf = 0x0b;
2679 else if (chan == 3)
2680 rf = 0x0a;
2681 else if (chan >= 4 && chan <= 6)
2682 rf = 0x09;
2683 else if (chan >= 7 && chan <= 12)
2684 rf = 0x08;
2685 else if (chan == 13)
2686 rf = 0x07;
2687 else
2688 rf = 0x06;
2689 rt3090_rf_write(sc, 59, rf);
2690 }
2691
2692 /* Tx/Rx h20M */
2693 h20mhz = (sc->rf24_20mhz & 0x20) >> 5;
2694 rf = rt3090_rf_read(sc, 30);
2695 rf = (rf & ~0x06) | (h20mhz << 1) | (h20mhz << 2);
2696 rt3090_rf_write(sc, 30, rf);
2697
2698 /* Rx BB filter VCM */
2699 rf = rt3090_rf_read(sc, 30);
2700 rf = (rf & ~0x18) | 0x10;
2701 rt3090_rf_write(sc, 30, rf);
2702
2703 /* Initiate VCO calibration. */
2704 rf = rt3090_rf_read(sc, 3);
2705 rf |= RT3593_VCOCAL;
2706 rt3090_rf_write(sc, 3, rf);
2707 }
2708
2709 static int
2710 rt3090_rf_init(struct rt2860_softc *sc)
2711 {
2712 uint32_t tmp;
2713 uint8_t rf, bbp;
2714 int i;
2715
2716 rf = rt3090_rf_read(sc, 30);
2717 /* toggle RF R30 bit 7 */
2718 rt3090_rf_write(sc, 30, rf | 0x80);
2719 DELAY(1000);
2720 rt3090_rf_write(sc, 30, rf & ~0x80);
2721
2722 tmp = RAL_READ(sc, RT3070_LDO_CFG0);
2723 tmp &= ~0x1f000000;
2724 if (sc->patch_dac && sc->mac_rev < 0x0211)
2725 tmp |= 0x0d000000; /* 1.35V */
2726 else
2727 tmp |= 0x01000000; /* 1.2V */
2728 RAL_WRITE(sc, RT3070_LDO_CFG0, tmp);
2729
2730 /* patch LNA_PE_G1 */
2731 tmp = RAL_READ(sc, RT3070_GPIO_SWITCH);
2732 RAL_WRITE(sc, RT3070_GPIO_SWITCH, tmp & ~0x20);
2733
2734 /* initialize RF registers to default value */
2735 for (i = 0; i < nitems(rt3090_def_rf); i++) {
2736 rt3090_rf_write(sc, rt3090_def_rf[i].reg,
2737 rt3090_def_rf[i].val);
2738 }
2739
2740 /* select 20MHz bandwidth */
2741 rt3090_rf_write(sc, 31, 0x14);
2742
2743 rf = rt3090_rf_read(sc, 6);
2744 rt3090_rf_write(sc, 6, rf | 0x40);
2745
2746 if (sc->mac_ver != 0x3593) {
2747 /* calibrate filter for 20MHz bandwidth */
2748 sc->rf24_20mhz = 0x1f; /* default value */
2749 rt3090_filter_calib(sc, 0x07, 0x16, &sc->rf24_20mhz);
2750
2751 /* select 40MHz bandwidth */
2752 bbp = rt2860_mcu_bbp_read(sc, 4);
2753 rt2860_mcu_bbp_write(sc, 4, (bbp & ~0x08) | 0x10);
2754 rf = rt3090_rf_read(sc, 31);
2755 rt3090_rf_write(sc, 31, rf | 0x20);
2756
2757 /* calibrate filter for 40MHz bandwidth */
2758 sc->rf24_40mhz = 0x2f; /* default value */
2759 rt3090_filter_calib(sc, 0x27, 0x19, &sc->rf24_40mhz);
2760
2761 /* go back to 20MHz bandwidth */
2762 bbp = rt2860_mcu_bbp_read(sc, 4);
2763 rt2860_mcu_bbp_write(sc, 4, bbp & ~0x18);
2764 }
2765 if (sc->mac_rev < 0x0211)
2766 rt3090_rf_write(sc, 27, 0x03);
2767
2768 tmp = RAL_READ(sc, RT3070_OPT_14);
2769 RAL_WRITE(sc, RT3070_OPT_14, tmp | 1);
2770
2771 if (sc->rf_rev == RT3070_RF_3020)
2772 rt3090_set_rx_antenna(sc, 0);
2773
2774 bbp = rt2860_mcu_bbp_read(sc, 138);
2775 if (sc->mac_ver == 0x3593) {
2776 if (sc->ntxchains == 1)
2777 bbp |= 0x60; /* turn off DAC1 and DAC2 */
2778 else if (sc->ntxchains == 2)
2779 bbp |= 0x40; /* turn off DAC2 */
2780 if (sc->nrxchains == 1)
2781 bbp &= ~0x06; /* turn off ADC1 and ADC2 */
2782 else if (sc->nrxchains == 2)
2783 bbp &= ~0x04; /* turn off ADC2 */
2784 } else {
2785 if (sc->ntxchains == 1)
2786 bbp |= 0x20; /* turn off DAC1 */
2787 if (sc->nrxchains == 1)
2788 bbp &= ~0x02; /* turn off ADC1 */
2789 }
2790 rt2860_mcu_bbp_write(sc, 138, bbp);
2791
2792 rf = rt3090_rf_read(sc, 1);
2793 rf &= ~(RT3070_RX0_PD | RT3070_TX0_PD);
2794 rf |= RT3070_RF_BLOCK | RT3070_RX1_PD | RT3070_TX1_PD;
2795 rt3090_rf_write(sc, 1, rf);
2796
2797 rf = rt3090_rf_read(sc, 15);
2798 rt3090_rf_write(sc, 15, rf & ~RT3070_TX_LO2);
2799
2800 rf = rt3090_rf_read(sc, 17);
2801 rf &= ~RT3070_TX_LO1;
2802 if (sc->mac_rev >= 0x0211 && !sc->ext_2ghz_lna)
2803 rf |= 0x20; /* fix for long range Rx issue */
2804 if (sc->txmixgain_2ghz >= 2)
2805 rf = (rf & ~0x7) | sc->txmixgain_2ghz;
2806 rt3090_rf_write(sc, 17, rf);
2807
2808 rf = rt3090_rf_read(sc, 20);
2809 rt3090_rf_write(sc, 20, rf & ~RT3070_RX_LO1);
2810
2811 rf = rt3090_rf_read(sc, 21);
2812 rt3090_rf_write(sc, 21, rf & ~RT3070_RX_LO2);
2813
2814 return (0);
2815 }
2816
2817 static void
2818 rt5390_rf_init(struct rt2860_softc *sc)
2819 {
2820 uint8_t rf, bbp;
2821 int i;
2822
2823 rf = rt3090_rf_read(sc, 2);
2824 /* Toggle RF R2 bit 7. */
2825 rt3090_rf_write(sc, 2, rf | RT3593_RESCAL);
2826 DELAY(1000);
2827 rt3090_rf_write(sc, 2, rf & ~RT3593_RESCAL);
2828
2829 /* Initialize RF registers to default value. */
2830 if (sc->mac_ver == 0x5392) {
2831 for (i = 0; i < nitems(rt5392_def_rf); i++) {
2832 rt3090_rf_write(sc, rt5392_def_rf[i].reg,
2833 rt5392_def_rf[i].val);
2834 }
2835 } else {
2836 for (i = 0; i < nitems(rt5390_def_rf); i++) {
2837 rt3090_rf_write(sc, rt5390_def_rf[i].reg,
2838 rt5390_def_rf[i].val);
2839 }
2840 }
2841
2842 sc->rf24_20mhz = 0x1f;
2843 sc->rf24_40mhz = 0x2f;
2844
2845 if (sc->mac_rev < 0x0211)
2846 rt3090_rf_write(sc, 27, 0x03);
2847
2848 /* Set led open drain enable. */
2849 RAL_WRITE(sc, RT3070_OPT_14, RAL_READ(sc, RT3070_OPT_14) | 1);
2850
2851 RAL_WRITE(sc, RT2860_TX_SW_CFG1, 0);
2852 RAL_WRITE(sc, RT2860_TX_SW_CFG2, 0);
2853
2854 if (sc->mac_ver == 0x5390)
2855 rt3090_set_rx_antenna(sc, 0);
2856
2857 /* Patch RSSI inaccurate issue. */
2858 rt2860_mcu_bbp_write(sc, 79, 0x13);
2859 rt2860_mcu_bbp_write(sc, 80, 0x05);
2860 rt2860_mcu_bbp_write(sc, 81, 0x33);
2861
2862 /* Enable DC filter. */
2863 if (sc->mac_rev >= 0x0211)
2864 rt2860_mcu_bbp_write(sc, 103, 0xc0);
2865
2866 bbp = rt2860_mcu_bbp_read(sc, 138);
2867 if (sc->ntxchains == 1)
2868 bbp |= 0x20; /* Turn off DAC1. */
2869 if (sc->nrxchains == 1)
2870 bbp &= ~0x02; /* Turn off ADC1. */
2871 rt2860_mcu_bbp_write(sc, 138, bbp);
2872
2873 /* Enable RX LO1 and LO2. */
2874 rt3090_rf_write(sc, 38, rt3090_rf_read(sc, 38) & ~RT5390_RX_LO1);
2875 rt3090_rf_write(sc, 39, rt3090_rf_read(sc, 39) & ~RT5390_RX_LO2);
2876
2877 /* Avoid data lost and CRC error. */
2878 rt2860_mcu_bbp_write(sc, 4,
2879 rt2860_mcu_bbp_read(sc, 4) | RT5390_MAC_IF_CTRL);
2880
2881 rf = rt3090_rf_read(sc, 30);
2882 rf = (rf & ~0x18) | 0x10;
2883 rt3090_rf_write(sc, 30, rf);
2884 }
2885
2886 static void
2887 rt3090_rf_wakeup(struct rt2860_softc *sc)
2888 {
2889 uint32_t tmp;
2890 uint8_t rf;
2891
2892 if (sc->mac_ver == 0x3593) {
2893 /* enable VCO */
2894 rf = rt3090_rf_read(sc, 1);
2895 rt3090_rf_write(sc, 1, rf | RT3593_VCO);
2896
2897 /* initiate VCO calibration */
2898 rf = rt3090_rf_read(sc, 3);
2899 rt3090_rf_write(sc, 3, rf | RT3593_VCOCAL);
2900
2901 /* enable VCO bias current control */
2902 rf = rt3090_rf_read(sc, 6);
2903 rt3090_rf_write(sc, 6, rf | RT3593_VCO_IC);
2904
2905 /* initiate res calibration */
2906 rf = rt3090_rf_read(sc, 2);
2907 rt3090_rf_write(sc, 2, rf | RT3593_RESCAL);
2908
2909 /* set reference current control to 0.33 mA */
2910 rf = rt3090_rf_read(sc, 22);
2911 rf &= ~RT3593_CP_IC_MASK;
2912 rf |= 1 << RT3593_CP_IC_SHIFT;
2913 rt3090_rf_write(sc, 22, rf);
2914
2915 /* enable RX CTB */
2916 rf = rt3090_rf_read(sc, 46);
2917 rt3090_rf_write(sc, 46, rf | RT3593_RX_CTB);
2918
2919 rf = rt3090_rf_read(sc, 20);
2920 rf &= ~(RT3593_LDO_RF_VC_MASK | RT3593_LDO_PLL_VC_MASK);
2921 rt3090_rf_write(sc, 20, rf);
2922 } else {
2923 /* enable RF block */
2924 rf = rt3090_rf_read(sc, 1);
2925 rt3090_rf_write(sc, 1, rf | RT3070_RF_BLOCK);
2926
2927 /* enable VCO bias current control */
2928 rf = rt3090_rf_read(sc, 7);
2929 rt3090_rf_write(sc, 7, rf | 0x30);
2930
2931 rf = rt3090_rf_read(sc, 9);
2932 rt3090_rf_write(sc, 9, rf | 0x0e);
2933
2934 /* enable RX CTB */
2935 rf = rt3090_rf_read(sc, 21);
2936 rt3090_rf_write(sc, 21, rf | RT3070_RX_CTB);
2937
2938 /* fix Tx to Rx IQ glitch by raising RF voltage */
2939 rf = rt3090_rf_read(sc, 27);
2940 rf &= ~0x77;
2941 if (sc->mac_rev < 0x0211)
2942 rf |= 0x03;
2943 rt3090_rf_write(sc, 27, rf);
2944 }
2945 if (sc->patch_dac && sc->mac_rev < 0x0211) {
2946 tmp = RAL_READ(sc, RT3070_LDO_CFG0);
2947 tmp = (tmp & ~0x1f000000) | 0x0d000000;
2948 RAL_WRITE(sc, RT3070_LDO_CFG0, tmp);
2949 }
2950 }
2951
2952 static void
2953 rt5390_rf_wakeup(struct rt2860_softc *sc)
2954 {
2955 uint32_t tmp;
2956 uint8_t rf;
2957
2958 rf = rt3090_rf_read(sc, 1);
2959 rf |= RT3070_RF_BLOCK | RT3070_PLL_PD | RT3070_RX0_PD |
2960 RT3070_TX0_PD;
2961 if (sc->mac_ver == 0x5392)
2962 rf |= RT3070_RX1_PD | RT3070_TX1_PD;
2963 rt3090_rf_write(sc, 1, rf);
2964
2965 rf = rt3090_rf_read(sc, 6);
2966 rf |= RT3593_VCO_IC | RT3593_VCOCAL;
2967 if (sc->mac_ver == 0x5390)
2968 rf &= ~RT3593_VCO_IC;
2969 rt3090_rf_write(sc, 6, rf);
2970
2971 rt3090_rf_write(sc, 2, rt3090_rf_read(sc, 2) | RT3593_RESCAL);
2972
2973 rf = rt3090_rf_read(sc, 22);
2974 rf = (rf & ~0xe0) | 0x20;
2975 rt3090_rf_write(sc, 22, rf);
2976
2977 rt3090_rf_write(sc, 42, rt3090_rf_read(sc, 42) | RT5390_RX_CTB);
2978 rt3090_rf_write(sc, 20, rt3090_rf_read(sc, 20) & ~0x77);
2979 rt3090_rf_write(sc, 3, rt3090_rf_read(sc, 3) | RT3593_VCOCAL);
2980
2981 if (sc->patch_dac && sc->mac_rev < 0x0211) {
2982 tmp = RAL_READ(sc, RT3070_LDO_CFG0);
2983 tmp = (tmp & ~0x1f000000) | 0x0d000000;
2984 RAL_WRITE(sc, RT3070_LDO_CFG0, tmp);
2985 }
2986 }
2987
2988 static int
2989 rt3090_filter_calib(struct rt2860_softc *sc, uint8_t init, uint8_t target,
2990 uint8_t *val)
2991 {
2992 uint8_t rf22, rf24;
2993 uint8_t bbp55_pb, bbp55_sb, delta;
2994 int ntries;
2995
2996 /* program filter */
2997 rf24 = rt3090_rf_read(sc, 24);
2998 rf24 = (rf24 & 0xc0) | init; /* initial filter value */
2999 rt3090_rf_write(sc, 24, rf24);
3000
3001 /* enable baseband loopback mode */
3002 rf22 = rt3090_rf_read(sc, 22);
3003 rt3090_rf_write(sc, 22, rf22 | RT3070_BB_LOOPBACK);
3004
3005 /* set power and frequency of passband test tone */
3006 rt2860_mcu_bbp_write(sc, 24, 0x00);
3007 for (ntries = 0; ntries < 100; ntries++) {
3008 /* transmit test tone */
3009 rt2860_mcu_bbp_write(sc, 25, 0x90);
3010 DELAY(1000);
3011 /* read received power */
3012 bbp55_pb = rt2860_mcu_bbp_read(sc, 55);
3013 if (bbp55_pb != 0)
3014 break;
3015 }
3016 if (ntries == 100)
3017 return (ETIMEDOUT);
3018
3019 /* set power and frequency of stopband test tone */
3020 rt2860_mcu_bbp_write(sc, 24, 0x06);
3021 for (ntries = 0; ntries < 100; ntries++) {
3022 /* transmit test tone */
3023 rt2860_mcu_bbp_write(sc, 25, 0x90);
3024 DELAY(1000);
3025 /* read received power */
3026 bbp55_sb = rt2860_mcu_bbp_read(sc, 55);
3027
3028 delta = bbp55_pb - bbp55_sb;
3029 if (delta > target)
3030 break;
3031
3032 /* reprogram filter */
3033 rf24++;
3034 rt3090_rf_write(sc, 24, rf24);
3035 }
3036 if (ntries < 100) {
3037 if (rf24 != init)
3038 rf24--; /* backtrack */
3039 *val = rf24;
3040 rt3090_rf_write(sc, 24, rf24);
3041 }
3042
3043 /* restore initial state */
3044 rt2860_mcu_bbp_write(sc, 24, 0x00);
3045
3046 /* disable baseband loopback mode */
3047 rf22 = rt3090_rf_read(sc, 22);
3048 rt3090_rf_write(sc, 22, rf22 & ~RT3070_BB_LOOPBACK);
3049
3050 return (0);
3051 }
3052
3053 static void
3054 rt3090_rf_setup(struct rt2860_softc *sc)
3055 {
3056 uint8_t bbp;
3057 int i;
3058
3059 if (sc->mac_rev >= 0x0211) {
3060 /* enable DC filter */
3061 rt2860_mcu_bbp_write(sc, 103, 0xc0);
3062
3063 /* improve power consumption */
3064 bbp = rt2860_mcu_bbp_read(sc, 31);
3065 rt2860_mcu_bbp_write(sc, 31, bbp & ~0x03);
3066 }
3067
3068 RAL_WRITE(sc, RT2860_TX_SW_CFG1, 0);
3069 if (sc->mac_rev < 0x0211) {
3070 RAL_WRITE(sc, RT2860_TX_SW_CFG2,
3071 sc->patch_dac ? 0x2c : 0x0f);
3072 } else
3073 RAL_WRITE(sc, RT2860_TX_SW_CFG2, 0);
3074
3075 /* initialize RF registers from ROM */
3076 if (sc->mac_ver < 0x5390) {
3077 for (i = 0; i < 10; i++) {
3078 if (sc->rf[i].reg == 0 || sc->rf[i].reg == 0xff)
3079 continue;
3080 rt3090_rf_write(sc, sc->rf[i].reg, sc->rf[i].val);
3081 }
3082 }
3083 }
3084
3085 static void
3086 rt2860_set_leds(struct rt2860_softc *sc, uint16_t which)
3087 {
3088 rt2860_mcu_cmd(sc, RT2860_MCU_CMD_LEDS,
3089 which | (sc->leds & 0x7f), 0);
3090 }
3091
3092 /*
3093 * Hardware has a general-purpose programmable timer interrupt that can
3094 * periodically raise MAC_INT_4.
3095 */
3096 static void
3097 rt2860_set_gp_timer(struct rt2860_softc *sc, int ms)
3098 {
3099 uint32_t tmp;
3100
3101 /* disable GP timer before reprogramming it */
3102 tmp = RAL_READ(sc, RT2860_INT_TIMER_EN);
3103 RAL_WRITE(sc, RT2860_INT_TIMER_EN, tmp & ~RT2860_GP_TIMER_EN);
3104
3105 if (ms == 0)
3106 return;
3107
3108 tmp = RAL_READ(sc, RT2860_INT_TIMER_CFG);
3109 ms *= 16; /* Unit: 64us */
3110 tmp = (tmp & 0xffff) | ms << RT2860_GP_TIMER_SHIFT;
3111 RAL_WRITE(sc, RT2860_INT_TIMER_CFG, tmp);
3112
3113 /* enable GP timer */
3114 tmp = RAL_READ(sc, RT2860_INT_TIMER_EN);
3115 RAL_WRITE(sc, RT2860_INT_TIMER_EN, tmp | RT2860_GP_TIMER_EN);
3116 }
3117
3118 static void
3119 rt2860_set_bssid(struct rt2860_softc *sc, const uint8_t *bssid)
3120 {
3121 RAL_WRITE(sc, RT2860_MAC_BSSID_DW0,
3122 bssid[0] | bssid[1] << 8 | bssid[2] << 16 | bssid[3] << 24);
3123 RAL_WRITE(sc, RT2860_MAC_BSSID_DW1,
3124 bssid[4] | bssid[5] << 8);
3125 }
3126
3127 static void
3128 rt2860_set_macaddr(struct rt2860_softc *sc, const uint8_t *addr)
3129 {
3130 RAL_WRITE(sc, RT2860_MAC_ADDR_DW0,
3131 addr[0] | addr[1] << 8 | addr[2] << 16 | addr[3] << 24);
3132 RAL_WRITE(sc, RT2860_MAC_ADDR_DW1,
3133 addr[4] | addr[5] << 8 | 0xff << 16);
3134 }
3135
3136 static void
3137 rt2860_updateslot(struct ieee80211com *ic)
3138 {
3139 struct rt2860_softc *sc = ic->ic_softc;
3140 uint32_t tmp;
3141
3142 tmp = RAL_READ(sc, RT2860_BKOFF_SLOT_CFG);
3143 tmp &= ~0xff;
3144 tmp |= IEEE80211_GET_SLOTTIME(ic);
3145 RAL_WRITE(sc, RT2860_BKOFF_SLOT_CFG, tmp);
3146 }
3147
3148 static void
3149 rt2860_updateprot(struct rt2860_softc *sc)
3150 {
3151 struct ieee80211com *ic = &sc->sc_ic;
3152 uint32_t tmp;
3153
3154 tmp = RT2860_RTSTH_EN | RT2860_PROT_NAV_SHORT | RT2860_TXOP_ALLOW_ALL;
3155 /* setup protection frame rate (MCS code) */
3156 tmp |= IEEE80211_IS_CHAN_5GHZ(ic->ic_curchan) ?
3157 rt2860_rates[RT2860_RIDX_OFDM6].mcs :
3158 rt2860_rates[RT2860_RIDX_CCK11].mcs;
3159
3160 /* CCK frames don't require protection */
3161 RAL_WRITE(sc, RT2860_CCK_PROT_CFG, tmp);
3162
3163 if (ic->ic_flags & IEEE80211_F_USEPROT) {
3164 if (ic->ic_protmode == IEEE80211_PROT_RTSCTS)
3165 tmp |= RT2860_PROT_CTRL_RTS_CTS;
3166 else if (ic->ic_protmode == IEEE80211_PROT_CTSONLY)
3167 tmp |= RT2860_PROT_CTRL_CTS;
3168 }
3169 RAL_WRITE(sc, RT2860_OFDM_PROT_CFG, tmp);
3170 }
3171
3172 static void
3173 rt2860_update_promisc(struct ieee80211com *ic)
3174 {
3175 struct rt2860_softc *sc = ic->ic_softc;
3176 uint32_t tmp;
3177
3178 tmp = RAL_READ(sc, RT2860_RX_FILTR_CFG);
3179 tmp &= ~RT2860_DROP_NOT_MYBSS;
3180 if (ic->ic_promisc == 0)
3181 tmp |= RT2860_DROP_NOT_MYBSS;
3182 RAL_WRITE(sc, RT2860_RX_FILTR_CFG, tmp);
3183 }
3184
3185 static int
3186 rt2860_updateedca(struct ieee80211com *ic)
3187 {
3188 struct rt2860_softc *sc = ic->ic_softc;
3189 const struct wmeParams *wmep;
3190 int aci;
3191
3192 wmep = ic->ic_wme.wme_chanParams.cap_wmeParams;
3193
3194 /* update MAC TX configuration registers */
3195 for (aci = 0; aci < WME_NUM_AC; aci++) {
3196 RAL_WRITE(sc, RT2860_EDCA_AC_CFG(aci),
3197 wmep[aci].wmep_logcwmax << 16 |
3198 wmep[aci].wmep_logcwmin << 12 |
3199 wmep[aci].wmep_aifsn << 8 |
3200 wmep[aci].wmep_txopLimit);
3201 }
3202
3203 /* update SCH/DMA registers too */
3204 RAL_WRITE(sc, RT2860_WMM_AIFSN_CFG,
3205 wmep[WME_AC_VO].wmep_aifsn << 12 |
3206 wmep[WME_AC_VI].wmep_aifsn << 8 |
3207 wmep[WME_AC_BK].wmep_aifsn << 4 |
3208 wmep[WME_AC_BE].wmep_aifsn);
3209 RAL_WRITE(sc, RT2860_WMM_CWMIN_CFG,
3210 wmep[WME_AC_VO].wmep_logcwmin << 12 |
3211 wmep[WME_AC_VI].wmep_logcwmin << 8 |
3212 wmep[WME_AC_BK].wmep_logcwmin << 4 |
3213 wmep[WME_AC_BE].wmep_logcwmin);
3214 RAL_WRITE(sc, RT2860_WMM_CWMAX_CFG,
3215 wmep[WME_AC_VO].wmep_logcwmax << 12 |
3216 wmep[WME_AC_VI].wmep_logcwmax << 8 |
3217 wmep[WME_AC_BK].wmep_logcwmax << 4 |
3218 wmep[WME_AC_BE].wmep_logcwmax);
3219 RAL_WRITE(sc, RT2860_WMM_TXOP0_CFG,
3220 wmep[WME_AC_BK].wmep_txopLimit << 16 |
3221 wmep[WME_AC_BE].wmep_txopLimit);
3222 RAL_WRITE(sc, RT2860_WMM_TXOP1_CFG,
3223 wmep[WME_AC_VO].wmep_txopLimit << 16 |
3224 wmep[WME_AC_VI].wmep_txopLimit);
3225
3226 return 0;
3227 }
3228
3229 #ifdef HW_CRYPTO
3230 static int
3231 rt2860_set_key(struct ieee80211com *ic, struct ieee80211_node *ni,
3232 struct ieee80211_key *k)
3233 {
3234 struct rt2860_softc *sc = ic->ic_softc;
3235 bus_size_t base;
3236 uint32_t attr;
3237 uint8_t mode, wcid, iv[8];
3238
3239 /* defer setting of WEP keys until interface is brought up */
3240 if ((ic->ic_if.if_flags & (IFF_UP | IFF_RUNNING)) !=
3241 (IFF_UP | IFF_RUNNING))
3242 return 0;
3243
3244 /* map net80211 cipher to RT2860 security mode */
3245 switch (k->k_cipher) {
3246 case IEEE80211_CIPHER_WEP40:
3247 mode = RT2860_MODE_WEP40;
3248 break;
3249 case IEEE80211_CIPHER_WEP104:
3250 mode = RT2860_MODE_WEP104;
3251 break;
3252 case IEEE80211_CIPHER_TKIP:
3253 mode = RT2860_MODE_TKIP;
3254 break;
3255 case IEEE80211_CIPHER_CCMP:
3256 mode = RT2860_MODE_AES_CCMP;
3257 break;
3258 default:
3259 return EINVAL;
3260 }
3261
3262 if (k->k_flags & IEEE80211_KEY_GROUP) {
3263 wcid = 0; /* NB: update WCID0 for group keys */
3264 base = RT2860_SKEY(0, k->k_id);
3265 } else {
3266 wcid = ((struct rt2860_node *)ni)->wcid;
3267 base = RT2860_PKEY(wcid);
3268 }
3269
3270 if (k->k_cipher == IEEE80211_CIPHER_TKIP) {
3271 RAL_WRITE_REGION_1(sc, base, k->k_key, 16);
3272 #ifndef IEEE80211_STA_ONLY
3273 if (ic->ic_opmode == IEEE80211_M_HOSTAP) {
3274 RAL_WRITE_REGION_1(sc, base + 16, &k->k_key[16], 8);
3275 RAL_WRITE_REGION_1(sc, base + 24, &k->k_key[24], 8);
3276 } else
3277 #endif
3278 {
3279 RAL_WRITE_REGION_1(sc, base + 16, &k->k_key[24], 8);
3280 RAL_WRITE_REGION_1(sc, base + 24, &k->k_key[16], 8);
3281 }
3282 } else
3283 RAL_WRITE_REGION_1(sc, base, k->k_key, k->k_len);
3284
3285 if (!(k->k_flags & IEEE80211_KEY_GROUP) ||
3286 (k->k_flags & IEEE80211_KEY_TX)) {
3287 /* set initial packet number in IV+EIV */
3288 if (k->k_cipher == IEEE80211_CIPHER_WEP40 ||
3289 k->k_cipher == IEEE80211_CIPHER_WEP104) {
3290 uint32_t val = arc4random();
3291 /* skip weak IVs from Fluhrer/Mantin/Shamir */
3292 if (val >= 0x03ff00 && (val & 0xf8ff00) == 0x00ff00)
3293 val += 0x000100;
3294 iv[0] = val;
3295 iv[1] = val >> 8;
3296 iv[2] = val >> 16;
3297 iv[3] = k->k_id << 6;
3298 iv[4] = iv[5] = iv[6] = iv[7] = 0;
3299 } else {
3300 if (k->k_cipher == IEEE80211_CIPHER_TKIP) {
3301 iv[0] = k->k_tsc >> 8;
3302 iv[1] = (iv[0] | 0x20) & 0x7f;
3303 iv[2] = k->k_tsc;
3304 } else /* CCMP */ {
3305 iv[0] = k->k_tsc;
3306 iv[1] = k->k_tsc >> 8;
3307 iv[2] = 0;
3308 }
3309 iv[3] = k->k_id << 6 | IEEE80211_WEP_EXTIV;
3310 iv[4] = k->k_tsc >> 16;
3311 iv[5] = k->k_tsc >> 24;
3312 iv[6] = k->k_tsc >> 32;
3313 iv[7] = k->k_tsc >> 40;
3314 }
3315 RAL_WRITE_REGION_1(sc, RT2860_IVEIV(wcid), iv, 8);
3316 }
3317
3318 if (k->k_flags & IEEE80211_KEY_GROUP) {
3319 /* install group key */
3320 attr = RAL_READ(sc, RT2860_SKEY_MODE_0_7);
3321 attr &= ~(0xf << (k->k_id * 4));
3322 attr |= mode << (k->k_id * 4);
3323 RAL_WRITE(sc, RT2860_SKEY_MODE_0_7, attr);
3324 } else {
3325 /* install pairwise key */
3326 attr = RAL_READ(sc, RT2860_WCID_ATTR(wcid));
3327 attr = (attr & ~0xf) | (mode << 1) | RT2860_RX_PKEY_EN;
3328 RAL_WRITE(sc, RT2860_WCID_ATTR(wcid), attr);
3329 }
3330 return 0;
3331 }
3332
3333 static void
3334 rt2860_delete_key(struct ieee80211com *ic, struct ieee80211_node *ni,
3335 struct ieee80211_key *k)
3336 {
3337 struct rt2860_softc *sc = ic->ic_softc;
3338 uint32_t attr;
3339 uint8_t wcid;
3340
3341 if (k->k_flags & IEEE80211_KEY_GROUP) {
3342 /* remove group key */
3343 attr = RAL_READ(sc, RT2860_SKEY_MODE_0_7);
3344 attr &= ~(0xf << (k->k_id * 4));
3345 RAL_WRITE(sc, RT2860_SKEY_MODE_0_7, attr);
3346
3347 } else {
3348 /* remove pairwise key */
3349 wcid = ((struct rt2860_node *)ni)->wcid;
3350 attr = RAL_READ(sc, RT2860_WCID_ATTR(wcid));
3351 attr &= ~0xf;
3352 RAL_WRITE(sc, RT2860_WCID_ATTR(wcid), attr);
3353 }
3354 }
3355 #endif
3356
3357 static int8_t
3358 rt2860_rssi2dbm(struct rt2860_softc *sc, uint8_t rssi, uint8_t rxchain)
3359 {
3360 struct ieee80211com *ic = &sc->sc_ic;
3361 struct ieee80211_channel *c = ic->ic_curchan;
3362 int delta;
3363
3364 if (IEEE80211_IS_CHAN_5GHZ(c)) {
3365 u_int chan = ieee80211_chan2ieee(ic, c);
3366 delta = sc->rssi_5ghz[rxchain];
3367
3368 /* determine channel group */
3369 if (chan <= 64)
3370 delta -= sc->lna[1];
3371 else if (chan <= 128)
3372 delta -= sc->lna[2];
3373 else
3374 delta -= sc->lna[3];
3375 } else
3376 delta = sc->rssi_2ghz[rxchain] - sc->lna[0];
3377
3378 return -12 - delta - rssi;
3379 }
3380
3381 /*
3382 * Add `delta' (signed) to each 4-bit sub-word of a 32-bit word.
3383 * Used to adjust per-rate Tx power registers.
3384 */
3385 static __inline uint32_t
3386 b4inc(uint32_t b32, int8_t delta)
3387 {
3388 int8_t i, b4;
3389
3390 for (i = 0; i < 8; i++) {
3391 b4 = b32 & 0xf;
3392 b4 += delta;
3393 if (b4 < 0)
3394 b4 = 0;
3395 else if (b4 > 0xf)
3396 b4 = 0xf;
3397 b32 = b32 >> 4 | b4 << 28;
3398 }
3399 return b32;
3400 }
3401
3402 static const char *
3403 rt2860_get_rf(uint16_t rev)
3404 {
3405 switch (rev) {
3406 case RT2860_RF_2820: return "RT2820";
3407 case RT2860_RF_2850: return "RT2850";
3408 case RT2860_RF_2720: return "RT2720";
3409 case RT2860_RF_2750: return "RT2750";
3410 case RT3070_RF_3020: return "RT3020";
3411 case RT3070_RF_2020: return "RT2020";
3412 case RT3070_RF_3021: return "RT3021";
3413 case RT3070_RF_3022: return "RT3022";
3414 case RT3070_RF_3052: return "RT3052";
3415 case RT3070_RF_3320: return "RT3320";
3416 case RT3070_RF_3053: return "RT3053";
3417 case RT5390_RF_5360: return "RT5360";
3418 case RT5390_RF_5390: return "RT5390";
3419 default: return "unknown";
3420 }
3421 }
3422
3423 static int
3424 rt2860_read_eeprom(struct rt2860_softc *sc, uint8_t macaddr[IEEE80211_ADDR_LEN])
3425 {
3426 int8_t delta_2ghz, delta_5ghz;
3427 uint32_t tmp;
3428 uint16_t val;
3429 int ridx, ant, i;
3430
3431 /* check whether the ROM is eFUSE ROM or EEPROM */
3432 sc->sc_srom_read = rt2860_eeprom_read_2;
3433 if (sc->mac_ver >= 0x3071) {
3434 tmp = RAL_READ(sc, RT3070_EFUSE_CTRL);
3435 DPRINTF(("EFUSE_CTRL=0x%08x\n", tmp));
3436 if (tmp & RT3070_SEL_EFUSE)
3437 sc->sc_srom_read = rt3090_efuse_read_2;
3438 }
3439
3440 #ifdef RAL_DEBUG
3441 /* read EEPROM version */
3442 val = rt2860_srom_read(sc, RT2860_EEPROM_VERSION);
3443 DPRINTF(("EEPROM rev=%d, FAE=%d\n", val >> 8, val & 0xff));
3444 #endif
3445
3446 /* read MAC address */
3447 val = rt2860_srom_read(sc, RT2860_EEPROM_MAC01);
3448 macaddr[0] = val & 0xff;
3449 macaddr[1] = val >> 8;
3450 val = rt2860_srom_read(sc, RT2860_EEPROM_MAC23);
3451 macaddr[2] = val & 0xff;
3452 macaddr[3] = val >> 8;
3453 val = rt2860_srom_read(sc, RT2860_EEPROM_MAC45);
3454 macaddr[4] = val & 0xff;
3455 macaddr[5] = val >> 8;
3456
3457 #ifdef RAL_DEBUG
3458 /* read country code */
3459 val = rt2860_srom_read(sc, RT2860_EEPROM_COUNTRY);
3460 DPRINTF(("EEPROM region code=0x%04x\n", val));
3461 #endif
3462
3463 /* read vendor BBP settings */
3464 for (i = 0; i < 8; i++) {
3465 val = rt2860_srom_read(sc, RT2860_EEPROM_BBP_BASE + i);
3466 sc->bbp[i].val = val & 0xff;
3467 sc->bbp[i].reg = val >> 8;
3468 DPRINTF(("BBP%d=0x%02x\n", sc->bbp[i].reg, sc->bbp[i].val));
3469 }
3470 if (sc->mac_ver >= 0x3071) {
3471 /* read vendor RF settings */
3472 for (i = 0; i < 10; i++) {
3473 val = rt2860_srom_read(sc, RT3071_EEPROM_RF_BASE + i);
3474 sc->rf[i].val = val & 0xff;
3475 sc->rf[i].reg = val >> 8;
3476 DPRINTF(("RF%d=0x%02x\n", sc->rf[i].reg,
3477 sc->rf[i].val));
3478 }
3479 }
3480
3481 /* read RF frequency offset from EEPROM */
3482 val = rt2860_srom_read(sc, RT2860_EEPROM_FREQ_LEDS);
3483 sc->freq = ((val & 0xff) != 0xff) ? val & 0xff : 0;
3484 DPRINTF(("EEPROM freq offset %d\n", sc->freq & 0xff));
3485 if ((val >> 8) != 0xff) {
3486 /* read LEDs operating mode */
3487 sc->leds = val >> 8;
3488 sc->led[0] = rt2860_srom_read(sc, RT2860_EEPROM_LED1);
3489 sc->led[1] = rt2860_srom_read(sc, RT2860_EEPROM_LED2);
3490 sc->led[2] = rt2860_srom_read(sc, RT2860_EEPROM_LED3);
3491 } else {
3492 /* broken EEPROM, use default settings */
3493 sc->leds = 0x01;
3494 sc->led[0] = 0x5555;
3495 sc->led[1] = 0x2221;
3496 sc->led[2] = 0xa9f8;
3497 }
3498 DPRINTF(("EEPROM LED mode=0x%02x, LEDs=0x%04x/0x%04x/0x%04x\n",
3499 sc->leds, sc->led[0], sc->led[1], sc->led[2]));
3500
3501 /* read RF information */
3502 val = rt2860_srom_read(sc, RT2860_EEPROM_ANTENNA);
3503 if (sc->mac_ver >= 0x5390)
3504 sc->rf_rev = rt2860_srom_read(sc, RT2860_EEPROM_CHIPID);
3505 else
3506 sc->rf_rev = (val >> 8) & 0xf;
3507 sc->ntxchains = (val >> 4) & 0xf;
3508 sc->nrxchains = val & 0xf;
3509 DPRINTF(("EEPROM RF rev=0x%02x chains=%dT%dR\n",
3510 sc->rf_rev, sc->ntxchains, sc->nrxchains));
3511
3512 /* check if RF supports automatic Tx access gain control */
3513 val = rt2860_srom_read(sc, RT2860_EEPROM_CONFIG);
3514 DPRINTF(("EEPROM CFG 0x%04x\n", val));
3515 /* check if driver should patch the DAC issue */
3516 if ((val >> 8) != 0xff)
3517 sc->patch_dac = (val >> 15) & 1;
3518 if ((val & 0xff) != 0xff) {
3519 sc->ext_5ghz_lna = (val >> 3) & 1;
3520 sc->ext_2ghz_lna = (val >> 2) & 1;
3521 /* check if RF supports automatic Tx access gain control */
3522 sc->calib_2ghz = sc->calib_5ghz = 0; /* XXX (val >> 1) & 1 */
3523 /* check if we have a hardware radio switch */
3524 sc->rfswitch = val & 1;
3525 }
3526 if (sc->sc_flags & RT2860_ADVANCED_PS) {
3527 /* read PCIe power save level */
3528 val = rt2860_srom_read(sc, RT2860_EEPROM_PCIE_PSLEVEL);
3529 if ((val & 0xff) != 0xff) {
3530 sc->pslevel = val & 0x3;
3531 val = rt2860_srom_read(sc, RT2860_EEPROM_REV);
3532 if ((val & 0xff80) != 0x9280)
3533 sc->pslevel = MIN(sc->pslevel, 1);
3534 DPRINTF(("EEPROM PCIe PS Level=%d\n", sc->pslevel));
3535 }
3536 }
3537
3538 /* read power settings for 2GHz channels */
3539 for (i = 0; i < 14; i += 2) {
3540 val = rt2860_srom_read(sc,
3541 RT2860_EEPROM_PWR2GHZ_BASE1 + i / 2);
3542 sc->txpow1[i + 0] = (int8_t)(val & 0xff);
3543 sc->txpow1[i + 1] = (int8_t)(val >> 8);
3544
3545 if (sc->mac_ver != 0x5390) {
3546 val = rt2860_srom_read(sc,
3547 RT2860_EEPROM_PWR2GHZ_BASE2 + i / 2);
3548 sc->txpow2[i + 0] = (int8_t)(val & 0xff);
3549 sc->txpow2[i + 1] = (int8_t)(val >> 8);
3550 }
3551 }
3552 /* fix broken Tx power entries */
3553 for (i = 0; i < 14; i++) {
3554 if (sc->txpow1[i] < 0 ||
3555 sc->txpow1[i] > ((sc->mac_ver >= 0x5390) ? 39 : 31))
3556 sc->txpow1[i] = 5;
3557 if (sc->mac_ver != 0x5390) {
3558 if (sc->txpow2[i] < 0 ||
3559 sc->txpow2[i] > ((sc->mac_ver == 0x5392) ? 39 : 31))
3560 sc->txpow2[i] = 5;
3561 }
3562 DPRINTF(("chan %d: power1=%d, power2=%d\n",
3563 rt2860_rf2850[i].chan, sc->txpow1[i], sc->txpow2[i]));
3564 }
3565 /* read power settings for 5GHz channels */
3566 for (i = 0; i < 40; i += 2) {
3567 val = rt2860_srom_read(sc,
3568 RT2860_EEPROM_PWR5GHZ_BASE1 + i / 2);
3569 sc->txpow1[i + 14] = (int8_t)(val & 0xff);
3570 sc->txpow1[i + 15] = (int8_t)(val >> 8);
3571
3572 val = rt2860_srom_read(sc,
3573 RT2860_EEPROM_PWR5GHZ_BASE2 + i / 2);
3574 sc->txpow2[i + 14] = (int8_t)(val & 0xff);
3575 sc->txpow2[i + 15] = (int8_t)(val >> 8);
3576 }
3577 /* fix broken Tx power entries */
3578 for (i = 0; i < 40; i++) {
3579 if (sc->txpow1[14 + i] < -7 || sc->txpow1[14 + i] > 15)
3580 sc->txpow1[14 + i] = 5;
3581 if (sc->txpow2[14 + i] < -7 || sc->txpow2[14 + i] > 15)
3582 sc->txpow2[14 + i] = 5;
3583 DPRINTF(("chan %d: power1=%d, power2=%d\n",
3584 rt2860_rf2850[14 + i].chan, sc->txpow1[14 + i],
3585 sc->txpow2[14 + i]));
3586 }
3587
3588 /* read Tx power compensation for each Tx rate */
3589 val = rt2860_srom_read(sc, RT2860_EEPROM_DELTAPWR);
3590 delta_2ghz = delta_5ghz = 0;
3591 if ((val & 0xff) != 0xff && (val & 0x80)) {
3592 delta_2ghz = val & 0xf;
3593 if (!(val & 0x40)) /* negative number */
3594 delta_2ghz = -delta_2ghz;
3595 }
3596 val >>= 8;
3597 if ((val & 0xff) != 0xff && (val & 0x80)) {
3598 delta_5ghz = val & 0xf;
3599 if (!(val & 0x40)) /* negative number */
3600 delta_5ghz = -delta_5ghz;
3601 }
3602 DPRINTF(("power compensation=%d (2GHz), %d (5GHz)\n",
3603 delta_2ghz, delta_5ghz));
3604
3605 for (ridx = 0; ridx < 5; ridx++) {
3606 uint32_t reg;
3607
3608 val = rt2860_srom_read(sc, RT2860_EEPROM_RPWR + ridx * 2);
3609 reg = val;
3610 val = rt2860_srom_read(sc, RT2860_EEPROM_RPWR + ridx * 2 + 1);
3611 reg |= (uint32_t)val << 16;
3612
3613 sc->txpow20mhz[ridx] = reg;
3614 sc->txpow40mhz_2ghz[ridx] = b4inc(reg, delta_2ghz);
3615 sc->txpow40mhz_5ghz[ridx] = b4inc(reg, delta_5ghz);
3616
3617 DPRINTF(("ridx %d: power 20MHz=0x%08x, 40MHz/2GHz=0x%08x, "
3618 "40MHz/5GHz=0x%08x\n", ridx, sc->txpow20mhz[ridx],
3619 sc->txpow40mhz_2ghz[ridx], sc->txpow40mhz_5ghz[ridx]));
3620 }
3621
3622 /* read factory-calibrated samples for temperature compensation */
3623 val = rt2860_srom_read(sc, RT2860_EEPROM_TSSI1_2GHZ);
3624 sc->tssi_2ghz[0] = val & 0xff; /* [-4] */
3625 sc->tssi_2ghz[1] = val >> 8; /* [-3] */
3626 val = rt2860_srom_read(sc, RT2860_EEPROM_TSSI2_2GHZ);
3627 sc->tssi_2ghz[2] = val & 0xff; /* [-2] */
3628 sc->tssi_2ghz[3] = val >> 8; /* [-1] */
3629 val = rt2860_srom_read(sc, RT2860_EEPROM_TSSI3_2GHZ);
3630 sc->tssi_2ghz[4] = val & 0xff; /* [+0] */
3631 sc->tssi_2ghz[5] = val >> 8; /* [+1] */
3632 val = rt2860_srom_read(sc, RT2860_EEPROM_TSSI4_2GHZ);
3633 sc->tssi_2ghz[6] = val & 0xff; /* [+2] */
3634 sc->tssi_2ghz[7] = val >> 8; /* [+3] */
3635 val = rt2860_srom_read(sc, RT2860_EEPROM_TSSI5_2GHZ);
3636 sc->tssi_2ghz[8] = val & 0xff; /* [+4] */
3637 sc->step_2ghz = val >> 8;
3638 DPRINTF(("TSSI 2GHz: 0x%02x 0x%02x 0x%02x 0x%02x 0x%02x 0x%02x 0x%02x "
3639 "0x%02x 0x%02x step=%d\n", sc->tssi_2ghz[0], sc->tssi_2ghz[1],
3640 sc->tssi_2ghz[2], sc->tssi_2ghz[3], sc->tssi_2ghz[4],
3641 sc->tssi_2ghz[5], sc->tssi_2ghz[6], sc->tssi_2ghz[7],
3642 sc->tssi_2ghz[8], sc->step_2ghz));
3643 /* check that ref value is correct, otherwise disable calibration */
3644 if (sc->tssi_2ghz[4] == 0xff)
3645 sc->calib_2ghz = 0;
3646
3647 val = rt2860_srom_read(sc, RT2860_EEPROM_TSSI1_5GHZ);
3648 sc->tssi_5ghz[0] = val & 0xff; /* [-4] */
3649 sc->tssi_5ghz[1] = val >> 8; /* [-3] */
3650 val = rt2860_srom_read(sc, RT2860_EEPROM_TSSI2_5GHZ);
3651 sc->tssi_5ghz[2] = val & 0xff; /* [-2] */
3652 sc->tssi_5ghz[3] = val >> 8; /* [-1] */
3653 val = rt2860_srom_read(sc, RT2860_EEPROM_TSSI3_5GHZ);
3654 sc->tssi_5ghz[4] = val & 0xff; /* [+0] */
3655 sc->tssi_5ghz[5] = val >> 8; /* [+1] */
3656 val = rt2860_srom_read(sc, RT2860_EEPROM_TSSI4_5GHZ);
3657 sc->tssi_5ghz[6] = val & 0xff; /* [+2] */
3658 sc->tssi_5ghz[7] = val >> 8; /* [+3] */
3659 val = rt2860_srom_read(sc, RT2860_EEPROM_TSSI5_5GHZ);
3660 sc->tssi_5ghz[8] = val & 0xff; /* [+4] */
3661 sc->step_5ghz = val >> 8;
3662 DPRINTF(("TSSI 5GHz: 0x%02x 0x%02x 0x%02x 0x%02x 0x%02x 0x%02x 0x%02x "
3663 "0x%02x 0x%02x step=%d\n", sc->tssi_5ghz[0], sc->tssi_5ghz[1],
3664 sc->tssi_5ghz[2], sc->tssi_5ghz[3], sc->tssi_5ghz[4],
3665 sc->tssi_5ghz[5], sc->tssi_5ghz[6], sc->tssi_5ghz[7],
3666 sc->tssi_5ghz[8], sc->step_5ghz));
3667 /* check that ref value is correct, otherwise disable calibration */
3668 if (sc->tssi_5ghz[4] == 0xff)
3669 sc->calib_5ghz = 0;
3670
3671 /* read RSSI offsets and LNA gains from EEPROM */
3672 val = rt2860_srom_read(sc, RT2860_EEPROM_RSSI1_2GHZ);
3673 sc->rssi_2ghz[0] = val & 0xff; /* Ant A */
3674 sc->rssi_2ghz[1] = val >> 8; /* Ant B */
3675 val = rt2860_srom_read(sc, RT2860_EEPROM_RSSI2_2GHZ);
3676 if (sc->mac_ver >= 0x3071) {
3677 /*
3678 * On RT3090 chips (limited to 2 Rx chains), this ROM
3679 * field contains the Tx mixer gain for the 2GHz band.
3680 */
3681 if ((val & 0xff) != 0xff)
3682 sc->txmixgain_2ghz = val & 0x7;
3683 DPRINTF(("tx mixer gain=%u (2GHz)\n", sc->txmixgain_2ghz));
3684 } else
3685 sc->rssi_2ghz[2] = val & 0xff; /* Ant C */
3686 sc->lna[2] = val >> 8; /* channel group 2 */
3687
3688 val = rt2860_srom_read(sc, RT2860_EEPROM_RSSI1_5GHZ);
3689 sc->rssi_5ghz[0] = val & 0xff; /* Ant A */
3690 sc->rssi_5ghz[1] = val >> 8; /* Ant B */
3691 val = rt2860_srom_read(sc, RT2860_EEPROM_RSSI2_5GHZ);
3692 sc->rssi_5ghz[2] = val & 0xff; /* Ant C */
3693 sc->lna[3] = val >> 8; /* channel group 3 */
3694
3695 val = rt2860_srom_read(sc, RT2860_EEPROM_LNA);
3696 if (sc->mac_ver >= 0x3071)
3697 sc->lna[0] = RT3090_DEF_LNA;
3698 else /* channel group 0 */
3699 sc->lna[0] = val & 0xff;
3700 sc->lna[1] = val >> 8; /* channel group 1 */
3701
3702 /* fix broken 5GHz LNA entries */
3703 if (sc->lna[2] == 0 || sc->lna[2] == 0xff) {
3704 DPRINTF(("invalid LNA for channel group %d\n", 2));
3705 sc->lna[2] = sc->lna[1];
3706 }
3707 if (sc->lna[3] == 0 || sc->lna[3] == 0xff) {
3708 DPRINTF(("invalid LNA for channel group %d\n", 3));
3709 sc->lna[3] = sc->lna[1];
3710 }
3711
3712 /* fix broken RSSI offset entries */
3713 for (ant = 0; ant < 3; ant++) {
3714 if (sc->rssi_2ghz[ant] < -10 || sc->rssi_2ghz[ant] > 10) {
3715 DPRINTF(("invalid RSSI%d offset: %d (2GHz)\n",
3716 ant + 1, sc->rssi_2ghz[ant]));
3717 sc->rssi_2ghz[ant] = 0;
3718 }
3719 if (sc->rssi_5ghz[ant] < -10 || sc->rssi_5ghz[ant] > 10) {
3720 DPRINTF(("invalid RSSI%d offset: %d (5GHz)\n",
3721 ant + 1, sc->rssi_5ghz[ant]));
3722 sc->rssi_5ghz[ant] = 0;
3723 }
3724 }
3725
3726 return 0;
3727 }
3728
3729 static int
3730 rt2860_bbp_init(struct rt2860_softc *sc)
3731 {
3732 int i, ntries;
3733
3734 /* wait for BBP to wake up */
3735 for (ntries = 0; ntries < 20; ntries++) {
3736 uint8_t bbp0 = rt2860_mcu_bbp_read(sc, 0);
3737 if (bbp0 != 0 && bbp0 != 0xff)
3738 break;
3739 }
3740 if (ntries == 20) {
3741 device_printf(sc->sc_dev,
3742 "timeout waiting for BBP to wake up\n");
3743 return (ETIMEDOUT);
3744 }
3745
3746 /* initialize BBP registers to default values */
3747 if (sc->mac_ver >= 0x5390)
3748 rt5390_bbp_init(sc);
3749 else {
3750 for (i = 0; i < nitems(rt2860_def_bbp); i++) {
3751 rt2860_mcu_bbp_write(sc, rt2860_def_bbp[i].reg,
3752 rt2860_def_bbp[i].val);
3753 }
3754 }
3755
3756 /* fix BBP84 for RT2860E */
3757 if (sc->mac_ver == 0x2860 && sc->mac_rev != 0x0101)
3758 rt2860_mcu_bbp_write(sc, 84, 0x19);
3759
3760 if (sc->mac_ver >= 0x3071) {
3761 rt2860_mcu_bbp_write(sc, 79, 0x13);
3762 rt2860_mcu_bbp_write(sc, 80, 0x05);
3763 rt2860_mcu_bbp_write(sc, 81, 0x33);
3764 } else if (sc->mac_ver == 0x2860 && sc->mac_rev == 0x0100) {
3765 rt2860_mcu_bbp_write(sc, 69, 0x16);
3766 rt2860_mcu_bbp_write(sc, 73, 0x12);
3767 }
3768
3769 return 0;
3770 }
3771
3772 static void
3773 rt5390_bbp_init(struct rt2860_softc *sc)
3774 {
3775 uint8_t bbp;
3776 int i;
3777
3778 /* Apply maximum likelihood detection for 2 stream case. */
3779 if (sc->nrxchains > 1) {
3780 bbp = rt2860_mcu_bbp_read(sc, 105);
3781 rt2860_mcu_bbp_write(sc, 105, bbp | RT5390_MLD);
3782 }
3783
3784 /* Avoid data lost and CRC error. */
3785 bbp = rt2860_mcu_bbp_read(sc, 4);
3786 rt2860_mcu_bbp_write(sc, 4, bbp | RT5390_MAC_IF_CTRL);
3787
3788 for (i = 0; i < nitems(rt5390_def_bbp); i++) {
3789 rt2860_mcu_bbp_write(sc, rt5390_def_bbp[i].reg,
3790 rt5390_def_bbp[i].val);
3791 }
3792
3793 if (sc->mac_ver == 0x5392) {
3794 rt2860_mcu_bbp_write(sc, 84, 0x9a);
3795 rt2860_mcu_bbp_write(sc, 95, 0x9a);
3796 rt2860_mcu_bbp_write(sc, 98, 0x12);
3797 rt2860_mcu_bbp_write(sc, 106, 0x05);
3798 rt2860_mcu_bbp_write(sc, 134, 0xd0);
3799 rt2860_mcu_bbp_write(sc, 135, 0xf6);
3800 }
3801
3802 bbp = rt2860_mcu_bbp_read(sc, 152);
3803 rt2860_mcu_bbp_write(sc, 152, bbp | 0x80);
3804
3805 /* Disable hardware antenna diversity. */
3806 if (sc->mac_ver == 0x5390)
3807 rt2860_mcu_bbp_write(sc, 154, 0);
3808 }
3809
3810 static int
3811 rt2860_txrx_enable(struct rt2860_softc *sc)
3812 {
3813 struct ieee80211com *ic = &sc->sc_ic;
3814 uint32_t tmp;
3815 int ntries;
3816
3817 /* enable Tx/Rx DMA engine */
3818 RAL_WRITE(sc, RT2860_MAC_SYS_CTRL, RT2860_MAC_TX_EN);
3819 RAL_BARRIER_READ_WRITE(sc);
3820 for (ntries = 0; ntries < 200; ntries++) {
3821 tmp = RAL_READ(sc, RT2860_WPDMA_GLO_CFG);
3822 if ((tmp & (RT2860_TX_DMA_BUSY | RT2860_RX_DMA_BUSY)) == 0)
3823 break;
3824 DELAY(1000);
3825 }
3826 if (ntries == 200) {
3827 device_printf(sc->sc_dev, "timeout waiting for DMA engine\n");
3828 return ETIMEDOUT;
3829 }
3830
3831 DELAY(50);
3832
3833 tmp |= RT2860_RX_DMA_EN | RT2860_TX_DMA_EN |
3834 RT2860_WPDMA_BT_SIZE64 << RT2860_WPDMA_BT_SIZE_SHIFT;
3835 RAL_WRITE(sc, RT2860_WPDMA_GLO_CFG, tmp);
3836
3837 /* set Rx filter */
3838 tmp = RT2860_DROP_CRC_ERR | RT2860_DROP_PHY_ERR;
3839 if (ic->ic_opmode != IEEE80211_M_MONITOR) {
3840 tmp |= RT2860_DROP_UC_NOME | RT2860_DROP_DUPL |
3841 RT2860_DROP_CTS | RT2860_DROP_BA | RT2860_DROP_ACK |
3842 RT2860_DROP_VER_ERR | RT2860_DROP_CTRL_RSV |
3843 RT2860_DROP_CFACK | RT2860_DROP_CFEND;
3844 if (ic->ic_opmode == IEEE80211_M_STA)
3845 tmp |= RT2860_DROP_RTS | RT2860_DROP_PSPOLL;
3846 }
3847 RAL_WRITE(sc, RT2860_RX_FILTR_CFG, tmp);
3848
3849 RAL_WRITE(sc, RT2860_MAC_SYS_CTRL,
3850 RT2860_MAC_RX_EN | RT2860_MAC_TX_EN);
3851
3852 return 0;
3853 }
3854
3855 static void
3856 rt2860_init(void *arg)
3857 {
3858 struct rt2860_softc *sc = arg;
3859 struct ieee80211com *ic = &sc->sc_ic;
3860
3861 RAL_LOCK(sc);
3862 rt2860_init_locked(sc);
3863 RAL_UNLOCK(sc);
3864
3865 if (sc->sc_flags & RT2860_RUNNING)
3866 ieee80211_start_all(ic);
3867 }
3868
3869 static void
3870 rt2860_init_locked(struct rt2860_softc *sc)
3871 {
3872 struct ieee80211com *ic = &sc->sc_ic;
3873 struct ieee80211vap *vap = TAILQ_FIRST(&ic->ic_vaps);
3874 uint32_t tmp;
3875 uint8_t bbp1, bbp3;
3876 int i, qid, ridx, ntries, error;
3877
3878 RAL_LOCK_ASSERT(sc);
3879
3880 if (sc->rfswitch) {
3881 /* hardware has a radio switch on GPIO pin 2 */
3882 if (!(RAL_READ(sc, RT2860_GPIO_CTRL) & (1 << 2))) {
3883 device_printf(sc->sc_dev,
3884 "radio is disabled by hardware switch\n");
3885 #ifdef notyet
3886 rt2860_stop_locked(sc);
3887 return;
3888 #endif
3889 }
3890 }
3891 RAL_WRITE(sc, RT2860_PWR_PIN_CFG, RT2860_IO_RA_PE);
3892
3893 /* disable DMA */
3894 tmp = RAL_READ(sc, RT2860_WPDMA_GLO_CFG);
3895 tmp &= 0xff0;
3896 RAL_WRITE(sc, RT2860_WPDMA_GLO_CFG, tmp);
3897
3898 /* PBF hardware reset */
3899 RAL_WRITE(sc, RT2860_SYS_CTRL, 0xe1f);
3900 RAL_BARRIER_WRITE(sc);
3901 RAL_WRITE(sc, RT2860_SYS_CTRL, 0xe00);
3902
3903 if ((error = rt2860_load_microcode(sc)) != 0) {
3904 device_printf(sc->sc_dev, "could not load 8051 microcode\n");
3905 rt2860_stop_locked(sc);
3906 return;
3907 }
3908
3909 rt2860_set_macaddr(sc, vap ? vap->iv_myaddr : ic->ic_macaddr);
3910
3911 /* init Tx power for all Tx rates (from EEPROM) */
3912 for (ridx = 0; ridx < 5; ridx++) {
3913 if (sc->txpow20mhz[ridx] == 0xffffffff)
3914 continue;
3915 RAL_WRITE(sc, RT2860_TX_PWR_CFG(ridx), sc->txpow20mhz[ridx]);
3916 }
3917
3918 for (ntries = 0; ntries < 100; ntries++) {
3919 tmp = RAL_READ(sc, RT2860_WPDMA_GLO_CFG);
3920 if ((tmp & (RT2860_TX_DMA_BUSY | RT2860_RX_DMA_BUSY)) == 0)
3921 break;
3922 DELAY(1000);
3923 }
3924 if (ntries == 100) {
3925 device_printf(sc->sc_dev, "timeout waiting for DMA engine\n");
3926 rt2860_stop_locked(sc);
3927 return;
3928 }
3929 tmp &= 0xff0;
3930 RAL_WRITE(sc, RT2860_WPDMA_GLO_CFG, tmp);
3931
3932 /* reset Rx ring and all 6 Tx rings */
3933 RAL_WRITE(sc, RT2860_WPDMA_RST_IDX, 0x1003f);
3934
3935 /* PBF hardware reset */
3936 RAL_WRITE(sc, RT2860_SYS_CTRL, 0xe1f);
3937 RAL_BARRIER_WRITE(sc);
3938 RAL_WRITE(sc, RT2860_SYS_CTRL, 0xe00);
3939
3940 RAL_WRITE(sc, RT2860_PWR_PIN_CFG, RT2860_IO_RA_PE | RT2860_IO_RF_PE);
3941
3942 RAL_WRITE(sc, RT2860_MAC_SYS_CTRL, RT2860_BBP_HRST | RT2860_MAC_SRST);
3943 RAL_BARRIER_WRITE(sc);
3944 RAL_WRITE(sc, RT2860_MAC_SYS_CTRL, 0);
3945
3946 for (i = 0; i < nitems(rt2860_def_mac); i++)
3947 RAL_WRITE(sc, rt2860_def_mac[i].reg, rt2860_def_mac[i].val);
3948 if (sc->mac_ver >= 0x5390)
3949 RAL_WRITE(sc, RT2860_TX_SW_CFG0, 0x00000404);
3950 else if (sc->mac_ver >= 0x3071) {
3951 /* set delay of PA_PE assertion to 1us (unit of 0.25us) */
3952 RAL_WRITE(sc, RT2860_TX_SW_CFG0,
3953 4 << RT2860_DLY_PAPE_EN_SHIFT);
3954 }
3955
3956 if (!(RAL_READ(sc, RT2860_PCI_CFG) & RT2860_PCI_CFG_PCI)) {
3957 sc->sc_flags |= RT2860_PCIE;
3958 /* PCIe has different clock cycle count than PCI */
3959 tmp = RAL_READ(sc, RT2860_US_CYC_CNT);
3960 tmp = (tmp & ~0xff) | 0x7d;
3961 RAL_WRITE(sc, RT2860_US_CYC_CNT, tmp);
3962 }
3963
3964 /* wait while MAC is busy */
3965 for (ntries = 0; ntries < 100; ntries++) {
3966 if (!(RAL_READ(sc, RT2860_MAC_STATUS_REG) &
3967 (RT2860_RX_STATUS_BUSY | RT2860_TX_STATUS_BUSY)))
3968 break;
3969 DELAY(1000);
3970 }
3971 if (ntries == 100) {
3972 device_printf(sc->sc_dev, "timeout waiting for MAC\n");
3973 rt2860_stop_locked(sc);
3974 return;
3975 }
3976
3977 /* clear Host to MCU mailbox */
3978 RAL_WRITE(sc, RT2860_H2M_BBPAGENT, 0);
3979 RAL_WRITE(sc, RT2860_H2M_MAILBOX, 0);
3980
3981 rt2860_mcu_cmd(sc, RT2860_MCU_CMD_RFRESET, 0, 0);
3982 DELAY(1000);
3983
3984 if ((error = rt2860_bbp_init(sc)) != 0) {
3985 rt2860_stop_locked(sc);
3986 return;
3987 }
3988
3989 /* clear RX WCID search table */
3990 RAL_SET_REGION_4(sc, RT2860_WCID_ENTRY(0), 0, 512);
3991 /* clear pairwise key table */
3992 RAL_SET_REGION_4(sc, RT2860_PKEY(0), 0, 2048);
3993 /* clear IV/EIV table */
3994 RAL_SET_REGION_4(sc, RT2860_IVEIV(0), 0, 512);
3995 /* clear WCID attribute table */
3996 RAL_SET_REGION_4(sc, RT2860_WCID_ATTR(0), 0, 256);
3997 /* clear shared key table */
3998 RAL_SET_REGION_4(sc, RT2860_SKEY(0, 0), 0, 8 * 32);
3999 /* clear shared key mode */
4000 RAL_SET_REGION_4(sc, RT2860_SKEY_MODE_0_7, 0, 4);
4001
4002 /* init Tx rings (4 EDCAs + HCCA + Mgt) */
4003 for (qid = 0; qid < 6; qid++) {
4004 RAL_WRITE(sc, RT2860_TX_BASE_PTR(qid), sc->txq[qid].paddr);
4005 RAL_WRITE(sc, RT2860_TX_MAX_CNT(qid), RT2860_TX_RING_COUNT);
4006 RAL_WRITE(sc, RT2860_TX_CTX_IDX(qid), 0);
4007 }
4008
4009 /* init Rx ring */
4010 RAL_WRITE(sc, RT2860_RX_BASE_PTR, sc->rxq.paddr);
4011 RAL_WRITE(sc, RT2860_RX_MAX_CNT, RT2860_RX_RING_COUNT);
4012 RAL_WRITE(sc, RT2860_RX_CALC_IDX, RT2860_RX_RING_COUNT - 1);
4013
4014 /* setup maximum buffer sizes */
4015 RAL_WRITE(sc, RT2860_MAX_LEN_CFG, 1 << 12 |
4016 (MCLBYTES - sizeof (struct rt2860_rxwi) - 2));
4017
4018 for (ntries = 0; ntries < 100; ntries++) {
4019 tmp = RAL_READ(sc, RT2860_WPDMA_GLO_CFG);
4020 if ((tmp & (RT2860_TX_DMA_BUSY | RT2860_RX_DMA_BUSY)) == 0)
4021 break;
4022 DELAY(1000);
4023 }
4024 if (ntries == 100) {
4025 device_printf(sc->sc_dev, "timeout waiting for DMA engine\n");
4026 rt2860_stop_locked(sc);
4027 return;
4028 }
4029 tmp &= 0xff0;
4030 RAL_WRITE(sc, RT2860_WPDMA_GLO_CFG, tmp);
4031
4032 /* disable interrupts mitigation */
4033 RAL_WRITE(sc, RT2860_DELAY_INT_CFG, 0);
4034
4035 /* write vendor-specific BBP values (from EEPROM) */
4036 for (i = 0; i < 8; i++) {
4037 if (sc->bbp[i].reg == 0 || sc->bbp[i].reg == 0xff)
4038 continue;
4039 rt2860_mcu_bbp_write(sc, sc->bbp[i].reg, sc->bbp[i].val);
4040 }
4041
4042 /* select Main antenna for 1T1R devices */
4043 if (sc->rf_rev == RT3070_RF_2020 ||
4044 sc->rf_rev == RT3070_RF_3020 ||
4045 sc->rf_rev == RT3070_RF_3320 ||
4046 sc->mac_ver == 0x5390)
4047 rt3090_set_rx_antenna(sc, 0);
4048
4049 /* send LEDs operating mode to microcontroller */
4050 rt2860_mcu_cmd(sc, RT2860_MCU_CMD_LED1, sc->led[0], 0);
4051 rt2860_mcu_cmd(sc, RT2860_MCU_CMD_LED2, sc->led[1], 0);
4052 rt2860_mcu_cmd(sc, RT2860_MCU_CMD_LED3, sc->led[2], 0);
4053
4054 if (sc->mac_ver >= 0x5390)
4055 rt5390_rf_init(sc);
4056 else if (sc->mac_ver >= 0x3071) {
4057 if ((error = rt3090_rf_init(sc)) != 0) {
4058 rt2860_stop_locked(sc);
4059 return;
4060 }
4061 }
4062
4063 rt2860_mcu_cmd(sc, RT2860_MCU_CMD_SLEEP, 0x02ff, 1);
4064 rt2860_mcu_cmd(sc, RT2860_MCU_CMD_WAKEUP, 0, 1);
4065
4066 if (sc->mac_ver >= 0x5390)
4067 rt5390_rf_wakeup(sc);
4068 else if (sc->mac_ver >= 0x3071)
4069 rt3090_rf_wakeup(sc);
4070
4071 /* disable non-existing Rx chains */
4072 bbp3 = rt2860_mcu_bbp_read(sc, 3);
4073 bbp3 &= ~(1 << 3 | 1 << 4);
4074 if (sc->nrxchains == 2)
4075 bbp3 |= 1 << 3;
4076 else if (sc->nrxchains == 3)
4077 bbp3 |= 1 << 4;
4078 rt2860_mcu_bbp_write(sc, 3, bbp3);
4079
4080 /* disable non-existing Tx chains */
4081 bbp1 = rt2860_mcu_bbp_read(sc, 1);
4082 if (sc->ntxchains == 1)
4083 bbp1 = (bbp1 & ~(1 << 3 | 1 << 4));
4084 else if (sc->mac_ver == 0x3593 && sc->ntxchains == 2)
4085 bbp1 = (bbp1 & ~(1 << 4)) | 1 << 3;
4086 else if (sc->mac_ver == 0x3593 && sc->ntxchains == 3)
4087 bbp1 = (bbp1 & ~(1 << 3)) | 1 << 4;
4088 rt2860_mcu_bbp_write(sc, 1, bbp1);
4089
4090 if (sc->mac_ver >= 0x3071)
4091 rt3090_rf_setup(sc);
4092
4093 /* select default channel */
4094 rt2860_switch_chan(sc, ic->ic_curchan);
4095
4096 /* reset RF from MCU */
4097 rt2860_mcu_cmd(sc, RT2860_MCU_CMD_RFRESET, 0, 0);
4098
4099 /* set RTS threshold */
4100 tmp = RAL_READ(sc, RT2860_TX_RTS_CFG);
4101 tmp &= ~0xffff00;
4102 tmp |= IEEE80211_RTS_DEFAULT << 8;
4103 RAL_WRITE(sc, RT2860_TX_RTS_CFG, tmp);
4104
4105 /* setup initial protection mode */
4106 rt2860_updateprot(sc);
4107
4108 /* turn radio LED on */
4109 rt2860_set_leds(sc, RT2860_LED_RADIO);
4110
4111 /* enable Tx/Rx DMA engine */
4112 if ((error = rt2860_txrx_enable(sc)) != 0) {
4113 rt2860_stop_locked(sc);
4114 return;
4115 }
4116
4117 /* clear pending interrupts */
4118 RAL_WRITE(sc, RT2860_INT_STATUS, 0xffffffff);
4119 /* enable interrupts */
4120 RAL_WRITE(sc, RT2860_INT_MASK, 0x3fffc);
4121
4122 if (sc->sc_flags & RT2860_ADVANCED_PS)
4123 rt2860_mcu_cmd(sc, RT2860_MCU_CMD_PSLEVEL, sc->pslevel, 0);
4124
4125 sc->sc_flags |= RT2860_RUNNING;
4126
4127 callout_reset(&sc->watchdog_ch, hz, rt2860_watchdog, sc);
4128 }
4129
4130 static void
4131 rt2860_stop(void *arg)
4132 {
4133 struct rt2860_softc *sc = arg;
4134
4135 RAL_LOCK(sc);
4136 rt2860_stop_locked(sc);
4137 RAL_UNLOCK(sc);
4138 }
4139
4140 static void
4141 rt2860_stop_locked(struct rt2860_softc *sc)
4142 {
4143 uint32_t tmp;
4144 int qid;
4145
4146 if (sc->sc_flags & RT2860_RUNNING)
4147 rt2860_set_leds(sc, 0); /* turn all LEDs off */
4148
4149 callout_stop(&sc->watchdog_ch);
4150 sc->sc_tx_timer = 0;
4151 sc->sc_flags &= ~RT2860_RUNNING;
4152
4153 /* disable interrupts */
4154 RAL_WRITE(sc, RT2860_INT_MASK, 0);
4155
4156 /* disable GP timer */
4157 rt2860_set_gp_timer(sc, 0);
4158
4159 /* disable Rx */
4160 tmp = RAL_READ(sc, RT2860_MAC_SYS_CTRL);
4161 tmp &= ~(RT2860_MAC_RX_EN | RT2860_MAC_TX_EN);
4162 RAL_WRITE(sc, RT2860_MAC_SYS_CTRL, tmp);
4163
4164 /* reset adapter */
4165 RAL_WRITE(sc, RT2860_MAC_SYS_CTRL, RT2860_BBP_HRST | RT2860_MAC_SRST);
4166 RAL_BARRIER_WRITE(sc);
4167 RAL_WRITE(sc, RT2860_MAC_SYS_CTRL, 0);
4168
4169 /* reset Tx and Rx rings (and reclaim TXWIs) */
4170 sc->qfullmsk = 0;
4171 for (qid = 0; qid < 6; qid++)
4172 rt2860_reset_tx_ring(sc, &sc->txq[qid]);
4173 rt2860_reset_rx_ring(sc, &sc->rxq);
4174 }
4175
4176 int
4177 rt2860_load_microcode(struct rt2860_softc *sc)
4178 {
4179 const struct firmware *fp;
4180 int ntries, error;
4181
4182 RAL_LOCK_ASSERT(sc);
4183
4184 RAL_UNLOCK(sc);
4185 fp = firmware_get("rt2860fw");
4186 RAL_LOCK(sc);
4187 if (fp == NULL) {
4188 device_printf(sc->sc_dev,
4189 "unable to receive rt2860fw firmware image\n");
4190 return EINVAL;
4191 }
4192
4193 /* set "host program ram write selection" bit */
4194 RAL_WRITE(sc, RT2860_SYS_CTRL, RT2860_HST_PM_SEL);
4195 /* write microcode image */
4196 RAL_WRITE_REGION_1(sc, RT2860_FW_BASE, fp->data, fp->datasize);
4197 /* kick microcontroller unit */
4198 RAL_WRITE(sc, RT2860_SYS_CTRL, 0);
4199 RAL_BARRIER_WRITE(sc);
4200 RAL_WRITE(sc, RT2860_SYS_CTRL, RT2860_MCU_RESET);
4201
4202 RAL_WRITE(sc, RT2860_H2M_BBPAGENT, 0);
4203 RAL_WRITE(sc, RT2860_H2M_MAILBOX, 0);
4204
4205 /* wait until microcontroller is ready */
4206 RAL_BARRIER_READ_WRITE(sc);
4207 for (ntries = 0; ntries < 1000; ntries++) {
4208 if (RAL_READ(sc, RT2860_SYS_CTRL) & RT2860_MCU_READY)
4209 break;
4210 DELAY(1000);
4211 }
4212 if (ntries == 1000) {
4213 device_printf(sc->sc_dev,
4214 "timeout waiting for MCU to initialize\n");
4215 error = ETIMEDOUT;
4216 } else
4217 error = 0;
4218
4219 firmware_put(fp, FIRMWARE_UNLOAD);
4220 return error;
4221 }
4222
4223 /*
4224 * This function is called periodically to adjust Tx power based on
4225 * temperature variation.
4226 */
4227 #ifdef NOT_YET
4228 static void
4229 rt2860_calib(struct rt2860_softc *sc)
4230 {
4231 struct ieee80211com *ic = &sc->sc_ic;
4232 const uint8_t *tssi;
4233 uint8_t step, bbp49;
4234 int8_t ridx, d;
4235
4236 /* read current temperature */
4237 bbp49 = rt2860_mcu_bbp_read(sc, 49);
4238
4239 if (IEEE80211_IS_CHAN_2GHZ(ic->ic_bss->ni_chan)) {
4240 tssi = &sc->tssi_2ghz[4];
4241 step = sc->step_2ghz;
4242 } else {
4243 tssi = &sc->tssi_5ghz[4];
4244 step = sc->step_5ghz;
4245 }
4246
4247 if (bbp49 < tssi[0]) { /* lower than reference */
4248 /* use higher Tx power than default */
4249 for (d = 0; d > -4 && bbp49 <= tssi[d - 1]; d--);
4250 } else if (bbp49 > tssi[0]) { /* greater than reference */
4251 /* use lower Tx power than default */
4252 for (d = 0; d < +4 && bbp49 >= tssi[d + 1]; d++);
4253 } else {
4254 /* use default Tx power */
4255 d = 0;
4256 }
4257 d *= step;
4258
4259 DPRINTF(("BBP49=0x%02x, adjusting Tx power by %d\n", bbp49, d));
4260
4261 /* write adjusted Tx power values for each Tx rate */
4262 for (ridx = 0; ridx < 5; ridx++) {
4263 if (sc->txpow20mhz[ridx] == 0xffffffff)
4264 continue;
4265 RAL_WRITE(sc, RT2860_TX_PWR_CFG(ridx),
4266 b4inc(sc->txpow20mhz[ridx], d));
4267 }
4268 }
4269 #endif
4270
4271 static void
4272 rt3090_set_rx_antenna(struct rt2860_softc *sc, int aux)
4273 {
4274 uint32_t tmp;
4275
4276 if (aux) {
4277 if (sc->mac_ver == 0x5390) {
4278 rt2860_mcu_bbp_write(sc, 152,
4279 rt2860_mcu_bbp_read(sc, 152) & ~0x80);
4280 } else {
4281 tmp = RAL_READ(sc, RT2860_PCI_EECTRL);
4282 RAL_WRITE(sc, RT2860_PCI_EECTRL, tmp & ~RT2860_C);
4283 tmp = RAL_READ(sc, RT2860_GPIO_CTRL);
4284 RAL_WRITE(sc, RT2860_GPIO_CTRL, (tmp & ~0x0808) | 0x08);
4285 }
4286 } else {
4287 if (sc->mac_ver == 0x5390) {
4288 rt2860_mcu_bbp_write(sc, 152,
4289 rt2860_mcu_bbp_read(sc, 152) | 0x80);
4290 } else {
4291 tmp = RAL_READ(sc, RT2860_PCI_EECTRL);
4292 RAL_WRITE(sc, RT2860_PCI_EECTRL, tmp | RT2860_C);
4293 tmp = RAL_READ(sc, RT2860_GPIO_CTRL);
4294 RAL_WRITE(sc, RT2860_GPIO_CTRL, tmp & ~0x0808);
4295 }
4296 }
4297 }
4298
4299 static void
4300 rt2860_switch_chan(struct rt2860_softc *sc, struct ieee80211_channel *c)
4301 {
4302 struct ieee80211com *ic = &sc->sc_ic;
4303 u_int chan, group;
4304
4305 chan = ieee80211_chan2ieee(ic, c);
4306 if (chan == 0 || chan == IEEE80211_CHAN_ANY)
4307 return;
4308
4309 if (sc->mac_ver >= 0x5390)
4310 rt5390_set_chan(sc, chan);
4311 else if (sc->mac_ver >= 0x3071)
4312 rt3090_set_chan(sc, chan);
4313 else
4314 rt2860_set_chan(sc, chan);
4315
4316 /* determine channel group */
4317 if (chan <= 14)
4318 group = 0;
4319 else if (chan <= 64)
4320 group = 1;
4321 else if (chan <= 128)
4322 group = 2;
4323 else
4324 group = 3;
4325
4326 /* XXX necessary only when group has changed! */
4327 if (sc->mac_ver < 0x5390)
4328 rt2860_select_chan_group(sc, group);
4329
4330 DELAY(1000);
4331 }
4332
4333 static int
4334 rt2860_setup_beacon(struct rt2860_softc *sc, struct ieee80211vap *vap)
4335 {
4336 struct ieee80211com *ic = vap->iv_ic;
4337 struct rt2860_txwi txwi;
4338 struct mbuf *m;
4339 int ridx;
4340
4341 if ((m = ieee80211_beacon_alloc(vap->iv_bss)) == NULL)
4342 return ENOBUFS;
4343
4344 memset(&txwi, 0, sizeof txwi);
4345 txwi.wcid = 0xff;
4346 txwi.len = htole16(m->m_pkthdr.len);
4347 /* send beacons at the lowest available rate */
4348 ridx = IEEE80211_IS_CHAN_5GHZ(ic->ic_bsschan) ?
4349 RT2860_RIDX_OFDM6 : RT2860_RIDX_CCK1;
4350 txwi.phy = htole16(rt2860_rates[ridx].mcs);
4351 if (rt2860_rates[ridx].phy == IEEE80211_T_OFDM)
4352 txwi.phy |= htole16(RT2860_PHY_OFDM);
4353 txwi.txop = RT2860_TX_TXOP_HT;
4354 txwi.flags = RT2860_TX_TS;
4355 txwi.xflags = RT2860_TX_NSEQ;
4356
4357 RAL_WRITE_REGION_1(sc, RT2860_BCN_BASE(0),
4358 (uint8_t *)&txwi, sizeof txwi);
4359 RAL_WRITE_REGION_1(sc, RT2860_BCN_BASE(0) + sizeof txwi,
4360 mtod(m, uint8_t *), m->m_pkthdr.len);
4361
4362 m_freem(m);
4363
4364 return 0;
4365 }
4366
4367 static void
4368 rt2860_enable_tsf_sync(struct rt2860_softc *sc)
4369 {
4370 struct ieee80211com *ic = &sc->sc_ic;
4371 struct ieee80211vap *vap = TAILQ_FIRST(&ic->ic_vaps);
4372 uint32_t tmp;
4373
4374 tmp = RAL_READ(sc, RT2860_BCN_TIME_CFG);
4375
4376 tmp &= ~0x1fffff;
4377 tmp |= vap->iv_bss->ni_intval * 16;
4378 tmp |= RT2860_TSF_TIMER_EN | RT2860_TBTT_TIMER_EN;
4379 if (vap->iv_opmode == IEEE80211_M_STA) {
4380 /*
4381 * Local TSF is always updated with remote TSF on beacon
4382 * reception.
4383 */
4384 tmp |= 1 << RT2860_TSF_SYNC_MODE_SHIFT;
4385 }
4386 else if (vap->iv_opmode == IEEE80211_M_IBSS ||
4387 vap->iv_opmode == IEEE80211_M_MBSS) {
4388 tmp |= RT2860_BCN_TX_EN;
4389 /*
4390 * Local TSF is updated with remote TSF on beacon reception
4391 * only if the remote TSF is greater than local TSF.
4392 */
4393 tmp |= 2 << RT2860_TSF_SYNC_MODE_SHIFT;
4394 } else if (vap->iv_opmode == IEEE80211_M_HOSTAP) {
4395 tmp |= RT2860_BCN_TX_EN;
4396 /* SYNC with nobody */
4397 tmp |= 3 << RT2860_TSF_SYNC_MODE_SHIFT;
4398 }
4399
4400 RAL_WRITE(sc, RT2860_BCN_TIME_CFG, tmp);
4401 }
DragonFly BSD