?  search:
summary | log | graphiclog1 | graphiclog2 | commit | commitdiff | tree | refs | edit | fork
blame | history | raw | HEAD
mp_probe() -> mptable_probe()
[dragonfly.git] / sys / platform / pc32 / i386 / mp_machdep.c
blob8568f15efd39348a72f88161a1a68c4c73f00400
1 /*
2 * Copyright (c) 1996, by Steve Passe
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
7 * are met:
8 * 1. Redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer.
10 * 2. The name of the developer may NOT be used to endorse or promote products
11 * derived from this software without specific prior written permission.
12 *
13 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
14 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
15 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
16 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
17 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
18 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
19 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
20 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
21 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
22 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
23 * SUCH DAMAGE.
24 *
25 * $FreeBSD: src/sys/i386/i386/mp_machdep.c,v 1.115.2.15 2003/03/14 21:22:35 jhb Exp $
26 * $DragonFly: src/sys/platform/pc32/i386/mp_machdep.c,v 1.60 2008/06/07 12:03:52 mneumann Exp $
27 */
28
29 #include "opt_cpu.h"
30
31 #include <sys/param.h>
32 #include <sys/systm.h>
33 #include <sys/kernel.h>
34 #include <sys/sysctl.h>
35 #include <sys/malloc.h>
36 #include <sys/memrange.h>
37 #include <sys/cons.h> /* cngetc() */
38 #include <sys/machintr.h>
39
40 #include <vm/vm.h>
41 #include <vm/vm_param.h>
42 #include <vm/pmap.h>
43 #include <vm/vm_kern.h>
44 #include <vm/vm_extern.h>
45 #include <sys/lock.h>
46 #include <vm/vm_map.h>
47 #include <sys/user.h>
48 #ifdef GPROF
49 #include <sys/gmon.h>
50 #endif
51
52 #include <machine/smp.h>
53 #include <machine_base/apic/apicreg.h>
54 #include <machine/atomic.h>
55 #include <machine/cpufunc.h>
56 #include <machine_base/apic/mpapic.h>
57 #include <machine/psl.h>
58 #include <machine/segments.h>
59 #include <machine/tss.h>
60 #include <machine/specialreg.h>
61 #include <machine/globaldata.h>
62
63 #include <machine/md_var.h> /* setidt() */
64 #include <machine_base/icu/icu.h> /* IPIs */
65 #include <machine_base/isa/intr_machdep.h> /* IPIs */
66
67 #define FIXUP_EXTRA_APIC_INTS 8 /* additional entries we may create */
68
69 #define WARMBOOT_TARGET 0
70 #define WARMBOOT_OFF (KERNBASE + 0x0467)
71 #define WARMBOOT_SEG (KERNBASE + 0x0469)
72
73 #define BIOS_BASE (0xf0000)
74 #define BIOS_SIZE (0x10000)
75 #define BIOS_COUNT (BIOS_SIZE/4)
76
77 #define CMOS_REG (0x70)
78 #define CMOS_DATA (0x71)
79 #define BIOS_RESET (0x0f)
80 #define BIOS_WARM (0x0a)
81
82 #define PROCENTRY_FLAG_EN 0x01
83 #define PROCENTRY_FLAG_BP 0x02
84 #define IOAPICENTRY_FLAG_EN 0x01
85
86
87 /* MP Floating Pointer Structure */
88 typedef struct MPFPS {
89 char signature[4];
90 u_int32_t pap;
91 u_char length;
92 u_char spec_rev;
93 u_char checksum;
94 u_char mpfb1;
95 u_char mpfb2;
96 u_char mpfb3;
97 u_char mpfb4;
98 u_char mpfb5;
99 } *mpfps_t;
100
101 /* MP Configuration Table Header */
102 typedef struct MPCTH {
103 char signature[4];
104 u_short base_table_length;
105 u_char spec_rev;
106 u_char checksum;
107 u_char oem_id[8];
108 u_char product_id[12];
109 void *oem_table_pointer;
110 u_short oem_table_size;
111 u_short entry_count;
112 void *apic_address;
113 u_short extended_table_length;
114 u_char extended_table_checksum;
115 u_char reserved;
116 } *mpcth_t;
117
118
119 typedef struct PROCENTRY {
120 u_char type;
121 u_char apic_id;
122 u_char apic_version;
123 u_char cpu_flags;
124 u_long cpu_signature;
125 u_long feature_flags;
126 u_long reserved1;
127 u_long reserved2;
128 } *proc_entry_ptr;
129
130 typedef struct BUSENTRY {
131 u_char type;
132 u_char bus_id;
133 char bus_type[6];
134 } *bus_entry_ptr;
135
136 typedef struct IOAPICENTRY {
137 u_char type;
138 u_char apic_id;
139 u_char apic_version;
140 u_char apic_flags;
141 void *apic_address;
142 } *io_apic_entry_ptr;
143
144 typedef struct INTENTRY {
145 u_char type;
146 u_char int_type;
147 u_short int_flags;
148 u_char src_bus_id;
149 u_char src_bus_irq;
150 u_char dst_apic_id;
151 u_char dst_apic_int;
152 } *int_entry_ptr;
153
154 /* descriptions of MP basetable entries */
155 typedef struct BASETABLE_ENTRY {
156 u_char type;
157 u_char length;
158 char name[16];
159 } basetable_entry;
160
161 struct mptable_pos {
162 mpfps_t mp_fps;
163 mpcth_t mp_cth;
164 vm_size_t mp_cth_mapsz;
165 };
166
167 /*
168 * this code MUST be enabled here and in mpboot.s.
169 * it follows the very early stages of AP boot by placing values in CMOS ram.
170 * it NORMALLY will never be needed and thus the primitive method for enabling.
171 *
172 */
173 #if defined(CHECK_POINTS)
174 #define CHECK_READ(A) (outb(CMOS_REG, (A)), inb(CMOS_DATA))
175 #define CHECK_WRITE(A,D) (outb(CMOS_REG, (A)), outb(CMOS_DATA, (D)))
176
177 #define CHECK_INIT(D); \
178 CHECK_WRITE(0x34, (D)); \
179 CHECK_WRITE(0x35, (D)); \
180 CHECK_WRITE(0x36, (D)); \
181 CHECK_WRITE(0x37, (D)); \
182 CHECK_WRITE(0x38, (D)); \
183 CHECK_WRITE(0x39, (D));
184
185 #define CHECK_PRINT(S); \
186 kprintf("%s: %d, %d, %d, %d, %d, %d\n", \
187 (S), \
188 CHECK_READ(0x34), \
189 CHECK_READ(0x35), \
190 CHECK_READ(0x36), \
191 CHECK_READ(0x37), \
192 CHECK_READ(0x38), \
193 CHECK_READ(0x39));
194
195 #else /* CHECK_POINTS */
196
197 #define CHECK_INIT(D)
198 #define CHECK_PRINT(S)
199
200 #endif /* CHECK_POINTS */
201
202 /*
203 * Values to send to the POST hardware.
204 */
205 #define MP_BOOTADDRESS_POST 0x10
206 #define MP_PROBE_POST 0x11
207 #define MPTABLE_PASS1_POST 0x12
208
209 #define MP_START_POST 0x13
210 #define MP_ENABLE_POST 0x14
211 #define MPTABLE_PASS2_POST 0x15
212
213 #define START_ALL_APS_POST 0x16
214 #define INSTALL_AP_TRAMP_POST 0x17
215 #define START_AP_POST 0x18
216
217 #define MP_ANNOUNCE_POST 0x19
218
219 static int need_hyperthreading_fixup;
220 static u_int logical_cpus;
221 u_int logical_cpus_mask;
222
223 /** XXX FIXME: where does this really belong, isa.h/isa.c perhaps? */
224 int current_postcode;
225
226 /** XXX FIXME: what system files declare these??? */
227 extern struct region_descriptor r_gdt, r_idt;
228
229 int bsp_apic_ready = 0; /* flags useability of BSP apic */
230 int mp_naps; /* # of Applications processors */
231 int mp_nbusses; /* # of busses */
232 #ifdef APIC_IO
233 int mp_napics; /* # of IO APICs */
234 #endif
235 int boot_cpu_id; /* designated BSP */
236 vm_offset_t cpu_apic_address;
237 #ifdef APIC_IO
238 vm_offset_t io_apic_address[NAPICID]; /* NAPICID is more than enough */
239 u_int32_t *io_apic_versions;
240 #endif
241 extern int nkpt;
242
243 u_int32_t cpu_apic_versions[MAXCPU];
244 int64_t tsc0_offset;
245 extern int64_t tsc_offsets[];
246
247 extern u_long ebda_addr;
248
249 #ifdef APIC_IO
250 struct apic_intmapinfo int_to_apicintpin[APIC_INTMAPSIZE];
251 #endif
252
253 /*
254 * APIC ID logical/physical mapping structures.
255 * We oversize these to simplify boot-time config.
256 */
257 int cpu_num_to_apic_id[NAPICID];
258 #ifdef APIC_IO
259 int io_num_to_apic_id[NAPICID];
260 #endif
261 int apic_id_to_logical[NAPICID];
262
263 /* AP uses this during bootstrap. Do not staticize. */
264 char *bootSTK;
265 static int bootAP;
266
267 /* Hotwire a 0->4MB V==P mapping */
268 extern pt_entry_t *KPTphys;
269
270 /*
271 * SMP page table page. Setup by locore to point to a page table
272 * page from which we allocate per-cpu privatespace areas io_apics,
273 * and so forth.
274 */
275
276 #define IO_MAPPING_START_INDEX \
277 (SMP_MAXCPU * sizeof(struct privatespace) / PAGE_SIZE)
278
279 extern pt_entry_t *SMPpt;
280 static int SMPpt_alloc_index = IO_MAPPING_START_INDEX;
281
282 struct pcb stoppcbs[MAXCPU];
283
284 /*
285 * Local data and functions.
286 */
287
288 static u_int boot_address;
289 static u_int base_memory;
290 static int mp_finish;
291
292 static int search_for_sig(u_int32_t target, int count);
293 static void mp_enable(u_int boot_addr);
294
295 static int mptable_probe(void);
296 static void mptable_hyperthread_fixup(u_int id_mask);
297 static void mptable_pass1(struct mptable_pos *);
298 static int mptable_pass2(struct mptable_pos *);
299 static void default_mp_table(int type);
300 static void fix_mp_table(void);
301 static void mptable_map(struct mptable_pos *, vm_paddr_t);
302 static void mptable_unmap(struct mptable_pos *);
303 #ifdef APIC_IO
304 static void setup_apic_irq_mapping(void);
305 static int apic_int_is_bus_type(int intr, int bus_type);
306 #endif
307 static int start_all_aps(u_int boot_addr);
308 static void install_ap_tramp(u_int boot_addr);
309 static int start_ap(struct mdglobaldata *gd, u_int boot_addr);
310
311 static cpumask_t smp_startup_mask = 1; /* which cpus have been started */
312 cpumask_t smp_active_mask = 1; /* which cpus are ready for IPIs etc? */
313 SYSCTL_INT(_machdep, OID_AUTO, smp_active, CTLFLAG_RD, &smp_active_mask, 0, "");
314
315 /*
316 * Calculate usable address in base memory for AP trampoline code.
317 */
318 u_int
319 mp_bootaddress(u_int basemem)
320 {
321 POSTCODE(MP_BOOTADDRESS_POST);
322
323 base_memory = basemem;
324
325 boot_address = base_memory & ~0xfff; /* round down to 4k boundary */
326 if ((base_memory - boot_address) < bootMP_size)
327 boot_address -= 4096; /* not enough, lower by 4k */
328
329 return boot_address;
330 }
331
332
333 /*
334 * Look for an Intel MP spec table (ie, SMP capable hardware).
335 */
336 static int
337 mptable_probe(void)
338 {
339 int x;
340 u_int32_t target;
341
342 /*
343 * Make sure our SMPpt[] page table is big enough to hold all the
344 * mappings we need.
345 */
346 KKASSERT(IO_MAPPING_START_INDEX < NPTEPG - 2);
347
348 POSTCODE(MP_PROBE_POST);
349
350 /* see if EBDA exists */
351 if (ebda_addr != 0) {
352 /* search first 1K of EBDA */
353 target = (u_int32_t)ebda_addr;
354 if ((x = search_for_sig(target, 1024 / 4)) > 0)
355 return x;
356 } else {
357 /* last 1K of base memory, effective 'top of base' passed in */
358 target = (u_int32_t)(base_memory - 0x400);
359 if ((x = search_for_sig(target, 1024 / 4)) > 0)
360 return x;
361 }
362
363 /* search the BIOS */
364 target = (u_int32_t)BIOS_BASE;
365 if ((x = search_for_sig(target, BIOS_COUNT)) > 0)
366 return x;
367
368 /* nothing found */
369 return 0;
370 }
371
372
373 /*
374 * Startup the SMP processors.
375 */
376 void
377 mp_start(void)
378 {
379 POSTCODE(MP_START_POST);
380 mp_enable(boot_address);
381 }
382
383
384 /*
385 * Print various information about the SMP system hardware and setup.
386 */
387 void
388 mp_announce(void)
389 {
390 int x;
391
392 POSTCODE(MP_ANNOUNCE_POST);
393
394 kprintf("DragonFly/MP: Multiprocessor motherboard\n");
395 kprintf(" cpu0 (BSP): apic id: %2d", CPU_TO_ID(0));
396 kprintf(", version: 0x%08x", cpu_apic_versions[0]);
397 kprintf(", at 0x%08x\n", cpu_apic_address);
398 for (x = 1; x <= mp_naps; ++x) {
399 kprintf(" cpu%d (AP): apic id: %2d", x, CPU_TO_ID(x));
400 kprintf(", version: 0x%08x", cpu_apic_versions[x]);
401 kprintf(", at 0x%08x\n", cpu_apic_address);
402 }
403
404 #if defined(APIC_IO)
405 for (x = 0; x < mp_napics; ++x) {
406 kprintf(" io%d (APIC): apic id: %2d", x, IO_TO_ID(x));
407 kprintf(", version: 0x%08x", io_apic_versions[x]);
408 kprintf(", at 0x%08x\n", io_apic_address[x]);
409 }
410 #else
411 kprintf(" Warning: APIC I/O disabled\n");
412 #endif /* APIC_IO */
413 }
414
415 /*
416 * AP cpu's call this to sync up protected mode.
417 *
418 * WARNING! We must ensure that the cpu is sufficiently initialized to
419 * be able to use to the FP for our optimized bzero/bcopy code before
420 * we enter more mainstream C code.
421 *
422 * WARNING! %fs is not set up on entry. This routine sets up %fs.
423 */
424 void
425 init_secondary(void)
426 {
427 int gsel_tss;
428 int x, myid = bootAP;
429 u_int cr0;
430 struct mdglobaldata *md;
431 struct privatespace *ps;
432
433 ps = &CPU_prvspace[myid];
434
435 gdt_segs[GPRIV_SEL].ssd_base = (int)ps;
436 gdt_segs[GPROC0_SEL].ssd_base =
437 (int) &ps->mdglobaldata.gd_common_tss;
438 ps->mdglobaldata.mi.gd_prvspace = ps;
439
440 for (x = 0; x < NGDT; x++) {
441 ssdtosd(&gdt_segs[x], &gdt[myid * NGDT + x].sd);
442 }
443
444 r_gdt.rd_limit = NGDT * sizeof(gdt[0]) - 1;
445 r_gdt.rd_base = (int) &gdt[myid * NGDT];
446 lgdt(&r_gdt); /* does magic intra-segment return */
447
448 lidt(&r_idt);
449
450 lldt(_default_ldt);
451 mdcpu->gd_currentldt = _default_ldt;
452
453 gsel_tss = GSEL(GPROC0_SEL, SEL_KPL);
454 gdt[myid * NGDT + GPROC0_SEL].sd.sd_type = SDT_SYS386TSS;
455
456 md = mdcpu; /* loaded through %fs:0 (mdglobaldata.mi.gd_prvspace)*/
457
458 md->gd_common_tss.tss_esp0 = 0; /* not used until after switch */
459 md->gd_common_tss.tss_ss0 = GSEL(GDATA_SEL, SEL_KPL);
460 md->gd_common_tss.tss_ioopt = (sizeof md->gd_common_tss) << 16;
461 md->gd_tss_gdt = &gdt[myid * NGDT + GPROC0_SEL].sd;
462 md->gd_common_tssd = *md->gd_tss_gdt;
463 ltr(gsel_tss);
464
465 /*
466 * Set to a known state:
467 * Set by mpboot.s: CR0_PG, CR0_PE
468 * Set by cpu_setregs: CR0_NE, CR0_MP, CR0_TS, CR0_WP, CR0_AM
469 */
470 cr0 = rcr0();
471 cr0 &= ~(CR0_CD | CR0_NW | CR0_EM);
472 load_cr0(cr0);
473 pmap_set_opt(); /* PSE/4MB pages, etc */
474
475 /* set up CPU registers and state */
476 cpu_setregs();
477
478 /* set up FPU state on the AP */
479 npxinit(__INITIAL_NPXCW__);
480
481 /* set up SSE registers */
482 enable_sse();
483 }
484
485 /*******************************************************************
486 * local functions and data
487 */
488
489 /*
490 * start the SMP system
491 */
492 static void
493 mp_enable(u_int boot_addr)
494 {
495 int x;
496 #if defined(APIC_IO)
497 int apic;
498 u_int ux;
499 #endif /* APIC_IO */
500 vm_paddr_t mpfps_paddr;
501 struct mptable_pos mpt;
502
503 POSTCODE(MP_ENABLE_POST);
504
505 mpfps_paddr = mptable_probe();
506 if (mpfps_paddr == 0)
507 panic("mp_enable: mptable_probe failed\n");
508
509 mptable_map(&mpt, mpfps_paddr);
510
511 /*
512 * We can safely map physical memory into SMPpt after
513 * mptable_pass1() completes.
514 */
515 mptable_pass1(&mpt);
516
517 if (cpu_apic_address == 0)
518 panic("mp_enable: no local apic!\n");
519
520 /* examine the MP table for needed info, uses physical addresses */
521 x = mptable_pass2(&mpt);
522
523 mptable_unmap(&mpt);
524
525 /* local apic is mapped on last page */
526 SMPpt[NPTEPG - 1] = (pt_entry_t)(PG_V | PG_RW | PG_N |
527 pmap_get_pgeflag() | (cpu_apic_address & PG_FRAME));
528
529 /* can't process default configs till the CPU APIC is pmapped */
530 if (x)
531 default_mp_table(x);
532
533 /* post scan cleanup */
534 fix_mp_table();
535
536 #if defined(APIC_IO)
537
538 setup_apic_irq_mapping();
539
540 /* fill the LOGICAL io_apic_versions table */
541 for (apic = 0; apic < mp_napics; ++apic) {
542 ux = io_apic_read(apic, IOAPIC_VER);
543 io_apic_versions[apic] = ux;
544 io_apic_set_id(apic, IO_TO_ID(apic));
545 }
546
547 /* program each IO APIC in the system */
548 for (apic = 0; apic < mp_napics; ++apic)
549 if (io_apic_setup(apic) < 0)
550 panic("IO APIC setup failure");
551
552 #endif /* APIC_IO */
553
554 /*
555 * These are required for SMP operation
556 */
557
558 /* install a 'Spurious INTerrupt' vector */
559 setidt(XSPURIOUSINT_OFFSET, Xspuriousint,
560 SDT_SYS386IGT, SEL_KPL, GSEL(GCODE_SEL, SEL_KPL));
561
562 /* install an inter-CPU IPI for TLB invalidation */
563 setidt(XINVLTLB_OFFSET, Xinvltlb,
564 SDT_SYS386IGT, SEL_KPL, GSEL(GCODE_SEL, SEL_KPL));
565
566 /* install an inter-CPU IPI for IPIQ messaging */
567 setidt(XIPIQ_OFFSET, Xipiq,
568 SDT_SYS386IGT, SEL_KPL, GSEL(GCODE_SEL, SEL_KPL));
569
570 /* install a timer vector */
571 setidt(XTIMER_OFFSET, Xtimer,
572 SDT_SYS386IGT, SEL_KPL, GSEL(GCODE_SEL, SEL_KPL));
573
574 /* install an inter-CPU IPI for CPU stop/restart */
575 setidt(XCPUSTOP_OFFSET, Xcpustop,
576 SDT_SYS386IGT, SEL_KPL, GSEL(GCODE_SEL, SEL_KPL));
577
578 /* start each Application Processor */
579 start_all_aps(boot_addr);
580 }
581
582
583 /*
584 * look for the MP spec signature
585 */
586
587 /* string defined by the Intel MP Spec as identifying the MP table */
588 #define MP_SIG 0x5f504d5f /* _MP_ */
589 #define NEXT(X) ((X) += 4)
590 static int
591 search_for_sig(u_int32_t target, int count)
592 {
593 vm_size_t map_size;
594 u_int32_t *addr;
595 int x, ret;
596
597 KKASSERT(target != 0);
598
599 map_size = count * sizeof(u_int32_t);
600 addr = pmap_mapdev((vm_paddr_t)target, map_size);
601
602 ret = 0;
603 for (x = 0; x < count; NEXT(x)) {
604 if (addr[x] == MP_SIG) {
605 /* make array index a byte index */
606 ret = target + (x * sizeof(u_int32_t));
607 break;
608 }
609 }
610
611 pmap_unmapdev((vm_offset_t)addr, map_size);
612 return ret;
613 }
614
615
616 static basetable_entry basetable_entry_types[] =
617 {
618 {0, 20, "Processor"},
619 {1, 8, "Bus"},
620 {2, 8, "I/O APIC"},
621 {3, 8, "I/O INT"},
622 {4, 8, "Local INT"}
623 };
624
625 typedef struct BUSDATA {
626 u_char bus_id;
627 enum busTypes bus_type;
628 } bus_datum;
629
630 typedef struct INTDATA {
631 u_char int_type;
632 u_short int_flags;
633 u_char src_bus_id;
634 u_char src_bus_irq;
635 u_char dst_apic_id;
636 u_char dst_apic_int;
637 u_char int_vector;
638 } io_int, local_int;
639
640 typedef struct BUSTYPENAME {
641 u_char type;
642 char name[7];
643 } bus_type_name;
644
645 static bus_type_name bus_type_table[] =
646 {
647 {CBUS, "CBUS"},
648 {CBUSII, "CBUSII"},
649 {EISA, "EISA"},
650 {MCA, "MCA"},
651 {UNKNOWN_BUSTYPE, "---"},
652 {ISA, "ISA"},
653 {MCA, "MCA"},
654 {UNKNOWN_BUSTYPE, "---"},
655 {UNKNOWN_BUSTYPE, "---"},
656 {UNKNOWN_BUSTYPE, "---"},
657 {UNKNOWN_BUSTYPE, "---"},
658 {UNKNOWN_BUSTYPE, "---"},
659 {PCI, "PCI"},
660 {UNKNOWN_BUSTYPE, "---"},
661 {UNKNOWN_BUSTYPE, "---"},
662 {UNKNOWN_BUSTYPE, "---"},
663 {UNKNOWN_BUSTYPE, "---"},
664 {XPRESS, "XPRESS"},
665 {UNKNOWN_BUSTYPE, "---"}
666 };
667 /* from MP spec v1.4, table 5-1 */
668 static int default_data[7][5] =
669 {
670 /* nbus, id0, type0, id1, type1 */
671 {1, 0, ISA, 255, 255},
672 {1, 0, EISA, 255, 255},
673 {1, 0, EISA, 255, 255},
674 {1, 0, MCA, 255, 255},
675 {2, 0, ISA, 1, PCI},
676 {2, 0, EISA, 1, PCI},
677 {2, 0, MCA, 1, PCI}
678 };
679
680
681 /* the bus data */
682 static bus_datum *bus_data;
683
684 #ifdef APIC_IO
685 /* the IO INT data, one entry per possible APIC INTerrupt */
686 static io_int *io_apic_ints;
687 static int nintrs;
688 #endif
689
690 static int processor_entry (proc_entry_ptr entry, int cpu);
691 static int bus_entry (bus_entry_ptr entry, int bus);
692 #ifdef APIC_IO
693 static int io_apic_entry (io_apic_entry_ptr entry, int apic);
694 static int int_entry (int_entry_ptr entry, int intr);
695 #endif
696 static int lookup_bus_type (char *name);
697
698
699 /*
700 * 1st pass on motherboard's Intel MP specification table.
701 *
702 * initializes:
703 * ncpus = 1
704 *
705 * determines:
706 * cpu_apic_address (common to all CPUs)
707 * io_apic_address[N]
708 * mp_naps
709 * mp_nbusses
710 * mp_napics
711 * nintrs
712 */
713 static void
714 mptable_pass1(struct mptable_pos *mpt)
715 {
716 #ifdef APIC_IO
717 int x;
718 #endif
719 mpfps_t fps;
720 mpcth_t cth;
721 int totalSize;
722 void* position;
723 int count;
724 int type;
725 u_int id_mask;
726
727 POSTCODE(MPTABLE_PASS1_POST);
728
729 fps = mpt->mp_fps;
730 KKASSERT(fps != NULL);
731
732 #ifdef APIC_IO
733 /* clear various tables */
734 for (x = 0; x < NAPICID; ++x) {
735 io_apic_address[x] = ~0; /* IO APIC address table */
736 }
737 #endif
738
739 /* init everything to empty */
740 mp_naps = 0;
741 mp_nbusses = 0;
742 #ifdef APIC_IO
743 mp_napics = 0;
744 nintrs = 0;
745 #endif
746 id_mask = 0;
747
748 /* check for use of 'default' configuration */
749 if (fps->mpfb1 != 0) {
750 /* use default addresses */
751 cpu_apic_address = DEFAULT_APIC_BASE;
752 #ifdef APIC_IO
753 io_apic_address[0] = DEFAULT_IO_APIC_BASE;
754 #endif
755
756 /* fill in with defaults */
757 mp_naps = 2; /* includes BSP */
758 mp_nbusses = default_data[fps->mpfb1 - 1][0];
759 #if defined(APIC_IO)
760 mp_napics = 1;
761 nintrs = 16;
762 #endif /* APIC_IO */
763 }
764 else {
765 cth = mpt->mp_cth;
766 if (cth == NULL)
767 panic("MP Configuration Table Header MISSING!");
768
769 cpu_apic_address = (vm_offset_t) cth->apic_address;
770
771 /* walk the table, recording info of interest */
772 totalSize = cth->base_table_length - sizeof(struct MPCTH);
773 position = (u_char *) cth + sizeof(struct MPCTH);
774 count = cth->entry_count;
775
776 while (count--) {
777 switch (type = *(u_char *) position) {
778 case 0: /* processor_entry */
779 if (((proc_entry_ptr)position)->cpu_flags
780 & PROCENTRY_FLAG_EN) {
781 ++mp_naps;
782 id_mask |= 1 <<
783 ((proc_entry_ptr)position)->apic_id;
784 }
785 break;
786 case 1: /* bus_entry */
787 ++mp_nbusses;
788 break;
789 case 2: /* io_apic_entry */
790 #ifdef APIC_IO
791 if (((io_apic_entry_ptr)position)->apic_flags
792 & IOAPICENTRY_FLAG_EN)
793 io_apic_address[mp_napics++] =
794 (vm_offset_t)((io_apic_entry_ptr)
795 position)->apic_address;
796 #endif
797 break;
798 case 3: /* int_entry */
799 #ifdef APIC_IO
800 ++nintrs;
801 #endif
802 break;
803 case 4: /* int_entry */
804 break;
805 default:
806 panic("mpfps Base Table HOSED!");
807 /* NOTREACHED */
808 }
809
810 totalSize -= basetable_entry_types[type].length;
811 position = (uint8_t *)position +
812 basetable_entry_types[type].length;
813 }
814 }
815
816 /* qualify the numbers */
817 if (mp_naps > MAXCPU) {
818 kprintf("Warning: only using %d of %d available CPUs!\n",
819 MAXCPU, mp_naps);
820 mp_naps = MAXCPU;
821 }
822
823 /* See if we need to fixup HT logical CPUs. */
824 mptable_hyperthread_fixup(id_mask);
825
826 --mp_naps; /* subtract the BSP */
827 }
828
829
830 /*
831 * 2nd pass on motherboard's Intel MP specification table.
832 *
833 * sets:
834 * boot_cpu_id
835 * ID_TO_IO(N), phy APIC ID to log CPU/IO table
836 * CPU_TO_ID(N), logical CPU to APIC ID table
837 * IO_TO_ID(N), logical IO to APIC ID table
838 * bus_data[N]
839 * io_apic_ints[N]
840 */
841 static int
842 mptable_pass2(struct mptable_pos *mpt)
843 {
844 struct PROCENTRY proc;
845 int x;
846 mpfps_t fps;
847 mpcth_t cth;
848 int totalSize;
849 void* position;
850 int count;
851 int type;
852 int apic, bus, cpu, intr;
853 int i;
854
855 POSTCODE(MPTABLE_PASS2_POST);
856
857 fps = mpt->mp_fps;
858 KKASSERT(fps != NULL);
859
860 /* Initialize fake proc entry for use with HT fixup. */
861 bzero(&proc, sizeof(proc));
862 proc.type = 0;
863 proc.cpu_flags = PROCENTRY_FLAG_EN;
864
865 #ifdef APIC_IO
866 MALLOC(io_apic_versions, u_int32_t *, sizeof(u_int32_t) * mp_napics,
867 M_DEVBUF, M_WAITOK);
868 MALLOC(ioapic, volatile ioapic_t **, sizeof(ioapic_t *) * mp_napics,
869 M_DEVBUF, M_WAITOK | M_ZERO);
870 MALLOC(io_apic_ints, io_int *, sizeof(io_int) * (nintrs + FIXUP_EXTRA_APIC_INTS),
871 M_DEVBUF, M_WAITOK);
872 #endif
873 MALLOC(bus_data, bus_datum *, sizeof(bus_datum) * mp_nbusses,
874 M_DEVBUF, M_WAITOK);
875
876 #ifdef APIC_IO
877 for (i = 0; i < mp_napics; i++) {
878 ioapic[i] = permanent_io_mapping(io_apic_address[i]);
879 }
880 #endif
881
882 /* clear various tables */
883 for (x = 0; x < NAPICID; ++x) {
884 CPU_TO_ID(x) = -1; /* logical CPU to APIC ID table */
885 #ifdef APIC_IO
886 ID_TO_IO(x) = -1; /* phy APIC ID to log CPU/IO table */
887 IO_TO_ID(x) = -1; /* logical IO to APIC ID table */
888 #endif
889 }
890
891 /* clear bus data table */
892 for (x = 0; x < mp_nbusses; ++x)
893 bus_data[x].bus_id = 0xff;
894
895 #ifdef APIC_IO
896 /* clear IO APIC INT table */
897 for (x = 0; x < (nintrs + 1); ++x) {
898 io_apic_ints[x].int_type = 0xff;
899 io_apic_ints[x].int_vector = 0xff;
900 }
901 #endif
902
903 /* setup the cpu/apic mapping arrays */
904 boot_cpu_id = -1;
905
906 /* record whether PIC or virtual-wire mode */
907 machintr_setvar_simple(MACHINTR_VAR_IMCR_PRESENT, fps->mpfb2 & 0x80);
908
909 /* check for use of 'default' configuration */
910 if (fps->mpfb1 != 0)
911 return fps->mpfb1; /* return default configuration type */
912
913 cth = mpt->mp_cth;
914 if (cth == NULL)
915 panic("MP Configuration Table Header MISSING!");
916
917 /* walk the table, recording info of interest */
918 totalSize = cth->base_table_length - sizeof(struct MPCTH);
919 position = (u_char *) cth + sizeof(struct MPCTH);
920 count = cth->entry_count;
921 apic = bus = intr = 0;
922 cpu = 1; /* pre-count the BSP */
923
924 while (count--) {
925 switch (type = *(u_char *) position) {
926 case 0:
927 if (processor_entry(position, cpu))
928 ++cpu;
929
930 if (need_hyperthreading_fixup) {
931 /*
932 * Create fake mptable processor entries
933 * and feed them to processor_entry() to
934 * enumerate the logical CPUs.
935 */
936 proc.apic_id = ((proc_entry_ptr)position)->apic_id;
937 for (i = 1; i < logical_cpus; i++) {
938 proc.apic_id++;
939 processor_entry(&proc, cpu);
940 logical_cpus_mask |= (1 << cpu);
941 cpu++;
942 }
943 }
944 break;
945 case 1:
946 if (bus_entry(position, bus))
947 ++bus;
948 break;
949 case 2:
950 #ifdef APIC_IO
951 if (io_apic_entry(position, apic))
952 ++apic;
953 #endif
954 break;
955 case 3:
956 #ifdef APIC_IO
957 if (int_entry(position, intr))
958 ++intr;
959 #endif
960 break;
961 case 4:
962 /* int_entry(position); */
963 break;
964 default:
965 panic("mpfps Base Table HOSED!");
966 /* NOTREACHED */
967 }
968
969 totalSize -= basetable_entry_types[type].length;
970 position = (uint8_t *)position + basetable_entry_types[type].length;
971 }
972
973 if (boot_cpu_id == -1)
974 panic("NO BSP found!");
975
976 /* report fact that its NOT a default configuration */
977 return 0;
978 }
979
980 /*
981 * Check if we should perform a hyperthreading "fix-up" to
982 * enumerate any logical CPU's that aren't already listed
983 * in the table.
984 *
985 * XXX: We assume that all of the physical CPUs in the
986 * system have the same number of logical CPUs.
987 *
988 * XXX: We assume that APIC ID's are allocated such that
989 * the APIC ID's for a physical processor are aligned
990 * with the number of logical CPU's in the processor.
991 */
992 static void
993 mptable_hyperthread_fixup(u_int id_mask)
994 {
995 u_int i, id;
996
997 /* Nothing to do if there is no HTT support. */
998 if ((cpu_feature & CPUID_HTT) == 0)
999 return;
1000 logical_cpus = (cpu_procinfo & CPUID_HTT_CORES) >> 16;
1001 if (logical_cpus <= 1)
1002 return;
1003
1004 /*
1005 * For each APIC ID of a CPU that is set in the mask,
1006 * scan the other candidate APIC ID's for this
1007 * physical processor. If any of those ID's are
1008 * already in the table, then kill the fixup.
1009 */
1010 for (id = 0; id <= MAXCPU; id++) {
1011 if ((id_mask & 1 << id) == 0)
1012 continue;
1013 /* First, make sure we are on a logical_cpus boundary. */
1014 if (id % logical_cpus != 0)
1015 return;
1016 for (i = id + 1; i < id + logical_cpus; i++)
1017 if ((id_mask & 1 << i) != 0)
1018 return;
1019 }
1020
1021 /*
1022 * Ok, the ID's checked out, so enable the fixup. We have to fixup
1023 * mp_naps right now.
1024 */
1025 need_hyperthreading_fixup = 1;
1026 mp_naps *= logical_cpus;
1027 }
1028
1029 static void
1030 mptable_map(struct mptable_pos *mpt, vm_paddr_t mpfps_paddr)
1031 {
1032 mpfps_t fps = NULL;
1033 mpcth_t cth = NULL;
1034 vm_size_t cth_mapsz = 0;
1035
1036 fps = pmap_mapdev(mpfps_paddr, sizeof(*fps));
1037 if (fps->pap != 0) {
1038 /*
1039 * Map configuration table header to get
1040 * the base table size
1041 */
1042 cth = pmap_mapdev(fps->pap, sizeof(*cth));
1043 cth_mapsz = cth->base_table_length;
1044 pmap_unmapdev((vm_offset_t)cth, sizeof(*cth));
1045
1046 /*
1047 * Map the base table
1048 */
1049 cth = pmap_mapdev(fps->pap, cth_mapsz);
1050 }
1051
1052 mpt->mp_fps = fps;
1053 mpt->mp_cth = cth;
1054 mpt->mp_cth_mapsz = cth_mapsz;
1055 }
1056
1057 static void
1058 mptable_unmap(struct mptable_pos *mpt)
1059 {
1060 if (mpt->mp_cth != NULL) {
1061 pmap_unmapdev((vm_offset_t)mpt->mp_cth, mpt->mp_cth_mapsz);
1062 mpt->mp_cth = NULL;
1063 mpt->mp_cth_mapsz = 0;
1064 }
1065 if (mpt->mp_fps != NULL) {
1066 pmap_unmapdev((vm_offset_t)mpt->mp_fps, sizeof(*mpt->mp_fps));
1067 mpt->mp_fps = NULL;
1068 }
1069 }
1070
1071 #ifdef APIC_IO
1072
1073 void
1074 assign_apic_irq(int apic, int intpin, int irq)
1075 {
1076 int x;
1077
1078 if (int_to_apicintpin[irq].ioapic != -1)
1079 panic("assign_apic_irq: inconsistent table");
1080
1081 int_to_apicintpin[irq].ioapic = apic;
1082 int_to_apicintpin[irq].int_pin = intpin;
1083 int_to_apicintpin[irq].apic_address = ioapic[apic];
1084 int_to_apicintpin[irq].redirindex = IOAPIC_REDTBL + 2 * intpin;
1085
1086 for (x = 0; x < nintrs; x++) {
1087 if ((io_apic_ints[x].int_type == 0 ||
1088 io_apic_ints[x].int_type == 3) &&
1089 io_apic_ints[x].int_vector == 0xff &&
1090 io_apic_ints[x].dst_apic_id == IO_TO_ID(apic) &&
1091 io_apic_ints[x].dst_apic_int == intpin)
1092 io_apic_ints[x].int_vector = irq;
1093 }
1094 }
1095
1096 void
1097 revoke_apic_irq(int irq)
1098 {
1099 int x;
1100 int oldapic;
1101 int oldintpin;
1102
1103 if (int_to_apicintpin[irq].ioapic == -1)
1104 panic("revoke_apic_irq: inconsistent table");
1105
1106 oldapic = int_to_apicintpin[irq].ioapic;
1107 oldintpin = int_to_apicintpin[irq].int_pin;
1108
1109 int_to_apicintpin[irq].ioapic = -1;
1110 int_to_apicintpin[irq].int_pin = 0;
1111 int_to_apicintpin[irq].apic_address = NULL;
1112 int_to_apicintpin[irq].redirindex = 0;
1113
1114 for (x = 0; x < nintrs; x++) {
1115 if ((io_apic_ints[x].int_type == 0 ||
1116 io_apic_ints[x].int_type == 3) &&
1117 io_apic_ints[x].int_vector != 0xff &&
1118 io_apic_ints[x].dst_apic_id == IO_TO_ID(oldapic) &&
1119 io_apic_ints[x].dst_apic_int == oldintpin)
1120 io_apic_ints[x].int_vector = 0xff;
1121 }
1122 }
1123
1124 /*
1125 * Allocate an IRQ
1126 */
1127 static void
1128 allocate_apic_irq(int intr)
1129 {
1130 int apic;
1131 int intpin;
1132 int irq;
1133
1134 if (io_apic_ints[intr].int_vector != 0xff)
1135 return; /* Interrupt handler already assigned */
1136
1137 if (io_apic_ints[intr].int_type != 0 &&
1138 (io_apic_ints[intr].int_type != 3 ||
1139 (io_apic_ints[intr].dst_apic_id == IO_TO_ID(0) &&
1140 io_apic_ints[intr].dst_apic_int == 0)))
1141 return; /* Not INT or ExtInt on != (0, 0) */
1142
1143 irq = 0;
1144 while (irq < APIC_INTMAPSIZE &&
1145 int_to_apicintpin[irq].ioapic != -1)
1146 irq++;
1147
1148 if (irq >= APIC_INTMAPSIZE)
1149 return; /* No free interrupt handlers */
1150
1151 apic = ID_TO_IO(io_apic_ints[intr].dst_apic_id);
1152 intpin = io_apic_ints[intr].dst_apic_int;
1153
1154 assign_apic_irq(apic, intpin, irq);
1155 io_apic_setup_intpin(apic, intpin);
1156 }
1157
1158
1159 static void
1160 swap_apic_id(int apic, int oldid, int newid)
1161 {
1162 int x;
1163 int oapic;
1164
1165
1166 if (oldid == newid)
1167 return; /* Nothing to do */
1168
1169 kprintf("Changing APIC ID for IO APIC #%d from %d to %d in MP table\n",
1170 apic, oldid, newid);
1171
1172 /* Swap physical APIC IDs in interrupt entries */
1173 for (x = 0; x < nintrs; x++) {
1174 if (io_apic_ints[x].dst_apic_id == oldid)
1175 io_apic_ints[x].dst_apic_id = newid;
1176 else if (io_apic_ints[x].dst_apic_id == newid)
1177 io_apic_ints[x].dst_apic_id = oldid;
1178 }
1179
1180 /* Swap physical APIC IDs in IO_TO_ID mappings */
1181 for (oapic = 0; oapic < mp_napics; oapic++)
1182 if (IO_TO_ID(oapic) == newid)
1183 break;
1184
1185 if (oapic < mp_napics) {
1186 kprintf("Changing APIC ID for IO APIC #%d from "
1187 "%d to %d in MP table\n",
1188 oapic, newid, oldid);
1189 IO_TO_ID(oapic) = oldid;
1190 }
1191 IO_TO_ID(apic) = newid;
1192 }
1193
1194
1195 static void
1196 fix_id_to_io_mapping(void)
1197 {
1198 int x;
1199
1200 for (x = 0; x < NAPICID; x++)
1201 ID_TO_IO(x) = -1;
1202
1203 for (x = 0; x <= mp_naps; x++)
1204 if (CPU_TO_ID(x) < NAPICID)
1205 ID_TO_IO(CPU_TO_ID(x)) = x;
1206
1207 for (x = 0; x < mp_napics; x++)
1208 if (IO_TO_ID(x) < NAPICID)
1209 ID_TO_IO(IO_TO_ID(x)) = x;
1210 }
1211
1212
1213 static int
1214 first_free_apic_id(void)
1215 {
1216 int freeid, x;
1217
1218 for (freeid = 0; freeid < NAPICID; freeid++) {
1219 for (x = 0; x <= mp_naps; x++)
1220 if (CPU_TO_ID(x) == freeid)
1221 break;
1222 if (x <= mp_naps)
1223 continue;
1224 for (x = 0; x < mp_napics; x++)
1225 if (IO_TO_ID(x) == freeid)
1226 break;
1227 if (x < mp_napics)
1228 continue;
1229 return freeid;
1230 }
1231 return freeid;
1232 }
1233
1234
1235 static int
1236 io_apic_id_acceptable(int apic, int id)
1237 {
1238 int cpu; /* Logical CPU number */
1239 int oapic; /* Logical IO APIC number for other IO APIC */
1240
1241 if (id >= NAPICID)
1242 return 0; /* Out of range */
1243
1244 for (cpu = 0; cpu <= mp_naps; cpu++)
1245 if (CPU_TO_ID(cpu) == id)
1246 return 0; /* Conflict with CPU */
1247
1248 for (oapic = 0; oapic < mp_napics && oapic < apic; oapic++)
1249 if (IO_TO_ID(oapic) == id)
1250 return 0; /* Conflict with other APIC */
1251
1252 return 1; /* ID is acceptable for IO APIC */
1253 }
1254
1255 static
1256 io_int *
1257 io_apic_find_int_entry(int apic, int pin)
1258 {
1259 int x;
1260
1261 /* search each of the possible INTerrupt sources */
1262 for (x = 0; x < nintrs; ++x) {
1263 if ((apic == ID_TO_IO(io_apic_ints[x].dst_apic_id)) &&
1264 (pin == io_apic_ints[x].dst_apic_int))
1265 return (&io_apic_ints[x]);
1266 }
1267 return NULL;
1268 }
1269
1270 #endif
1271
1272 /*
1273 * parse an Intel MP specification table
1274 */
1275 static void
1276 fix_mp_table(void)
1277 {
1278 int x;
1279 #ifdef APIC_IO
1280 int id;
1281 int apic; /* IO APIC unit number */
1282 int freeid; /* Free physical APIC ID */
1283 int physid; /* Current physical IO APIC ID */
1284 io_int *io14;
1285 #endif
1286 int bus_0 = 0; /* Stop GCC warning */
1287 int bus_pci = 0; /* Stop GCC warning */
1288 int num_pci_bus;
1289
1290 /*
1291 * Fix mis-numbering of the PCI bus and its INT entries if the BIOS
1292 * did it wrong. The MP spec says that when more than 1 PCI bus
1293 * exists the BIOS must begin with bus entries for the PCI bus and use
1294 * actual PCI bus numbering. This implies that when only 1 PCI bus
1295 * exists the BIOS can choose to ignore this ordering, and indeed many
1296 * MP motherboards do ignore it. This causes a problem when the PCI
1297 * sub-system makes requests of the MP sub-system based on PCI bus
1298 * numbers. So here we look for the situation and renumber the
1299 * busses and associated INTs in an effort to "make it right".
1300 */
1301
1302 /* find bus 0, PCI bus, count the number of PCI busses */
1303 for (num_pci_bus = 0, x = 0; x < mp_nbusses; ++x) {
1304 if (bus_data[x].bus_id == 0) {
1305 bus_0 = x;
1306 }
1307 if (bus_data[x].bus_type == PCI) {
1308 ++num_pci_bus;
1309 bus_pci = x;
1310 }
1311 }
1312 /*
1313 * bus_0 == slot of bus with ID of 0
1314 * bus_pci == slot of last PCI bus encountered
1315 */
1316
1317 /* check the 1 PCI bus case for sanity */
1318 /* if it is number 0 all is well */
1319 if (num_pci_bus == 1 &&
1320 bus_data[bus_pci].bus_id != 0) {
1321
1322 /* mis-numbered, swap with whichever bus uses slot 0 */
1323
1324 /* swap the bus entry types */
1325 bus_data[bus_pci].bus_type = bus_data[bus_0].bus_type;
1326 bus_data[bus_0].bus_type = PCI;
1327
1328 #ifdef APIC_IO
1329 /* swap each relavant INTerrupt entry */
1330 id = bus_data[bus_pci].bus_id;
1331 for (x = 0; x < nintrs; ++x) {
1332 if (io_apic_ints[x].src_bus_id == id) {
1333 io_apic_ints[x].src_bus_id = 0;
1334 }
1335 else if (io_apic_ints[x].src_bus_id == 0) {
1336 io_apic_ints[x].src_bus_id = id;
1337 }
1338 }
1339 #endif
1340 }
1341
1342 #ifdef APIC_IO
1343 /* Assign IO APIC IDs.
1344 *
1345 * First try the existing ID. If a conflict is detected, try
1346 * the ID in the MP table. If a conflict is still detected, find
1347 * a free id.
1348 *
1349 * We cannot use the ID_TO_IO table before all conflicts has been
1350 * resolved and the table has been corrected.
1351 */
1352 for (apic = 0; apic < mp_napics; ++apic) { /* For all IO APICs */
1353
1354 /* First try to use the value set by the BIOS */
1355 physid = io_apic_get_id(apic);
1356 if (io_apic_id_acceptable(apic, physid)) {
1357 if (IO_TO_ID(apic) != physid)
1358 swap_apic_id(apic, IO_TO_ID(apic), physid);
1359 continue;
1360 }
1361
1362 /* Then check if the value in the MP table is acceptable */
1363 if (io_apic_id_acceptable(apic, IO_TO_ID(apic)))
1364 continue;
1365
1366 /* Last resort, find a free APIC ID and use it */
1367 freeid = first_free_apic_id();
1368 if (freeid >= NAPICID)
1369 panic("No free physical APIC IDs found");
1370
1371 if (io_apic_id_acceptable(apic, freeid)) {
1372 swap_apic_id(apic, IO_TO_ID(apic), freeid);
1373 continue;
1374 }
1375 panic("Free physical APIC ID not usable");
1376 }
1377 fix_id_to_io_mapping();
1378 #endif
1379
1380 #ifdef APIC_IO
1381 /* detect and fix broken Compaq MP table */
1382 if (apic_int_type(0, 0) == -1) {
1383 kprintf("APIC_IO: MP table broken: 8259->APIC entry missing!\n");
1384 io_apic_ints[nintrs].int_type = 3; /* ExtInt */
1385 io_apic_ints[nintrs].int_vector = 0xff; /* Unassigned */
1386 /* XXX fixme, set src bus id etc, but it doesn't seem to hurt */
1387 io_apic_ints[nintrs].dst_apic_id = IO_TO_ID(0);
1388 io_apic_ints[nintrs].dst_apic_int = 0; /* Pin 0 */
1389 nintrs++;
1390 } else if (apic_int_type(0, 0) == 0) {
1391 kprintf("APIC_IO: MP table broken: ExtINT entry corrupt!\n");
1392 for (x = 0; x < nintrs; ++x)
1393 if ((0 == ID_TO_IO(io_apic_ints[x].dst_apic_id)) &&
1394 (0 == io_apic_ints[x].dst_apic_int)) {
1395 io_apic_ints[x].int_type = 3;
1396 io_apic_ints[x].int_vector = 0xff;
1397 break;
1398 }
1399 }
1400
1401 /*
1402 * Fix missing IRQ 15 when IRQ 14 is an ISA interrupt. IDE
1403 * controllers universally come in pairs. If IRQ 14 is specified
1404 * as an ISA interrupt, then IRQ 15 had better be too.
1405 *
1406 * [ Shuttle XPC / AMD Athlon X2 ]
1407 * The MPTable is missing an entry for IRQ 15. Note that the
1408 * ACPI table has an entry for both 14 and 15.
1409 */
1410 if (apic_int_type(0, 14) == 0 && apic_int_type(0, 15) == -1) {
1411 kprintf("APIC_IO: MP table broken: IRQ 15 not ISA when IRQ 14 is!\n");
1412 io14 = io_apic_find_int_entry(0, 14);
1413 io_apic_ints[nintrs] = *io14;
1414 io_apic_ints[nintrs].src_bus_irq = 15;
1415 io_apic_ints[nintrs].dst_apic_int = 15;
1416 nintrs++;
1417 }
1418 #endif
1419 }
1420
1421 #ifdef APIC_IO
1422
1423 /* Assign low level interrupt handlers */
1424 static void
1425 setup_apic_irq_mapping(void)
1426 {
1427 int x;
1428 int int_vector;
1429
1430 /* Clear array */
1431 for (x = 0; x < APIC_INTMAPSIZE; x++) {
1432 int_to_apicintpin[x].ioapic = -1;
1433 int_to_apicintpin[x].int_pin = 0;
1434 int_to_apicintpin[x].apic_address = NULL;
1435 int_to_apicintpin[x].redirindex = 0;
1436 }
1437
1438 /* First assign ISA/EISA interrupts */
1439 for (x = 0; x < nintrs; x++) {
1440 int_vector = io_apic_ints[x].src_bus_irq;
1441 if (int_vector < APIC_INTMAPSIZE &&
1442 io_apic_ints[x].int_vector == 0xff &&
1443 int_to_apicintpin[int_vector].ioapic == -1 &&
1444 (apic_int_is_bus_type(x, ISA) ||
1445 apic_int_is_bus_type(x, EISA)) &&
1446 io_apic_ints[x].int_type == 0) {
1447 assign_apic_irq(ID_TO_IO(io_apic_ints[x].dst_apic_id),
1448 io_apic_ints[x].dst_apic_int,
1449 int_vector);
1450 }
1451 }
1452
1453 /* Assign ExtInt entry if no ISA/EISA interrupt 0 entry */
1454 for (x = 0; x < nintrs; x++) {
1455 if (io_apic_ints[x].dst_apic_int == 0 &&
1456 io_apic_ints[x].dst_apic_id == IO_TO_ID(0) &&
1457 io_apic_ints[x].int_vector == 0xff &&
1458 int_to_apicintpin[0].ioapic == -1 &&
1459 io_apic_ints[x].int_type == 3) {
1460 assign_apic_irq(0, 0, 0);
1461 break;
1462 }
1463 }
1464 /* PCI interrupt assignment is deferred */
1465 }
1466
1467 #endif
1468
1469 static int
1470 processor_entry(proc_entry_ptr entry, int cpu)
1471 {
1472 /* check for usability */
1473 if (!(entry->cpu_flags & PROCENTRY_FLAG_EN))
1474 return 0;
1475
1476 if(entry->apic_id >= NAPICID)
1477 panic("CPU APIC ID out of range (0..%d)", NAPICID - 1);
1478 /* check for BSP flag */
1479 if (entry->cpu_flags & PROCENTRY_FLAG_BP) {
1480 boot_cpu_id = entry->apic_id;
1481 CPU_TO_ID(0) = entry->apic_id;
1482 ID_TO_CPU(entry->apic_id) = 0;
1483 return 0; /* its already been counted */
1484 }
1485
1486 /* add another AP to list, if less than max number of CPUs */
1487 else if (cpu < MAXCPU) {
1488 CPU_TO_ID(cpu) = entry->apic_id;
1489 ID_TO_CPU(entry->apic_id) = cpu;
1490 return 1;
1491 }
1492
1493 return 0;
1494 }
1495
1496
1497 static int
1498 bus_entry(bus_entry_ptr entry, int bus)
1499 {
1500 int x;
1501 char c, name[8];
1502
1503 /* encode the name into an index */
1504 for (x = 0; x < 6; ++x) {
1505 if ((c = entry->bus_type[x]) == ' ')
1506 break;
1507 name[x] = c;
1508 }
1509 name[x] = '\0';
1510
1511 if ((x = lookup_bus_type(name)) == UNKNOWN_BUSTYPE)
1512 panic("unknown bus type: '%s'", name);
1513
1514 bus_data[bus].bus_id = entry->bus_id;
1515 bus_data[bus].bus_type = x;
1516
1517 return 1;
1518 }
1519
1520 #ifdef APIC_IO
1521
1522 static int
1523 io_apic_entry(io_apic_entry_ptr entry, int apic)
1524 {
1525 if (!(entry->apic_flags & IOAPICENTRY_FLAG_EN))
1526 return 0;
1527
1528 IO_TO_ID(apic) = entry->apic_id;
1529 if (entry->apic_id < NAPICID)
1530 ID_TO_IO(entry->apic_id) = apic;
1531
1532 return 1;
1533 }
1534
1535 #endif
1536
1537 static int
1538 lookup_bus_type(char *name)
1539 {
1540 int x;
1541
1542 for (x = 0; x < MAX_BUSTYPE; ++x)
1543 if (strcmp(bus_type_table[x].name, name) == 0)
1544 return bus_type_table[x].type;
1545
1546 return UNKNOWN_BUSTYPE;
1547 }
1548
1549 #ifdef APIC_IO
1550
1551 static int
1552 int_entry(int_entry_ptr entry, int intr)
1553 {
1554 int apic;
1555
1556 io_apic_ints[intr].int_type = entry->int_type;
1557 io_apic_ints[intr].int_flags = entry->int_flags;
1558 io_apic_ints[intr].src_bus_id = entry->src_bus_id;
1559 io_apic_ints[intr].src_bus_irq = entry->src_bus_irq;
1560 if (entry->dst_apic_id == 255) {
1561 /* This signal goes to all IO APICS. Select an IO APIC
1562 with sufficient number of interrupt pins */
1563 for (apic = 0; apic < mp_napics; apic++)
1564 if (((io_apic_read(apic, IOAPIC_VER) &
1565 IOART_VER_MAXREDIR) >> MAXREDIRSHIFT) >=
1566 entry->dst_apic_int)
1567 break;
1568 if (apic < mp_napics)
1569 io_apic_ints[intr].dst_apic_id = IO_TO_ID(apic);
1570 else
1571 io_apic_ints[intr].dst_apic_id = entry->dst_apic_id;
1572 } else
1573 io_apic_ints[intr].dst_apic_id = entry->dst_apic_id;
1574 io_apic_ints[intr].dst_apic_int = entry->dst_apic_int;
1575
1576 return 1;
1577 }
1578
1579 static int
1580 apic_int_is_bus_type(int intr, int bus_type)
1581 {
1582 int bus;
1583
1584 for (bus = 0; bus < mp_nbusses; ++bus)
1585 if ((bus_data[bus].bus_id == io_apic_ints[intr].src_bus_id)
1586 && ((int) bus_data[bus].bus_type == bus_type))
1587 return 1;
1588
1589 return 0;
1590 }
1591
1592 /*
1593 * Given a traditional ISA INT mask, return an APIC mask.
1594 */
1595 u_int
1596 isa_apic_mask(u_int isa_mask)
1597 {
1598 int isa_irq;
1599 int apic_pin;
1600
1601 #if defined(SKIP_IRQ15_REDIRECT)
1602 if (isa_mask == (1 << 15)) {
1603 kprintf("skipping ISA IRQ15 redirect\n");
1604 return isa_mask;
1605 }
1606 #endif /* SKIP_IRQ15_REDIRECT */
1607
1608 isa_irq = ffs(isa_mask); /* find its bit position */
1609 if (isa_irq == 0) /* doesn't exist */
1610 return 0;
1611 --isa_irq; /* make it zero based */
1612
1613 apic_pin = isa_apic_irq(isa_irq); /* look for APIC connection */
1614 if (apic_pin == -1)
1615 return 0;
1616
1617 return (1 << apic_pin); /* convert pin# to a mask */
1618 }
1619
1620 /*
1621 * Determine which APIC pin an ISA/EISA INT is attached to.
1622 */
1623 #define INTTYPE(I) (io_apic_ints[(I)].int_type)
1624 #define INTPIN(I) (io_apic_ints[(I)].dst_apic_int)
1625 #define INTIRQ(I) (io_apic_ints[(I)].int_vector)
1626 #define INTAPIC(I) (ID_TO_IO(io_apic_ints[(I)].dst_apic_id))
1627
1628 #define SRCBUSIRQ(I) (io_apic_ints[(I)].src_bus_irq)
1629 int
1630 isa_apic_irq(int isa_irq)
1631 {
1632 int intr;
1633
1634 for (intr = 0; intr < nintrs; ++intr) { /* check each record */
1635 if (INTTYPE(intr) == 0) { /* standard INT */
1636 if (SRCBUSIRQ(intr) == isa_irq) {
1637 if (apic_int_is_bus_type(intr, ISA) ||
1638 apic_int_is_bus_type(intr, EISA)) {
1639 if (INTIRQ(intr) == 0xff)
1640 return -1; /* unassigned */
1641 return INTIRQ(intr); /* found */
1642 }
1643 }
1644 }
1645 }
1646 return -1; /* NOT found */
1647 }
1648
1649
1650 /*
1651 * Determine which APIC pin a PCI INT is attached to.
1652 */
1653 #define SRCBUSID(I) (io_apic_ints[(I)].src_bus_id)
1654 #define SRCBUSDEVICE(I) ((io_apic_ints[(I)].src_bus_irq >> 2) & 0x1f)
1655 #define SRCBUSLINE(I) (io_apic_ints[(I)].src_bus_irq & 0x03)
1656 int
1657 pci_apic_irq(int pciBus, int pciDevice, int pciInt)
1658 {
1659 int intr;
1660
1661 --pciInt; /* zero based */
1662
1663 for (intr = 0; intr < nintrs; ++intr) { /* check each record */
1664 if ((INTTYPE(intr) == 0) /* standard INT */
1665 && (SRCBUSID(intr) == pciBus)
1666 && (SRCBUSDEVICE(intr) == pciDevice)
1667 && (SRCBUSLINE(intr) == pciInt)) { /* a candidate IRQ */
1668 if (apic_int_is_bus_type(intr, PCI)) {
1669 if (INTIRQ(intr) == 0xff)
1670 allocate_apic_irq(intr);
1671 if (INTIRQ(intr) == 0xff)
1672 return -1; /* unassigned */
1673 return INTIRQ(intr); /* exact match */
1674 }
1675 }
1676 }
1677
1678 return -1; /* NOT found */
1679 }
1680
1681 int
1682 next_apic_irq(int irq)
1683 {
1684 int intr, ointr;
1685 int bus, bustype;
1686
1687 bus = 0;
1688 bustype = 0;
1689 for (intr = 0; intr < nintrs; intr++) {
1690 if (INTIRQ(intr) != irq || INTTYPE(intr) != 0)
1691 continue;
1692 bus = SRCBUSID(intr);
1693 bustype = apic_bus_type(bus);
1694 if (bustype != ISA &&
1695 bustype != EISA &&
1696 bustype != PCI)
1697 continue;
1698 break;
1699 }
1700 if (intr >= nintrs) {
1701 return -1;
1702 }
1703 for (ointr = intr + 1; ointr < nintrs; ointr++) {
1704 if (INTTYPE(ointr) != 0)
1705 continue;
1706 if (bus != SRCBUSID(ointr))
1707 continue;
1708 if (bustype == PCI) {
1709 if (SRCBUSDEVICE(intr) != SRCBUSDEVICE(ointr))
1710 continue;
1711 if (SRCBUSLINE(intr) != SRCBUSLINE(ointr))
1712 continue;
1713 }
1714 if (bustype == ISA || bustype == EISA) {
1715 if (SRCBUSIRQ(intr) != SRCBUSIRQ(ointr))
1716 continue;
1717 }
1718 if (INTPIN(intr) == INTPIN(ointr))
1719 continue;
1720 break;
1721 }
1722 if (ointr >= nintrs) {
1723 return -1;
1724 }
1725 return INTIRQ(ointr);
1726 }
1727 #undef SRCBUSLINE
1728 #undef SRCBUSDEVICE
1729 #undef SRCBUSID
1730 #undef SRCBUSIRQ
1731
1732 #undef INTPIN
1733 #undef INTIRQ
1734 #undef INTAPIC
1735 #undef INTTYPE
1736
1737 #endif
1738
1739 /*
1740 * Reprogram the MB chipset to NOT redirect an ISA INTerrupt.
1741 *
1742 * XXX FIXME:
1743 * Exactly what this means is unclear at this point. It is a solution
1744 * for motherboards that redirect the MBIRQ0 pin. Generically a motherboard
1745 * could route any of the ISA INTs to upper (>15) IRQ values. But most would
1746 * NOT be redirected via MBIRQ0, thus "undirect()ing" them would NOT be an
1747 * option.
1748 */
1749 int
1750 undirect_isa_irq(int rirq)
1751 {
1752 #if defined(READY)
1753 if (bootverbose)
1754 kprintf("Freeing redirected ISA irq %d.\n", rirq);
1755 /** FIXME: tickle the MB redirector chip */
1756 return /* XXX */;
1757 #else
1758 if (bootverbose)
1759 kprintf("Freeing (NOT implemented) redirected ISA irq %d.\n", rirq);
1760 return 0;
1761 #endif /* READY */
1762 }
1763
1764
1765 /*
1766 * Reprogram the MB chipset to NOT redirect a PCI INTerrupt
1767 */
1768 int
1769 undirect_pci_irq(int rirq)
1770 {
1771 #if defined(READY)
1772 if (bootverbose)
1773 kprintf("Freeing redirected PCI irq %d.\n", rirq);
1774
1775 /** FIXME: tickle the MB redirector chip */
1776 return /* XXX */;
1777 #else
1778 if (bootverbose)
1779 kprintf("Freeing (NOT implemented) redirected PCI irq %d.\n",
1780 rirq);
1781 return 0;
1782 #endif /* READY */
1783 }
1784
1785
1786 /*
1787 * given a bus ID, return:
1788 * the bus type if found
1789 * -1 if NOT found
1790 */
1791 int
1792 apic_bus_type(int id)
1793 {
1794 int x;
1795
1796 for (x = 0; x < mp_nbusses; ++x)
1797 if (bus_data[x].bus_id == id)
1798 return bus_data[x].bus_type;
1799
1800 return -1;
1801 }
1802
1803 #ifdef APIC_IO
1804
1805 /*
1806 * given a LOGICAL APIC# and pin#, return:
1807 * the associated src bus ID if found
1808 * -1 if NOT found
1809 */
1810 int
1811 apic_src_bus_id(int apic, int pin)
1812 {
1813 int x;
1814
1815 /* search each of the possible INTerrupt sources */
1816 for (x = 0; x < nintrs; ++x)
1817 if ((apic == ID_TO_IO(io_apic_ints[x].dst_apic_id)) &&
1818 (pin == io_apic_ints[x].dst_apic_int))
1819 return (io_apic_ints[x].src_bus_id);
1820
1821 return -1; /* NOT found */
1822 }
1823
1824 /*
1825 * given a LOGICAL APIC# and pin#, return:
1826 * the associated src bus IRQ if found
1827 * -1 if NOT found
1828 */
1829 int
1830 apic_src_bus_irq(int apic, int pin)
1831 {
1832 int x;
1833
1834 for (x = 0; x < nintrs; x++)
1835 if ((apic == ID_TO_IO(io_apic_ints[x].dst_apic_id)) &&
1836 (pin == io_apic_ints[x].dst_apic_int))
1837 return (io_apic_ints[x].src_bus_irq);
1838
1839 return -1; /* NOT found */
1840 }
1841
1842
1843 /*
1844 * given a LOGICAL APIC# and pin#, return:
1845 * the associated INTerrupt type if found
1846 * -1 if NOT found
1847 */
1848 int
1849 apic_int_type(int apic, int pin)
1850 {
1851 int x;
1852
1853 /* search each of the possible INTerrupt sources */
1854 for (x = 0; x < nintrs; ++x) {
1855 if ((apic == ID_TO_IO(io_apic_ints[x].dst_apic_id)) &&
1856 (pin == io_apic_ints[x].dst_apic_int))
1857 return (io_apic_ints[x].int_type);
1858 }
1859 return -1; /* NOT found */
1860 }
1861
1862 /*
1863 * Return the IRQ associated with an APIC pin
1864 */
1865 int
1866 apic_irq(int apic, int pin)
1867 {
1868 int x;
1869 int res;
1870
1871 for (x = 0; x < nintrs; ++x) {
1872 if ((apic == ID_TO_IO(io_apic_ints[x].dst_apic_id)) &&
1873 (pin == io_apic_ints[x].dst_apic_int)) {
1874 res = io_apic_ints[x].int_vector;
1875 if (res == 0xff)
1876 return -1;
1877 if (apic != int_to_apicintpin[res].ioapic)
1878 panic("apic_irq: inconsistent table %d/%d", apic, int_to_apicintpin[res].ioapic);
1879 if (pin != int_to_apicintpin[res].int_pin)
1880 panic("apic_irq inconsistent table (2)");
1881 return res;
1882 }
1883 }
1884 return -1;
1885 }
1886
1887
1888 /*
1889 * given a LOGICAL APIC# and pin#, return:
1890 * the associated trigger mode if found
1891 * -1 if NOT found
1892 */
1893 int
1894 apic_trigger(int apic, int pin)
1895 {
1896 int x;
1897
1898 /* search each of the possible INTerrupt sources */
1899 for (x = 0; x < nintrs; ++x)
1900 if ((apic == ID_TO_IO(io_apic_ints[x].dst_apic_id)) &&
1901 (pin == io_apic_ints[x].dst_apic_int))
1902 return ((io_apic_ints[x].int_flags >> 2) & 0x03);
1903
1904 return -1; /* NOT found */
1905 }
1906
1907
1908 /*
1909 * given a LOGICAL APIC# and pin#, return:
1910 * the associated 'active' level if found
1911 * -1 if NOT found
1912 */
1913 int
1914 apic_polarity(int apic, int pin)
1915 {
1916 int x;
1917
1918 /* search each of the possible INTerrupt sources */
1919 for (x = 0; x < nintrs; ++x)
1920 if ((apic == ID_TO_IO(io_apic_ints[x].dst_apic_id)) &&
1921 (pin == io_apic_ints[x].dst_apic_int))
1922 return (io_apic_ints[x].int_flags & 0x03);
1923
1924 return -1; /* NOT found */
1925 }
1926
1927 #endif
1928
1929 /*
1930 * set data according to MP defaults
1931 * FIXME: probably not complete yet...
1932 */
1933 static void
1934 default_mp_table(int type)
1935 {
1936 int ap_cpu_id;
1937 #if defined(APIC_IO)
1938 int io_apic_id;
1939 int pin;
1940 #endif /* APIC_IO */
1941
1942 #if 0
1943 kprintf(" MP default config type: %d\n", type);
1944 switch (type) {
1945 case 1:
1946 kprintf(" bus: ISA, APIC: 82489DX\n");
1947 break;
1948 case 2:
1949 kprintf(" bus: EISA, APIC: 82489DX\n");
1950 break;
1951 case 3:
1952 kprintf(" bus: EISA, APIC: 82489DX\n");
1953 break;
1954 case 4:
1955 kprintf(" bus: MCA, APIC: 82489DX\n");
1956 break;
1957 case 5:
1958 kprintf(" bus: ISA+PCI, APIC: Integrated\n");
1959 break;
1960 case 6:
1961 kprintf(" bus: EISA+PCI, APIC: Integrated\n");
1962 break;
1963 case 7:
1964 kprintf(" bus: MCA+PCI, APIC: Integrated\n");
1965 break;
1966 default:
1967 kprintf(" future type\n");
1968 break;
1969 /* NOTREACHED */
1970 }
1971 #endif /* 0 */
1972
1973 boot_cpu_id = (lapic.id & APIC_ID_MASK) >> 24;
1974 ap_cpu_id = (boot_cpu_id == 0) ? 1 : 0;
1975
1976 /* BSP */
1977 CPU_TO_ID(0) = boot_cpu_id;
1978 ID_TO_CPU(boot_cpu_id) = 0;
1979
1980 /* one and only AP */
1981 CPU_TO_ID(1) = ap_cpu_id;
1982 ID_TO_CPU(ap_cpu_id) = 1;
1983
1984 #if defined(APIC_IO)
1985 /* one and only IO APIC */
1986 io_apic_id = (io_apic_read(0, IOAPIC_ID) & APIC_ID_MASK) >> 24;
1987
1988 /*
1989 * sanity check, refer to MP spec section 3.6.6, last paragraph
1990 * necessary as some hardware isn't properly setting up the IO APIC
1991 */
1992 #if defined(REALLY_ANAL_IOAPICID_VALUE)
1993 if (io_apic_id != 2) {
1994 #else
1995 if ((io_apic_id == 0) || (io_apic_id == 1) || (io_apic_id == 15)) {
1996 #endif /* REALLY_ANAL_IOAPICID_VALUE */
1997 io_apic_set_id(0, 2);
1998 io_apic_id = 2;
1999 }
2000 IO_TO_ID(0) = io_apic_id;
2001 ID_TO_IO(io_apic_id) = 0;
2002 #endif /* APIC_IO */
2003
2004 /* fill out bus entries */
2005 switch (type) {
2006 case 1:
2007 case 2:
2008 case 3:
2009 case 4:
2010 case 5:
2011 case 6:
2012 case 7:
2013 bus_data[0].bus_id = default_data[type - 1][1];
2014 bus_data[0].bus_type = default_data[type - 1][2];
2015 bus_data[1].bus_id = default_data[type - 1][3];
2016 bus_data[1].bus_type = default_data[type - 1][4];
2017 break;
2018
2019 /* case 4: case 7: MCA NOT supported */
2020 default: /* illegal/reserved */
2021 panic("BAD default MP config: %d", type);
2022 /* NOTREACHED */
2023 }
2024
2025 #if defined(APIC_IO)
2026 /* general cases from MP v1.4, table 5-2 */
2027 for (pin = 0; pin < 16; ++pin) {
2028 io_apic_ints[pin].int_type = 0;
2029 io_apic_ints[pin].int_flags = 0x05; /* edge/active-hi */
2030 io_apic_ints[pin].src_bus_id = 0;
2031 io_apic_ints[pin].src_bus_irq = pin; /* IRQ2 caught below */
2032 io_apic_ints[pin].dst_apic_id = io_apic_id;
2033 io_apic_ints[pin].dst_apic_int = pin; /* 1-to-1 */
2034 }
2035
2036 /* special cases from MP v1.4, table 5-2 */
2037 if (type == 2) {
2038 io_apic_ints[2].int_type = 0xff; /* N/C */
2039 io_apic_ints[13].int_type = 0xff; /* N/C */
2040 #if !defined(APIC_MIXED_MODE)
2041 /** FIXME: ??? */
2042 panic("sorry, can't support type 2 default yet");
2043 #endif /* APIC_MIXED_MODE */
2044 }
2045 else
2046 io_apic_ints[2].src_bus_irq = 0; /* ISA IRQ0 is on APIC INT 2 */
2047
2048 if (type == 7)
2049 io_apic_ints[0].int_type = 0xff; /* N/C */
2050 else
2051 io_apic_ints[0].int_type = 3; /* vectored 8259 */
2052 #endif /* APIC_IO */
2053 }
2054
2055 /*
2056 * Map a physical memory address representing I/O into KVA. The I/O
2057 * block is assumed not to cross a page boundary.
2058 */
2059 void *
2060 permanent_io_mapping(vm_paddr_t pa)
2061 {
2062 vm_offset_t vaddr;
2063 int pgeflag;
2064 int i;
2065
2066 KKASSERT(pa < 0x100000000LL);
2067
2068 pgeflag = 0; /* not used for SMP yet */
2069
2070 /*
2071 * If the requested physical address has already been incidently
2072 * mapped, just use the existing mapping. Otherwise create a new
2073 * mapping.
2074 */
2075 for (i = IO_MAPPING_START_INDEX; i < SMPpt_alloc_index; ++i) {
2076 if (((vm_offset_t)SMPpt[i] & PG_FRAME) ==
2077 ((vm_offset_t)pa & PG_FRAME)) {
2078 break;
2079 }
2080 }
2081 if (i == SMPpt_alloc_index) {
2082 if (i == NPTEPG - 2) {
2083 panic("permanent_io_mapping: We ran out of space"
2084 " in SMPpt[]!");
2085 }
2086 SMPpt[i] = (pt_entry_t)(PG_V | PG_RW | pgeflag |
2087 ((vm_offset_t)pa & PG_FRAME));
2088 ++SMPpt_alloc_index;
2089 }
2090 vaddr = (vm_offset_t)CPU_prvspace + (i * PAGE_SIZE) +
2091 ((vm_offset_t)pa & PAGE_MASK);
2092 return ((void *)vaddr);
2093 }
2094
2095 /*
2096 * start each AP in our list
2097 */
2098 static int
2099 start_all_aps(u_int boot_addr)
2100 {
2101 int x, i, pg;
2102 int shift;
2103 u_char mpbiosreason;
2104 u_long mpbioswarmvec;
2105 struct mdglobaldata *gd;
2106 struct privatespace *ps;
2107 char *stack;
2108 uintptr_t kptbase;
2109
2110 POSTCODE(START_ALL_APS_POST);
2111
2112 /* Initialize BSP's local APIC */
2113 apic_initialize(TRUE);
2114 bsp_apic_ready = 1;
2115
2116 /* install the AP 1st level boot code */
2117 install_ap_tramp(boot_addr);
2118
2119
2120 /* save the current value of the warm-start vector */
2121 mpbioswarmvec = *((u_long *) WARMBOOT_OFF);
2122 outb(CMOS_REG, BIOS_RESET);
2123 mpbiosreason = inb(CMOS_DATA);
2124
2125 /* set up temporary P==V mapping for AP boot */
2126 /* XXX this is a hack, we should boot the AP on its own stack/PTD */
2127 kptbase = (uintptr_t)(void *)KPTphys;
2128 for (x = 0; x < NKPT; x++) {
2129 PTD[x] = (pd_entry_t)(PG_V | PG_RW |
2130 ((kptbase + x * PAGE_SIZE) & PG_FRAME));
2131 }
2132 cpu_invltlb();
2133
2134 /* start each AP */
2135 for (x = 1; x <= mp_naps; ++x) {
2136
2137 /* This is a bit verbose, it will go away soon. */
2138
2139 /* first page of AP's private space */
2140 pg = x * i386_btop(sizeof(struct privatespace));
2141
2142 /* allocate new private data page(s) */
2143 gd = (struct mdglobaldata *)kmem_alloc(&kernel_map,
2144 MDGLOBALDATA_BASEALLOC_SIZE);
2145 /* wire it into the private page table page */
2146 for (i = 0; i < MDGLOBALDATA_BASEALLOC_SIZE; i += PAGE_SIZE) {
2147 SMPpt[pg + i / PAGE_SIZE] = (pt_entry_t)
2148 (PG_V | PG_RW | vtophys_pte((char *)gd + i));
2149 }
2150 pg += MDGLOBALDATA_BASEALLOC_PAGES;
2151
2152 SMPpt[pg + 0] = 0; /* *gd_CMAP1 */
2153 SMPpt[pg + 1] = 0; /* *gd_CMAP2 */
2154 SMPpt[pg + 2] = 0; /* *gd_CMAP3 */
2155 SMPpt[pg + 3] = 0; /* *gd_PMAP1 */
2156
2157 /* allocate and set up an idle stack data page */
2158 stack = (char *)kmem_alloc(&kernel_map, UPAGES*PAGE_SIZE);
2159 for (i = 0; i < UPAGES; i++) {
2160 SMPpt[pg + 4 + i] = (pt_entry_t)
2161 (PG_V | PG_RW | vtophys_pte(PAGE_SIZE * i + stack));
2162 }
2163
2164 gd = &CPU_prvspace[x].mdglobaldata; /* official location */
2165 bzero(gd, sizeof(*gd));
2166 gd->mi.gd_prvspace = ps = &CPU_prvspace[x];
2167
2168 /* prime data page for it to use */
2169 mi_gdinit(&gd->mi, x);
2170 cpu_gdinit(gd, x);
2171 gd->gd_CMAP1 = &SMPpt[pg + 0];
2172 gd->gd_CMAP2 = &SMPpt[pg + 1];
2173 gd->gd_CMAP3 = &SMPpt[pg + 2];
2174 gd->gd_PMAP1 = &SMPpt[pg + 3];
2175 gd->gd_CADDR1 = ps->CPAGE1;
2176 gd->gd_CADDR2 = ps->CPAGE2;
2177 gd->gd_CADDR3 = ps->CPAGE3;
2178 gd->gd_PADDR1 = (unsigned *)ps->PPAGE1;
2179 gd->mi.gd_ipiq = (void *)kmem_alloc(&kernel_map, sizeof(lwkt_ipiq) * (mp_naps + 1));
2180 bzero(gd->mi.gd_ipiq, sizeof(lwkt_ipiq) * (mp_naps + 1));
2181
2182 /* setup a vector to our boot code */
2183 *((volatile u_short *) WARMBOOT_OFF) = WARMBOOT_TARGET;
2184 *((volatile u_short *) WARMBOOT_SEG) = (boot_addr >> 4);
2185 outb(CMOS_REG, BIOS_RESET);
2186 outb(CMOS_DATA, BIOS_WARM); /* 'warm-start' */
2187
2188 /*
2189 * Setup the AP boot stack
2190 */
2191 bootSTK = &ps->idlestack[UPAGES*PAGE_SIZE/2];
2192 bootAP = x;
2193
2194 /* attempt to start the Application Processor */
2195 CHECK_INIT(99); /* setup checkpoints */
2196 if (!start_ap(gd, boot_addr)) {
2197 kprintf("AP #%d (PHY# %d) failed!\n", x, CPU_TO_ID(x));
2198 CHECK_PRINT("trace"); /* show checkpoints */
2199 /* better panic as the AP may be running loose */
2200 kprintf("panic y/n? [y] ");
2201 if (cngetc() != 'n')
2202 panic("bye-bye");
2203 }
2204 CHECK_PRINT("trace"); /* show checkpoints */
2205
2206 /* record its version info */
2207 cpu_apic_versions[x] = cpu_apic_versions[0];
2208 }
2209
2210 /* set ncpus to 1 + highest logical cpu. Not all may have come up */
2211 ncpus = x;
2212
2213 /* ncpus2 -- ncpus rounded down to the nearest power of 2 */
2214 for (shift = 0; (1 << shift) <= ncpus; ++shift)
2215 ;
2216 --shift;
2217 ncpus2_shift = shift;
2218 ncpus2 = 1 << shift;
2219 ncpus2_mask = ncpus2 - 1;
2220
2221 /* ncpus_fit -- ncpus rounded up to the nearest power of 2 */
2222 if ((1 << shift) < ncpus)
2223 ++shift;
2224 ncpus_fit = 1 << shift;
2225 ncpus_fit_mask = ncpus_fit - 1;
2226
2227 /* build our map of 'other' CPUs */
2228 mycpu->gd_other_cpus = smp_startup_mask & ~(1 << mycpu->gd_cpuid);
2229 mycpu->gd_ipiq = (void *)kmem_alloc(&kernel_map, sizeof(lwkt_ipiq) * ncpus);
2230 bzero(mycpu->gd_ipiq, sizeof(lwkt_ipiq) * ncpus);
2231
2232 /* fill in our (BSP) APIC version */
2233 cpu_apic_versions[0] = lapic.version;
2234
2235 /* restore the warmstart vector */
2236 *(u_long *) WARMBOOT_OFF = mpbioswarmvec;
2237 outb(CMOS_REG, BIOS_RESET);
2238 outb(CMOS_DATA, mpbiosreason);
2239
2240 /*
2241 * NOTE! The idlestack for the BSP was setup by locore. Finish
2242 * up, clean out the P==V mapping we did earlier.
2243 */
2244 for (x = 0; x < NKPT; x++)
2245 PTD[x] = 0;
2246 pmap_set_opt();
2247
2248 /* number of APs actually started */
2249 return ncpus - 1;
2250 }
2251
2252
2253 /*
2254 * load the 1st level AP boot code into base memory.
2255 */
2256
2257 /* targets for relocation */
2258 extern void bigJump(void);
2259 extern void bootCodeSeg(void);
2260 extern void bootDataSeg(void);
2261 extern void MPentry(void);
2262 extern u_int MP_GDT;
2263 extern u_int mp_gdtbase;
2264
2265 static void
2266 install_ap_tramp(u_int boot_addr)
2267 {
2268 int x;
2269 int size = *(int *) ((u_long) & bootMP_size);
2270 u_char *src = (u_char *) ((u_long) bootMP);
2271 u_char *dst = (u_char *) boot_addr + KERNBASE;
2272 u_int boot_base = (u_int) bootMP;
2273 u_int8_t *dst8;
2274 u_int16_t *dst16;
2275 u_int32_t *dst32;
2276
2277 POSTCODE(INSTALL_AP_TRAMP_POST);
2278
2279 for (x = 0; x < size; ++x)
2280 *dst++ = *src++;
2281
2282 /*
2283 * modify addresses in code we just moved to basemem. unfortunately we
2284 * need fairly detailed info about mpboot.s for this to work. changes
2285 * to mpboot.s might require changes here.
2286 */
2287
2288 /* boot code is located in KERNEL space */
2289 dst = (u_char *) boot_addr + KERNBASE;
2290
2291 /* modify the lgdt arg */
2292 dst32 = (u_int32_t *) (dst + ((u_int) & mp_gdtbase - boot_base));
2293 *dst32 = boot_addr + ((u_int) & MP_GDT - boot_base);
2294
2295 /* modify the ljmp target for MPentry() */
2296 dst32 = (u_int32_t *) (dst + ((u_int) bigJump - boot_base) + 1);
2297 *dst32 = ((u_int) MPentry - KERNBASE);
2298
2299 /* modify the target for boot code segment */
2300 dst16 = (u_int16_t *) (dst + ((u_int) bootCodeSeg - boot_base));
2301 dst8 = (u_int8_t *) (dst16 + 1);
2302 *dst16 = (u_int) boot_addr & 0xffff;
2303 *dst8 = ((u_int) boot_addr >> 16) & 0xff;
2304
2305 /* modify the target for boot data segment */
2306 dst16 = (u_int16_t *) (dst + ((u_int) bootDataSeg - boot_base));
2307 dst8 = (u_int8_t *) (dst16 + 1);
2308 *dst16 = (u_int) boot_addr & 0xffff;
2309 *dst8 = ((u_int) boot_addr >> 16) & 0xff;
2310 }
2311
2312
2313 /*
2314 * this function starts the AP (application processor) identified
2315 * by the APIC ID 'physicalCpu'. It does quite a "song and dance"
2316 * to accomplish this. This is necessary because of the nuances
2317 * of the different hardware we might encounter. It ain't pretty,
2318 * but it seems to work.
2319 *
2320 * NOTE: eventually an AP gets to ap_init(), which is called just
2321 * before the AP goes into the LWKT scheduler's idle loop.
2322 */
2323 static int
2324 start_ap(struct mdglobaldata *gd, u_int boot_addr)
2325 {
2326 int physical_cpu;
2327 int vector;
2328 u_long icr_lo, icr_hi;
2329
2330 POSTCODE(START_AP_POST);
2331
2332 /* get the PHYSICAL APIC ID# */
2333 physical_cpu = CPU_TO_ID(gd->mi.gd_cpuid);
2334
2335 /* calculate the vector */
2336 vector = (boot_addr >> 12) & 0xff;
2337
2338 /* Make sure the target cpu sees everything */
2339 wbinvd();
2340
2341 /*
2342 * first we do an INIT/RESET IPI this INIT IPI might be run, reseting
2343 * and running the target CPU. OR this INIT IPI might be latched (P5
2344 * bug), CPU waiting for STARTUP IPI. OR this INIT IPI might be
2345 * ignored.
2346 */
2347
2348 /* setup the address for the target AP */
2349 icr_hi = lapic.icr_hi & ~APIC_ID_MASK;
2350 icr_hi |= (physical_cpu << 24);
2351 lapic.icr_hi = icr_hi;
2352
2353 /* do an INIT IPI: assert RESET */
2354 icr_lo = lapic.icr_lo & 0xfff00000;
2355 lapic.icr_lo = icr_lo | 0x0000c500;
2356
2357 /* wait for pending status end */
2358 while (lapic.icr_lo & APIC_DELSTAT_MASK)
2359 /* spin */ ;
2360
2361 /* do an INIT IPI: deassert RESET */
2362 lapic.icr_lo = icr_lo | 0x00008500;
2363
2364 /* wait for pending status end */
2365 u_sleep(10000); /* wait ~10mS */
2366 while (lapic.icr_lo & APIC_DELSTAT_MASK)
2367 /* spin */ ;
2368
2369 /*
2370 * next we do a STARTUP IPI: the previous INIT IPI might still be
2371 * latched, (P5 bug) this 1st STARTUP would then terminate
2372 * immediately, and the previously started INIT IPI would continue. OR
2373 * the previous INIT IPI has already run. and this STARTUP IPI will
2374 * run. OR the previous INIT IPI was ignored. and this STARTUP IPI
2375 * will run.
2376 */
2377
2378 /* do a STARTUP IPI */
2379 lapic.icr_lo = icr_lo | 0x00000600 | vector;
2380 while (lapic.icr_lo & APIC_DELSTAT_MASK)
2381 /* spin */ ;
2382 u_sleep(200); /* wait ~200uS */
2383
2384 /*
2385 * finally we do a 2nd STARTUP IPI: this 2nd STARTUP IPI should run IF
2386 * the previous STARTUP IPI was cancelled by a latched INIT IPI. OR
2387 * this STARTUP IPI will be ignored, as only ONE STARTUP IPI is
2388 * recognized after hardware RESET or INIT IPI.
2389 */
2390
2391 lapic.icr_lo = icr_lo | 0x00000600 | vector;
2392 while (lapic.icr_lo & APIC_DELSTAT_MASK)
2393 /* spin */ ;
2394 u_sleep(200); /* wait ~200uS */
2395
2396 /* wait for it to start, see ap_init() */
2397 set_apic_timer(5000000);/* == 5 seconds */
2398 while (read_apic_timer()) {
2399 if (smp_startup_mask & (1 << gd->mi.gd_cpuid))
2400 return 1; /* return SUCCESS */
2401 }
2402 return 0; /* return FAILURE */
2403 }
2404
2405
2406 /*
2407 * Lazy flush the TLB on all other CPU's. DEPRECATED.
2408 *
2409 * If for some reason we were unable to start all cpus we cannot safely
2410 * use broadcast IPIs.
2411 */
2412 void
2413 smp_invltlb(void)
2414 {
2415 #ifdef SMP
2416 if (smp_startup_mask == smp_active_mask) {
2417 all_but_self_ipi(XINVLTLB_OFFSET);
2418 } else {
2419 selected_apic_ipi(smp_active_mask, XINVLTLB_OFFSET,
2420 APIC_DELMODE_FIXED);
2421 }
2422 #endif
2423 }
2424
2425 /*
2426 * When called the executing CPU will send an IPI to all other CPUs
2427 * requesting that they halt execution.
2428 *
2429 * Usually (but not necessarily) called with 'other_cpus' as its arg.
2430 *
2431 * - Signals all CPUs in map to stop.
2432 * - Waits for each to stop.
2433 *
2434 * Returns:
2435 * -1: error
2436 * 0: NA
2437 * 1: ok
2438 *
2439 * XXX FIXME: this is not MP-safe, needs a lock to prevent multiple CPUs
2440 * from executing at same time.
2441 */
2442 int
2443 stop_cpus(u_int map)
2444 {
2445 map &= smp_active_mask;
2446
2447 /* send the Xcpustop IPI to all CPUs in map */
2448 selected_apic_ipi(map, XCPUSTOP_OFFSET, APIC_DELMODE_FIXED);
2449
2450 while ((stopped_cpus & map) != map)
2451 /* spin */ ;
2452
2453 return 1;
2454 }
2455
2456
2457 /*
2458 * Called by a CPU to restart stopped CPUs.
2459 *
2460 * Usually (but not necessarily) called with 'stopped_cpus' as its arg.
2461 *
2462 * - Signals all CPUs in map to restart.
2463 * - Waits for each to restart.
2464 *
2465 * Returns:
2466 * -1: error
2467 * 0: NA
2468 * 1: ok
2469 */
2470 int
2471 restart_cpus(u_int map)
2472 {
2473 /* signal other cpus to restart */
2474 started_cpus = map & smp_active_mask;
2475
2476 while ((stopped_cpus & map) != 0) /* wait for each to clear its bit */
2477 /* spin */ ;
2478
2479 return 1;
2480 }
2481
2482 /*
2483 * This is called once the mpboot code has gotten us properly relocated
2484 * and the MMU turned on, etc. ap_init() is actually the idle thread,
2485 * and when it returns the scheduler will call the real cpu_idle() main
2486 * loop for the idlethread. Interrupts are disabled on entry and should
2487 * remain disabled at return.
2488 */
2489 void
2490 ap_init(void)
2491 {
2492 u_int apic_id;
2493
2494 /*
2495 * Adjust smp_startup_mask to signal the BSP that we have started
2496 * up successfully. Note that we do not yet hold the BGL. The BSP
2497 * is waiting for our signal.
2498 *
2499 * We can't set our bit in smp_active_mask yet because we are holding
2500 * interrupts physically disabled and remote cpus could deadlock
2501 * trying to send us an IPI.
2502 */
2503 smp_startup_mask |= 1 << mycpu->gd_cpuid;
2504 cpu_mfence();
2505
2506 /*
2507 * Interlock for finalization. Wait until mp_finish is non-zero,
2508 * then get the MP lock.
2509 *
2510 * Note: We are in a critical section.
2511 *
2512 * Note: We have to synchronize td_mpcount to our desired MP state
2513 * before calling cpu_try_mplock().
2514 *
2515 * Note: we are the idle thread, we can only spin.
2516 *
2517 * Note: The load fence is memory volatile and prevents the compiler
2518 * from improperly caching mp_finish, and the cpu from improperly
2519 * caching it.
2520 */
2521 while (mp_finish == 0)
2522 cpu_lfence();
2523 ++curthread->td_mpcount;
2524 while (cpu_try_mplock() == 0)
2525 ;
2526
2527 if (cpu_feature & CPUID_TSC) {
2528 /*
2529 * The BSP is constantly updating tsc0_offset, figure out the
2530 * relative difference to synchronize ktrdump.
2531 */
2532 tsc_offsets[mycpu->gd_cpuid] = rdtsc() - tsc0_offset;
2533 }
2534
2535 /* BSP may have changed PTD while we're waiting for the lock */
2536 cpu_invltlb();
2537
2538 #if defined(I586_CPU) && !defined(NO_F00F_HACK)
2539 lidt(&r_idt);
2540 #endif
2541
2542 /* Build our map of 'other' CPUs. */
2543 mycpu->gd_other_cpus = smp_startup_mask & ~(1 << mycpu->gd_cpuid);
2544
2545 kprintf("SMP: AP CPU #%d Launched!\n", mycpu->gd_cpuid);
2546
2547 /* A quick check from sanity claus */
2548 apic_id = (apic_id_to_logical[(lapic.id & 0x0f000000) >> 24]);
2549 if (mycpu->gd_cpuid != apic_id) {
2550 kprintf("SMP: cpuid = %d\n", mycpu->gd_cpuid);
2551 kprintf("SMP: apic_id = %d\n", apic_id);
2552 kprintf("PTD[MPPTDI] = %p\n", (void *)PTD[MPPTDI]);
2553 panic("cpuid mismatch! boom!!");
2554 }
2555
2556 /* Initialize AP's local APIC for irq's */
2557 apic_initialize(FALSE);
2558
2559 /* Set memory range attributes for this CPU to match the BSP */
2560 mem_range_AP_init();
2561
2562 /*
2563 * Once we go active we must process any IPIQ messages that may
2564 * have been queued, because no actual IPI will occur until we
2565 * set our bit in the smp_active_mask. If we don't the IPI
2566 * message interlock could be left set which would also prevent
2567 * further IPIs.
2568 *
2569 * The idle loop doesn't expect the BGL to be held and while
2570 * lwkt_switch() normally cleans things up this is a special case
2571 * because we returning almost directly into the idle loop.
2572 *
2573 * The idle thread is never placed on the runq, make sure
2574 * nothing we've done put it there.
2575 */
2576 KKASSERT(curthread->td_mpcount == 1);
2577 smp_active_mask |= 1 << mycpu->gd_cpuid;
2578
2579 /*
2580 * Enable interrupts here. idle_restore will also do it, but
2581 * doing it here lets us clean up any strays that got posted to
2582 * the CPU during the AP boot while we are still in a critical
2583 * section.
2584 */
2585 __asm __volatile("sti; pause; pause"::);
2586 mdcpu->gd_fpending = 0;
2587 mdcpu->gd_ipending = 0;
2588
2589 initclocks_pcpu(); /* clock interrupts (via IPIs) */
2590 lwkt_process_ipiq();
2591
2592 /*
2593 * Releasing the mp lock lets the BSP finish up the SMP init
2594 */
2595 rel_mplock();
2596 KKASSERT((curthread->td_flags & TDF_RUNQ) == 0);
2597 }
2598
2599 /*
2600 * Get SMP fully working before we start initializing devices.
2601 */
2602 static
2603 void
2604 ap_finish(void)
2605 {
2606 mp_finish = 1;
2607 if (bootverbose)
2608 kprintf("Finish MP startup\n");
2609 if (cpu_feature & CPUID_TSC)
2610 tsc0_offset = rdtsc();
2611 tsc_offsets[0] = 0;
2612 rel_mplock();
2613 while (smp_active_mask != smp_startup_mask) {
2614 cpu_lfence();
2615 if (cpu_feature & CPUID_TSC)
2616 tsc0_offset = rdtsc();
2617 }
2618 while (try_mplock() == 0)
2619 ;
2620 if (bootverbose)
2621 kprintf("Active CPU Mask: %08x\n", smp_active_mask);
2622 }
2623
2624 SYSINIT(finishsmp, SI_BOOT2_FINISH_SMP, SI_ORDER_FIRST, ap_finish, NULL)
2625
2626 void
2627 cpu_send_ipiq(int dcpu)
2628 {
2629 if ((1 << dcpu) & smp_active_mask)
2630 single_apic_ipi(dcpu, XIPIQ_OFFSET, APIC_DELMODE_FIXED);
2631 }
2632
2633 #if 0 /* single_apic_ipi_passive() not working yet */
2634 /*
2635 * Returns 0 on failure, 1 on success
2636 */
2637 int
2638 cpu_send_ipiq_passive(int dcpu)
2639 {
2640 int r = 0;
2641 if ((1 << dcpu) & smp_active_mask) {
2642 r = single_apic_ipi_passive(dcpu, XIPIQ_OFFSET,
2643 APIC_DELMODE_FIXED);
2644 }
2645 return(r);
2646 }
2647 #endif
2648
DragonFly BSD