sys/dev/atm/hea/eni.h

   1 /*
   2  *
   3  * ===================================
   4  * HARP  |  Host ATM Research Platform
   5  * ===================================
   6  *
   7  *
   8  * This Host ATM Research Platform ("HARP") file (the "Software") is
   9  * made available by Network Computing Services, Inc. ("NetworkCS")
  10  * "AS IS".  NetworkCS does not provide maintenance, improvements or
  11  * support of any kind.
  12  *
  13  * NETWORKCS MAKES NO WARRANTIES OR REPRESENTATIONS, EXPRESS OR IMPLIED,
  14  * INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF MERCHANTABILITY
  15  * AND FITNESS FOR A PARTICULAR PURPOSE, AS TO ANY ELEMENT OF THE
  16  * SOFTWARE OR ANY SUPPORT PROVIDED IN CONNECTION WITH THIS SOFTWARE.
  17  * In no event shall NetworkCS be responsible for any damages, including
  18  * but not limited to consequential damages, arising from or relating to
  19  * any use of the Software or related support.
  20  *
  21  * Copyright 1994-1998 Network Computing Services, Inc.
  22  *
  23  * Copies of this Software may be made, however, the above copyright
  24  * notice must be reproduced on all copies.
  25  *
  26  *      @(#) $FreeBSD: src/sys/dev/hea/eni.h,v 1.2 1999/08/28 00:41:43 peter Exp $
  27  *      @(#) $DragonFly: src/sys/dev/atm/hea/eni.h,v 1.4 2005/02/01 00:51:49 joerg Exp $
  28  *
  29  */
  30
  31 /*
  32  * Efficient ENI Adapter Support
  33  *
  34  * Protocol and implementation definitions
  35  *
  36  */
  37
  38 #ifndef _ENI_ENI_H
  39 #define _ENI_ENI_H
  40
  41 #include <bus/pci/pcireg.h>
  42 #include <bus/pci/pcivar.h>
  43
  44 /*
  45  * Physical device name - used to configure HARP devices
  46  */
  47 #ifndef ENI_DEV_NAME
  48 #define ENI_DEV_NAME    "hea"           /* HARP Efficient ATM */
  49 #endif
  50
  51 #define ENI_MAX_UNITS   4
  52
  53 #define ENI_IFF_MTU     9188
  54 #define ENI_MAX_VCI     1023            /* 0 - 1023 */
  55 #define ENI_MAX_VPI     0
  56
  57 #define ENI_IFQ_MAXLEN  1000            /* rx/tx queue lengths */
  58
  59 /*
  60  * Size of small and large receive buffers
  61  */
  62 #define ENI_SMALL_BSIZE         64
  63 #define ENI_LARGE_BSIZE         MCLBYTES
  64
  65 /*
  66  * ENI memory map offsets IN WORDS, not bytes
  67  *
  68  * The Efficient Adapter implements a 4 MB address space. The lower
  69  * 2 MB are used by bootprom (E)EPROM and by chipset registers such
  70  * as the MIDWAY and SUNI chips. The (upto) upper 2 MB is used for
  71  * RAM. Of the RAM, the lower 28 KB is used for fixed tables - the
  72  * VCI table, the RX and TX DMA queues, and the Service List queue.
  73  * Memory above the 28 KB range is available for RX and TX buffers.
  74  *
  75  * NOTE: Access to anything other then the (E)EPROM MUST be as a 32 bit
  76  * access. Also note that Efficient uses both byte addresses and word
  77  * addresses when describing offsets. BE CAREFUL or you'll get confused!
  78  */
  79 /*
  80  * Size of memory space reserved for registers and expansion (e)eprom.
  81  */
  82 #define ENI_REG_SIZE    0x200000        /* Two megabytes */
  83
  84 #define SUNI_OFFSET     0x008000        /* SUNI chip registers */
  85 #define MIDWAY_OFFSET   0x010000        /* MIDWAY chip registers */
  86 #define RAM_OFFSET      0x080000        /* Adapter RAM */
  87 #define VCITBL_OFFSET   0x080000        /* VCI Table offset */
  88 #define RXQUEUE_OFFSET  0x081000        /* RX DMA Queue offset */
  89 #define TXQUEUE_OFFSET  0x081400        /* TX DMA Queue offset */
  90 #define SVCLIST_OFFSET  0x081800        /* SVC List Queue offset */
  91
  92 #define SEGBUF_BASE     0x007000        /* Base from start of RAM */
  93
  94 #define DMA_LIST_SIZE   512             /* 1024 words / 2 words per entry */
  95 #define SVC_LIST_SIZE   1024            /* 1024 words / 1 word  per entry */
  96
  97 /*
  98  * Values for testing size of RAM on adapter
  99  *
 100  * Efficient has (at least) two different memory sizes available. One
 101  * is a client card which has either 128 KB or 512 KB RAM, the other
 102  * is a server card which has 2 MB RAM. The driver will size and test
 103  * the memory to correctly determine what's available.
 104  */
 105 #define MAX_ENI_MEM     0x200000        /* 2 MB - max. mem supported */
 106 #define TEST_STEP       0x000400        /* Look at 1 KB steps */
 107 #define TEST_PAT        0xA5A5A5A5      /* Test pattern */
 108
 109 /*
 110  * Values for memory allocator
 111  */
 112 #define ENI_BUF_PGSZ    1024            /* Allocation unit of buffers */
 113 #define ENI_BUF_NBIT    8               /* Number of bits to get from */
 114                                         /* min buffer (1KB) to max (128KB) */
 115
 116 /*
 117  * Values for allocating TX buffers
 118  */
 119 #define MAX_CLIENT_RAM  512             /* Most RAM a client card will have */
 120 #define TX_SMALL_BSIZE  32              /* Small buffer - 32KB */
 121 #define TX_LARGE_BSIZE  128             /* Large buffer - 128KB */
 122
 123 /*
 124  * Values for allocating RX buffers
 125  */
 126 #define RX_SIG_BSIZE    4               /* Signalling buffer - 4KB */
 127 #define RX_CLIENT_BSIZE 16              /* Client buffer - 16KB */
 128 #define RX_SERVER_BSIZE 32              /* Server buffer - 32KB */
 129
 130 /*
 131  * Adapter bases all addresses off of some power from 1KB. Thus, it
 132  * only needs to store the most sigificant bits and can drop the lower
 133  * 10 bits.
 134  */
 135 #define ENI_LOC_PREDIV  10              /* Bits location is shifted */
 136                                         /* Location is prescaled by 1KB */
 137                                         /* before use in various places */
 138
 139 #define MIDWAY_DELAY    10              /* Time to wait for Midway finish */
 140
 141 /*
 142  * Define the MIDWAY register offsets and any interesting bits within
 143  * the register
 144  */
 145 #define MIDWAY_ID               0x00            /* ID/Reset register */
 146         #define MIDWAY_RESET    0               /* iWrite of any value */
 147         #define ID_SHIFT        27              /* Midway ID version */
 148         #define ID_MASK         0x1F            /* ID mask */
 149         #define MID_SHIFT       7               /* Mother board ID */
 150         #define MID_MASK        0x7             /* MID mask */
 151         #define DID_SHIFT       0               /* Daughter board ID */
 152         #define DID_MASK        0x1F            /* DID mask */
 153         /*
 154          * Efficient defines the following IDs for their adapters:
 155          * 0x420/0x620 - SONET MMF, client memory size
 156          * 0x430/0x630 - SONET MMF, server memory size
 157          * 0x424/0x624 - UTP-5, client memory size
 158          * 0x434/0x634 - UTP-5, server memory size
 159          */
 160         #define MEDIA_MASK      0x04            /* Mask off UTP-5/MMF media */
 161
 162 #define MIDWAY_ISA              0x01            /* Interrupt Status Ack. */
 163                                                 /* Reading this register */
 164                                                 /* also acknowledges the */
 165                                                 /* posted interrupt(s) */
 166
 167 #define MIDWAY_IS               0x02            /* Interrupt Status */
 168                                                 /* Reading this register */
 169                                                 /* does NOT acknowledge the */
 170                                                 /* posted interrupt(s) */
 171         /* Interrupt names */
 172         #define ENI_INT_STAT            0x00000001
 173         #define ENI_INT_SUNI            0x00000002
 174         #define ENI_INT_SERVICE         0x00000004
 175         #define ENI_INT_TX_DMA          0x00000008
 176         #define ENI_INT_RX_DMA          0x00000010
 177         #define ENI_INT_DMA_ERR         0x00000020
 178         #define ENI_INT_DMA_LERR        0x00000040
 179         #define ENI_INT_IDEN            0x00000080
 180         #define ENI_INT_DMA_OVFL        0x00000100
 181         #define ENI_INT_TX_MASK         0x0001FE00
 182
 183 #define MIDWAY_IE               0x03            /* Interrupt Enable register */
 184         /* Interrupt enable bits are the same as the Interrupt names */
 185
 186 #define MIDWAY_MASTER           0x04            /* Master Control */
 187         /* Master control bits */
 188         #define ENI_M_WAIT500   0x00000001      /* Disable interrupts .5 ms */
 189         #define ENI_M_WAIT1     0x00000002      /* Disable interrupts 1 ms */
 190         #define ENI_M_RXENABLE  0x00000004      /* Enable RX engine */
 191         #define ENI_M_TXENABLE  0x00000008      /* Enable TX engine */
 192         #define ENI_M_DMAENABLE 0x00000010      /* Enable DMA */
 193         #define ENI_M_TXLOCK    0x00000020      /* 0: Streaming, 1: Lock */
 194         #define ENI_M_INTSEL    0x000001C0      /* Int Select mask */
 195         #define ENI_ISEL_SHIFT  6               /* Bits to shift ISEL value */
 196
 197 #define MIDWAY_STAT             0x05            /* Statistics register */
 198
 199 #define MIDWAY_SVCWR            0x06            /* Svc List write pointer */
 200         #define SVC_SIZE_MASK   0x3FF           /* Valid bits in svc pointer */
 201
 202 #define MIDWAY_DMAADDR          0x07            /* Current virtual DMA addr */
 203
 204 #define MIDWAY_RX_WR            0x08            /* Write ptr to RX DMA queue */
 205
 206 #define MIDWAY_RX_RD            0x09            /* Read ptr to RX DMA queue */
 207
 208 #define MIDWAY_TX_WR            0x0A            /* Write ptr to TX DMA queue */
 209
 210 #define MIDWAY_TX_RD            0x0B            /* Read ptr to TX DMA queue */
 211
 212 /*
 213  * Registers 0x0C - 0x0F are unused
 214  */
 215
 216 /*
 217  * MIDWAY supports 8 transmit channels. Each channel has 3 registers
 218  * to control operation. Each new channel starts on N * 4 set. Thus,
 219  * channel 0 uses register 0x10 - 0x13, channel 1 uses 0x14 - 0x17, etc.
 220  * Register 0x13 + N * 4 is unused.
 221  */
 222
 223 #define MIDWAY_TXPLACE          0x10            /* Channel N TX location */
 224         #define TXSIZE_SHIFT    11              /* Bits to shift size by */
 225         #define TX_PLACE_MASK   0x7FF           /* Valid bits in TXPLACE */
 226
 227 #define MIDWAY_RDPTR            0x11            /* Channel N Read ptr */
 228
 229 #define MIDWAY_DESCR            0x12            /* Channel N Descr ptr */
 230
 231 /*
 232  * Register 0x30 on up are unused
 233  */
 234
 235 /*
 236  * Part of PCI configuration registers but not defined in <pci/pcireg.h>
 237  */
 238 #define PCI_CONTROL_REG         0x60
 239 #define ENDIAN_SWAP_DMA         0x80            /* Enable endian swaps on DMA */
 240
 241 /*
 242  * The Efficient adapter references adapter RAM through the use of
 243  * location and size values. Eight sizes are defined. When allocating
 244  * buffers, there size must be rounded up to the next size which will
 245  * hold the requested size. Buffers are allocated on 'SIZE' boundaries.
 246  * See eni_buffer.c for more info.
 247  */
 248
 249 /*
 250  * Buffer SIZE definitions - in words, so from 1 KB to 128 KB
 251  */
 252 #define SIZE_256        0x00
 253 #define SIZE_512        0x01
 254 #define SIZE_1K         0x02
 255 #define SIZE_2K         0x03
 256 #define SIZE_4K         0x04
 257 #define SIZE_8K         0x05
 258 #define SIZE_16K        0x06
 259 #define SIZE_32K        0x07
 260
 261 /*
 262  * Define values for DMA type - DMA descriptors include a type field and a
 263  * count field except in the special case of JK (just-kidding). With type JK,
 264  * the count field should be set to the address which will be loaded
 265  * into the pointer, ie. where the pointer should next point to, since
 266  * JK doesn't have a "size" associated with it. JK DMA is used to skip
 267  * over descriptor words, and to strip off padding of AAL5 PDUs. The
 268  * DMA_nWORDM types will do a n word DMA burst, but the count field
 269  * does not have to equal n. Any difference results in garbage filling
 270  * the remaining words of the DMA. These types could be used where a
 271  * particular burst size yields better DMA performance.
 272  */
 273 #define DMA_WORD        0x00
 274 #define DMA_BYTE        0x01
 275 #define DMA_HWORD       0x02
 276 #define DMA_JK          0x03
 277 #define DMA_4WORD       0x04
 278 #define DMA_8WORD       0x05
 279 #define DMA_16WORD      0x06
 280 #define DMA_2WORD       0x07
 281 #define DMA_4WORDM      0x0C
 282 #define DMA_8WORDM      0x0D
 283 #define DMA_16WORDM     0x0E
 284 #define DMA_2WORDM      0x0F
 285
 286 /*
 287  * Define the size of the local DMA list we'll build before
 288  * giving up on the PDU.
 289  */
 290 #define TEMP_DMA_SIZE   120             /* Enough for 58/59 buffers */
 291
 292 #define DMA_COUNT_SHIFT 16              /* Number of bits to shift count */
 293                                         /* in DMA descriptor word */
 294 #define DMA_VCC_SHIFT   6               /* Number of bits to shift RX VCC or */
 295                                         /* TX channel in DMA descriptor word */
 296 #define DMA_END_BIT     0x20            /* Signal end of DMA list */
 297
 298 /*
 299  * Defines for VCI table
 300  *
 301  * The VCI table is a 1K by 4 word table allowing up to 1024 (0-1023)
 302  * VCIs. Entries into the table use the VCI number as the index.
 303  */
 304 struct vci_table {
 305         u_long  vci_control;            /* Control word */
 306         u_long  vci_descr;              /* Descr/ReadPtr */
 307         u_long  vci_write;              /* WritePtr/State/Cell count */
 308         u_long  vci_crc;                /* ongoing CRC calculation */
 309 };
 310 typedef volatile struct vci_table VCI_Table;
 311
 312 #define VCI_MODE_SHIFT  30              /* Shift to get MODE field */
 313 #define VCI_MODE_MASK   0x3FFFFFFF      /* Bits to strip MODE off */
 314 #define VCI_PTI_SHIFT   29              /* Shift to get PTI mode field */
 315 #define VCI_LOC_SHIFT   18              /* Shift to get location field */
 316 #define VCI_LOC_MASK    0x7FF           /* Valid bits in location field */
 317 #define VCI_SIZE_SHIFT  15              /* Shift to get size field */
 318 #define VCI_SIZE_MASK   7               /* Valid bits in size field */
 319 #define VCI_IN_SERVICE  1               /* Mask for IN_SERVICE field */
 320
 321 /*
 322  * Defines for VC mode
 323  */
 324 #define VCI_MODE_TRASH  0x00            /* Trash all cells for this VC */
 325 #define VCI_MODE_AAL0   0x01            /* Reassemble as AAL_0 PDU */
 326 #define VCI_MODE_AAL5   0x02            /* Reassemble as AAL_5 PDU */
 327 /*
 328  * Defines for handling cells with PTI(2) set to 1.
 329  */
 330 #define PTI_MODE_TRASH  0x00            /* Trash cell */
 331 #define PTI_MODE_PRESV  0x01            /* Send cell to OAM channel */
 332 /*
 333  * Current state of VC
 334  */
 335 #define VCI_STATE_IDLE  0x00            /* VC is idle */
 336 #define VCI_STATE_REASM 0x01            /* VC is reassembling PDU */
 337 #define VCI_STATE_TRASH 0x03            /* VC is trashing cells */
 338
 339 /*
 340  * RX Descriptor word values
 341  */
 342 #define DESCR_TRASH_BIT         0x1000  /* VCI was trashing cells */
 343 #define DESCR_CRC_ERR           0x0800  /* PDU has CRC error */
 344 #define DESCR_CELL_COUNT        0x07FF  /* Mask to get cell count */
 345 /*
 346  * TX Descriptor word values
 347  */
 348 #define TX_IDEN_SHIFT   28              /* Unique identifier location */
 349 #define TX_MODE_SHIFT   27              /* AAL5 or AAL0 */
 350 #define TX_VCI_SHIFT    4               /* Bits to shift VCI value */
 351
 352 /*
 353  * When setting up descriptor words (at head of segmentation queues), there
 354  * is a unique identifier used to help detect sync problems.
 355  */
 356 #define MIDWAY_UNQ_ID   0x0B
 357
 358 /*
 359  * Defines for cell sizes
 360  */
 361 #define BYTES_PER_CELL  48              /* Number of data bytes per cell */
 362 #define WORDS_PER_CELL  12              /* Number of data words per cell */
 363
 364 /*
 365  * Access to Serial EEPROM [as opposed to expansion (E)PROM].
 366  *
 367  * This is a ATMEL AT24C01 serial EEPROM part.
 368  * See http://www.atmel.com/atmel/products/prod162.htm for timimg diagrams
 369  * for START/STOP/ACK/READ cycles.
 370  */
 371 #define SEEPROM         PCI_CONTROL_REG /* Serial EEPROM is accessed thru */
 372                                         /* PCI control register           */
 373 #define SEPROM_DATA     0x02            /* SEEPROM DATA line */
 374 #define SEPROM_CLK      0x01            /* SEEPROM CLK line */
 375 #define SEPROM_SIZE     128             /* Size of Serial EEPROM */
 376 #define SEPROM_MAC_OFF  64              /* Offset to MAC address */
 377 #define SEPROM_SN_OFF   112             /* Offset to serial number */
 378 #define SEPROM_DELAY    10              /* Delay when strobing CLK/DATA lines */
 379
 380 /*
 381  * Host protocol control blocks
 382  *
 383  */
 384
 385 /*
 386  * Device VCC Entry
 387  *
 388  * Contains the common and ENI-specific information for each VCC
 389  * which is opened through a ENI device.
 390  */
 391 struct eni_vcc {
 392         struct cmn_vcc  ev_cmn;         /* Common VCC stuff */
 393         caddr_t         ev_rxbuf;       /* Receive buffer */
 394         u_long          ev_rxpos;       /* Adapter buffer read pointer */
 395 };
 396 typedef struct eni_vcc Eni_vcc;
 397
 398 #define ev_next         ev_cmn.cv_next
 399 #define ev_toku         ev_cmn.cv_toku
 400 #define ev_upper        ev_cmn.cv_upper
 401 #define ev_connvc       ev_cmn.cv_connvc
 402 #define ev_state        ev_cmn.cv_state
 403
 404 typedef volatile unsigned long *        Eni_mem;
 405
 406 /*
 407  * Define the ID's we'll look for in the PCI config
 408  * register when deciding if we'll support this device.
 409  * The DEV_ID will need to be turned into an array of
 410  * ID's in order to support multiple adapters with
 411  * the same driver.
 412  */
 413 #define EFF_VENDOR_ID   0x111A
 414 #define EFF_DEV_ID      0x0002
 415
 416 /*
 417  * Memory allocator defines and buffer descriptors
 418  */
 419 #define MEM_FREE        0
 420 #define MEM_INUSE       1
 421
 422 typedef struct mbd Mbd;
 423 struct mbd {
 424         Mbd     *prev;
 425         Mbd     *next;
 426         caddr_t base;                   /* Adapter base address */
 427         int     size;                   /* Size of buffer */
 428         int     state;                  /* INUSE or FREE */
 429 };
 430
 431 /*
 432  * We use a hack to allocate a smaller RX buffer for signalling
 433  * channels as they tend to have small MTU lengths.
 434  */
 435 #define UNI_SIG_VCI     5
 436
 437 /*
 438  * Device Unit Structure
 439  *
 440  * Contains all the information for a single device (adapter).
 441  */
 442 struct eni_unit {
 443         Cmn_unit        eu_cmn;         /* Common unit stuff */
 444         pcici_t         eu_pcitag;      /* PCI tag */
 445         Eni_mem         eu_base;        /* Adapter memory base */
 446         Eni_mem         eu_ram;         /* Adapter RAM */
 447         u_long          eu_ramsize;
 448
 449         Eni_mem         eu_suni;        /* SUNI registers */
 450
 451         Eni_mem         eu_midway;      /* MIDWAY registers */
 452
 453         VCI_Table       *eu_vcitbl;     /* VCI Table */
 454         Eni_mem         eu_rxdma;       /* Receive DMA queue */
 455         Eni_mem         eu_txdma;       /* Transmit DMA queue */
 456         Eni_mem         eu_svclist;     /* Service list */
 457         u_long          eu_servread;    /* Read pointer into Service list */
 458
 459         caddr_t         eu_txbuf;       /* One large TX buff for everything */
 460         u_long          eu_txsize;      /* Size of TX buffer */
 461         u_long          eu_txpos;       /* Current word being stored in RAM */
 462         u_long          eu_txfirst;     /* First word of unack'ed data */
 463
 464         u_long          eu_trash;
 465         u_long          eu_ovfl;
 466
 467         struct ifqueue  eu_txqueue;
 468         u_long          eu_txdmawr;
 469         struct ifqueue  eu_rxqueue;
 470         u_long          eu_rxdmawr;     /* DMA list write pointer */
 471
 472         u_char          eu_seeprom[SEPROM_SIZE]; /* Serial EEPROM contents */
 473         u_int           eu_sevar;       /* Unique (per unit) seeprom var. */
 474
 475         Mbd             *eu_memmap;     /* Adapter RAM memory allocator map */
 476         int             eu_memclicks[ENI_BUF_NBIT];/* Count of INUSE buffers */
 477
 478         Eni_stats       eu_stats;       /* Statistics */
 479
 480 };
 481 typedef struct eni_unit         Eni_unit;
 482
 483 #define eu_pif          eu_cmn.cu_pif
 484 #define eu_unit         eu_cmn.cu_unit
 485 #define eu_flags        eu_cmn.cu_flags
 486 #define eu_mtu          eu_cmn.cu_mtu
 487 #define eu_open_vcc     eu_cmn.cu_open_vcc
 488 #define eu_vcc          eu_cmn.cu_vcc
 489 #define eu_vcc_pool     eu_cmn.cu_vcc_pool
 490 #define eu_nif_pool     eu_cmn.cu_nif_pool
 491 #define eu_ioctl        eu_cmn.cu_ioctl
 492 #define eu_instvcc      eu_cmn.cu_instvcc
 493 #define eu_openvcc      eu_cmn.cu_openvcc
 494 #define eu_closevcc     eu_cmn.cu_closevcc
 495 #define eu_output       eu_cmn.cu_output
 496 #define eu_config       eu_cmn.cu_config
 497
 498 #endif  /* _ENI_ENI_H */