2 * Copyright (c) 2000 Doug Rabson
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
8 * 1. Redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer.
10 * 2. Redistributions in binary form must reproduce the above copyright
11 * notice, this list of conditions and the following disclaimer in the
12 * documentation and/or other materials provided with the distribution.
14 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
15 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
16 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
17 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
18 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
19 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
20 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
21 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
22 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
23 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
26 * $FreeBSD: src/sys/dev/agp/agp_intel.c,v 1.36 2007/11/12 21:51:36 jhb Exp $
27 * $DragonFly: src/sys/dev/agp/agp_intel.c,v 1.10 2008/01/07 01:34:58 corecode Exp $
32 #include <sys/param.h>
33 #include <sys/systm.h>
34 #include <sys/malloc.h>
35 #include <sys/kernel.h>
39 #include <bus/pci/pcivar.h>
40 #include <bus/pci/pcireg.h>
45 #include <vm/vm_object.h>
48 #define MAX_APSIZE 0x3f /* 256 MB */
50 struct agp_intel_softc
{
52 u_int32_t initial_aperture
; /* aperture size at startup */
53 struct agp_gatt
*gatt
;
55 u_int32_t current_aperture
; /* current aperture size */
59 agp_intel_match(device_t dev
)
61 if (pci_get_class(dev
) != PCIC_BRIDGE
62 || pci_get_subclass(dev
) != PCIS_BRIDGE_HOST
)
65 if (agp_find_caps(dev
) == 0)
68 switch (pci_get_devid(dev
)) {
69 /* Intel -- vendor 0x8086 */
71 return ("Intel 82443LX (440 LX) host to PCI bridge");
73 return ("Intel 82443BX (440 BX) host to PCI bridge");
75 return ("Intel 82443GX host to PCI bridge");
77 return ("Intel 82443GX host to AGP bridge");
79 return ("Intel 82815 (i815 GMCH) host to PCI bridge");
82 return ("Intel 82820 host to AGP bridge");
84 return ("Intel 82830 host to AGP bridge");
86 return ("Intel 82840 host to AGP bridge");
88 return ("Intel 82845 host to AGP bridge");
90 return ("Intel 82850 host to AGP bridge");
92 return ("Intel 82855 host to AGP bridge");
94 return ("Intel 82860 host to AGP bridge");
96 return ("Intel 82865 host to AGP bridge");
98 return ("Intel E7205 host to AGP bridge");
100 return ("Intel E7505 host to AGP bridge");
102 return ("Intel 82875P host to AGP bridge");
104 return ("Intel 82845G host to AGP bridge");
106 return ("Intel 82855GM host to AGP bridge");
113 agp_intel_probe(device_t dev
)
117 if (resource_disabled("agp", device_get_unit(dev
)))
119 desc
= agp_intel_match(dev
);
122 device_set_desc(dev
, desc
);
123 return (BUS_PROBE_DEFAULT
);
130 agp_intel_commit_gatt(device_t dev
)
132 struct agp_intel_softc
*sc
;
136 sc
= device_get_softc(dev
);
137 type
= pci_get_devid(dev
);
139 /* Install the gatt. */
140 pci_write_config(dev
, AGP_INTEL_ATTBASE
, sc
->gatt
->ag_physical
, 4);
142 /* Enable the GLTB and setup the control register. */
144 case 0x71908086: /* 440LX/EX */
145 pci_write_config(dev
, AGP_INTEL_AGPCTRL
, 0x2080, 4);
147 case 0x71808086: /* 440BX */
149 * XXX: Should be 0xa080? Bit 9 is undefined, and
150 * bit 13 being on and bit 15 being clear is illegal.
152 pci_write_config(dev
, AGP_INTEL_AGPCTRL
, 0x2280, 4);
155 value
= pci_read_config(dev
, AGP_INTEL_AGPCTRL
, 4);
156 pci_write_config(dev
, AGP_INTEL_AGPCTRL
, value
| 0x80, 4);
159 /* Enable aperture accesses. */
161 case 0x25008086: /* i820 */
162 case 0x25018086: /* i820 */
163 pci_write_config(dev
, AGP_INTEL_I820_RDCR
,
164 (pci_read_config(dev
, AGP_INTEL_I820_RDCR
, 1)
167 case 0x1a308086: /* i845 */
168 case 0x25608086: /* i845G */
169 case 0x33408086: /* i855 */
170 case 0x35808086: /* i855GM */
171 case 0x25708086: /* i865 */
172 case 0x25788086: /* i875P */
173 pci_write_config(dev
, AGP_INTEL_I845_AGPM
,
174 (pci_read_config(dev
, AGP_INTEL_I845_AGPM
, 1)
177 case 0x1a218086: /* i840 */
178 case 0x25308086: /* i850 */
179 case 0x25318086: /* i860 */
180 case 0x255d8086: /* E7205 */
181 case 0x25508086: /* E7505 */
182 pci_write_config(dev
, AGP_INTEL_MCHCFG
,
183 (pci_read_config(dev
, AGP_INTEL_MCHCFG
, 2)
186 default: /* Intel Generic (maybe) */
187 pci_write_config(dev
, AGP_INTEL_NBXCFG
,
188 (pci_read_config(dev
, AGP_INTEL_NBXCFG
, 4)
189 & ~(1 << 10)) | (1 << 9), 4);
194 case 0x1a218086: /* i840 */
195 pci_write_config(dev
, AGP_INTEL_I8XX_ERRSTS
, 0xc000, 2);
197 case 0x25008086: /* i820 */
198 case 0x25018086: /* i820 */
199 case 0x1a308086: /* i845 */
200 case 0x25608086: /* i845G */
201 case 0x25308086: /* i850 */
202 case 0x33408086: /* i855 */
203 case 0x25318086: /* i860 */
204 case 0x25708086: /* i865 */
205 case 0x25788086: /* i875P */
206 case 0x255d8086: /* E7205 */
207 case 0x25508086: /* E7505 */
208 pci_write_config(dev
, AGP_INTEL_I8XX_ERRSTS
, 0x00ff, 2);
210 default: /* Intel Generic (maybe) */
211 pci_write_config(dev
, AGP_INTEL_ERRSTS
+ 1, 7, 1);
216 agp_intel_attach(device_t dev
)
218 struct agp_intel_softc
*sc
;
219 struct agp_gatt
*gatt
;
223 sc
= device_get_softc(dev
);
225 error
= agp_generic_attach(dev
);
229 /* Determine maximum supported aperture size. */
230 value
= pci_read_config(dev
, AGP_INTEL_APSIZE
, 1);
231 pci_write_config(dev
, AGP_INTEL_APSIZE
, MAX_APSIZE
, 1);
232 sc
->aperture_mask
= pci_read_config(dev
, AGP_INTEL_APSIZE
, 1) &
234 pci_write_config(dev
, AGP_INTEL_APSIZE
, value
, 1);
235 sc
->current_aperture
= sc
->initial_aperture
= AGP_GET_APERTURE(dev
);
236 if (sc
->initial_aperture
== 0) {
237 device_printf(dev
, "bad initial aperture size, disabling\n");
242 gatt
= agp_alloc_gatt(dev
);
247 * Probably contigmalloc failure. Try reducing the
248 * aperture so that the gatt size reduces.
250 if (AGP_SET_APERTURE(dev
, AGP_GET_APERTURE(dev
) / 2)) {
251 agp_generic_detach(dev
);
257 agp_intel_commit_gatt(dev
);
263 agp_intel_detach(device_t dev
)
265 struct agp_intel_softc
*sc
;
268 sc
= device_get_softc(dev
);
272 /* Disable aperture accesses. */
273 switch (pci_get_devid(dev
)) {
274 case 0x25008086: /* i820 */
275 case 0x25018086: /* i820 */
276 reg
= pci_read_config(dev
, AGP_INTEL_I820_RDCR
, 1) & ~(1 << 1);
277 kprintf("%s: set RDCR to %02x\n", __func__
, reg
& 0xff);
278 pci_write_config(dev
, AGP_INTEL_I820_RDCR
, reg
, 1);
280 case 0x1a308086: /* i845 */
281 case 0x25608086: /* i845G */
282 case 0x33408086: /* i855 */
283 case 0x35808086: /* i855GM */
284 case 0x25708086: /* i865 */
285 case 0x25788086: /* i875P */
286 reg
= pci_read_config(dev
, AGP_INTEL_I845_AGPM
, 1) & ~(1 << 1);
287 kprintf("%s: set AGPM to %02x\n", __func__
, reg
& 0xff);
288 pci_write_config(dev
, AGP_INTEL_I845_AGPM
, reg
, 1);
290 case 0x1a218086: /* i840 */
291 case 0x25308086: /* i850 */
292 case 0x25318086: /* i860 */
293 case 0x255d8086: /* E7205 */
294 case 0x25508086: /* E7505 */
295 reg
= pci_read_config(dev
, AGP_INTEL_MCHCFG
, 2) & ~(1 << 9);
296 kprintf("%s: set MCHCFG to %x04\n", __func__
, reg
& 0xffff);
297 pci_write_config(dev
, AGP_INTEL_MCHCFG
, reg
, 2);
299 default: /* Intel Generic (maybe) */
300 reg
= pci_read_config(dev
, AGP_INTEL_NBXCFG
, 4) & ~(1 << 9);
301 kprintf("%s: set NBXCFG to %08x\n", __func__
, reg
);
302 pci_write_config(dev
, AGP_INTEL_NBXCFG
, reg
, 4);
304 pci_write_config(dev
, AGP_INTEL_ATTBASE
, 0, 4);
305 AGP_SET_APERTURE(dev
, sc
->initial_aperture
);
306 agp_free_gatt(sc
->gatt
);
313 agp_intel_resume(device_t dev
)
315 struct agp_intel_softc
*sc
;
316 sc
= device_get_softc(dev
);
318 AGP_SET_APERTURE(dev
, sc
->current_aperture
);
319 agp_intel_commit_gatt(dev
);
320 return (bus_generic_resume(dev
));
324 agp_intel_get_aperture(device_t dev
)
326 struct agp_intel_softc
*sc
;
329 sc
= device_get_softc(dev
);
331 apsize
= pci_read_config(dev
, AGP_INTEL_APSIZE
, 1) & sc
->aperture_mask
;
334 * The size is determined by the number of low bits of
335 * register APBASE which are forced to zero. The low 22 bits
336 * are always forced to zero and each zero bit in the apsize
337 * field just read forces the corresponding bit in the 27:22
338 * to be zero. We calculate the aperture size accordingly.
340 return ((((apsize
^ sc
->aperture_mask
) << 22) | ((1 << 22) - 1)) + 1);
344 agp_intel_set_aperture(device_t dev
, u_int32_t aperture
)
346 struct agp_intel_softc
*sc
;
349 sc
= device_get_softc(dev
);
352 * Reverse the magic from get_aperture.
354 apsize
= ((aperture
- 1) >> 22) ^ sc
->aperture_mask
;
357 * Double check for sanity.
359 if ((((apsize
^ sc
->aperture_mask
) << 22) | ((1 << 22) - 1)) + 1 != aperture
)
362 sc
->current_aperture
= apsize
;
364 pci_write_config(dev
, AGP_INTEL_APSIZE
, apsize
, 1);
370 agp_intel_bind_page(device_t dev
, int offset
, vm_offset_t physical
)
372 struct agp_intel_softc
*sc
;
374 sc
= device_get_softc(dev
);
376 if (offset
< 0 || offset
>= (sc
->gatt
->ag_entries
<< AGP_PAGE_SHIFT
))
379 sc
->gatt
->ag_virtual
[offset
>> AGP_PAGE_SHIFT
] = physical
| 0x17;
384 agp_intel_unbind_page(device_t dev
, int offset
)
386 struct agp_intel_softc
*sc
;
388 sc
= device_get_softc(dev
);
390 if (offset
< 0 || offset
>= (sc
->gatt
->ag_entries
<< AGP_PAGE_SHIFT
))
393 sc
->gatt
->ag_virtual
[offset
>> AGP_PAGE_SHIFT
] = 0;
398 agp_intel_flush_tlb(device_t dev
)
402 val
= pci_read_config(dev
, AGP_INTEL_AGPCTRL
, 4);
403 pci_write_config(dev
, AGP_INTEL_AGPCTRL
, val
& ~(1 << 7), 4);
404 pci_write_config(dev
, AGP_INTEL_AGPCTRL
, val
, 4);
407 static device_method_t agp_intel_methods
[] = {
408 /* Device interface */
409 DEVMETHOD(device_probe
, agp_intel_probe
),
410 DEVMETHOD(device_attach
, agp_intel_attach
),
411 DEVMETHOD(device_detach
, agp_intel_detach
),
412 DEVMETHOD(device_shutdown
, bus_generic_shutdown
),
413 DEVMETHOD(device_suspend
, bus_generic_suspend
),
414 DEVMETHOD(device_resume
, agp_intel_resume
),
417 DEVMETHOD(agp_get_aperture
, agp_intel_get_aperture
),
418 DEVMETHOD(agp_set_aperture
, agp_intel_set_aperture
),
419 DEVMETHOD(agp_bind_page
, agp_intel_bind_page
),
420 DEVMETHOD(agp_unbind_page
, agp_intel_unbind_page
),
421 DEVMETHOD(agp_flush_tlb
, agp_intel_flush_tlb
),
422 DEVMETHOD(agp_enable
, agp_generic_enable
),
423 DEVMETHOD(agp_alloc_memory
, agp_generic_alloc_memory
),
424 DEVMETHOD(agp_free_memory
, agp_generic_free_memory
),
425 DEVMETHOD(agp_bind_memory
, agp_generic_bind_memory
),
426 DEVMETHOD(agp_unbind_memory
, agp_generic_unbind_memory
),
431 static driver_t agp_intel_driver
= {
434 sizeof(struct agp_intel_softc
),
437 static devclass_t agp_devclass
;
439 DRIVER_MODULE(agp_intel
, pci
, agp_intel_driver
, agp_devclass
, 0, 0);
440 MODULE_DEPEND(agp_intel
, agp
, 1, 1, 1);
441 MODULE_DEPEND(agp_intel
, pci
, 1, 1, 1);