3 * Joerg Sonnenberger <joerg@bec.de>. All rights reserved.
5 * Copyright (c) 1997, 1998-2003
6 * Bill Paul <wpaul@windriver.com>. All rights reserved.
8 * Redistribution and use in source and binary forms, with or without
9 * modification, are permitted provided that the following conditions
11 * 1. Redistributions of source code must retain the above copyright
12 * notice, this list of conditions and the following disclaimer.
13 * 2. Redistributions in binary form must reproduce the above copyright
14 * notice, this list of conditions and the following disclaimer in the
15 * documentation and/or other materials provided with the distribution.
16 * 3. All advertising materials mentioning features or use of this software
17 * must display the following acknowledgement:
18 * This product includes software developed by Bill Paul.
19 * 4. Neither the name of the author nor the names of any co-contributors
20 * may be used to endorse or promote products derived from this software
21 * without specific prior written permission.
23 * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND
24 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
25 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
26 * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD
27 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
28 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
29 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
30 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
31 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
32 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
33 * THE POSSIBILITY OF SUCH DAMAGE.
35 * $FreeBSD: src/sys/dev/re/if_re.c,v 1.25 2004/06/09 14:34:01 naddy Exp $
39 * RealTek 8139C+/8169/8169S/8110S/8168/8111/8101E PCI NIC driver
41 * Written by Bill Paul <wpaul@windriver.com>
42 * Senior Networking Software Engineer
47 * This driver is designed to support RealTek's next generation of
48 * 10/100 and 10/100/1000 PCI ethernet controllers. There are currently
49 * seven devices in this family: the RTL8139C+, the RTL8169, the RTL8169S,
50 * RTL8110S, the RTL8168, the RTL8111 and the RTL8101E.
52 * The 8139C+ is a 10/100 ethernet chip. It is backwards compatible
53 * with the older 8139 family, however it also supports a special
54 * C+ mode of operation that provides several new performance enhancing
55 * features. These include:
57 * o Descriptor based DMA mechanism. Each descriptor represents
58 * a single packet fragment. Data buffers may be aligned on
63 * o TCP/IP checksum offload for both RX and TX
65 * o High and normal priority transmit DMA rings
67 * o VLAN tag insertion and extraction
69 * o TCP large send (segmentation offload)
71 * Like the 8139, the 8139C+ also has a built-in 10/100 PHY. The C+
72 * programming API is fairly straightforward. The RX filtering, EEPROM
73 * access and PHY access is the same as it is on the older 8139 series
76 * The 8169 is a 64-bit 10/100/1000 gigabit ethernet MAC. It has almost the
77 * same programming API and feature set as the 8139C+ with the following
78 * differences and additions:
84 * o GMII and TBI ports/registers for interfacing with copper
87 * o RX and TX DMA rings can have up to 1024 descriptors
88 * (the 8139C+ allows a maximum of 64)
90 * o Slight differences in register layout from the 8139C+
92 * The TX start and timer interrupt registers are at different locations
93 * on the 8169 than they are on the 8139C+. Also, the status word in the
94 * RX descriptor has a slightly different bit layout. The 8169 does not
95 * have a built-in PHY. Most reference boards use a Marvell 88E1000 'Alaska'
98 * The 8169S/8110S 10/100/1000 devices have built-in copper gigE PHYs
99 * (the 'S' stands for 'single-chip'). These devices have the same
100 * programming API as the older 8169, but also have some vendor-specific
101 * registers for the on-board PHY. The 8110S is a LAN-on-motherboard
102 * part designed to be pin-compatible with the RealTek 8100 10/100 chip.
104 * This driver takes advantage of the RX and TX checksum offload and
105 * VLAN tag insertion/extraction features. It also implements TX
106 * interrupt moderation using the timer interrupt registers, which
107 * significantly reduces TX interrupt load. There is also support
108 * for jumbo frames, however the 8169/8169S/8110S can not transmit
109 * jumbo frames larger than 7440, so the max MTU possible with this
110 * driver is 7422 bytes.
115 #include "opt_ifpoll.h"
117 #include <sys/param.h>
119 #include <sys/endian.h>
120 #include <sys/kernel.h>
121 #include <sys/in_cksum.h>
122 #include <sys/interrupt.h>
123 #include <sys/malloc.h>
124 #include <sys/mbuf.h>
125 #include <sys/rman.h>
126 #include <sys/serialize.h>
127 #include <sys/socket.h>
128 #include <sys/sockio.h>
129 #include <sys/sysctl.h>
132 #include <net/ethernet.h>
134 #include <net/ifq_var.h>
135 #include <net/if_arp.h>
136 #include <net/if_dl.h>
137 #include <net/if_media.h>
138 #include <net/if_poll.h>
139 #include <net/if_types.h>
140 #include <net/vlan/if_vlan_var.h>
141 #include <net/vlan/if_vlan_ether.h>
143 #include <netinet/ip.h>
145 #include <dev/netif/mii_layer/mii.h>
146 #include <dev/netif/mii_layer/miivar.h>
149 #include <bus/pci/pcireg.h>
150 #include <bus/pci/pcivar.h>
152 /* "device miibus" required. See GENERIC if you get errors here. */
153 #include "miibus_if.h"
155 #include <dev/netif/re/if_rereg.h>
156 #include <dev/netif/re/if_revar.h>
159 * Various supported device vendors/types and their names.
161 static const struct re_type
{
166 { PCI_VENDOR_DLINK
, PCI_PRODUCT_DLINK_DGE528T
,
167 "D-Link DGE-528(T) Gigabit Ethernet Adapter" },
169 { PCI_VENDOR_REALTEK
, PCI_PRODUCT_REALTEK_RT8139
,
170 "RealTek 8139C+ 10/100BaseTX" },
172 { PCI_VENDOR_REALTEK
, PCI_PRODUCT_REALTEK_RT8101E
,
173 "RealTek 810x PCIe 10/100baseTX" },
175 { PCI_VENDOR_REALTEK
, PCI_PRODUCT_REALTEK_RT8168
,
176 "RealTek 8111/8168 PCIe Gigabit Ethernet" },
178 { PCI_VENDOR_REALTEK
, PCI_PRODUCT_REALTEK_RT8169
,
179 "RealTek 8110/8169 Gigabit Ethernet" },
181 { PCI_VENDOR_REALTEK
, PCI_PRODUCT_REALTEK_RT8169SC
,
182 "RealTek 8169SC/8110SC Single-chip Gigabit Ethernet" },
184 { PCI_VENDOR_COREGA
, PCI_PRODUCT_COREGA_CG_LAPCIGT
,
185 "Corega CG-LAPCIGT Gigabit Ethernet" },
187 { PCI_VENDOR_LINKSYS
, PCI_PRODUCT_LINKSYS_EG1032
,
188 "Linksys EG1032 Gigabit Ethernet" },
190 { PCI_VENDOR_USR2
, PCI_PRODUCT_USR2_997902
,
191 "US Robotics 997902 Gigabit Ethernet" },
193 { PCI_VENDOR_TTTECH
, PCI_PRODUCT_TTTECH_MC322
,
194 "TTTech MC322 Gigabit Ethernet" },
199 static const struct re_hwrev re_hwrevs
[] = {
200 { RE_HWREV_8139CPLUS
, ETHERMTU
,
201 RE_C_HWCSUM
| RE_C_8139CP
| RE_C_FASTE
},
203 { RE_HWREV_8169
, ETHERMTU
,
204 RE_C_HWCSUM
| RE_C_8169
},
206 { RE_HWREV_8110S
, RE_MTU_6K
,
207 RE_C_HWCSUM
| RE_C_8169
},
209 { RE_HWREV_8169S
, RE_MTU_6K
,
210 RE_C_HWCSUM
| RE_C_8169
},
212 { RE_HWREV_8169SB
, RE_MTU_6K
,
213 RE_C_HWCSUM
| RE_C_PHYPMGT
| RE_C_8169
},
215 { RE_HWREV_8169SC
, RE_MTU_6K
,
216 RE_C_HWCSUM
| RE_C_PHYPMGT
| RE_C_8169
},
218 { RE_HWREV_8168B1
, RE_MTU_6K
,
219 RE_C_HWIM
| RE_C_HWCSUM
| RE_C_PHYPMGT
},
221 { RE_HWREV_8168B2
, RE_MTU_6K
,
222 RE_C_HWIM
| RE_C_HWCSUM
| RE_C_PHYPMGT
| RE_C_AUTOPAD
},
224 { RE_HWREV_8168C
, RE_MTU_6K
,
225 RE_C_HWIM
| RE_C_HWCSUM
| RE_C_MAC2
| RE_C_PHYPMGT
|
226 RE_C_AUTOPAD
| RE_C_CONTIGRX
| RE_C_STOP_RXTX
},
228 { RE_HWREV_8168CP
, RE_MTU_6K
,
229 RE_C_HWIM
| RE_C_HWCSUM
| RE_C_MAC2
| RE_C_PHYPMGT
|
230 RE_C_AUTOPAD
| RE_C_CONTIGRX
| RE_C_STOP_RXTX
},
232 { RE_HWREV_8168D
, RE_MTU_9K
,
233 RE_C_HWIM
| RE_C_HWCSUM
| RE_C_MAC2
| RE_C_PHYPMGT
|
234 RE_C_AUTOPAD
| RE_C_CONTIGRX
| RE_C_STOP_RXTX
},
236 { RE_HWREV_8168DP
, RE_MTU_9K
,
237 RE_C_HWIM
| RE_C_HWCSUM
| RE_C_MAC2
| RE_C_PHYPMGT
|
238 RE_C_AUTOPAD
| RE_C_CONTIGRX
| RE_C_STOP_RXTX
},
240 { RE_HWREV_8168E
, RE_MTU_9K
,
241 RE_C_HWIM
| RE_C_HWCSUM
| RE_C_MAC2
| RE_C_PHYPMGT
|
242 RE_C_AUTOPAD
| RE_C_CONTIGRX
| RE_C_STOP_RXTX
},
244 { RE_HWREV_8168F
, RE_MTU_9K
,
245 RE_C_HWIM
| RE_C_HWCSUM
| RE_C_MAC2
| RE_C_PHYPMGT
|
246 RE_C_AUTOPAD
| RE_C_CONTIGRX
| RE_C_STOP_RXTX
},
248 { RE_HWREV_8111F
, RE_MTU_9K
,
249 RE_C_HWIM
| RE_C_HWCSUM
| RE_C_MAC2
| RE_C_PHYPMGT
|
250 RE_C_AUTOPAD
| RE_C_CONTIGRX
| RE_C_STOP_RXTX
},
252 { RE_HWREV_8411
, ETHERMTU
,
253 RE_C_HWIM
| RE_C_HWCSUM
| RE_C_MAC2
| RE_C_PHYPMGT
|
254 RE_C_AUTOPAD
| RE_C_CONTIGRX
| RE_C_STOP_RXTX
},
256 { RE_HWREV_8168G
, ETHERMTU
,
257 RE_C_HWIM
| RE_C_HWCSUM
| RE_C_MAC2
| RE_C_PHYPMGT
|
258 RE_C_AUTOPAD
| RE_C_CONTIGRX
| RE_C_STOP_RXTX
},
260 { RE_HWREV_8168EP
, ETHERMTU
,
261 RE_C_HWIM
| RE_C_HWCSUM
| RE_C_MAC2
| RE_C_PHYPMGT
|
262 RE_C_AUTOPAD
| RE_C_CONTIGRX
| RE_C_STOP_RXTX
},
264 { RE_HWREV_8168GU
, ETHERMTU
,
265 RE_C_HWIM
| RE_C_HWCSUM
| RE_C_MAC2
| RE_C_PHYPMGT
|
266 RE_C_AUTOPAD
| RE_C_CONTIGRX
| RE_C_STOP_RXTX
},
268 { RE_HWREV_8168H
, ETHERMTU
,
269 RE_C_HWIM
| RE_C_HWCSUM
| RE_C_MAC2
| RE_C_PHYPMGT
|
270 RE_C_AUTOPAD
| RE_C_CONTIGRX
| RE_C_STOP_RXTX
},
272 { RE_HWREV_8411B
, ETHERMTU
,
273 RE_C_HWIM
| RE_C_HWCSUM
| RE_C_MAC2
| RE_C_PHYPMGT
|
274 RE_C_AUTOPAD
| RE_C_CONTIGRX
| RE_C_STOP_RXTX
},
276 { RE_HWREV_8100E
, ETHERMTU
,
277 RE_C_HWCSUM
| RE_C_FASTE
},
279 { RE_HWREV_8101E
, ETHERMTU
,
280 RE_C_HWCSUM
| RE_C_FASTE
},
282 { RE_HWREV_8102E
, ETHERMTU
,
283 RE_C_HWCSUM
| RE_C_MAC2
| RE_C_AUTOPAD
| RE_C_STOP_RXTX
|
286 { RE_HWREV_8102EL
, ETHERMTU
,
287 RE_C_HWCSUM
| RE_C_MAC2
| RE_C_AUTOPAD
| RE_C_STOP_RXTX
|
290 { RE_HWREV_8105E
, ETHERMTU
,
291 RE_C_HWCSUM
| RE_C_MAC2
| RE_C_PHYPMGT
| RE_C_AUTOPAD
|
292 RE_C_STOP_RXTX
| RE_C_FASTE
},
294 { RE_HWREV_8401E
, ETHERMTU
,
295 RE_C_HWCSUM
| RE_C_MAC2
| RE_C_PHYPMGT
| RE_C_AUTOPAD
|
296 RE_C_STOP_RXTX
| RE_C_FASTE
},
298 { RE_HWREV_8402
, ETHERMTU
,
299 RE_C_HWCSUM
| RE_C_MAC2
| RE_C_PHYPMGT
| RE_C_AUTOPAD
|
300 RE_C_STOP_RXTX
| RE_C_FASTE
},
302 { RE_HWREV_8106E
, ETHERMTU
,
303 RE_C_HWCSUM
| RE_C_MAC2
| RE_C_PHYPMGT
| RE_C_AUTOPAD
|
304 RE_C_STOP_RXTX
| RE_C_FASTE
},
306 { RE_HWREV_NULL
, 0, 0 }
309 static int re_probe(device_t
);
310 static int re_attach(device_t
);
311 static int re_detach(device_t
);
312 static int re_suspend(device_t
);
313 static int re_resume(device_t
);
314 static void re_shutdown(device_t
);
316 static int re_allocmem(device_t
);
317 static void re_freemem(device_t
);
318 static void re_freebufmem(struct re_softc
*, int, int);
319 static int re_encap(struct re_softc
*, struct mbuf
**, int *);
320 static int re_newbuf_std(struct re_softc
*, int, int);
321 static int re_newbuf_jumbo(struct re_softc
*, int, int);
322 static void re_setup_rxdesc(struct re_softc
*, int);
323 static int re_rx_list_init(struct re_softc
*);
324 static int re_tx_list_init(struct re_softc
*);
325 static int re_rxeof(struct re_softc
*);
326 static int re_txeof(struct re_softc
*);
327 static int re_tx_collect(struct re_softc
*);
328 static void re_intr(void *);
329 static void re_tick(void *);
330 static void re_tick_serialized(void *);
332 static void re_start(struct ifnet
*, struct ifaltq_subque
*);
333 static int re_ioctl(struct ifnet
*, u_long
, caddr_t
, struct ucred
*);
334 static void re_init(void *);
335 static void re_stop(struct re_softc
*);
336 static void re_watchdog(struct ifnet
*);
337 static int re_ifmedia_upd(struct ifnet
*);
338 static void re_ifmedia_sts(struct ifnet
*, struct ifmediareq
*);
340 static void re_eeprom_putbyte(struct re_softc
*, int);
341 static void re_eeprom_getword(struct re_softc
*, int, u_int16_t
*);
342 static void re_read_eeprom(struct re_softc
*, caddr_t
, int, int);
343 static void re_get_eewidth(struct re_softc
*);
345 static int re_gmii_readreg(device_t
, int, int);
346 static int re_gmii_writereg(device_t
, int, int, int);
348 static int re_miibus_readreg(device_t
, int, int);
349 static int re_miibus_writereg(device_t
, int, int, int);
350 static void re_miibus_statchg(device_t
);
352 static void re_setmulti(struct re_softc
*);
353 static void re_reset(struct re_softc
*, int);
354 static void re_get_eaddr(struct re_softc
*, uint8_t *);
356 static void re_setup_hw_im(struct re_softc
*);
357 static void re_setup_sim_im(struct re_softc
*);
358 static void re_disable_hw_im(struct re_softc
*);
359 static void re_disable_sim_im(struct re_softc
*);
360 static void re_config_imtype(struct re_softc
*, int);
361 static void re_setup_intr(struct re_softc
*, int, int);
363 static int re_sysctl_hwtime(SYSCTL_HANDLER_ARGS
, int *);
364 static int re_sysctl_rxtime(SYSCTL_HANDLER_ARGS
);
365 static int re_sysctl_txtime(SYSCTL_HANDLER_ARGS
);
366 static int re_sysctl_simtime(SYSCTL_HANDLER_ARGS
);
367 static int re_sysctl_imtype(SYSCTL_HANDLER_ARGS
);
369 static int re_jpool_alloc(struct re_softc
*);
370 static void re_jpool_free(struct re_softc
*);
371 static struct re_jbuf
*re_jbuf_alloc(struct re_softc
*);
372 static void re_jbuf_free(void *);
373 static void re_jbuf_ref(void *);
376 static int re_diag(struct re_softc
*);
380 static void re_npoll(struct ifnet
*, struct ifpoll_info
*);
381 static void re_npoll_compat(struct ifnet
*, void *, int);
384 static device_method_t re_methods
[] = {
385 /* Device interface */
386 DEVMETHOD(device_probe
, re_probe
),
387 DEVMETHOD(device_attach
, re_attach
),
388 DEVMETHOD(device_detach
, re_detach
),
389 DEVMETHOD(device_suspend
, re_suspend
),
390 DEVMETHOD(device_resume
, re_resume
),
391 DEVMETHOD(device_shutdown
, re_shutdown
),
394 DEVMETHOD(bus_print_child
, bus_generic_print_child
),
395 DEVMETHOD(bus_driver_added
, bus_generic_driver_added
),
398 DEVMETHOD(miibus_readreg
, re_miibus_readreg
),
399 DEVMETHOD(miibus_writereg
, re_miibus_writereg
),
400 DEVMETHOD(miibus_statchg
, re_miibus_statchg
),
405 static driver_t re_driver
= {
408 sizeof(struct re_softc
)
411 static devclass_t re_devclass
;
413 DECLARE_DUMMY_MODULE(if_re
);
414 MODULE_DEPEND(if_re
, miibus
, 1, 1, 1);
415 DRIVER_MODULE(if_re
, pci
, re_driver
, re_devclass
, NULL
, NULL
);
416 DRIVER_MODULE(if_re
, cardbus
, re_driver
, re_devclass
, NULL
, NULL
);
417 DRIVER_MODULE(miibus
, re
, miibus_driver
, miibus_devclass
, NULL
, NULL
);
419 static int re_rx_desc_count
= RE_RX_DESC_CNT_DEF
;
420 static int re_tx_desc_count
= RE_TX_DESC_CNT_DEF
;
421 static int re_msi_enable
= 0;
423 TUNABLE_INT("hw.re.rx_desc_count", &re_rx_desc_count
);
424 TUNABLE_INT("hw.re.tx_desc_count", &re_tx_desc_count
);
425 TUNABLE_INT("hw.re.msi.enable", &re_msi_enable
);
428 CSR_WRITE_1(sc, RE_EECMD, CSR_READ_1(sc, RE_EECMD) | (x))
431 CSR_WRITE_1(sc, RE_EECMD, CSR_READ_1(sc, RE_EECMD) & ~(x))
434 re_free_rxchain(struct re_softc
*sc
)
436 if (sc
->re_head
!= NULL
) {
437 m_freem(sc
->re_head
);
438 sc
->re_head
= sc
->re_tail
= NULL
;
443 * Send a read command and address to the EEPROM, check for ACK.
446 re_eeprom_putbyte(struct re_softc
*sc
, int addr
)
450 d
= addr
| (RE_9346_READ
<< sc
->re_eewidth
);
453 * Feed in each bit and strobe the clock.
455 for (i
= 1 << (sc
->re_eewidth
+ 3); i
; i
>>= 1) {
457 EE_SET(RE_EE_DATAIN
);
459 EE_CLR(RE_EE_DATAIN
);
469 * Read a word of data stored in the EEPROM at address 'addr.'
472 re_eeprom_getword(struct re_softc
*sc
, int addr
, uint16_t *dest
)
478 * Send address of word we want to read.
480 re_eeprom_putbyte(sc
, addr
);
483 * Start reading bits from EEPROM.
485 for (i
= 0x8000; i
!= 0; i
>>= 1) {
488 if (CSR_READ_1(sc
, RE_EECMD
) & RE_EE_DATAOUT
)
498 * Read a sequence of words from the EEPROM.
501 re_read_eeprom(struct re_softc
*sc
, caddr_t dest
, int off
, int cnt
)
504 uint16_t word
= 0, *ptr
;
506 CSR_SETBIT_1(sc
, RE_EECMD
, RE_EEMODE_PROGRAM
);
509 for (i
= 0; i
< cnt
; i
++) {
510 CSR_SETBIT_1(sc
, RE_EECMD
, RE_EE_SEL
);
511 re_eeprom_getword(sc
, off
+ i
, &word
);
512 CSR_CLRBIT_1(sc
, RE_EECMD
, RE_EE_SEL
);
513 ptr
= (uint16_t *)(dest
+ (i
* 2));
517 CSR_CLRBIT_1(sc
, RE_EECMD
, RE_EEMODE_PROGRAM
);
521 re_get_eewidth(struct re_softc
*sc
)
526 re_read_eeprom(sc
, (caddr_t
)&re_did
, 0, 1);
527 if (re_did
!= 0x8129)
532 re_gmii_readreg(device_t dev
, int phy
, int reg
)
534 struct re_softc
*sc
= device_get_softc(dev
);
541 /* Let the rgephy driver read the GMEDIASTAT register */
543 if (reg
== RE_GMEDIASTAT
)
544 return(CSR_READ_1(sc
, RE_GMEDIASTAT
));
546 CSR_WRITE_4(sc
, RE_PHYAR
, reg
<< 16);
549 for (i
= 0; i
< RE_TIMEOUT
; i
++) {
550 rval
= CSR_READ_4(sc
, RE_PHYAR
);
551 if (rval
& RE_PHYAR_BUSY
)
556 if (i
== RE_TIMEOUT
) {
557 device_printf(dev
, "PHY read failed\n");
561 return(rval
& RE_PHYAR_PHYDATA
);
565 re_gmii_writereg(device_t dev
, int phy
, int reg
, int data
)
567 struct re_softc
*sc
= device_get_softc(dev
);
571 CSR_WRITE_4(sc
, RE_PHYAR
,
572 (reg
<< 16) | (data
& RE_PHYAR_PHYDATA
) | RE_PHYAR_BUSY
);
575 for (i
= 0; i
< RE_TIMEOUT
; i
++) {
576 rval
= CSR_READ_4(sc
, RE_PHYAR
);
577 if ((rval
& RE_PHYAR_BUSY
) == 0)
583 device_printf(dev
, "PHY write failed\n");
589 re_miibus_readreg(device_t dev
, int phy
, int reg
)
591 struct re_softc
*sc
= device_get_softc(dev
);
593 uint16_t re8139_reg
= 0;
595 if (!RE_IS_8139CP(sc
)) {
596 rval
= re_gmii_readreg(dev
, phy
, reg
);
600 /* Pretend the internal PHY is only at address 0 */
606 re8139_reg
= RE_BMCR
;
609 re8139_reg
= RE_BMSR
;
612 re8139_reg
= RE_ANAR
;
615 re8139_reg
= RE_ANER
;
618 re8139_reg
= RE_LPAR
;
624 * Allow the rlphy driver to read the media status
625 * register. If we have a link partner which does not
626 * support NWAY, this is the register which will tell
627 * us the results of parallel detection.
630 return(CSR_READ_1(sc
, RE_MEDIASTAT
));
632 device_printf(dev
, "bad phy register\n");
635 rval
= CSR_READ_2(sc
, re8139_reg
);
636 if (re8139_reg
== RE_BMCR
) {
637 /* 8139C+ has different bit layout. */
638 rval
&= ~(BMCR_LOOP
| BMCR_ISO
);
644 re_miibus_writereg(device_t dev
, int phy
, int reg
, int data
)
646 struct re_softc
*sc
= device_get_softc(dev
);
647 u_int16_t re8139_reg
= 0;
649 if (!RE_IS_8139CP(sc
))
650 return(re_gmii_writereg(dev
, phy
, reg
, data
));
652 /* Pretend the internal PHY is only at address 0 */
658 re8139_reg
= RE_BMCR
;
659 /* 8139C+ has different bit layout. */
660 data
&= ~(BMCR_LOOP
| BMCR_ISO
);
663 re8139_reg
= RE_BMSR
;
666 re8139_reg
= RE_ANAR
;
669 re8139_reg
= RE_ANER
;
672 re8139_reg
= RE_LPAR
;
678 device_printf(dev
, "bad phy register\n");
681 CSR_WRITE_2(sc
, re8139_reg
, data
);
686 re_miibus_statchg(device_t dev
)
691 * Program the 64-bit multicast hash filter.
694 re_setmulti(struct re_softc
*sc
)
696 struct ifnet
*ifp
= &sc
->arpcom
.ac_if
;
698 uint32_t hashes
[2] = { 0, 0 };
699 struct ifmultiaddr
*ifma
;
703 rxfilt
= CSR_READ_4(sc
, RE_RXCFG
);
705 /* Set the individual bit to receive frames for this host only. */
706 rxfilt
|= RE_RXCFG_RX_INDIV
;
707 /* Set capture broadcast bit to capture broadcast frames. */
708 rxfilt
|= RE_RXCFG_RX_BROAD
;
710 rxfilt
&= ~(RE_RXCFG_RX_ALLPHYS
| RE_RXCFG_RX_MULTI
);
711 if ((ifp
->if_flags
& IFF_ALLMULTI
) || (ifp
->if_flags
& IFF_PROMISC
)) {
712 rxfilt
|= RE_RXCFG_RX_MULTI
;
714 /* If we want promiscuous mode, set the allframes bit. */
715 if (ifp
->if_flags
& IFF_PROMISC
)
716 rxfilt
|= RE_RXCFG_RX_ALLPHYS
;
718 CSR_WRITE_4(sc
, RE_RXCFG
, rxfilt
);
719 CSR_WRITE_4(sc
, RE_MAR0
, 0xFFFFFFFF);
720 CSR_WRITE_4(sc
, RE_MAR4
, 0xFFFFFFFF);
724 /* first, zot all the existing hash bits */
725 CSR_WRITE_4(sc
, RE_MAR0
, 0);
726 CSR_WRITE_4(sc
, RE_MAR4
, 0);
728 /* now program new ones */
729 TAILQ_FOREACH(ifma
, &ifp
->if_multiaddrs
, ifma_link
) {
730 if (ifma
->ifma_addr
->sa_family
!= AF_LINK
)
732 h
= ether_crc32_be(LLADDR((struct sockaddr_dl
*)
733 ifma
->ifma_addr
), ETHER_ADDR_LEN
) >> 26;
735 hashes
[0] |= (1 << h
);
737 hashes
[1] |= (1 << (h
- 32));
742 rxfilt
|= RE_RXCFG_RX_MULTI
;
744 rxfilt
&= ~RE_RXCFG_RX_MULTI
;
746 CSR_WRITE_4(sc
, RE_RXCFG
, rxfilt
);
749 * For some unfathomable reason, RealTek decided to reverse
750 * the order of the multicast hash registers in the PCI Express
751 * parts. This means we have to write the hash pattern in reverse
752 * order for those devices.
754 if (sc
->re_caps
& RE_C_PCIE
) {
755 CSR_WRITE_4(sc
, RE_MAR0
, bswap32(hashes
[1]));
756 CSR_WRITE_4(sc
, RE_MAR4
, bswap32(hashes
[0]));
758 CSR_WRITE_4(sc
, RE_MAR0
, hashes
[0]);
759 CSR_WRITE_4(sc
, RE_MAR4
, hashes
[1]);
764 re_reset(struct re_softc
*sc
, int running
)
768 if ((sc
->re_caps
& RE_C_STOP_RXTX
) && running
) {
769 CSR_WRITE_1(sc
, RE_COMMAND
,
770 RE_CMD_STOPREQ
| RE_CMD_TX_ENB
| RE_CMD_RX_ENB
);
774 CSR_WRITE_1(sc
, RE_COMMAND
, RE_CMD_RESET
);
776 for (i
= 0; i
< RE_TIMEOUT
; i
++) {
778 if ((CSR_READ_1(sc
, RE_COMMAND
) & RE_CMD_RESET
) == 0)
782 if_printf(&sc
->arpcom
.ac_if
, "reset never completed!\n");
787 * The following routine is designed to test for a defect on some
788 * 32-bit 8169 cards. Some of these NICs have the REQ64# and ACK64#
789 * lines connected to the bus, however for a 32-bit only card, they
790 * should be pulled high. The result of this defect is that the
791 * NIC will not work right if you plug it into a 64-bit slot: DMA
792 * operations will be done with 64-bit transfers, which will fail
793 * because the 64-bit data lines aren't connected.
795 * There's no way to work around this (short of talking a soldering
796 * iron to the board), however we can detect it. The method we use
797 * here is to put the NIC into digital loopback mode, set the receiver
798 * to promiscuous mode, and then try to send a frame. We then compare
799 * the frame data we sent to what was received. If the data matches,
800 * then the NIC is working correctly, otherwise we know the user has
801 * a defective NIC which has been mistakenly plugged into a 64-bit PCI
802 * slot. In the latter case, there's no way the NIC can work correctly,
803 * so we print out a message on the console and abort the device attach.
807 re_diag(struct re_softc
*sc
)
809 struct ifnet
*ifp
= &sc
->arpcom
.ac_if
;
811 struct ether_header
*eh
;
812 struct re_desc
*cur_rx
;
814 int total_len
, i
, error
= 0, phyaddr
;
815 uint8_t dst
[ETHER_ADDR_LEN
] = { 0x00, 'h', 'e', 'l', 'l', 'o' };
816 uint8_t src
[ETHER_ADDR_LEN
] = { 0x00, 'w', 'o', 'r', 'l', 'd' };
817 char ethstr
[2][ETHER_ADDRSTRLEN
+ 1];
819 /* Allocate a single mbuf */
821 MGETHDR(m0
, M_NOWAIT
, MT_DATA
);
826 * Initialize the NIC in test mode. This sets the chip up
827 * so that it can send and receive frames, but performs the
828 * following special functions:
829 * - Puts receiver in promiscuous mode
830 * - Enables digital loopback mode
831 * - Leaves interrupts turned off
834 ifp
->if_flags
|= IFF_PROMISC
;
835 sc
->re_flags
|= RE_F_TESTMODE
;
837 sc
->re_flags
|= RE_F_LINKED
;
838 if (!RE_IS_8139CP(sc
))
843 re_miibus_writereg(sc
->re_dev
, phyaddr
, MII_BMCR
, BMCR_RESET
);
844 for (i
= 0; i
< RE_TIMEOUT
; i
++) {
845 status
= re_miibus_readreg(sc
->re_dev
, phyaddr
, MII_BMCR
);
846 if (!(status
& BMCR_RESET
))
850 re_miibus_writereg(sc
->re_dev
, phyaddr
, MII_BMCR
, BMCR_LOOP
);
851 CSR_WRITE_2(sc
, RE_ISR
, RE_INTRS_DIAG
);
855 /* Put some data in the mbuf */
857 eh
= mtod(m0
, struct ether_header
*);
858 bcopy (dst
, eh
->ether_dhost
, ETHER_ADDR_LEN
);
859 bcopy (src
, eh
->ether_shost
, ETHER_ADDR_LEN
);
860 eh
->ether_type
= htons(ETHERTYPE_IP
);
861 m0
->m_pkthdr
.len
= m0
->m_len
= ETHER_MIN_LEN
- ETHER_CRC_LEN
;
864 * Queue the packet, start transmission.
865 * Note: ifq_handoff() ultimately calls re_start() for us.
868 CSR_WRITE_2(sc
, RE_ISR
, 0xFFFF);
869 error
= ifq_handoff(ifp
, m0
, NULL
);
876 /* Wait for it to propagate through the chip */
879 for (i
= 0; i
< RE_TIMEOUT
; i
++) {
880 status
= CSR_READ_2(sc
, RE_ISR
);
881 CSR_WRITE_2(sc
, RE_ISR
, status
);
882 if ((status
& (RE_ISR_TIMEOUT_EXPIRED
|RE_ISR_RX_OK
)) ==
883 (RE_ISR_TIMEOUT_EXPIRED
|RE_ISR_RX_OK
))
888 if (i
== RE_TIMEOUT
) {
889 if_printf(ifp
, "diagnostic failed to receive packet "
890 "in loopback mode\n");
896 * The packet should have been dumped into the first
897 * entry in the RX DMA ring. Grab it from there.
900 bus_dmamap_sync(sc
->re_ldata
.re_rx_mtag
, sc
->re_ldata
.re_rx_dmamap
[0],
901 BUS_DMASYNC_POSTREAD
);
902 bus_dmamap_unload(sc
->re_ldata
.re_rx_mtag
,
903 sc
->re_ldata
.re_rx_dmamap
[0]);
905 m0
= sc
->re_ldata
.re_rx_mbuf
[0];
906 sc
->re_ldata
.re_rx_mbuf
[0] = NULL
;
907 eh
= mtod(m0
, struct ether_header
*);
909 cur_rx
= &sc
->re_ldata
.re_rx_list
[0];
910 total_len
= RE_RXBYTES(cur_rx
);
912 if (total_len
!= ETHER_MIN_LEN
) {
913 if_printf(ifp
, "diagnostic failed, received short packet\n");
918 /* Test that the received packet data matches what we sent. */
920 if (bcmp(eh
->ether_dhost
, dst
, ETHER_ADDR_LEN
) ||
921 bcmp(eh
->ether_shost
, &src
, ETHER_ADDR_LEN
) ||
922 be16toh(eh
->ether_type
) != ETHERTYPE_IP
) {
923 if_printf(ifp
, "WARNING, DMA FAILURE!\n");
924 if_printf(ifp
, "expected TX data: %s/%s/0x%x\n",
925 kether_ntoa(dst
, ethstr
[0]), kether_ntoa(src
, ethstr
[1]), ETHERTYPE_IP
);
926 if_printf(ifp
, "received RX data: %s/%s/0x%x\n",
927 kether_ntoa(eh
->ether_dhost
, ethstr
[0]),
928 kether_ntoa(eh
->ether_shost
, ethstr
[1]),
929 ntohs(eh
->ether_type
));
930 if_printf(ifp
, "You may have a defective 32-bit NIC plugged "
931 "into a 64-bit PCI slot.\n");
932 if_printf(ifp
, "Please re-install the NIC in a 32-bit slot "
933 "for proper operation.\n");
934 if_printf(ifp
, "Read the re(4) man page for more details.\n");
939 /* Turn interface off, release resources */
941 sc
->re_flags
&= ~(RE_F_LINKED
| RE_F_TESTMODE
);
942 ifp
->if_flags
&= ~IFF_PROMISC
;
952 * Probe for a RealTek 8139C+/8169/8110 chip. Check the PCI vendor and device
953 * IDs against our list and return a device name if we find a match.
956 re_probe(device_t dev
)
958 const struct re_type
*t
;
959 const struct re_hwrev
*hw_rev
;
962 uint32_t hwrev
, macmode
, txcfg
;
963 uint16_t vendor
, product
;
965 vendor
= pci_get_vendor(dev
);
966 product
= pci_get_device(dev
);
969 * Only attach to rev.3 of the Linksys EG1032 adapter.
970 * Rev.2 is supported by sk(4).
972 if (vendor
== PCI_VENDOR_LINKSYS
&&
973 product
== PCI_PRODUCT_LINKSYS_EG1032
&&
974 pci_get_subdevice(dev
) != PCI_SUBDEVICE_LINKSYS_EG1032_REV3
)
977 if (vendor
== PCI_VENDOR_REALTEK
&&
978 product
== PCI_PRODUCT_REALTEK_RT8139
&&
979 pci_get_revid(dev
) != PCI_REVID_REALTEK_RT8139CP
) {
984 for (t
= re_devs
; t
->re_name
!= NULL
; t
++) {
985 if (product
== t
->re_did
&& vendor
== t
->re_vid
)
990 * Check if we found a RealTek device.
992 if (t
->re_name
== NULL
)
996 * Temporarily map the I/O space so we can read the chip ID register.
998 sc
= kmalloc(sizeof(*sc
), M_TEMP
, M_WAITOK
| M_ZERO
);
1000 sc
->re_res
= bus_alloc_resource_any(dev
, SYS_RES_IOPORT
, &rid
,
1002 if (sc
->re_res
== NULL
) {
1003 device_printf(dev
, "couldn't map ports/memory\n");
1008 sc
->re_btag
= rman_get_bustag(sc
->re_res
);
1009 sc
->re_bhandle
= rman_get_bushandle(sc
->re_res
);
1011 txcfg
= CSR_READ_4(sc
, RE_TXCFG
);
1012 hwrev
= txcfg
& RE_TXCFG_HWREV
;
1013 macmode
= txcfg
& RE_TXCFG_MACMODE
;
1014 bus_release_resource(dev
, SYS_RES_IOPORT
, RE_PCI_LOIO
, sc
->re_res
);
1018 * and continue matching for the specific chip...
1020 for (hw_rev
= re_hwrevs
; hw_rev
->re_hwrev
!= RE_HWREV_NULL
; hw_rev
++) {
1021 if (hw_rev
->re_hwrev
== hwrev
) {
1022 sc
= device_get_softc(dev
);
1024 sc
->re_hwrev
= hw_rev
->re_hwrev
;
1025 sc
->re_caps
= hw_rev
->re_caps
;
1026 sc
->re_maxmtu
= hw_rev
->re_maxmtu
;
1029 * Apply chip property fixup
1031 switch (sc
->re_hwrev
) {
1032 case RE_HWREV_8168GU
:
1033 if (vendor
== PCI_VENDOR_REALTEK
&&
1034 product
== PCI_PRODUCT_REALTEK_RT8101E
) {
1036 sc
->re_caps
= RE_C_HWCSUM
| RE_C_MAC2
|
1037 RE_C_PHYPMGT
| RE_C_AUTOPAD
|
1038 RE_C_STOP_RXTX
| RE_C_FASTE
;
1039 sc
->re_maxmtu
= ETHERMTU
;
1040 device_printf(dev
, "8106EUS fixup\n");
1047 case RE_HWREV_8168E
:
1048 if (vendor
== PCI_VENDOR_REALTEK
&&
1049 product
== PCI_PRODUCT_REALTEK_RT8101E
) {
1051 sc
->re_caps
= RE_C_HWCSUM
| RE_C_MAC2
|
1052 RE_C_PHYPMGT
| RE_C_AUTOPAD
|
1053 RE_C_STOP_RXTX
| RE_C_FASTE
;
1054 sc
->re_maxmtu
= ETHERMTU
;
1055 device_printf(dev
, "8105E fixup\n");
1061 case RE_HWREV_8101E
:
1062 case RE_HWREV_8102E
:
1063 case RE_HWREV_8102EL
:
1064 case RE_HWREV_8401E
:
1065 case RE_HWREV_8105E
:
1066 case RE_HWREV_8106E
:
1068 sc
->re_caps
|= RE_C_EE_EADDR
;
1069 sc
->re_ee_eaddr
= RE_EE_EADDR0
;
1072 case RE_HWREV_8168F
:
1073 case RE_HWREV_8111F
:
1074 case RE_HWREV_8168G
:
1076 macmode
== 0x100000) {
1077 sc
->re_caps
|= RE_C_EE_EADDR
;
1078 sc
->re_ee_eaddr
= RE_EE_EADDR1
;
1083 case RE_HWREV_8168EP
:
1084 case RE_HWREV_8168H
:
1085 case RE_HWREV_8411B
:
1087 sc
->re_caps
|= RE_C_EE_EADDR
;
1088 sc
->re_ee_eaddr
= RE_EE_EADDR1
;
1091 if (pci_is_pcie(dev
))
1092 sc
->re_caps
|= RE_C_PCIE
;
1094 device_set_desc(dev
, t
->re_name
);
1098 device_printf(dev
, "unknown hwrev 0x%08x, macmode 0x%08x\n",
1105 re_allocmem(device_t dev
)
1107 struct re_softc
*sc
= device_get_softc(dev
);
1112 * Allocate list data
1114 sc
->re_ldata
.re_tx_mbuf
=
1115 kmalloc(sc
->re_tx_desc_cnt
* sizeof(struct mbuf
*),
1116 M_DEVBUF
, M_ZERO
| M_WAITOK
);
1118 sc
->re_ldata
.re_rx_mbuf
=
1119 kmalloc(sc
->re_rx_desc_cnt
* sizeof(struct mbuf
*),
1120 M_DEVBUF
, M_ZERO
| M_WAITOK
);
1122 sc
->re_ldata
.re_rx_paddr
=
1123 kmalloc(sc
->re_rx_desc_cnt
* sizeof(bus_addr_t
),
1124 M_DEVBUF
, M_ZERO
| M_WAITOK
);
1126 sc
->re_ldata
.re_tx_dmamap
=
1127 kmalloc(sc
->re_tx_desc_cnt
* sizeof(bus_dmamap_t
),
1128 M_DEVBUF
, M_ZERO
| M_WAITOK
);
1130 sc
->re_ldata
.re_rx_dmamap
=
1131 kmalloc(sc
->re_rx_desc_cnt
* sizeof(bus_dmamap_t
),
1132 M_DEVBUF
, M_ZERO
| M_WAITOK
);
1135 * Allocate the parent bus DMA tag appropriate for PCI.
1137 error
= bus_dma_tag_create(NULL
, /* parent */
1138 1, 0, /* alignment, boundary */
1139 BUS_SPACE_MAXADDR
, /* lowaddr */
1140 BUS_SPACE_MAXADDR
, /* highaddr */
1141 NULL
, NULL
, /* filter, filterarg */
1142 BUS_SPACE_MAXSIZE_32BIT
,/* maxsize */
1144 BUS_SPACE_MAXSIZE_32BIT
,/* maxsegsize */
1146 &sc
->re_parent_tag
);
1148 device_printf(dev
, "could not allocate parent dma tag\n");
1152 /* Allocate TX descriptor list. */
1153 error
= bus_dmamem_coherent(sc
->re_parent_tag
,
1155 BUS_SPACE_MAXADDR
, BUS_SPACE_MAXADDR
,
1156 RE_TX_LIST_SZ(sc
), BUS_DMA_WAITOK
| BUS_DMA_ZERO
,
1159 device_printf(dev
, "could not allocate TX ring\n");
1162 sc
->re_ldata
.re_tx_list_tag
= dmem
.dmem_tag
;
1163 sc
->re_ldata
.re_tx_list_map
= dmem
.dmem_map
;
1164 sc
->re_ldata
.re_tx_list
= dmem
.dmem_addr
;
1165 sc
->re_ldata
.re_tx_list_addr
= dmem
.dmem_busaddr
;
1167 /* Allocate RX descriptor list. */
1168 error
= bus_dmamem_coherent(sc
->re_parent_tag
,
1170 BUS_SPACE_MAXADDR
, BUS_SPACE_MAXADDR
,
1171 RE_RX_LIST_SZ(sc
), BUS_DMA_WAITOK
| BUS_DMA_ZERO
,
1174 device_printf(dev
, "could not allocate RX ring\n");
1177 sc
->re_ldata
.re_rx_list_tag
= dmem
.dmem_tag
;
1178 sc
->re_ldata
.re_rx_list_map
= dmem
.dmem_map
;
1179 sc
->re_ldata
.re_rx_list
= dmem
.dmem_addr
;
1180 sc
->re_ldata
.re_rx_list_addr
= dmem
.dmem_busaddr
;
1182 /* Allocate maps for TX mbufs. */
1183 error
= bus_dma_tag_create(sc
->re_parent_tag
,
1185 BUS_SPACE_MAXADDR
, BUS_SPACE_MAXADDR
,
1187 RE_FRAMELEN_MAX
, RE_MAXSEGS
, MCLBYTES
,
1188 BUS_DMA_ALLOCNOW
| BUS_DMA_WAITOK
| BUS_DMA_ONEBPAGE
,
1189 &sc
->re_ldata
.re_tx_mtag
);
1191 device_printf(dev
, "could not allocate TX buf dma tag\n");
1195 /* Create DMA maps for TX buffers */
1196 for (i
= 0; i
< sc
->re_tx_desc_cnt
; i
++) {
1197 error
= bus_dmamap_create(sc
->re_ldata
.re_tx_mtag
,
1198 BUS_DMA_WAITOK
| BUS_DMA_ONEBPAGE
,
1199 &sc
->re_ldata
.re_tx_dmamap
[i
]);
1201 device_printf(dev
, "can't create DMA map for TX buf\n");
1202 re_freebufmem(sc
, i
, 0);
1207 /* Allocate maps for RX mbufs. */
1208 error
= bus_dma_tag_create(sc
->re_parent_tag
,
1210 BUS_SPACE_MAXADDR
, BUS_SPACE_MAXADDR
,
1212 MCLBYTES
, 1, MCLBYTES
,
1213 BUS_DMA_ALLOCNOW
| BUS_DMA_WAITOK
| BUS_DMA_ALIGNED
,
1214 &sc
->re_ldata
.re_rx_mtag
);
1216 device_printf(dev
, "could not allocate RX buf dma tag\n");
1220 /* Create spare DMA map for RX */
1221 error
= bus_dmamap_create(sc
->re_ldata
.re_rx_mtag
, BUS_DMA_WAITOK
,
1222 &sc
->re_ldata
.re_rx_spare
);
1224 device_printf(dev
, "can't create spare DMA map for RX\n");
1225 bus_dma_tag_destroy(sc
->re_ldata
.re_rx_mtag
);
1226 sc
->re_ldata
.re_rx_mtag
= NULL
;
1230 /* Create DMA maps for RX buffers */
1231 for (i
= 0; i
< sc
->re_rx_desc_cnt
; i
++) {
1232 error
= bus_dmamap_create(sc
->re_ldata
.re_rx_mtag
,
1233 BUS_DMA_WAITOK
, &sc
->re_ldata
.re_rx_dmamap
[i
]);
1235 device_printf(dev
, "can't create DMA map for RX buf\n");
1236 re_freebufmem(sc
, sc
->re_tx_desc_cnt
, i
);
1241 /* Create jumbo buffer pool for RX if required */
1242 if (sc
->re_caps
& RE_C_CONTIGRX
) {
1243 error
= re_jpool_alloc(sc
);
1246 /* Disable jumbo frame support */
1247 sc
->re_maxmtu
= ETHERMTU
;
1254 re_freebufmem(struct re_softc
*sc
, int tx_cnt
, int rx_cnt
)
1258 /* Destroy all the RX and TX buffer maps */
1259 if (sc
->re_ldata
.re_tx_mtag
) {
1260 for (i
= 0; i
< tx_cnt
; i
++) {
1261 bus_dmamap_destroy(sc
->re_ldata
.re_tx_mtag
,
1262 sc
->re_ldata
.re_tx_dmamap
[i
]);
1264 bus_dma_tag_destroy(sc
->re_ldata
.re_tx_mtag
);
1265 sc
->re_ldata
.re_tx_mtag
= NULL
;
1268 if (sc
->re_ldata
.re_rx_mtag
) {
1269 for (i
= 0; i
< rx_cnt
; i
++) {
1270 bus_dmamap_destroy(sc
->re_ldata
.re_rx_mtag
,
1271 sc
->re_ldata
.re_rx_dmamap
[i
]);
1273 bus_dmamap_destroy(sc
->re_ldata
.re_rx_mtag
,
1274 sc
->re_ldata
.re_rx_spare
);
1275 bus_dma_tag_destroy(sc
->re_ldata
.re_rx_mtag
);
1276 sc
->re_ldata
.re_rx_mtag
= NULL
;
1281 re_freemem(device_t dev
)
1283 struct re_softc
*sc
= device_get_softc(dev
);
1285 /* Unload and free the RX DMA ring memory and map */
1286 if (sc
->re_ldata
.re_rx_list_tag
) {
1287 bus_dmamap_unload(sc
->re_ldata
.re_rx_list_tag
,
1288 sc
->re_ldata
.re_rx_list_map
);
1289 bus_dmamem_free(sc
->re_ldata
.re_rx_list_tag
,
1290 sc
->re_ldata
.re_rx_list
,
1291 sc
->re_ldata
.re_rx_list_map
);
1292 bus_dma_tag_destroy(sc
->re_ldata
.re_rx_list_tag
);
1295 /* Unload and free the TX DMA ring memory and map */
1296 if (sc
->re_ldata
.re_tx_list_tag
) {
1297 bus_dmamap_unload(sc
->re_ldata
.re_tx_list_tag
,
1298 sc
->re_ldata
.re_tx_list_map
);
1299 bus_dmamem_free(sc
->re_ldata
.re_tx_list_tag
,
1300 sc
->re_ldata
.re_tx_list
,
1301 sc
->re_ldata
.re_tx_list_map
);
1302 bus_dma_tag_destroy(sc
->re_ldata
.re_tx_list_tag
);
1305 /* Free RX/TX buf DMA stuffs */
1306 re_freebufmem(sc
, sc
->re_tx_desc_cnt
, sc
->re_rx_desc_cnt
);
1308 /* Unload and free the stats buffer and map */
1309 if (sc
->re_ldata
.re_stag
) {
1310 bus_dmamap_unload(sc
->re_ldata
.re_stag
, sc
->re_ldata
.re_smap
);
1311 bus_dmamem_free(sc
->re_ldata
.re_stag
,
1312 sc
->re_ldata
.re_stats
,
1313 sc
->re_ldata
.re_smap
);
1314 bus_dma_tag_destroy(sc
->re_ldata
.re_stag
);
1317 if (sc
->re_caps
& RE_C_CONTIGRX
)
1320 if (sc
->re_parent_tag
)
1321 bus_dma_tag_destroy(sc
->re_parent_tag
);
1323 if (sc
->re_ldata
.re_tx_mbuf
!= NULL
)
1324 kfree(sc
->re_ldata
.re_tx_mbuf
, M_DEVBUF
);
1325 if (sc
->re_ldata
.re_rx_mbuf
!= NULL
)
1326 kfree(sc
->re_ldata
.re_rx_mbuf
, M_DEVBUF
);
1327 if (sc
->re_ldata
.re_rx_paddr
!= NULL
)
1328 kfree(sc
->re_ldata
.re_rx_paddr
, M_DEVBUF
);
1329 if (sc
->re_ldata
.re_tx_dmamap
!= NULL
)
1330 kfree(sc
->re_ldata
.re_tx_dmamap
, M_DEVBUF
);
1331 if (sc
->re_ldata
.re_rx_dmamap
!= NULL
)
1332 kfree(sc
->re_ldata
.re_rx_dmamap
, M_DEVBUF
);
1336 * Attach the interface. Allocate softc structures, do ifmedia
1337 * setup and ethernet/BPF attach.
1340 re_attach(device_t dev
)
1342 struct re_softc
*sc
= device_get_softc(dev
);
1344 struct sysctl_ctx_list
*ctx
;
1345 struct sysctl_oid
*tree
;
1346 uint8_t eaddr
[ETHER_ADDR_LEN
];
1347 int error
= 0, qlen
, msi_enable
;
1350 callout_init_mp(&sc
->re_timer
);
1353 if (RE_IS_8139CP(sc
)) {
1354 sc
->re_rx_desc_cnt
= RE_RX_DESC_CNT_8139CP
;
1355 sc
->re_tx_desc_cnt
= RE_TX_DESC_CNT_8139CP
;
1357 sc
->re_rx_desc_cnt
= re_rx_desc_count
;
1358 if (sc
->re_rx_desc_cnt
> RE_RX_DESC_CNT_MAX
)
1359 sc
->re_rx_desc_cnt
= RE_RX_DESC_CNT_MAX
;
1361 sc
->re_tx_desc_cnt
= re_tx_desc_count
;
1362 if (sc
->re_tx_desc_cnt
> RE_TX_DESC_CNT_MAX
)
1363 sc
->re_tx_desc_cnt
= RE_TX_DESC_CNT_MAX
;
1366 qlen
= RE_IFQ_MAXLEN
;
1367 if (sc
->re_tx_desc_cnt
> qlen
)
1368 qlen
= sc
->re_tx_desc_cnt
;
1370 sc
->re_rxbuf_size
= MCLBYTES
;
1371 sc
->re_newbuf
= re_newbuf_std
;
1373 sc
->re_tx_time
= 5; /* 125us */
1374 sc
->re_rx_time
= 2; /* 50us */
1375 if (sc
->re_caps
& RE_C_PCIE
)
1376 sc
->re_sim_time
= 75; /* 75us */
1378 sc
->re_sim_time
= 125; /* 125us */
1379 if (!RE_IS_8139CP(sc
)) {
1380 /* simulated interrupt moderation */
1381 sc
->re_imtype
= RE_IMTYPE_SIM
;
1383 sc
->re_imtype
= RE_IMTYPE_NONE
;
1385 re_config_imtype(sc
, sc
->re_imtype
);
1387 ctx
= device_get_sysctl_ctx(dev
);
1388 tree
= device_get_sysctl_tree(dev
);
1389 SYSCTL_ADD_INT(ctx
, SYSCTL_CHILDREN(tree
), OID_AUTO
,
1390 "rx_desc_count", CTLFLAG_RD
, &sc
->re_rx_desc_cnt
,
1391 0, "RX desc count");
1392 SYSCTL_ADD_INT(ctx
, SYSCTL_CHILDREN(tree
), OID_AUTO
,
1393 "tx_desc_count", CTLFLAG_RD
, &sc
->re_tx_desc_cnt
,
1394 0, "TX desc count");
1395 SYSCTL_ADD_PROC(ctx
, SYSCTL_CHILDREN(tree
), OID_AUTO
, "sim_time",
1396 CTLTYPE_INT
| CTLFLAG_RW
,
1397 sc
, 0, re_sysctl_simtime
, "I",
1398 "Simulated interrupt moderation time (usec).");
1399 SYSCTL_ADD_PROC(ctx
, SYSCTL_CHILDREN(tree
), OID_AUTO
, "imtype",
1400 CTLTYPE_INT
| CTLFLAG_RW
,
1401 sc
, 0, re_sysctl_imtype
, "I",
1402 "Interrupt moderation type -- "
1403 "0:disable, 1:simulated, "
1404 "2:hardware(if supported)");
1405 if (sc
->re_caps
& RE_C_HWIM
) {
1406 SYSCTL_ADD_PROC(ctx
, SYSCTL_CHILDREN(tree
),
1407 OID_AUTO
, "hw_rxtime",
1408 CTLTYPE_INT
| CTLFLAG_RW
,
1409 sc
, 0, re_sysctl_rxtime
, "I",
1410 "Hardware interrupt moderation time "
1412 SYSCTL_ADD_PROC(ctx
, SYSCTL_CHILDREN(tree
),
1413 OID_AUTO
, "hw_txtime",
1414 CTLTYPE_INT
| CTLFLAG_RW
,
1415 sc
, 0, re_sysctl_txtime
, "I",
1416 "Hardware interrupt moderation time "
1420 #ifndef BURN_BRIDGES
1422 * Handle power management nonsense.
1425 if (pci_get_powerstate(dev
) != PCI_POWERSTATE_D0
) {
1426 uint32_t membase
, irq
;
1428 /* Save important PCI config data. */
1429 membase
= pci_read_config(dev
, RE_PCI_LOMEM
, 4);
1430 irq
= pci_read_config(dev
, PCIR_INTLINE
, 4);
1432 /* Reset the power state. */
1433 device_printf(dev
, "chip is in D%d power mode "
1434 "-- setting to D0\n", pci_get_powerstate(dev
));
1436 pci_set_powerstate(dev
, PCI_POWERSTATE_D0
);
1438 /* Restore PCI config data. */
1439 pci_write_config(dev
, RE_PCI_LOMEM
, membase
, 4);
1440 pci_write_config(dev
, PCIR_INTLINE
, irq
, 4);
1444 * Map control/status registers.
1446 pci_enable_busmaster(dev
);
1448 if (pci_is_pcie(dev
)) {
1449 sc
->re_res_rid
= PCIR_BAR(2);
1450 sc
->re_res_type
= SYS_RES_MEMORY
;
1452 sc
->re_res_rid
= PCIR_BAR(0);
1453 sc
->re_res_type
= SYS_RES_IOPORT
;
1455 sc
->re_res
= bus_alloc_resource_any(dev
, sc
->re_res_type
,
1456 &sc
->re_res_rid
, RF_ACTIVE
);
1457 if (sc
->re_res
== NULL
) {
1458 device_printf(dev
, "couldn't map IO\n");
1463 sc
->re_btag
= rman_get_bustag(sc
->re_res
);
1464 sc
->re_bhandle
= rman_get_bushandle(sc
->re_res
);
1467 * Allocate interrupt
1469 if (pci_is_pcie(dev
))
1470 msi_enable
= re_msi_enable
;
1473 sc
->re_irq_type
= pci_alloc_1intr(dev
, msi_enable
,
1474 &sc
->re_irq_rid
, &irq_flags
);
1476 sc
->re_irq
= bus_alloc_resource_any(dev
, SYS_RES_IRQ
, &sc
->re_irq_rid
,
1478 if (sc
->re_irq
== NULL
) {
1479 device_printf(dev
, "couldn't map interrupt\n");
1484 /* Reset the adapter. */
1487 if (RE_IS_8139CP(sc
)) {
1488 sc
->re_bus_speed
= 33; /* XXX */
1489 } else if (sc
->re_caps
& RE_C_PCIE
) {
1490 sc
->re_bus_speed
= 125;
1494 cfg2
= CSR_READ_1(sc
, RE_CFG2
);
1495 switch (cfg2
& RE_CFG2_PCICLK_MASK
) {
1496 case RE_CFG2_PCICLK_33MHZ
:
1497 sc
->re_bus_speed
= 33;
1499 case RE_CFG2_PCICLK_66MHZ
:
1500 sc
->re_bus_speed
= 66;
1503 device_printf(dev
, "unknown bus speed, assume 33MHz\n");
1504 sc
->re_bus_speed
= 33;
1507 if (cfg2
& RE_CFG2_PCI64
)
1508 sc
->re_caps
|= RE_C_PCI64
;
1510 device_printf(dev
, "Hardware rev. 0x%08x; PCI%s %dMHz\n",
1512 (sc
->re_caps
& RE_C_PCIE
) ?
1513 "-E" : ((sc
->re_caps
& RE_C_PCI64
) ? "64" : "32"),
1518 * DO NOT try to adjust config1 and config5 which was spotted in
1519 * Realtek's Linux drivers. It will _permanently_ damage certain
1520 * cards EEPROM, e.g. one of my 8168B (0x38000000) card ...
1523 re_get_eaddr(sc
, eaddr
);
1525 if (!RE_IS_8139CP(sc
)) {
1526 /* Set RX length mask */
1527 sc
->re_rxlenmask
= RE_RDESC_STAT_GFRAGLEN
;
1528 sc
->re_txstart
= RE_GTXSTART
;
1530 /* Set RX length mask */
1531 sc
->re_rxlenmask
= RE_RDESC_STAT_FRAGLEN
;
1532 sc
->re_txstart
= RE_TXSTART
;
1535 /* Allocate DMA stuffs */
1536 error
= re_allocmem(dev
);
1541 * Apply some magic PCI settings from Realtek ...
1543 if (RE_IS_8169(sc
)) {
1544 CSR_WRITE_1(sc
, 0x82, 1);
1545 pci_write_config(dev
, PCIR_CACHELNSZ
, 0x8, 1);
1547 pci_write_config(dev
, PCIR_LATTIMER
, 0x40, 1);
1549 if (sc
->re_caps
& RE_C_MAC2
) {
1551 * Following part is extracted from Realtek BSD driver v176.
1552 * However, this does _not_ make much/any sense:
1553 * 8168C's PCI Express device control is located at 0x78,
1554 * so the reading from 0x79 (higher part of 0x78) and setting
1555 * the 4~6bits intend to enlarge the "max read request size"
1556 * (we will do it). The content of the rest part of this
1557 * register is not meaningful to other PCI registers, so
1558 * writing the value to 0x54 could be completely wrong.
1559 * 0x80 is the lower part of PCI Express device status, non-
1560 * reserved bits are RW1C, writing 0 to them will not have
1561 * any effect at all.
1566 val
= pci_read_config(dev
, 0x79, 1);
1567 val
= (val
& ~0x70) | 0x50;
1568 pci_write_config(dev
, 0x54, val
, 1);
1569 pci_write_config(dev
, 0x80, 0, 1);
1574 * Apply some PHY fixup from Realtek ...
1576 if (sc
->re_hwrev
== RE_HWREV_8110S
) {
1577 CSR_WRITE_1(sc
, 0x82, 1);
1578 re_miibus_writereg(dev
, 1, 0xb, 0);
1580 if (sc
->re_caps
& RE_C_PHYPMGT
) {
1582 re_miibus_writereg(dev
, 1, 0x1f, 0);
1583 re_miibus_writereg(dev
, 1, 0xe, 0);
1587 if (mii_phy_probe(dev
, &sc
->re_miibus
,
1588 re_ifmedia_upd
, re_ifmedia_sts
)) {
1589 device_printf(dev
, "MII without any phy!\n");
1594 ifp
= &sc
->arpcom
.ac_if
;
1596 if_initname(ifp
, device_get_name(dev
), device_get_unit(dev
));
1597 ifp
->if_flags
= IFF_BROADCAST
| IFF_SIMPLEX
| IFF_MULTICAST
;
1598 ifp
->if_ioctl
= re_ioctl
;
1599 ifp
->if_start
= re_start
;
1600 #ifdef IFPOLL_ENABLE
1601 ifp
->if_npoll
= re_npoll
;
1603 ifp
->if_watchdog
= re_watchdog
;
1604 ifp
->if_init
= re_init
;
1605 if (!RE_IS_8139CP(sc
)) /* XXX */
1606 ifp
->if_baudrate
= 1000000000;
1608 ifp
->if_baudrate
= 100000000;
1609 ifp
->if_nmbclusters
= sc
->re_rx_desc_cnt
;
1610 ifq_set_maxlen(&ifp
->if_snd
, qlen
);
1611 ifq_set_ready(&ifp
->if_snd
);
1613 ifp
->if_capabilities
= IFCAP_VLAN_MTU
| IFCAP_VLAN_HWTAGGING
;
1614 if (sc
->re_caps
& RE_C_HWCSUM
)
1615 ifp
->if_capabilities
|= IFCAP_HWCSUM
;
1617 ifp
->if_capenable
= ifp
->if_capabilities
;
1618 if (ifp
->if_capabilities
& IFCAP_HWCSUM
) {
1620 * RTL8168/8111C generates wrong IP checksummed frame if the
1621 * packet has IP options so disable TX IP checksum offloading.
1623 if (sc
->re_hwrev
== RE_HWREV_8168CP
||
1624 sc
->re_hwrev
== RE_HWREV_8168C
)
1625 sc
->re_hwassist
= CSUM_TCP
| CSUM_UDP
;
1627 sc
->re_hwassist
= CSUM_IP
| CSUM_TCP
| CSUM_UDP
;
1629 ifp
->if_hwassist
= sc
->re_hwassist
;
1632 * Call MI attach routine.
1634 ether_ifattach(ifp
, eaddr
, NULL
);
1636 ifq_set_cpuid(&ifp
->if_snd
, rman_get_cpuid(sc
->re_irq
));
1638 #ifdef IFPOLL_ENABLE
1639 ifpoll_compat_setup(&sc
->re_npoll
, ctx
, (struct sysctl_oid
*)tree
,
1640 device_get_unit(dev
), ifp
->if_serializer
);
1645 * Perform hardware diagnostic on the original RTL8169.
1646 * Some 32-bit cards were incorrectly wired and would
1647 * malfunction if plugged into a 64-bit slot.
1649 if (sc
->re_hwrev
== RE_HWREV_8169
) {
1650 lwkt_serialize_enter(ifp
->if_serializer
);
1651 error
= re_diag(sc
);
1652 lwkt_serialize_exit(ifp
->if_serializer
);
1655 device_printf(dev
, "hardware diagnostic failure\n");
1656 ether_ifdetach(ifp
);
1660 #endif /* RE_DIAG */
1662 /* Hook interrupt last to avoid having to lock softc */
1663 error
= bus_setup_intr(dev
, sc
->re_irq
, INTR_MPSAFE
, re_intr
, sc
,
1664 &sc
->re_intrhand
, ifp
->if_serializer
);
1667 device_printf(dev
, "couldn't set up irq\n");
1668 ether_ifdetach(ifp
);
1680 * Shutdown hardware and free up resources. This can be called any
1681 * time after the mutex has been initialized. It is called in both
1682 * the error case in attach and the normal detach case so it needs
1683 * to be careful about only freeing resources that have actually been
1687 re_detach(device_t dev
)
1689 struct re_softc
*sc
= device_get_softc(dev
);
1690 struct ifnet
*ifp
= &sc
->arpcom
.ac_if
;
1692 /* These should only be active if attach succeeded */
1693 if (device_is_attached(dev
)) {
1694 lwkt_serialize_enter(ifp
->if_serializer
);
1696 bus_teardown_intr(dev
, sc
->re_irq
, sc
->re_intrhand
);
1697 lwkt_serialize_exit(ifp
->if_serializer
);
1699 ether_ifdetach(ifp
);
1702 device_delete_child(dev
, sc
->re_miibus
);
1703 bus_generic_detach(dev
);
1706 bus_release_resource(dev
, SYS_RES_IRQ
, sc
->re_irq_rid
,
1709 if (sc
->re_irq_type
== PCI_INTR_TYPE_MSI
)
1710 pci_release_msi(dev
);
1713 bus_release_resource(dev
, sc
->re_res_type
, sc
->re_res_rid
,
1717 /* Free DMA stuffs */
1724 re_setup_rxdesc(struct re_softc
*sc
, int idx
)
1730 paddr
= sc
->re_ldata
.re_rx_paddr
[idx
];
1731 d
= &sc
->re_ldata
.re_rx_list
[idx
];
1733 d
->re_bufaddr_lo
= htole32(RE_ADDR_LO(paddr
));
1734 d
->re_bufaddr_hi
= htole32(RE_ADDR_HI(paddr
));
1736 cmdstat
= sc
->re_rxbuf_size
| RE_RDESC_CMD_OWN
;
1737 if (idx
== (sc
->re_rx_desc_cnt
- 1))
1738 cmdstat
|= RE_RDESC_CMD_EOR
;
1739 d
->re_cmdstat
= htole32(cmdstat
);
1743 re_newbuf_std(struct re_softc
*sc
, int idx
, int init
)
1745 bus_dma_segment_t seg
;
1750 m
= m_getcl(init
? M_WAITOK
: M_NOWAIT
, MT_DATA
, M_PKTHDR
);
1755 if_printf(&sc
->arpcom
.ac_if
, "m_getcl failed\n");
1761 m
->m_len
= m
->m_pkthdr
.len
= MCLBYTES
;
1765 * re(4) chips need address of the receive buffer to be 8-byte
1766 * aligned, so don't call m_adj(m, ETHER_ALIGN) here.
1769 error
= bus_dmamap_load_mbuf_segment(sc
->re_ldata
.re_rx_mtag
,
1770 sc
->re_ldata
.re_rx_spare
, m
,
1771 &seg
, 1, &nsegs
, BUS_DMA_NOWAIT
);
1775 if_printf(&sc
->arpcom
.ac_if
, "can't load RX mbuf\n");
1783 bus_dmamap_sync(sc
->re_ldata
.re_rx_mtag
,
1784 sc
->re_ldata
.re_rx_dmamap
[idx
],
1785 BUS_DMASYNC_POSTREAD
);
1786 bus_dmamap_unload(sc
->re_ldata
.re_rx_mtag
,
1787 sc
->re_ldata
.re_rx_dmamap
[idx
]);
1789 sc
->re_ldata
.re_rx_mbuf
[idx
] = m
;
1790 sc
->re_ldata
.re_rx_paddr
[idx
] = seg
.ds_addr
;
1792 map
= sc
->re_ldata
.re_rx_dmamap
[idx
];
1793 sc
->re_ldata
.re_rx_dmamap
[idx
] = sc
->re_ldata
.re_rx_spare
;
1794 sc
->re_ldata
.re_rx_spare
= map
;
1796 re_setup_rxdesc(sc
, idx
);
1801 re_newbuf_jumbo(struct re_softc
*sc
, int idx
, int init
)
1804 struct re_jbuf
*jbuf
;
1807 MGETHDR(m
, init
? M_WAITOK
: M_NOWAIT
, MT_DATA
);
1811 if_printf(&sc
->arpcom
.ac_if
, "MGETHDR failed\n");
1818 jbuf
= re_jbuf_alloc(sc
);
1824 if_printf(&sc
->arpcom
.ac_if
, "jpool is empty\n");
1831 m
->m_ext
.ext_arg
= jbuf
;
1832 m
->m_ext
.ext_buf
= jbuf
->re_buf
;
1833 m
->m_ext
.ext_free
= re_jbuf_free
;
1834 m
->m_ext
.ext_ref
= re_jbuf_ref
;
1835 m
->m_ext
.ext_size
= sc
->re_rxbuf_size
;
1837 m
->m_data
= m
->m_ext
.ext_buf
;
1838 m
->m_flags
|= M_EXT
;
1839 m
->m_len
= m
->m_pkthdr
.len
= m
->m_ext
.ext_size
;
1843 * Some re(4) chips(e.g. RTL8101E) need address of the receive buffer
1844 * to be 8-byte aligned, so don't call m_adj(m, ETHER_ALIGN) here.
1847 sc
->re_ldata
.re_rx_mbuf
[idx
] = m
;
1848 sc
->re_ldata
.re_rx_paddr
[idx
] = jbuf
->re_paddr
;
1850 re_setup_rxdesc(sc
, idx
);
1855 re_tx_list_init(struct re_softc
*sc
)
1857 bzero(sc
->re_ldata
.re_tx_list
, RE_TX_LIST_SZ(sc
));
1859 sc
->re_ldata
.re_tx_prodidx
= 0;
1860 sc
->re_ldata
.re_tx_considx
= 0;
1861 sc
->re_ldata
.re_tx_free
= sc
->re_tx_desc_cnt
;
1867 re_rx_list_init(struct re_softc
*sc
)
1871 bzero(sc
->re_ldata
.re_rx_list
, RE_RX_LIST_SZ(sc
));
1873 for (i
= 0; i
< sc
->re_rx_desc_cnt
; i
++) {
1874 error
= sc
->re_newbuf(sc
, i
, 1);
1879 sc
->re_ldata
.re_rx_prodidx
= 0;
1880 sc
->re_head
= sc
->re_tail
= NULL
;
1885 #define RE_IP4_PACKET 0x1
1886 #define RE_TCP_PACKET 0x2
1887 #define RE_UDP_PACKET 0x4
1889 static __inline
uint8_t
1890 re_packet_type(struct re_softc
*sc
, uint32_t rxstat
, uint32_t rxctrl
)
1892 uint8_t packet_type
= 0;
1894 if (sc
->re_caps
& RE_C_MAC2
) {
1895 if (rxctrl
& RE_RDESC_CTL_PROTOIP4
)
1896 packet_type
|= RE_IP4_PACKET
;
1898 if (rxstat
& RE_RDESC_STAT_PROTOID
)
1899 packet_type
|= RE_IP4_PACKET
;
1901 if (RE_TCPPKT(rxstat
))
1902 packet_type
|= RE_TCP_PACKET
;
1903 else if (RE_UDPPKT(rxstat
))
1904 packet_type
|= RE_UDP_PACKET
;
1909 * RX handler for C+ and 8169. For the gigE chips, we support
1910 * the reception of jumbo frames that have been fragmented
1911 * across multiple 2K mbuf cluster buffers.
1914 re_rxeof(struct re_softc
*sc
)
1916 struct ifnet
*ifp
= &sc
->arpcom
.ac_if
;
1918 struct re_desc
*cur_rx
;
1919 uint32_t rxstat
, rxctrl
;
1920 int i
, total_len
, rx
= 0;
1922 for (i
= sc
->re_ldata
.re_rx_prodidx
;
1923 RE_OWN(&sc
->re_ldata
.re_rx_list
[i
]) == 0; RE_RXDESC_INC(sc
, i
)) {
1924 cur_rx
= &sc
->re_ldata
.re_rx_list
[i
];
1925 m
= sc
->re_ldata
.re_rx_mbuf
[i
];
1926 total_len
= RE_RXBYTES(cur_rx
);
1927 rxstat
= le32toh(cur_rx
->re_cmdstat
);
1928 rxctrl
= le32toh(cur_rx
->re_control
);
1933 if (sc
->re_flags
& RE_F_USE_JPOOL
)
1934 KKASSERT(rxstat
& RE_RDESC_STAT_EOF
);
1937 if ((rxstat
& RE_RDESC_STAT_EOF
) == 0) {
1938 if (sc
->re_flags
& RE_F_DROP_RXFRAG
) {
1939 re_setup_rxdesc(sc
, i
);
1943 if (sc
->re_newbuf(sc
, i
, 0)) {
1944 /* Drop upcoming fragments */
1945 sc
->re_flags
|= RE_F_DROP_RXFRAG
;
1949 m
->m_len
= MCLBYTES
;
1950 if (sc
->re_head
== NULL
) {
1951 sc
->re_head
= sc
->re_tail
= m
;
1953 sc
->re_tail
->m_next
= m
;
1957 } else if (sc
->re_flags
& RE_F_DROP_RXFRAG
) {
1959 * Last fragment of a multi-fragment packet.
1961 * Since error already happened, this fragment
1962 * must be dropped as well as the fragment chain.
1964 re_setup_rxdesc(sc
, i
);
1965 re_free_rxchain(sc
);
1966 sc
->re_flags
&= ~RE_F_DROP_RXFRAG
;
1971 * NOTE: for the 8139C+, the frame length field
1972 * is always 12 bits in size, but for the gigE chips,
1973 * it is 13 bits (since the max RX frame length is 16K).
1974 * Unfortunately, all 32 bits in the status word
1975 * were already used, so to make room for the extra
1976 * length bit, RealTek took out the 'frame alignment
1977 * error' bit and shifted the other status bits
1978 * over one slot. The OWN, EOR, FS and LS bits are
1979 * still in the same places. We have already extracted
1980 * the frame length and checked the OWN bit, so rather
1981 * than using an alternate bit mapping, we shift the
1982 * status bits one space to the right so we can evaluate
1983 * them using the 8169 status as though it was in the
1984 * same format as that of the 8139C+.
1986 if (!RE_IS_8139CP(sc
))
1989 if (rxstat
& RE_RDESC_STAT_RXERRSUM
) {
1990 IFNET_STAT_INC(ifp
, ierrors
, 1);
1992 * If this is part of a multi-fragment packet,
1993 * discard all the pieces.
1995 re_free_rxchain(sc
);
1996 re_setup_rxdesc(sc
, i
);
2001 * If allocating a replacement mbuf fails,
2002 * reload the current one.
2005 if (sc
->re_newbuf(sc
, i
, 0)) {
2006 IFNET_STAT_INC(ifp
, ierrors
, 1);
2010 if (sc
->re_head
!= NULL
) {
2011 m
->m_len
= total_len
% MCLBYTES
;
2013 * Special case: if there's 4 bytes or less
2014 * in this buffer, the mbuf can be discarded:
2015 * the last 4 bytes is the CRC, which we don't
2016 * care about anyway.
2018 if (m
->m_len
<= ETHER_CRC_LEN
) {
2019 sc
->re_tail
->m_len
-=
2020 (ETHER_CRC_LEN
- m
->m_len
);
2023 m
->m_len
-= ETHER_CRC_LEN
;
2024 sc
->re_tail
->m_next
= m
;
2027 sc
->re_head
= sc
->re_tail
= NULL
;
2028 m
->m_pkthdr
.len
= total_len
- ETHER_CRC_LEN
;
2030 m
->m_pkthdr
.len
= m
->m_len
=
2031 (total_len
- ETHER_CRC_LEN
);
2034 IFNET_STAT_INC(ifp
, ipackets
, 1);
2035 m
->m_pkthdr
.rcvif
= ifp
;
2037 /* Do RX checksumming if enabled */
2039 if (ifp
->if_capenable
& IFCAP_RXCSUM
) {
2040 uint8_t packet_type
;
2042 packet_type
= re_packet_type(sc
, rxstat
, rxctrl
);
2044 /* Check IP header checksum */
2045 if (packet_type
& RE_IP4_PACKET
) {
2046 m
->m_pkthdr
.csum_flags
|= CSUM_IP_CHECKED
;
2047 if ((rxstat
& RE_RDESC_STAT_IPSUMBAD
) == 0)
2048 m
->m_pkthdr
.csum_flags
|= CSUM_IP_VALID
;
2051 /* Check TCP/UDP checksum */
2052 if (((packet_type
& RE_TCP_PACKET
) &&
2053 (rxstat
& RE_RDESC_STAT_TCPSUMBAD
) == 0) ||
2054 ((packet_type
& RE_UDP_PACKET
) &&
2055 (rxstat
& RE_RDESC_STAT_UDPSUMBAD
) == 0)) {
2056 m
->m_pkthdr
.csum_flags
|=
2057 CSUM_DATA_VALID
|CSUM_PSEUDO_HDR
|
2058 CSUM_FRAG_NOT_CHECKED
;
2059 m
->m_pkthdr
.csum_data
= 0xffff;
2063 if (rxctrl
& RE_RDESC_CTL_HASTAG
) {
2064 m
->m_flags
|= M_VLANTAG
;
2065 m
->m_pkthdr
.ether_vlantag
=
2066 be16toh((rxctrl
& RE_RDESC_CTL_TAGDATA
));
2068 ifp
->if_input(ifp
, m
, NULL
, -1);
2071 sc
->re_ldata
.re_rx_prodidx
= i
;
2076 #undef RE_IP4_PACKET
2077 #undef RE_TCP_PACKET
2078 #undef RE_UDP_PACKET
2081 re_tx_collect(struct re_softc
*sc
)
2083 struct ifnet
*ifp
= &sc
->arpcom
.ac_if
;
2087 for (idx
= sc
->re_ldata
.re_tx_considx
;
2088 sc
->re_ldata
.re_tx_free
< sc
->re_tx_desc_cnt
;
2089 RE_TXDESC_INC(sc
, idx
)) {
2090 txstat
= le32toh(sc
->re_ldata
.re_tx_list
[idx
].re_cmdstat
);
2091 if (txstat
& RE_TDESC_CMD_OWN
)
2096 sc
->re_ldata
.re_tx_list
[idx
].re_bufaddr_lo
= 0;
2099 * We only stash mbufs in the last descriptor
2100 * in a fragment chain, which also happens to
2101 * be the only place where the TX status bits
2104 if (txstat
& RE_TDESC_CMD_EOF
) {
2105 bus_dmamap_unload(sc
->re_ldata
.re_tx_mtag
,
2106 sc
->re_ldata
.re_tx_dmamap
[idx
]);
2107 m_freem(sc
->re_ldata
.re_tx_mbuf
[idx
]);
2108 sc
->re_ldata
.re_tx_mbuf
[idx
] = NULL
;
2109 if (txstat
& (RE_TDESC_STAT_EXCESSCOL
|
2110 RE_TDESC_STAT_COLCNT
))
2111 IFNET_STAT_INC(ifp
, collisions
, 1);
2112 if (txstat
& RE_TDESC_STAT_TXERRSUM
)
2113 IFNET_STAT_INC(ifp
, oerrors
, 1);
2115 IFNET_STAT_INC(ifp
, opackets
, 1);
2117 sc
->re_ldata
.re_tx_free
++;
2119 sc
->re_ldata
.re_tx_considx
= idx
;
2125 re_txeof(struct re_softc
*sc
)
2127 struct ifnet
*ifp
= &sc
->arpcom
.ac_if
;
2130 tx
= re_tx_collect(sc
);
2132 /* There is enough free TX descs */
2133 if (sc
->re_ldata
.re_tx_free
> RE_TXDESC_SPARE
)
2134 ifq_clr_oactive(&ifp
->if_snd
);
2137 * Some chips will ignore a second TX request issued while an
2138 * existing transmission is in progress. If the transmitter goes
2139 * idle but there are still packets waiting to be sent, we need
2140 * to restart the channel here to flush them out. This only seems
2141 * to be required with the PCIe devices.
2143 if (sc
->re_ldata
.re_tx_free
< sc
->re_tx_desc_cnt
)
2144 CSR_WRITE_1(sc
, sc
->re_txstart
, RE_TXSTART_START
);
2154 struct re_softc
*sc
= xsc
;
2156 lwkt_serialize_enter(sc
->arpcom
.ac_if
.if_serializer
);
2157 re_tick_serialized(xsc
);
2158 lwkt_serialize_exit(sc
->arpcom
.ac_if
.if_serializer
);
2162 re_tick_serialized(void *xsc
)
2164 struct re_softc
*sc
= xsc
;
2165 struct ifnet
*ifp
= &sc
->arpcom
.ac_if
;
2166 struct mii_data
*mii
;
2168 ASSERT_SERIALIZED(ifp
->if_serializer
);
2170 mii
= device_get_softc(sc
->re_miibus
);
2172 if (sc
->re_flags
& RE_F_LINKED
) {
2173 if (!(mii
->mii_media_status
& IFM_ACTIVE
))
2174 sc
->re_flags
&= ~RE_F_LINKED
;
2176 if (mii
->mii_media_status
& IFM_ACTIVE
&&
2177 IFM_SUBTYPE(mii
->mii_media_active
) != IFM_NONE
) {
2178 sc
->re_flags
|= RE_F_LINKED
;
2179 if (!ifq_is_empty(&ifp
->if_snd
))
2184 callout_reset(&sc
->re_timer
, hz
, re_tick
, sc
);
2187 #ifdef IFPOLL_ENABLE
2190 re_npoll_compat(struct ifnet
*ifp
, void *arg __unused
, int count
)
2192 struct re_softc
*sc
= ifp
->if_softc
;
2194 ASSERT_SERIALIZED(ifp
->if_serializer
);
2196 if (sc
->re_npoll
.ifpc_stcount
-- == 0) {
2199 sc
->re_npoll
.ifpc_stcount
= sc
->re_npoll
.ifpc_stfrac
;
2201 status
= CSR_READ_2(sc
, RE_ISR
);
2202 if (status
== 0xffff)
2205 CSR_WRITE_2(sc
, RE_ISR
, status
);
2208 * XXX check behaviour on receiver stalls.
2211 if (status
& RE_ISR_SYSTEM_ERR
)
2215 sc
->rxcycles
= count
;
2219 if (!ifq_is_empty(&ifp
->if_snd
))
2224 re_npoll(struct ifnet
*ifp
, struct ifpoll_info
*info
)
2226 struct re_softc
*sc
= ifp
->if_softc
;
2228 ASSERT_SERIALIZED(ifp
->if_serializer
);
2231 int cpuid
= sc
->re_npoll
.ifpc_cpuid
;
2233 info
->ifpi_rx
[cpuid
].poll_func
= re_npoll_compat
;
2234 info
->ifpi_rx
[cpuid
].arg
= NULL
;
2235 info
->ifpi_rx
[cpuid
].serializer
= ifp
->if_serializer
;
2237 if (ifp
->if_flags
& IFF_RUNNING
)
2238 re_setup_intr(sc
, 0, RE_IMTYPE_NONE
);
2239 ifq_set_cpuid(&ifp
->if_snd
, cpuid
);
2241 if (ifp
->if_flags
& IFF_RUNNING
)
2242 re_setup_intr(sc
, 1, sc
->re_imtype
);
2243 ifq_set_cpuid(&ifp
->if_snd
, rman_get_cpuid(sc
->re_irq
));
2246 #endif /* IFPOLL_ENABLE */
2251 struct re_softc
*sc
= arg
;
2252 struct ifnet
*ifp
= &sc
->arpcom
.ac_if
;
2256 ASSERT_SERIALIZED(ifp
->if_serializer
);
2258 if ((sc
->re_flags
& RE_F_SUSPENDED
) ||
2259 (ifp
->if_flags
& IFF_RUNNING
) == 0)
2264 status
= CSR_READ_2(sc
, RE_ISR
);
2265 /* If the card has gone away the read returns 0xffff. */
2266 if (status
== 0xffff)
2269 CSR_WRITE_2(sc
, RE_ISR
, status
);
2271 if ((status
& sc
->re_intrs
) == 0)
2274 if (status
& (sc
->re_rx_ack
| RE_ISR_RX_ERR
))
2277 if (status
& (sc
->re_tx_ack
| RE_ISR_TX_ERR
))
2280 if (status
& RE_ISR_SYSTEM_ERR
)
2283 if (status
& RE_ISR_LINKCHG
) {
2284 callout_stop(&sc
->re_timer
);
2285 re_tick_serialized(sc
);
2289 if (sc
->re_imtype
== RE_IMTYPE_SIM
) {
2290 if ((sc
->re_flags
& RE_F_TIMER_INTR
)) {
2291 if ((tx
| rx
) == 0) {
2293 * Nothing needs to be processed, fallback
2294 * to use TX/RX interrupts.
2296 re_setup_intr(sc
, 1, RE_IMTYPE_NONE
);
2299 * Recollect, mainly to avoid the possible
2300 * race introduced by changing interrupt
2306 CSR_WRITE_4(sc
, RE_TIMERCNT
, 1); /* reload */
2308 } else if (tx
| rx
) {
2310 * Assume that using simulated interrupt moderation
2311 * (hardware timer based) could reduce the interript
2314 re_setup_intr(sc
, 1, RE_IMTYPE_SIM
);
2318 if (tx
&& !ifq_is_empty(&ifp
->if_snd
))
2323 re_encap(struct re_softc
*sc
, struct mbuf
**m_head
, int *idx0
)
2325 struct mbuf
*m
= *m_head
;
2326 bus_dma_segment_t segs
[RE_MAXSEGS
];
2328 int error
, maxsegs
, idx
, i
, nsegs
;
2329 struct re_desc
*d
, *tx_ring
;
2330 uint32_t cmd_csum
, ctl_csum
, vlantag
;
2332 KASSERT(sc
->re_ldata
.re_tx_free
> RE_TXDESC_SPARE
,
2333 ("not enough free TX desc"));
2335 map
= sc
->re_ldata
.re_tx_dmamap
[*idx0
];
2338 * Set up checksum offload. Note: checksum offload bits must
2339 * appear in all descriptors of a multi-descriptor transmit
2340 * attempt. (This is according to testing done with an 8169
2341 * chip. I'm not sure if this is a requirement or a bug.)
2343 cmd_csum
= ctl_csum
= 0;
2344 if (m
->m_pkthdr
.csum_flags
& CSUM_IP
) {
2345 cmd_csum
|= RE_TDESC_CMD_IPCSUM
;
2346 ctl_csum
|= RE_TDESC_CTL_IPCSUM
;
2348 if (m
->m_pkthdr
.csum_flags
& CSUM_TCP
) {
2349 cmd_csum
|= RE_TDESC_CMD_TCPCSUM
;
2350 ctl_csum
|= RE_TDESC_CTL_TCPCSUM
;
2352 if (m
->m_pkthdr
.csum_flags
& CSUM_UDP
) {
2353 cmd_csum
|= RE_TDESC_CMD_UDPCSUM
;
2354 ctl_csum
|= RE_TDESC_CTL_UDPCSUM
;
2357 /* For MAC2 chips, csum flags are set on re_control */
2358 if (sc
->re_caps
& RE_C_MAC2
)
2363 if ((sc
->re_caps
& RE_C_AUTOPAD
) == 0) {
2365 * With some of the RealTek chips, using the checksum offload
2366 * support in conjunction with the autopadding feature results
2367 * in the transmission of corrupt frames. For example, if we
2368 * need to send a really small IP fragment that's less than 60
2369 * bytes in size, and IP header checksumming is enabled, the
2370 * resulting ethernet frame that appears on the wire will
2371 * have garbled payload. To work around this, if TX checksum
2372 * offload is enabled, we always manually pad short frames out
2373 * to the minimum ethernet frame size.
2375 * Note: this appears unnecessary for TCP, and doing it for TCP
2376 * with PCIe adapters seems to result in bad checksums.
2378 if ((m
->m_pkthdr
.csum_flags
&
2379 (CSUM_DELAY_IP
| CSUM_DELAY_DATA
)) &&
2380 (m
->m_pkthdr
.csum_flags
& CSUM_TCP
) == 0 &&
2381 m
->m_pkthdr
.len
< RE_MIN_FRAMELEN
) {
2382 error
= m_devpad(m
, RE_MIN_FRAMELEN
);
2389 if (m
->m_flags
& M_VLANTAG
) {
2390 vlantag
= htobe16(m
->m_pkthdr
.ether_vlantag
) |
2391 RE_TDESC_CTL_INSTAG
;
2394 maxsegs
= sc
->re_ldata
.re_tx_free
;
2395 if (maxsegs
> RE_MAXSEGS
)
2396 maxsegs
= RE_MAXSEGS
;
2398 error
= bus_dmamap_load_mbuf_defrag(sc
->re_ldata
.re_tx_mtag
, map
,
2399 m_head
, segs
, maxsegs
, &nsegs
, BUS_DMA_NOWAIT
);
2404 bus_dmamap_sync(sc
->re_ldata
.re_tx_mtag
, map
, BUS_DMASYNC_PREWRITE
);
2407 * Map the segment array into descriptors. We also keep track
2408 * of the end of the ring and set the end-of-ring bits as needed,
2409 * and we set the ownership bits in all except the very first
2410 * descriptor, whose ownership bits will be turned on later.
2412 tx_ring
= sc
->re_ldata
.re_tx_list
;
2420 cmdstat
= segs
[i
].ds_len
;
2421 d
->re_bufaddr_lo
= htole32(RE_ADDR_LO(segs
[i
].ds_addr
));
2422 d
->re_bufaddr_hi
= htole32(RE_ADDR_HI(segs
[i
].ds_addr
));
2424 cmdstat
|= RE_TDESC_CMD_SOF
;
2426 cmdstat
|= RE_TDESC_CMD_OWN
;
2427 if (idx
== (sc
->re_tx_desc_cnt
- 1))
2428 cmdstat
|= RE_TDESC_CMD_EOR
;
2429 d
->re_cmdstat
= htole32(cmdstat
| cmd_csum
);
2430 d
->re_control
= htole32(ctl_csum
| vlantag
);
2435 RE_TXDESC_INC(sc
, idx
);
2437 d
->re_cmdstat
|= htole32(RE_TDESC_CMD_EOF
);
2439 /* Transfer ownership of packet to the chip. */
2440 d
->re_cmdstat
|= htole32(RE_TDESC_CMD_OWN
);
2442 tx_ring
[*idx0
].re_cmdstat
|= htole32(RE_TDESC_CMD_OWN
);
2445 * Insure that the map for this transmission
2446 * is placed at the array index of the last descriptor
2449 sc
->re_ldata
.re_tx_dmamap
[*idx0
] = sc
->re_ldata
.re_tx_dmamap
[idx
];
2450 sc
->re_ldata
.re_tx_dmamap
[idx
] = map
;
2452 sc
->re_ldata
.re_tx_mbuf
[idx
] = m
;
2453 sc
->re_ldata
.re_tx_free
-= nsegs
;
2455 RE_TXDESC_INC(sc
, idx
);
2466 * Main transmit routine for C+ and gigE NICs.
2470 re_start(struct ifnet
*ifp
, struct ifaltq_subque
*ifsq
)
2472 struct re_softc
*sc
= ifp
->if_softc
;
2473 struct mbuf
*m_head
;
2474 int idx
, need_trans
, oactive
, error
;
2476 ASSERT_ALTQ_SQ_DEFAULT(ifp
, ifsq
);
2477 ASSERT_SERIALIZED(ifp
->if_serializer
);
2479 if ((sc
->re_flags
& RE_F_LINKED
) == 0) {
2480 ifq_purge(&ifp
->if_snd
);
2484 if ((ifp
->if_flags
& IFF_RUNNING
) == 0 || ifq_is_oactive(&ifp
->if_snd
))
2487 idx
= sc
->re_ldata
.re_tx_prodidx
;
2491 while (sc
->re_ldata
.re_tx_mbuf
[idx
] == NULL
) {
2492 if (sc
->re_ldata
.re_tx_free
<= RE_TXDESC_SPARE
) {
2494 if (re_tx_collect(sc
)) {
2499 ifq_set_oactive(&ifp
->if_snd
);
2503 m_head
= ifq_dequeue(&ifp
->if_snd
);
2507 error
= re_encap(sc
, &m_head
, &idx
);
2509 /* m_head is freed by re_encap(), if we reach here */
2510 IFNET_STAT_INC(ifp
, oerrors
, 1);
2512 if (error
== EFBIG
&& !oactive
) {
2513 if (re_tx_collect(sc
)) {
2518 ifq_set_oactive(&ifp
->if_snd
);
2526 * If there's a BPF listener, bounce a copy of this frame
2529 ETHER_BPF_MTAP(ifp
, m_head
);
2533 * If sc->re_ldata.re_tx_mbuf[idx] is not NULL it is possible
2534 * for OACTIVE to not be properly set when we also do not
2535 * have sufficient free tx descriptors, leaving packet in
2536 * ifp->if_snd. This can cause if_start_dispatch() to loop
2537 * infinitely so make sure OACTIVE is set properly.
2539 if (sc
->re_ldata
.re_tx_free
<= RE_TXDESC_SPARE
) {
2540 if (!ifq_is_oactive(&ifp
->if_snd
)) {
2542 if_printf(ifp
, "Debug: OACTIVE was not set when "
2543 "re_tx_free was below minimum!\n");
2545 ifq_set_oactive(&ifp
->if_snd
);
2551 sc
->re_ldata
.re_tx_prodidx
= idx
;
2554 * RealTek put the TX poll request register in a different
2555 * location on the 8169 gigE chip. I don't know why.
2557 CSR_WRITE_1(sc
, sc
->re_txstart
, RE_TXSTART_START
);
2560 * Set a timeout in case the chip goes out to lunch.
2568 struct re_softc
*sc
= xsc
;
2569 struct ifnet
*ifp
= &sc
->arpcom
.ac_if
;
2570 struct mii_data
*mii
;
2571 int error
, framelen
;
2573 ASSERT_SERIALIZED(ifp
->if_serializer
);
2575 mii
= device_get_softc(sc
->re_miibus
);
2578 * Cancel pending I/O and free all RX/TX buffers.
2582 if (sc
->re_caps
& RE_C_CONTIGRX
) {
2583 if (ifp
->if_mtu
> ETHERMTU
) {
2584 KKASSERT(sc
->re_ldata
.re_jbuf
!= NULL
);
2585 sc
->re_flags
|= RE_F_USE_JPOOL
;
2586 sc
->re_rxbuf_size
= RE_FRAMELEN_MAX
;
2587 sc
->re_newbuf
= re_newbuf_jumbo
;
2589 sc
->re_flags
&= ~RE_F_USE_JPOOL
;
2590 sc
->re_rxbuf_size
= MCLBYTES
;
2591 sc
->re_newbuf
= re_newbuf_std
;
2596 * Adjust max read request size according to MTU; mainly to
2597 * improve TX performance for common case (ETHERMTU) on GigE
2598 * NICs. However, this could _not_ be done on 10/100 only
2599 * NICs; their DMA engines will malfunction using non-default
2600 * max read request size.
2602 if ((sc
->re_caps
& (RE_C_PCIE
| RE_C_FASTE
)) == RE_C_PCIE
) {
2603 if (ifp
->if_mtu
> ETHERMTU
) {
2605 * 512 seems to be the only value that works
2606 * reliably with jumbo frame
2608 pcie_set_max_readrq(sc
->re_dev
,
2609 PCIEM_DEVCTL_MAX_READRQ_512
);
2611 pcie_set_max_readrq(sc
->re_dev
,
2612 PCIEM_DEVCTL_MAX_READRQ_4096
);
2617 * Enable C+ RX and TX mode, as well as VLAN stripping and
2618 * RX checksum offload. We must configure the C+ register
2619 * before all others.
2621 CSR_WRITE_2(sc
, RE_CPLUS_CMD
, RE_CPLUSCMD_RXENB
| RE_CPLUSCMD_TXENB
|
2622 RE_CPLUSCMD_PCI_MRW
|
2623 (ifp
->if_capenable
& IFCAP_VLAN_HWTAGGING
?
2624 RE_CPLUSCMD_VLANSTRIP
: 0) |
2625 (ifp
->if_capenable
& IFCAP_RXCSUM
?
2626 RE_CPLUSCMD_RXCSUM_ENB
: 0));
2629 * Init our MAC address. Even though the chipset
2630 * documentation doesn't mention it, we need to enter "Config
2631 * register write enable" mode to modify the ID registers.
2633 CSR_WRITE_1(sc
, RE_EECMD
, RE_EEMODE_WRITECFG
);
2634 CSR_WRITE_4(sc
, RE_IDR0
,
2635 htole32(*(uint32_t *)(&sc
->arpcom
.ac_enaddr
[0])));
2636 CSR_WRITE_2(sc
, RE_IDR4
,
2637 htole16(*(uint16_t *)(&sc
->arpcom
.ac_enaddr
[4])));
2638 CSR_WRITE_1(sc
, RE_EECMD
, RE_EEMODE_OFF
);
2641 * For C+ mode, initialize the RX descriptors and mbufs.
2643 error
= re_rx_list_init(sc
);
2648 error
= re_tx_list_init(sc
);
2655 * Load the addresses of the RX and TX lists into the chip.
2657 CSR_WRITE_4(sc
, RE_RXLIST_ADDR_HI
,
2658 RE_ADDR_HI(sc
->re_ldata
.re_rx_list_addr
));
2659 CSR_WRITE_4(sc
, RE_RXLIST_ADDR_LO
,
2660 RE_ADDR_LO(sc
->re_ldata
.re_rx_list_addr
));
2662 CSR_WRITE_4(sc
, RE_TXLIST_ADDR_HI
,
2663 RE_ADDR_HI(sc
->re_ldata
.re_tx_list_addr
));
2664 CSR_WRITE_4(sc
, RE_TXLIST_ADDR_LO
,
2665 RE_ADDR_LO(sc
->re_ldata
.re_tx_list_addr
));
2668 * Enable transmit and receive.
2670 CSR_WRITE_1(sc
, RE_COMMAND
, RE_CMD_TX_ENB
|RE_CMD_RX_ENB
);
2673 * Set the initial TX and RX configuration.
2675 if (sc
->re_flags
& RE_F_TESTMODE
) {
2676 if (!RE_IS_8139CP(sc
))
2677 CSR_WRITE_4(sc
, RE_TXCFG
,
2678 RE_TXCFG_CONFIG
| RE_LOOPTEST_ON
);
2680 CSR_WRITE_4(sc
, RE_TXCFG
,
2681 RE_TXCFG_CONFIG
| RE_LOOPTEST_ON_CPLUS
);
2683 CSR_WRITE_4(sc
, RE_TXCFG
, RE_TXCFG_CONFIG
);
2685 framelen
= RE_FRAMELEN(ifp
->if_mtu
);
2686 if (framelen
< MCLBYTES
)
2687 CSR_WRITE_1(sc
, RE_EARLY_TX_THRESH
, howmany(MCLBYTES
, 128));
2689 CSR_WRITE_1(sc
, RE_EARLY_TX_THRESH
, howmany(framelen
, 128));
2691 CSR_WRITE_4(sc
, RE_RXCFG
, RE_RXCFG_CONFIG
);
2694 * Program the multicast filter, if necessary.
2698 #ifdef IFPOLL_ENABLE
2700 * Disable interrupts if we are polling.
2702 if (ifp
->if_flags
& IFF_NPOLLING
)
2703 re_setup_intr(sc
, 0, RE_IMTYPE_NONE
);
2704 else /* otherwise ... */
2705 #endif /* IFPOLL_ENABLE */
2707 * Enable interrupts.
2709 if (sc
->re_flags
& RE_F_TESTMODE
)
2710 CSR_WRITE_2(sc
, RE_IMR
, 0);
2712 re_setup_intr(sc
, 1, sc
->re_imtype
);
2713 CSR_WRITE_2(sc
, RE_ISR
, sc
->re_intrs
);
2715 /* Start RX/TX process. */
2716 CSR_WRITE_4(sc
, RE_MISSEDPKT
, 0);
2719 /* Enable receiver and transmitter. */
2720 CSR_WRITE_1(sc
, RE_COMMAND
, RE_CMD_TX_ENB
|RE_CMD_RX_ENB
);
2724 * For 8169 gigE NICs, set the max allowed RX packet
2725 * size so we can receive jumbo frames.
2727 if (!RE_IS_8139CP(sc
)) {
2728 if (sc
->re_caps
& RE_C_CONTIGRX
)
2729 CSR_WRITE_2(sc
, RE_MAXRXPKTLEN
, sc
->re_rxbuf_size
);
2731 CSR_WRITE_2(sc
, RE_MAXRXPKTLEN
, 16383);
2734 if (sc
->re_flags
& RE_F_TESTMODE
)
2739 CSR_WRITE_1(sc
, RE_CFG1
, RE_CFG1_DRVLOAD
|RE_CFG1_FULLDUPLEX
);
2741 ifp
->if_flags
|= IFF_RUNNING
;
2742 ifq_clr_oactive(&ifp
->if_snd
);
2744 callout_reset(&sc
->re_timer
, hz
, re_tick
, sc
);
2748 * Set media options.
2751 re_ifmedia_upd(struct ifnet
*ifp
)
2753 struct re_softc
*sc
= ifp
->if_softc
;
2754 struct mii_data
*mii
;
2756 ASSERT_SERIALIZED(ifp
->if_serializer
);
2758 mii
= device_get_softc(sc
->re_miibus
);
2765 * Report current media status.
2768 re_ifmedia_sts(struct ifnet
*ifp
, struct ifmediareq
*ifmr
)
2770 struct re_softc
*sc
= ifp
->if_softc
;
2771 struct mii_data
*mii
;
2773 ASSERT_SERIALIZED(ifp
->if_serializer
);
2775 mii
= device_get_softc(sc
->re_miibus
);
2778 ifmr
->ifm_active
= mii
->mii_media_active
;
2779 ifmr
->ifm_status
= mii
->mii_media_status
;
2783 re_ioctl(struct ifnet
*ifp
, u_long command
, caddr_t data
, struct ucred
*cr
)
2785 struct re_softc
*sc
= ifp
->if_softc
;
2786 struct ifreq
*ifr
= (struct ifreq
*) data
;
2787 struct mii_data
*mii
;
2788 int error
= 0, mask
;
2790 ASSERT_SERIALIZED(ifp
->if_serializer
);
2794 if (ifr
->ifr_mtu
> sc
->re_maxmtu
) {
2796 } else if (ifp
->if_mtu
!= ifr
->ifr_mtu
) {
2797 ifp
->if_mtu
= ifr
->ifr_mtu
;
2798 if (ifp
->if_flags
& IFF_RUNNING
)
2804 if (ifp
->if_flags
& IFF_UP
) {
2805 if (ifp
->if_flags
& IFF_RUNNING
) {
2806 if ((ifp
->if_flags
^ sc
->re_if_flags
) &
2807 (IFF_PROMISC
| IFF_ALLMULTI
))
2812 } else if (ifp
->if_flags
& IFF_RUNNING
) {
2815 sc
->re_if_flags
= ifp
->if_flags
;
2825 mii
= device_get_softc(sc
->re_miibus
);
2826 error
= ifmedia_ioctl(ifp
, ifr
, &mii
->mii_media
, command
);
2830 mask
= (ifr
->ifr_reqcap
^ ifp
->if_capenable
) &
2831 ifp
->if_capabilities
;
2832 ifp
->if_capenable
^= mask
;
2834 if (mask
& IFCAP_HWCSUM
) {
2835 if (ifp
->if_capenable
& IFCAP_TXCSUM
)
2836 ifp
->if_hwassist
= sc
->re_hwassist
;
2838 ifp
->if_hwassist
= 0;
2840 if (mask
&& (ifp
->if_flags
& IFF_RUNNING
))
2845 error
= ether_ioctl(ifp
, command
, data
);
2852 re_watchdog(struct ifnet
*ifp
)
2854 struct re_softc
*sc
= ifp
->if_softc
;
2856 ASSERT_SERIALIZED(ifp
->if_serializer
);
2858 if_printf(ifp
, "watchdog timeout\n");
2860 IFNET_STAT_INC(ifp
, oerrors
, 1);
2867 if (!ifq_is_empty(&ifp
->if_snd
))
2872 * Stop the adapter and free any mbufs allocated to the
2876 re_stop(struct re_softc
*sc
)
2878 struct ifnet
*ifp
= &sc
->arpcom
.ac_if
;
2881 ASSERT_SERIALIZED(ifp
->if_serializer
);
2883 /* Reset the adapter. */
2884 re_reset(sc
, ifp
->if_flags
& IFF_RUNNING
);
2887 callout_stop(&sc
->re_timer
);
2889 ifp
->if_flags
&= ~IFF_RUNNING
;
2890 ifq_clr_oactive(&ifp
->if_snd
);
2891 sc
->re_flags
&= ~(RE_F_TIMER_INTR
| RE_F_DROP_RXFRAG
| RE_F_LINKED
);
2893 CSR_WRITE_1(sc
, RE_COMMAND
, 0x00);
2894 CSR_WRITE_2(sc
, RE_IMR
, 0x0000);
2895 CSR_WRITE_2(sc
, RE_ISR
, 0xFFFF);
2897 re_free_rxchain(sc
);
2899 /* Free the TX list buffers. */
2900 for (i
= 0; i
< sc
->re_tx_desc_cnt
; i
++) {
2901 if (sc
->re_ldata
.re_tx_mbuf
[i
] != NULL
) {
2902 bus_dmamap_unload(sc
->re_ldata
.re_tx_mtag
,
2903 sc
->re_ldata
.re_tx_dmamap
[i
]);
2904 m_freem(sc
->re_ldata
.re_tx_mbuf
[i
]);
2905 sc
->re_ldata
.re_tx_mbuf
[i
] = NULL
;
2909 /* Free the RX list buffers. */
2910 for (i
= 0; i
< sc
->re_rx_desc_cnt
; i
++) {
2911 if (sc
->re_ldata
.re_rx_mbuf
[i
] != NULL
) {
2912 if ((sc
->re_flags
& RE_F_USE_JPOOL
) == 0) {
2913 bus_dmamap_unload(sc
->re_ldata
.re_rx_mtag
,
2914 sc
->re_ldata
.re_rx_dmamap
[i
]);
2916 m_freem(sc
->re_ldata
.re_rx_mbuf
[i
]);
2917 sc
->re_ldata
.re_rx_mbuf
[i
] = NULL
;
2923 * Device suspend routine. Stop the interface and save some PCI
2924 * settings in case the BIOS doesn't restore them properly on
2928 re_suspend(device_t dev
)
2930 #ifndef BURN_BRIDGES
2933 struct re_softc
*sc
= device_get_softc(dev
);
2934 struct ifnet
*ifp
= &sc
->arpcom
.ac_if
;
2936 lwkt_serialize_enter(ifp
->if_serializer
);
2940 #ifndef BURN_BRIDGES
2941 for (i
= 0; i
< 5; i
++)
2942 sc
->saved_maps
[i
] = pci_read_config(dev
, PCIR_MAPS
+ i
* 4, 4);
2943 sc
->saved_biosaddr
= pci_read_config(dev
, PCIR_BIOS
, 4);
2944 sc
->saved_intline
= pci_read_config(dev
, PCIR_INTLINE
, 1);
2945 sc
->saved_cachelnsz
= pci_read_config(dev
, PCIR_CACHELNSZ
, 1);
2946 sc
->saved_lattimer
= pci_read_config(dev
, PCIR_LATTIMER
, 1);
2949 sc
->re_flags
|= RE_F_SUSPENDED
;
2951 lwkt_serialize_exit(ifp
->if_serializer
);
2957 * Device resume routine. Restore some PCI settings in case the BIOS
2958 * doesn't, re-enable busmastering, and restart the interface if
2962 re_resume(device_t dev
)
2964 struct re_softc
*sc
= device_get_softc(dev
);
2965 struct ifnet
*ifp
= &sc
->arpcom
.ac_if
;
2966 #ifndef BURN_BRIDGES
2970 lwkt_serialize_enter(ifp
->if_serializer
);
2972 #ifndef BURN_BRIDGES
2973 /* better way to do this? */
2974 for (i
= 0; i
< 5; i
++)
2975 pci_write_config(dev
, PCIR_MAPS
+ i
* 4, sc
->saved_maps
[i
], 4);
2976 pci_write_config(dev
, PCIR_BIOS
, sc
->saved_biosaddr
, 4);
2977 pci_write_config(dev
, PCIR_INTLINE
, sc
->saved_intline
, 1);
2978 pci_write_config(dev
, PCIR_CACHELNSZ
, sc
->saved_cachelnsz
, 1);
2979 pci_write_config(dev
, PCIR_LATTIMER
, sc
->saved_lattimer
, 1);
2981 /* reenable busmastering */
2982 pci_enable_busmaster(dev
);
2983 pci_enable_io(dev
, SYS_RES_IOPORT
);
2986 /* reinitialize interface if necessary */
2987 if (ifp
->if_flags
& IFF_UP
)
2990 sc
->re_flags
&= ~RE_F_SUSPENDED
;
2992 lwkt_serialize_exit(ifp
->if_serializer
);
2998 * Stop all chip I/O so that the kernel's probe routines don't
2999 * get confused by errant DMAs when rebooting.
3002 re_shutdown(device_t dev
)
3004 struct re_softc
*sc
= device_get_softc(dev
);
3005 struct ifnet
*ifp
= &sc
->arpcom
.ac_if
;
3007 lwkt_serialize_enter(ifp
->if_serializer
);
3009 lwkt_serialize_exit(ifp
->if_serializer
);
3013 re_sysctl_rxtime(SYSCTL_HANDLER_ARGS
)
3015 struct re_softc
*sc
= arg1
;
3017 return re_sysctl_hwtime(oidp
, arg1
, arg2
, req
, &sc
->re_rx_time
);
3021 re_sysctl_txtime(SYSCTL_HANDLER_ARGS
)
3023 struct re_softc
*sc
= arg1
;
3025 return re_sysctl_hwtime(oidp
, arg1
, arg2
, req
, &sc
->re_tx_time
);
3029 re_sysctl_hwtime(SYSCTL_HANDLER_ARGS
, int *hwtime
)
3031 struct re_softc
*sc
= arg1
;
3032 struct ifnet
*ifp
= &sc
->arpcom
.ac_if
;
3035 lwkt_serialize_enter(ifp
->if_serializer
);
3038 error
= sysctl_handle_int(oidp
, &v
, 0, req
);
3039 if (error
|| req
->newptr
== NULL
)
3050 if ((ifp
->if_flags
& (IFF_RUNNING
| IFF_NPOLLING
)) ==
3051 IFF_RUNNING
&& sc
->re_imtype
== RE_IMTYPE_HW
)
3055 lwkt_serialize_exit(ifp
->if_serializer
);
3060 re_sysctl_simtime(SYSCTL_HANDLER_ARGS
)
3062 struct re_softc
*sc
= arg1
;
3063 struct ifnet
*ifp
= &sc
->arpcom
.ac_if
;
3066 lwkt_serialize_enter(ifp
->if_serializer
);
3068 v
= sc
->re_sim_time
;
3069 error
= sysctl_handle_int(oidp
, &v
, 0, req
);
3070 if (error
|| req
->newptr
== NULL
)
3078 if (v
!= sc
->re_sim_time
) {
3079 sc
->re_sim_time
= v
;
3081 if ((ifp
->if_flags
& (IFF_RUNNING
| IFF_NPOLLING
)) ==
3082 IFF_RUNNING
&& sc
->re_imtype
== RE_IMTYPE_SIM
) {
3087 * Following code causes various strange
3088 * performance problems. Hmm ...
3090 CSR_WRITE_2(sc
, RE_IMR
, 0);
3091 if (!RE_IS_8139CP(sc
))
3092 reg
= RE_TIMERINT_8169
;
3095 CSR_WRITE_4(sc
, reg
, 0);
3096 CSR_READ_4(sc
, reg
); /* flush */
3098 CSR_WRITE_2(sc
, RE_IMR
, sc
->re_intrs
);
3099 re_setup_sim_im(sc
);
3101 re_setup_intr(sc
, 0, RE_IMTYPE_NONE
);
3103 re_setup_intr(sc
, 1, RE_IMTYPE_SIM
);
3108 lwkt_serialize_exit(ifp
->if_serializer
);
3113 re_sysctl_imtype(SYSCTL_HANDLER_ARGS
)
3115 struct re_softc
*sc
= arg1
;
3116 struct ifnet
*ifp
= &sc
->arpcom
.ac_if
;
3119 lwkt_serialize_enter(ifp
->if_serializer
);
3122 error
= sysctl_handle_int(oidp
, &v
, 0, req
);
3123 if (error
|| req
->newptr
== NULL
)
3126 if (v
!= RE_IMTYPE_HW
&& v
!= RE_IMTYPE_SIM
&& v
!= RE_IMTYPE_NONE
) {
3130 if (v
== RE_IMTYPE_HW
&& (sc
->re_caps
& RE_C_HWIM
) == 0) {
3131 /* Can't do hardware interrupt moderation */
3136 if (v
!= sc
->re_imtype
) {
3138 if ((ifp
->if_flags
& (IFF_RUNNING
| IFF_NPOLLING
)) ==
3140 re_setup_intr(sc
, 1, sc
->re_imtype
);
3143 lwkt_serialize_exit(ifp
->if_serializer
);
3148 re_setup_hw_im(struct re_softc
*sc
)
3150 KKASSERT(sc
->re_caps
& RE_C_HWIM
);
3153 * Interrupt moderation
3156 * A - unknown (maybe TX related)
3157 * B - TX timer (unit: 25us)
3158 * C - unknown (maybe RX related)
3159 * D - RX timer (unit: 25us)
3162 * re(4)'s interrupt moderation is actually controlled by
3163 * two variables, like most other NICs (bge, bce etc.)
3165 * o number of packets [P]
3167 * The logic relationship between these two variables is
3168 * similar to other NICs too:
3169 * if (timer expire || packets > [P])
3170 * Interrupt is delivered
3172 * Currently we only know how to set 'timer', but not
3173 * 'number of packets', which should be ~30, as far as I
3174 * tested (sink ~900Kpps, interrupt rate is 30KHz)
3176 CSR_WRITE_2(sc
, RE_IM
,
3177 RE_IM_RXTIME(sc
->re_rx_time
) |
3178 RE_IM_TXTIME(sc
->re_tx_time
) |
3183 re_disable_hw_im(struct re_softc
*sc
)
3185 if (sc
->re_caps
& RE_C_HWIM
)
3186 CSR_WRITE_2(sc
, RE_IM
, 0);
3190 re_setup_sim_im(struct re_softc
*sc
)
3192 if (!RE_IS_8139CP(sc
)) {
3196 * Datasheet says tick decreases at bus speed,
3197 * but it seems the clock runs a little bit
3198 * faster, so we do some compensation here.
3200 ticks
= (sc
->re_sim_time
* sc
->re_bus_speed
* 8) / 5;
3201 CSR_WRITE_4(sc
, RE_TIMERINT_8169
, ticks
);
3203 CSR_WRITE_4(sc
, RE_TIMERINT
, 0x400); /* XXX */
3205 CSR_WRITE_4(sc
, RE_TIMERCNT
, 1); /* reload */
3206 sc
->re_flags
|= RE_F_TIMER_INTR
;
3210 re_disable_sim_im(struct re_softc
*sc
)
3212 if (!RE_IS_8139CP(sc
))
3213 CSR_WRITE_4(sc
, RE_TIMERINT_8169
, 0);
3215 CSR_WRITE_4(sc
, RE_TIMERINT
, 0);
3216 sc
->re_flags
&= ~RE_F_TIMER_INTR
;
3220 re_config_imtype(struct re_softc
*sc
, int imtype
)
3224 KKASSERT(sc
->re_caps
& RE_C_HWIM
);
3226 case RE_IMTYPE_NONE
:
3227 sc
->re_intrs
= RE_INTRS
;
3228 sc
->re_rx_ack
= RE_ISR_RX_OK
| RE_ISR_FIFO_OFLOW
|
3230 sc
->re_tx_ack
= RE_ISR_TX_OK
;
3234 sc
->re_intrs
= RE_INTRS_TIMER
;
3235 sc
->re_rx_ack
= RE_ISR_TIMEOUT_EXPIRED
;
3236 sc
->re_tx_ack
= RE_ISR_TIMEOUT_EXPIRED
;
3240 panic("%s: unknown imtype %d",
3241 sc
->arpcom
.ac_if
.if_xname
, imtype
);
3246 re_setup_intr(struct re_softc
*sc
, int enable_intrs
, int imtype
)
3248 re_config_imtype(sc
, imtype
);
3251 CSR_WRITE_2(sc
, RE_IMR
, sc
->re_intrs
);
3253 CSR_WRITE_2(sc
, RE_IMR
, 0);
3255 sc
->re_npoll
.ifpc_stcount
= 0;
3258 case RE_IMTYPE_NONE
:
3259 re_disable_sim_im(sc
);
3260 re_disable_hw_im(sc
);
3264 KKASSERT(sc
->re_caps
& RE_C_HWIM
);
3265 re_disable_sim_im(sc
);
3270 re_disable_hw_im(sc
);
3271 re_setup_sim_im(sc
);
3275 panic("%s: unknown imtype %d",
3276 sc
->arpcom
.ac_if
.if_xname
, imtype
);
3281 re_get_eaddr(struct re_softc
*sc
, uint8_t *eaddr
)
3285 if (sc
->re_caps
& RE_C_EE_EADDR
) {
3289 re_read_eeprom(sc
, (caddr_t
)&re_did
, 0, 1);
3290 if (re_did
== 0x8128) {
3291 uint16_t as
[ETHER_ADDR_LEN
/ 2];
3294 * Get station address from the EEPROM.
3296 re_read_eeprom(sc
, (caddr_t
)as
, sc
->re_ee_eaddr
, 3);
3297 for (i
= 0; i
< ETHER_ADDR_LEN
/ 2; i
++)
3298 as
[i
] = le16toh(as
[i
]);
3299 bcopy(as
, eaddr
, ETHER_ADDR_LEN
);
3305 * Get station address from IDRx.
3307 for (i
= 0; i
< ETHER_ADDR_LEN
; ++i
)
3308 eaddr
[i
] = CSR_READ_1(sc
, RE_IDR0
+ i
);
3312 re_jpool_alloc(struct re_softc
*sc
)
3314 struct re_list_data
*ldata
= &sc
->re_ldata
;
3315 struct re_jbuf
*jbuf
;
3317 bus_size_t jpool_size
;
3322 lwkt_serialize_init(&ldata
->re_jbuf_serializer
);
3324 ldata
->re_jbuf
= kmalloc(sizeof(struct re_jbuf
) * RE_JBUF_COUNT(sc
),
3325 M_DEVBUF
, M_WAITOK
| M_ZERO
);
3327 jpool_size
= RE_JBUF_COUNT(sc
) * RE_JBUF_SIZE
;
3329 error
= bus_dmamem_coherent(sc
->re_parent_tag
,
3331 BUS_SPACE_MAXADDR
, BUS_SPACE_MAXADDR
,
3332 jpool_size
, BUS_DMA_WAITOK
, &dmem
);
3334 device_printf(sc
->re_dev
, "could not allocate jumbo memory\n");
3337 ldata
->re_jpool_tag
= dmem
.dmem_tag
;
3338 ldata
->re_jpool_map
= dmem
.dmem_map
;
3339 ldata
->re_jpool
= dmem
.dmem_addr
;
3340 paddr
= dmem
.dmem_busaddr
;
3342 /* ..and split it into 9KB chunks */
3343 SLIST_INIT(&ldata
->re_jbuf_free
);
3345 buf
= ldata
->re_jpool
;
3346 for (i
= 0; i
< RE_JBUF_COUNT(sc
); i
++) {
3347 jbuf
= &ldata
->re_jbuf
[i
];
3353 jbuf
->re_paddr
= paddr
;
3355 SLIST_INSERT_HEAD(&ldata
->re_jbuf_free
, jbuf
, re_link
);
3357 buf
+= RE_JBUF_SIZE
;
3358 paddr
+= RE_JBUF_SIZE
;
3364 re_jpool_free(struct re_softc
*sc
)
3366 struct re_list_data
*ldata
= &sc
->re_ldata
;
3368 if (ldata
->re_jpool_tag
!= NULL
) {
3369 bus_dmamap_unload(ldata
->re_jpool_tag
, ldata
->re_jpool_map
);
3370 bus_dmamem_free(ldata
->re_jpool_tag
, ldata
->re_jpool
,
3371 ldata
->re_jpool_map
);
3372 bus_dma_tag_destroy(ldata
->re_jpool_tag
);
3373 ldata
->re_jpool_tag
= NULL
;
3376 if (ldata
->re_jbuf
!= NULL
) {
3377 kfree(ldata
->re_jbuf
, M_DEVBUF
);
3378 ldata
->re_jbuf
= NULL
;
3382 static struct re_jbuf
*
3383 re_jbuf_alloc(struct re_softc
*sc
)
3385 struct re_list_data
*ldata
= &sc
->re_ldata
;
3386 struct re_jbuf
*jbuf
;
3388 lwkt_serialize_enter(&ldata
->re_jbuf_serializer
);
3390 jbuf
= SLIST_FIRST(&ldata
->re_jbuf_free
);
3392 SLIST_REMOVE_HEAD(&ldata
->re_jbuf_free
, re_link
);
3396 lwkt_serialize_exit(&ldata
->re_jbuf_serializer
);
3402 re_jbuf_free(void *arg
)
3404 struct re_jbuf
*jbuf
= arg
;
3405 struct re_softc
*sc
= jbuf
->re_sc
;
3406 struct re_list_data
*ldata
= &sc
->re_ldata
;
3408 if (&ldata
->re_jbuf
[jbuf
->re_slot
] != jbuf
) {
3409 panic("%s: free wrong jumbo buffer",
3410 sc
->arpcom
.ac_if
.if_xname
);
3411 } else if (jbuf
->re_inuse
== 0) {
3412 panic("%s: jumbo buffer already freed",
3413 sc
->arpcom
.ac_if
.if_xname
);
3416 lwkt_serialize_enter(&ldata
->re_jbuf_serializer
);
3417 atomic_subtract_int(&jbuf
->re_inuse
, 1);
3418 if (jbuf
->re_inuse
== 0)
3419 SLIST_INSERT_HEAD(&ldata
->re_jbuf_free
, jbuf
, re_link
);
3420 lwkt_serialize_exit(&ldata
->re_jbuf_serializer
);
3424 re_jbuf_ref(void *arg
)
3426 struct re_jbuf
*jbuf
= arg
;
3427 struct re_softc
*sc
= jbuf
->re_sc
;
3428 struct re_list_data
*ldata
= &sc
->re_ldata
;
3430 if (&ldata
->re_jbuf
[jbuf
->re_slot
] != jbuf
) {
3431 panic("%s: ref wrong jumbo buffer",
3432 sc
->arpcom
.ac_if
.if_xname
);
3433 } else if (jbuf
->re_inuse
== 0) {
3434 panic("%s: jumbo buffer already freed",
3435 sc
->arpcom
.ac_if
.if_xname
);
3437 atomic_add_int(&jbuf
->re_inuse
, 1);