sys/dev/netif/ar/if_arregs.h

   1 /*-
   2  * Copyright (c) 1995 - 2001 John Hay.  All rights reserved.
   3  *
   4  * Redistribution and use in source and binary forms, with or without
   5  * modification, are permitted provided that the following conditions
   6  * are met:
   7  * 1. Redistributions of source code must retain the above copyright
   8  *    notice, this list of conditions and the following disclaimer.
   9  * 2. Redistributions in binary form must reproduce the above copyright
  10  *    notice, this list of conditions and the following disclaimer in the
  11  *    documentation and/or other materials provided with the distribution.
  12  * 3. Neither the name of the author nor the names of any co-contributors
  13  *    may be used to endorse or promote products derived from this software
  14  *    without specific prior written permission.
  15  *
  16  * THIS SOFTWARE IS PROVIDED BY [your name] AND CONTRIBUTORS ``AS IS'' AND
  17  * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
  18  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
  19  * ARE DISCLAIMED.  IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE
  20  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
  21  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
  22  * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
  23  * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
  24  * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
  25  * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
  26  * SUCH DAMAGE.
  27  *
  28  * $FreeBSD: src/sys/dev/ar/if_arregs.h,v 1.10 2005/01/06 01:42:28 imp Exp $
  29  * $DragonFly: src/sys/dev/netif/ar/if_arregs.h,v 1.3 2005/02/08 14:31:16 joerg Exp $
  30  */
  31 #ifndef _IF_ARREGS_H_
  32 #define _IF_ARREGS_H_
  33
  34 #define NCHAN                   2    /* A HD64570 chip have 2 channels */
  35 #define NPORT                   4    /* An ArNet board can have 4 ports or */
  36                                      /* channels */
  37
  38 #define AR_BUF_SIZ              512
  39 #define AR_TX_BLOCKS            2
  40 #define ARC_IO_SIZ              0x10
  41 #define ARC_WIN_SIZ             0x00004000
  42 #define ARC_WIN_MSK             (ARC_WIN_SIZ - 1)
  43 #define ARC_WIN_SHFT            14
  44
  45 /* Some PCI specific offsets. */
  46 #define AR_PCI_SCA_1_OFFSET     0x00040000
  47 #define AR_PCI_SCA_2_OFFSET     0x00040400
  48 #define AR_PCI_ORBASE_OFFSET    0x00041000
  49 #define AR_PCI_SCA_PCR          0x0208
  50 #define AR_PCI_SCA_DMER         0x0309
  51 /* PCI Legacy (below 1M) offsets. */
  52 #define AR_PCI_L_SCA_1_OFFSET   0x00004000
  53 #define AR_PCI_L_SCA_2_OFFSET   0x00004400
  54 #define AR_PCI_L_ORBASE_OFFSET  0x00005000
  55
  56 #define AR_ID_5                 0x00 /* RO, Card probe '5' */
  57 #define AR_ID_7                 0x01 /* RO, Card probe '7' */
  58 #define AR_ID_0                 0x02 /* RO, Card probe '0' */
  59 #define AR_BMI                  0x03 /* RO, Bus, mem and interface type */
  60 #define AR_REV                  0x04 /* RO, Adapter revision */
  61 #define AR_PNUM                 0x05 /* RO, Port number */
  62 #define AR_HNDSH                0x06 /* RO, Supported handshake */
  63 #define AR_ISTAT                0x07 /* RO, DCD and Interrupt status */
  64 #define AR_MSCA_EN              0x08 /* WO, Memory and SCA enable */
  65 #define AR_TXC_DTR0             0x09 /* WO, Tx Clock and DTR control 0 + 1 */
  66 #define AR_SEC_PAL              0x0A /* RW, Security PAL */
  67 #define AR_INT_ACK0             0x0B /* RO, Interrupt Acknowledge 0 + 1 */
  68 #define AR_INT_SEL              0x0C /* RW, Interrupt Select */
  69 #define AR_MEM_SEL              0x0D /* RW, Memory Select */
  70 #define AR_INT_ACK2             0x0E /* RO, Interrupt Acknowledge 2 + 3 */
  71 #define AR_TXC_DTR2             0x0E /* WO, Tx Clock and DTR control 2 + 3 */
  72 /* PCI only */
  73 #define AR_PIMCTRL              0x4C /* RW, PIM and LEDs */
  74 #define AR_INT_SCB              0x50 /* RO, Interrupt Scoreboard */
  75
  76 #define AR_REV_MSK              0x0F
  77 #define AR_WSIZ_MSK             0xE0
  78 #define AR_WSIZ_SHFT            5
  79 /* Bus memory and interface type */
  80 #define AR_BUS_MSK              0x03
  81 #define AR_BUS_ISA              0x00
  82 #define AR_BUS_MCA              0x01
  83 #define AR_BUS_EISA             0x02
  84 #define AR_BUS_PCI              0x03
  85
  86 #define AR_MEM_MSK              0x1C
  87 #define AR_MEM_SHFT             0x02
  88 #define AR_MEM_64K              0x00
  89 #define AR_MEM_128K             0x04
  90 #define AR_MEM_256K             0x08
  91 #define AR_MEM_512K             0x0C
  92
  93 /*
  94  * EIA-232
  95  * V.35/EIA-232
  96  * EIA-530
  97  * X.21
  98  * EIA-530/X.21 Combo
  99  */
 100 #define AR_IFACE_MSK            0xE0
 101 #define AR_IFACE_SHFT           0x05
 102 #define AR_IFACE_EIA_232        0x00  /* Only on the 570 card, not 570i */
 103 #define AR_IFACE_V_35           0x20  /* Selectable between V.35 and EIA-232 */
 104 #define AR_IFACE_EIA_530        0x40
 105 #define AR_IFACE_X_21           0x60
 106 #define AR_IFACE_COMBO          0xC0  /* X.21 / EIA-530 */
 107 #define AR_IFACE_PIM            0xE0  /* PIM module */
 108 #define AR_IFACE_LOOPBACK       0xFE
 109 #define AR_IFACE_UNKNOWN        0xFF
 110
 111 /* Supported Handshake signals */
 112 #define AR_SHSK_DTR             0x01
 113 #define AR_SHSK_RTS             0x02
 114 #define AR_SHSK_CTS             0x10
 115 #define AR_SHSK_DSR             0x20
 116 #define AR_SHSK_RI              0x40
 117 #define AR_SHSK_DCD             0x80
 118
 119 /* DCD and Interrupt status */
 120 #define AR_BD_INT               0x01
 121 #define AR_INT_0                0x20
 122 #define AR_INT_1                0x40
 123
 124 #define AR_DCD_MSK              0x1E
 125 #define AR_DCD_SHFT             0x01
 126 #define AR_DCD_0                0x02
 127 #define AR_DCD_1                0x04
 128 #define AR_DCD_2                0x08
 129 #define AR_DCD_3                0x10
 130
 131 /* Memory and SCA enable */
 132 #define AR_WIN_MSK              0x1F
 133
 134 #define AR_SEL_SCA_0            0x00
 135 #define AR_SEL_SCA_1            0x20
 136 #define AR_ENA_SCA              0x40
 137 #define AR_ENA_MEM              0x80
 138
 139 /* Transmit Clock and DTR and RESET */
 140 #define AR_TXC_DTR_TX0          0x01
 141 #define AR_TXC_DTR_TX1          0x02
 142 #define AR_TXC_DTR_DTR0         0x04
 143 #define AR_TXC_DTR_DTR1         0x08
 144 #define AR_TXC_DTR_TXCS0        0x10
 145 #define AR_TXC_DTR_TXCS1        0x20
 146 #define AR_TXC_DTR_NOTRESET     0x40
 147 #define AR_TXC_DTR_RESET        0x00
 148
 149 /* Interrupt select register */
 150 #define AR_INTS_CEN             0x01
 151 #define AR_INTS_ISEL0           0x02
 152 #define AR_INTS_ISEL1           0x04
 153 #define AR_INTS_ISEL2           0x08
 154 #define AR_INTS_CMA14           0x10
 155 #define AR_INTS_CMA15           0x20
 156
 157 /* Advanced PIM Control */
 158 #define AR_PIM_STROBE           0x01
 159 #define AR_PIM_DATA             0x02
 160 #define AR_PIM_MODEG            0x04
 161 #define AR_PIM_A2D_STROBE       0x04
 162 #define AR_PIM_MODEY            0x08
 163 #define AR_PIM_A2D_DOUT         0x08
 164 #define AR_PIM_AUTO_LED         0x10
 165 #define AR_PIM_INT              0x20
 166
 167 #define AR_PIM_RESET            0x00 /* MODEG and MODEY 0 */
 168 #define AR_PIM_READ             AR_PIM_MODEG
 169 #define AR_PIM_WRITE            AR_PIM_MODEY
 170
 171 #define ARC_GET_WIN(addr)       ((addr >> ARC_WIN_SHFT) & AR_WIN_MSK)
 172
 173 #define ARC_SET_MEM(hc,win)     ar_outb(hc, AR_MSCA_EN, AR_ENA_MEM | \
 174                                 ARC_GET_WIN(win))
 175 #define ARC_SET_SCA(hc,ch)      ar_outb(hc, AR_MSCA_EN, AR_ENA_MEM | \
 176                                 AR_ENA_SCA | (ch ? AR_SEL_SCA_1:AR_SEL_SCA_0))
 177 #define ARC_SET_OFF(hc)         ar_outb(hc, AR_MSCA_EN, 0)
 178
 179 struct ar_hardc {
 180         int cunit;
 181         struct ar_softc *sc;
 182         int isa_irq;
 183         int numports;
 184         caddr_t mem_start;
 185         caddr_t mem_end;
 186         u_char *orbase;
 187
 188         u_int memsize;          /* in bytes */
 189         u_int winsize;          /* in bytes */
 190         u_int winmsk;
 191         u_char bustype;         /* ISA, MCA, PCI.... */
 192         u_char interface[NPORT];/* X21, V.35, EIA-530.... */
 193         u_char revision;
 194         u_char handshake;       /* handshake lines supported by card. */
 195
 196         u_char txc_dtr[NPORT/NCHAN]; /* the register is write only */
 197         u_int txc_dtr_off[NPORT/NCHAN];
 198
 199         sca_regs *sca[NPORT/NCHAN];
 200
 201         bus_space_tag_t bt;
 202         bus_space_handle_t bh;
 203         int rid_ioport;
 204         int rid_memory;
 205         int rid_plx_memory;
 206         int rid_irq;
 207         int rid_drq;
 208         struct resource* res_ioport;    /* resource for port range */
 209         struct resource* res_memory;    /* resource for mem range */
 210         struct resource* res_plx_memory;
 211         struct resource* res_irq;       /* resource for irq range */
 212         struct resource* res_drq;       /* resource for dma channel */
 213         void    *intr_cookie;
 214 };
 215
 216 extern devclass_t ar_devclass;
 217
 218 int ar_allocate_ioport(device_t device, int rid, u_long size);
 219 int ar_allocate_irq(device_t device, int rid, u_long size);
 220 int ar_allocate_memory(device_t device, int rid, u_long size);
 221 int ar_allocate_plx_memory(device_t device, int rid, u_long size);
 222 int ar_deallocate_resources(device_t device);
 223 int ar_attach(device_t device);
 224 int ar_detach (device_t);
 225
 226 #define ar_inb(hc, port) \
 227         bus_space_read_1((hc)->bt, (hc)->bh, (port))
 228
 229 #define ar_outb(hc, port, value) \
 230         bus_space_write_1((hc)->bt, (hc)->bh, (port), (value))
 231
 232 #endif /* _IF_ARREGS_H_ */