2 * Copyright © 2008 Keith Packard
4 * Permission to use, copy, modify, distribute, and sell this software and its
5 * documentation for any purpose is hereby granted without fee, provided that
6 * the above copyright notice appear in all copies and that both that copyright
7 * notice and this permission notice appear in supporting documentation, and
8 * that the name of the copyright holders not be used in advertising or
9 * publicity pertaining to distribution of the software without specific,
10 * written prior permission. The copyright holders make no representations
11 * about the suitability of this software for any purpose. It is provided "as
12 * is" without express or implied warranty.
14 * THE COPYRIGHT HOLDERS DISCLAIM ALL WARRANTIES WITH REGARD TO THIS SOFTWARE,
15 * INCLUDING ALL IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS, IN NO
16 * EVENT SHALL THE COPYRIGHT HOLDERS BE LIABLE FOR ANY SPECIAL, INDIRECT OR
17 * CONSEQUENTIAL DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE,
18 * DATA OR PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER
19 * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR PERFORMANCE
23 #ifndef _DRM_DP_HELPER_H_
24 #define _DRM_DP_HELPER_H_
26 #include <linux/types.h>
27 #include <linux/i2c.h>
28 #include <linux/delay.h>
31 * Unless otherwise noted, all values are from the DP 1.1a spec. Note that
32 * DP and DPCD versions are independent. Differences from 1.0 are not noted,
33 * 1.0 devices basically don't exist in the wild.
35 * Abbreviations, in chronological order:
37 * eDP: Embedded DisplayPort version 1
38 * DPI: DisplayPort Interoperability Guideline v1.1a
39 * 1.2: DisplayPort 1.2
40 * MST: Multistream Transport - part of DP 1.2a
42 * 1.2 formally includes both eDP and DPI definitions.
45 #define DP_AUX_I2C_WRITE 0x0
46 #define DP_AUX_I2C_READ 0x1
47 #define DP_AUX_I2C_STATUS 0x2
48 #define DP_AUX_I2C_MOT 0x4
49 #define DP_AUX_NATIVE_WRITE 0x8
50 #define DP_AUX_NATIVE_READ 0x9
52 #define DP_AUX_NATIVE_REPLY_ACK (0x0 << 0)
53 #define DP_AUX_NATIVE_REPLY_NACK (0x1 << 0)
54 #define DP_AUX_NATIVE_REPLY_DEFER (0x2 << 0)
55 #define DP_AUX_NATIVE_REPLY_MASK (0x3 << 0)
57 #define DP_AUX_I2C_REPLY_ACK (0x0 << 2)
58 #define DP_AUX_I2C_REPLY_NACK (0x1 << 2)
59 #define DP_AUX_I2C_REPLY_DEFER (0x2 << 2)
60 #define DP_AUX_I2C_REPLY_MASK (0x3 << 2)
62 /* AUX CH addresses */
64 #define DP_DPCD_REV 0x000
66 #define DP_MAX_LINK_RATE 0x001
68 #define DP_MAX_LANE_COUNT 0x002
69 # define DP_MAX_LANE_COUNT_MASK 0x1f
70 # define DP_TPS3_SUPPORTED (1 << 6) /* 1.2 */
71 # define DP_ENHANCED_FRAME_CAP (1 << 7)
73 #define DP_MAX_DOWNSPREAD 0x003
74 # define DP_NO_AUX_HANDSHAKE_LINK_TRAINING (1 << 6)
78 #define DP_DOWNSTREAMPORT_PRESENT 0x005
79 # define DP_DWN_STRM_PORT_PRESENT (1 << 0)
80 # define DP_DWN_STRM_PORT_TYPE_MASK 0x06
81 # define DP_DWN_STRM_PORT_TYPE_DP (0 << 1)
82 # define DP_DWN_STRM_PORT_TYPE_ANALOG (1 << 1)
83 # define DP_DWN_STRM_PORT_TYPE_TMDS (2 << 1)
84 # define DP_DWN_STRM_PORT_TYPE_OTHER (3 << 1)
85 # define DP_FORMAT_CONVERSION (1 << 3)
86 # define DP_DETAILED_CAP_INFO_AVAILABLE (1 << 4) /* DPI */
88 #define DP_MAIN_LINK_CHANNEL_CODING 0x006
90 #define DP_DOWN_STREAM_PORT_COUNT 0x007
91 # define DP_PORT_COUNT_MASK 0x0f
92 # define DP_MSA_TIMING_PAR_IGNORED (1 << 6) /* eDP */
93 # define DP_OUI_SUPPORT (1 << 7)
95 #define DP_I2C_SPEED_CAP 0x00c /* DPI */
96 # define DP_I2C_SPEED_1K 0x01
97 # define DP_I2C_SPEED_5K 0x02
98 # define DP_I2C_SPEED_10K 0x04
99 # define DP_I2C_SPEED_100K 0x08
100 # define DP_I2C_SPEED_400K 0x10
101 # define DP_I2C_SPEED_1M 0x20
103 #define DP_EDP_CONFIGURATION_CAP 0x00d /* XXX 1.2? */
104 #define DP_TRAINING_AUX_RD_INTERVAL 0x00e /* XXX 1.2? */
106 /* Multiple stream transport */
107 #define DP_FAUX_CAP 0x020 /* 1.2 */
108 # define DP_FAUX_CAP_1 (1 << 0)
110 #define DP_MSTM_CAP 0x021 /* 1.2 */
111 # define DP_MST_CAP (1 << 0)
113 #define DP_GUID 0x030 /* 1.2 */
115 #define DP_PSR_SUPPORT 0x070 /* XXX 1.2? */
116 # define DP_PSR_IS_SUPPORTED 1
117 #define DP_PSR_CAPS 0x071 /* XXX 1.2? */
118 # define DP_PSR_NO_TRAIN_ON_EXIT 1
119 # define DP_PSR_SETUP_TIME_330 (0 << 1)
120 # define DP_PSR_SETUP_TIME_275 (1 << 1)
121 # define DP_PSR_SETUP_TIME_220 (2 << 1)
122 # define DP_PSR_SETUP_TIME_165 (3 << 1)
123 # define DP_PSR_SETUP_TIME_110 (4 << 1)
124 # define DP_PSR_SETUP_TIME_55 (5 << 1)
125 # define DP_PSR_SETUP_TIME_0 (6 << 1)
126 # define DP_PSR_SETUP_TIME_MASK (7 << 1)
127 # define DP_PSR_SETUP_TIME_SHIFT 1
130 * 0x80-0x8f describe downstream port capabilities, but there are two layouts
131 * based on whether DP_DETAILED_CAP_INFO_AVAILABLE was set. If it was not,
132 * each port's descriptor is one byte wide. If it was set, each port's is
133 * four bytes wide, starting with the one byte from the base info. As of
134 * DP interop v1.1a only VGA defines additional detail.
138 #define DP_DOWNSTREAM_PORT_0 0x80
139 # define DP_DS_PORT_TYPE_MASK (7 << 0)
140 # define DP_DS_PORT_TYPE_DP 0
141 # define DP_DS_PORT_TYPE_VGA 1
142 # define DP_DS_PORT_TYPE_DVI 2
143 # define DP_DS_PORT_TYPE_HDMI 3
144 # define DP_DS_PORT_TYPE_NON_EDID 4
145 # define DP_DS_PORT_HPD (1 << 3)
146 /* offset 1 for VGA is maximum megapixels per second / 8 */
148 # define DP_DS_VGA_MAX_BPC_MASK (3 << 0)
149 # define DP_DS_VGA_8BPC 0
150 # define DP_DS_VGA_10BPC 1
151 # define DP_DS_VGA_12BPC 2
152 # define DP_DS_VGA_16BPC 3
154 /* link configuration */
155 #define DP_LINK_BW_SET 0x100
156 # define DP_LINK_BW_1_62 0x06
157 # define DP_LINK_BW_2_7 0x0a
158 # define DP_LINK_BW_5_4 0x14 /* 1.2 */
160 #define DP_LANE_COUNT_SET 0x101
161 # define DP_LANE_COUNT_MASK 0x0f
162 # define DP_LANE_COUNT_ENHANCED_FRAME_EN (1 << 7)
164 #define DP_TRAINING_PATTERN_SET 0x102
165 # define DP_TRAINING_PATTERN_DISABLE 0
166 # define DP_TRAINING_PATTERN_1 1
167 # define DP_TRAINING_PATTERN_2 2
168 # define DP_TRAINING_PATTERN_3 3 /* 1.2 */
169 # define DP_TRAINING_PATTERN_MASK 0x3
171 # define DP_LINK_QUAL_PATTERN_DISABLE (0 << 2)
172 # define DP_LINK_QUAL_PATTERN_D10_2 (1 << 2)
173 # define DP_LINK_QUAL_PATTERN_ERROR_RATE (2 << 2)
174 # define DP_LINK_QUAL_PATTERN_PRBS7 (3 << 2)
175 # define DP_LINK_QUAL_PATTERN_MASK (3 << 2)
177 # define DP_RECOVERED_CLOCK_OUT_EN (1 << 4)
178 # define DP_LINK_SCRAMBLING_DISABLE (1 << 5)
180 # define DP_SYMBOL_ERROR_COUNT_BOTH (0 << 6)
181 # define DP_SYMBOL_ERROR_COUNT_DISPARITY (1 << 6)
182 # define DP_SYMBOL_ERROR_COUNT_SYMBOL (2 << 6)
183 # define DP_SYMBOL_ERROR_COUNT_MASK (3 << 6)
185 #define DP_TRAINING_LANE0_SET 0x103
186 #define DP_TRAINING_LANE1_SET 0x104
187 #define DP_TRAINING_LANE2_SET 0x105
188 #define DP_TRAINING_LANE3_SET 0x106
190 # define DP_TRAIN_VOLTAGE_SWING_MASK 0x3
191 # define DP_TRAIN_VOLTAGE_SWING_SHIFT 0
192 # define DP_TRAIN_MAX_SWING_REACHED (1 << 2)
193 # define DP_TRAIN_VOLTAGE_SWING_400 (0 << 0)
194 # define DP_TRAIN_VOLTAGE_SWING_600 (1 << 0)
195 # define DP_TRAIN_VOLTAGE_SWING_800 (2 << 0)
196 # define DP_TRAIN_VOLTAGE_SWING_1200 (3 << 0)
198 # define DP_TRAIN_PRE_EMPHASIS_MASK (3 << 3)
199 # define DP_TRAIN_PRE_EMPHASIS_0 (0 << 3)
200 # define DP_TRAIN_PRE_EMPHASIS_3_5 (1 << 3)
201 # define DP_TRAIN_PRE_EMPHASIS_6 (2 << 3)
202 # define DP_TRAIN_PRE_EMPHASIS_9_5 (3 << 3)
204 # define DP_TRAIN_PRE_EMPHASIS_SHIFT 3
205 # define DP_TRAIN_MAX_PRE_EMPHASIS_REACHED (1 << 5)
207 #define DP_DOWNSPREAD_CTRL 0x107
208 # define DP_SPREAD_AMP_0_5 (1 << 4)
209 # define DP_MSA_TIMING_PAR_IGNORE_EN (1 << 7) /* eDP */
211 #define DP_MAIN_LINK_CHANNEL_CODING_SET 0x108
212 # define DP_SET_ANSI_8B10B (1 << 0)
214 #define DP_I2C_SPEED_CONTROL_STATUS 0x109 /* DPI */
215 /* bitmask as for DP_I2C_SPEED_CAP */
217 #define DP_EDP_CONFIGURATION_SET 0x10a /* XXX 1.2? */
219 #define DP_MSTM_CTRL 0x111 /* 1.2 */
220 # define DP_MST_EN (1 << 0)
221 # define DP_UP_REQ_EN (1 << 1)
222 # define DP_UPSTREAM_IS_SRC (1 << 2)
224 #define DP_PSR_EN_CFG 0x170 /* XXX 1.2? */
225 # define DP_PSR_ENABLE (1 << 0)
226 # define DP_PSR_MAIN_LINK_ACTIVE (1 << 1)
227 # define DP_PSR_CRC_VERIFICATION (1 << 2)
228 # define DP_PSR_FRAME_CAPTURE (1 << 3)
230 #define DP_ADAPTER_CTRL 0x1a0
231 # define DP_ADAPTER_CTRL_FORCE_LOAD_SENSE (1 << 0)
233 #define DP_BRANCH_DEVICE_CTRL 0x1a1
234 # define DP_BRANCH_DEVICE_IRQ_HPD (1 << 0)
236 #define DP_PAYLOAD_ALLOCATE_SET 0x1c0
237 #define DP_PAYLOAD_ALLOCATE_START_TIME_SLOT 0x1c1
238 #define DP_PAYLOAD_ALLOCATE_TIME_SLOT_COUNT 0x1c2
240 #define DP_SINK_COUNT 0x200
241 /* prior to 1.2 bit 7 was reserved mbz */
242 # define DP_GET_SINK_COUNT(x) ((((x) & 0x80) >> 1) | ((x) & 0x3f))
243 # define DP_SINK_CP_READY (1 << 6)
245 #define DP_DEVICE_SERVICE_IRQ_VECTOR 0x201
246 # define DP_REMOTE_CONTROL_COMMAND_PENDING (1 << 0)
247 # define DP_AUTOMATED_TEST_REQUEST (1 << 1)
248 # define DP_CP_IRQ (1 << 2)
249 # define DP_MCCS_IRQ (1 << 3)
250 # define DP_DOWN_REP_MSG_RDY (1 << 4) /* 1.2 MST */
251 # define DP_UP_REQ_MSG_RDY (1 << 5) /* 1.2 MST */
252 # define DP_SINK_SPECIFIC_IRQ (1 << 6)
254 #define DP_LANE0_1_STATUS 0x202
255 #define DP_LANE2_3_STATUS 0x203
256 # define DP_LANE_CR_DONE (1 << 0)
257 # define DP_LANE_CHANNEL_EQ_DONE (1 << 1)
258 # define DP_LANE_SYMBOL_LOCKED (1 << 2)
260 #define DP_CHANNEL_EQ_BITS (DP_LANE_CR_DONE | \
261 DP_LANE_CHANNEL_EQ_DONE | \
262 DP_LANE_SYMBOL_LOCKED)
264 #define DP_LANE_ALIGN_STATUS_UPDATED 0x204
266 #define DP_INTERLANE_ALIGN_DONE (1 << 0)
267 #define DP_DOWNSTREAM_PORT_STATUS_CHANGED (1 << 6)
268 #define DP_LINK_STATUS_UPDATED (1 << 7)
270 #define DP_SINK_STATUS 0x205
272 #define DP_RECEIVE_PORT_0_STATUS (1 << 0)
273 #define DP_RECEIVE_PORT_1_STATUS (1 << 1)
275 #define DP_ADJUST_REQUEST_LANE0_1 0x206
276 #define DP_ADJUST_REQUEST_LANE2_3 0x207
277 # define DP_ADJUST_VOLTAGE_SWING_LANE0_MASK 0x03
278 # define DP_ADJUST_VOLTAGE_SWING_LANE0_SHIFT 0
279 # define DP_ADJUST_PRE_EMPHASIS_LANE0_MASK 0x0c
280 # define DP_ADJUST_PRE_EMPHASIS_LANE0_SHIFT 2
281 # define DP_ADJUST_VOLTAGE_SWING_LANE1_MASK 0x30
282 # define DP_ADJUST_VOLTAGE_SWING_LANE1_SHIFT 4
283 # define DP_ADJUST_PRE_EMPHASIS_LANE1_MASK 0xc0
284 # define DP_ADJUST_PRE_EMPHASIS_LANE1_SHIFT 6
286 #define DP_TEST_REQUEST 0x218
287 # define DP_TEST_LINK_TRAINING (1 << 0)
288 # define DP_TEST_LINK_VIDEO_PATTERN (1 << 1)
289 # define DP_TEST_LINK_EDID_READ (1 << 2)
290 # define DP_TEST_LINK_PHY_TEST_PATTERN (1 << 3) /* DPCD >= 1.1 */
291 # define DP_TEST_LINK_FAUX_PATTERN (1 << 4) /* DPCD >= 1.2 */
293 #define DP_TEST_LINK_RATE 0x219
294 # define DP_LINK_RATE_162 (0x6)
295 # define DP_LINK_RATE_27 (0xa)
297 #define DP_TEST_LANE_COUNT 0x220
299 #define DP_TEST_PATTERN 0x221
301 #define DP_TEST_CRC_R_CR 0x240
302 #define DP_TEST_CRC_G_Y 0x242
303 #define DP_TEST_CRC_B_CB 0x244
305 #define DP_TEST_SINK_MISC 0x246
306 #define DP_TEST_CRC_SUPPORTED (1 << 5)
308 #define DP_TEST_RESPONSE 0x260
309 # define DP_TEST_ACK (1 << 0)
310 # define DP_TEST_NAK (1 << 1)
311 # define DP_TEST_EDID_CHECKSUM_WRITE (1 << 2)
313 #define DP_TEST_EDID_CHECKSUM 0x261
315 #define DP_TEST_SINK 0x270
316 #define DP_TEST_SINK_START (1 << 0)
318 #define DP_PAYLOAD_TABLE_UPDATE_STATUS 0x2c0 /* 1.2 MST */
319 # define DP_PAYLOAD_TABLE_UPDATED (1 << 0)
320 # define DP_PAYLOAD_ACT_HANDLED (1 << 1)
322 #define DP_VC_PAYLOAD_ID_SLOT_1 0x2c1 /* 1.2 MST */
323 /* up to ID_SLOT_63 at 0x2ff */
325 #define DP_SOURCE_OUI 0x300
326 #define DP_SINK_OUI 0x400
327 #define DP_BRANCH_OUI 0x500
329 #define DP_SET_POWER 0x600
330 # define DP_SET_POWER_D0 0x1
331 # define DP_SET_POWER_D3 0x2
332 # define DP_SET_POWER_MASK 0x3
334 #define DP_SIDEBAND_MSG_DOWN_REQ_BASE 0x1000 /* 1.2 MST */
335 #define DP_SIDEBAND_MSG_UP_REP_BASE 0x1200 /* 1.2 MST */
336 #define DP_SIDEBAND_MSG_DOWN_REP_BASE 0x1400 /* 1.2 MST */
337 #define DP_SIDEBAND_MSG_UP_REQ_BASE 0x1600 /* 1.2 MST */
339 #define DP_SINK_COUNT_ESI 0x2002 /* 1.2 */
341 # define DP_SINK_COUNT_CP_READY (1 << 6)
343 #define DP_DEVICE_SERVICE_IRQ_VECTOR_ESI0 0x2003 /* 1.2 */
345 #define DP_DEVICE_SERVICE_IRQ_VECTOR_ESI1 0x2004 /* 1.2 */
347 #define DP_LINK_SERVICE_IRQ_VECTOR_ESI0 0x2005 /* 1.2 */
349 #define DP_PSR_ERROR_STATUS 0x2006 /* XXX 1.2? */
350 # define DP_PSR_LINK_CRC_ERROR (1 << 0)
351 # define DP_PSR_RFB_STORAGE_ERROR (1 << 1)
353 #define DP_PSR_ESI 0x2007 /* XXX 1.2? */
354 # define DP_PSR_CAPS_CHANGE (1 << 0)
356 #define DP_PSR_STATUS 0x2008 /* XXX 1.2? */
357 # define DP_PSR_SINK_INACTIVE 0
358 # define DP_PSR_SINK_ACTIVE_SRC_SYNCED 1
359 # define DP_PSR_SINK_ACTIVE_RFB 2
360 # define DP_PSR_SINK_ACTIVE_SINK_SYNCED 3
361 # define DP_PSR_SINK_ACTIVE_RESYNC 4
362 # define DP_PSR_SINK_INTERNAL_ERROR 7
363 # define DP_PSR_SINK_STATE_MASK 0x07
365 /* DP 1.2 Sideband message defines */
366 /* peer device type - DP 1.2a Table 2-92 */
367 #define DP_PEER_DEVICE_NONE 0x0
368 #define DP_PEER_DEVICE_SOURCE_OR_SST 0x1
369 #define DP_PEER_DEVICE_MST_BRANCHING 0x2
370 #define DP_PEER_DEVICE_SST_SINK 0x3
371 #define DP_PEER_DEVICE_DP_LEGACY_CONV 0x4
373 /* DP 1.2 MST sideband request names DP 1.2a Table 2-80 */
374 #define DP_LINK_ADDRESS 0x01
375 #define DP_CONNECTION_STATUS_NOTIFY 0x02
376 #define DP_ENUM_PATH_RESOURCES 0x10
377 #define DP_ALLOCATE_PAYLOAD 0x11
378 #define DP_QUERY_PAYLOAD 0x12
379 #define DP_RESOURCE_STATUS_NOTIFY 0x13
380 #define DP_CLEAR_PAYLOAD_ID_TABLE 0x14
381 #define DP_REMOTE_DPCD_READ 0x20
382 #define DP_REMOTE_DPCD_WRITE 0x21
383 #define DP_REMOTE_I2C_READ 0x22
384 #define DP_REMOTE_I2C_WRITE 0x23
385 #define DP_POWER_UP_PHY 0x24
386 #define DP_POWER_DOWN_PHY 0x25
387 #define DP_SINK_EVENT_NOTIFY 0x30
388 #define DP_QUERY_STREAM_ENC_STATUS 0x38
390 /* DP 1.2 MST sideband nak reasons - table 2.84 */
391 #define DP_NAK_WRITE_FAILURE 0x01
392 #define DP_NAK_INVALID_READ 0x02
393 #define DP_NAK_CRC_FAILURE 0x03
394 #define DP_NAK_BAD_PARAM 0x04
395 #define DP_NAK_DEFER 0x05
396 #define DP_NAK_LINK_FAILURE 0x06
397 #define DP_NAK_NO_RESOURCES 0x07
398 #define DP_NAK_DPCD_FAIL 0x08
399 #define DP_NAK_I2C_NAK 0x09
400 #define DP_NAK_ALLOCATE_FAIL 0x0a
402 #define MODE_I2C_START 1
403 #define MODE_I2C_WRITE 2
404 #define MODE_I2C_READ 4
405 #define MODE_I2C_STOP 8
408 * struct i2c_algo_dp_aux_data - driver interface structure for i2c over dp
410 * @running: set by the algo indicating whether an i2c is ongoing or whether
411 * the i2c bus is quiescent
412 * @address: i2c target address for the currently ongoing transfer
413 * @aux_ch: driver callback to transfer a single byte of the i2c payload
415 struct i2c_algo_dp_aux_data
{
418 int (*aux_ch
) (struct device
*adapter
,
419 int mode
, uint8_t write_byte
,
425 int iic_dp_aux_add_bus(device_t dev
, const char *name
,
426 int (*ch
)(device_t idev
, int mode
, uint8_t write_byte
, uint8_t *read_byte
),
427 void *priv
, device_t
*bus
, device_t
*adapter
);
430 #define DP_LINK_STATUS_SIZE 6
431 bool drm_dp_channel_eq_ok(const u8 link_status
[DP_LINK_STATUS_SIZE
],
433 bool drm_dp_clock_recovery_ok(const u8 link_status
[DP_LINK_STATUS_SIZE
],
435 u8
drm_dp_get_adjust_request_voltage(const u8 link_status
[DP_LINK_STATUS_SIZE
],
437 u8
drm_dp_get_adjust_request_pre_emphasis(const u8 link_status
[DP_LINK_STATUS_SIZE
],
440 #define DP_RECEIVER_CAP_SIZE 0xf
441 #define EDP_PSR_RECEIVER_CAP_SIZE 2
443 void drm_dp_link_train_clock_recovery_delay(const u8 dpcd
[DP_RECEIVER_CAP_SIZE
]);
444 void drm_dp_link_train_channel_eq_delay(const u8 dpcd
[DP_RECEIVER_CAP_SIZE
]);
446 u8
drm_dp_link_rate_to_bw_code(int link_rate
);
447 int drm_dp_bw_code_to_link_rate(u8 link_bw
);
449 struct edp_sdp_header
{
450 u8 HB0
; /* Secondary Data Packet ID */
451 u8 HB1
; /* Secondary Data Packet Type */
452 u8 HB2
; /* 7:5 reserved, 4:0 revision number */
453 u8 HB3
; /* 7:5 reserved, 4:0 number of valid data bytes */
456 #define EDP_SDP_HEADER_REVISION_MASK 0x1F
457 #define EDP_SDP_HEADER_VALID_PAYLOAD_BYTES 0x1F
460 struct edp_sdp_header sdp_header
;
461 u8 DB0
; /* Stereo Interface */
462 u8 DB1
; /* 0 - PSR State; 1 - Update RFB; 2 - CRC Valid */
463 u8 DB2
; /* CRC value bits 7:0 of the R or Cr component */
464 u8 DB3
; /* CRC value bits 15:8 of the R or Cr component */
465 u8 DB4
; /* CRC value bits 7:0 of the G or Y component */
466 u8 DB5
; /* CRC value bits 15:8 of the G or Y component */
467 u8 DB6
; /* CRC value bits 7:0 of the B or Cb component */
468 u8 DB7
; /* CRC value bits 15:8 of the B or Cb component */
469 u8 DB8_31
[24]; /* Reserved */
472 #define EDP_VSC_PSR_STATE_ACTIVE (1<<0)
473 #define EDP_VSC_PSR_UPDATE_RFB (1<<1)
474 #define EDP_VSC_PSR_CRC_VALUES_VALID (1<<2)
477 drm_dp_max_link_rate(const u8 dpcd
[DP_RECEIVER_CAP_SIZE
])
479 return drm_dp_bw_code_to_link_rate(dpcd
[DP_MAX_LINK_RATE
]);
483 drm_dp_max_lane_count(const u8 dpcd
[DP_RECEIVER_CAP_SIZE
])
485 return dpcd
[DP_MAX_LANE_COUNT
] & DP_MAX_LANE_COUNT_MASK
;
489 drm_dp_enhanced_frame_cap(const u8 dpcd
[DP_RECEIVER_CAP_SIZE
])
491 return dpcd
[DP_DPCD_REV
] >= 0x11 &&
492 (dpcd
[DP_MAX_LANE_COUNT
] & DP_ENHANCED_FRAME_CAP
);
496 * DisplayPort AUX channel
500 * struct drm_dp_aux_msg - DisplayPort AUX channel transaction
501 * @address: address of the (first) register to access
502 * @request: contains the type of transaction (see DP_AUX_* macros)
503 * @reply: upon completion, contains the reply type of the transaction
504 * @buffer: pointer to a transmission or reception buffer
505 * @size: size of @buffer
507 struct drm_dp_aux_msg
{
508 unsigned int address
;
516 * struct drm_dp_aux - DisplayPort AUX channel
517 * @name: user-visible name of this AUX channel and the I2C-over-AUX adapter
518 * @ddc: I2C adapter that can be used for I2C-over-AUX communication
519 * @dev: pointer to struct device that is the parent for this AUX channel
520 * @hw_mutex: internal mutex used for locking transfers
521 * @transfer: transfers a message representing a single AUX transaction
523 * The .dev field should be set to a pointer to the device that implements
526 * The .name field may be used to specify the name of the I2C adapter. If set to
527 * NULL, dev_name() of .dev will be used.
529 * Drivers provide a hardware-specific implementation of how transactions
530 * are executed via the .transfer() function. A pointer to a drm_dp_aux_msg
531 * structure describing the transaction is passed into this function. Upon
532 * success, the implementation should return the number of payload bytes
533 * that were transferred, or a negative error-code on failure. Helpers
534 * propagate errors from the .transfer() function, with the exception of
535 * the -EBUSY error, which causes a transaction to be retried. On a short,
536 * helpers will return -EPROTO to make it simpler to check for failure.
538 * An AUX channel can also be used to transport I2C messages to a sink. A
539 * typical application of that is to access an EDID that's present in the
540 * sink device. The .transfer() function can also be used to execute such
541 * transactions. The drm_dp_aux_register_i2c_bus() function registers an
542 * I2C adapter that can be passed to drm_probe_ddc(). Upon removal, drivers
543 * should call drm_dp_aux_unregister_i2c_bus() to remove the I2C adapter.
545 * Note that the aux helper code assumes that the .transfer() function
546 * only modifies the reply field of the drm_dp_aux_msg structure. The
547 * retry logic and i2c helpers assume this is the case.
553 struct lock hw_mutex
;
554 ssize_t (*transfer
)(struct drm_dp_aux
*aux
,
555 struct drm_dp_aux_msg
*msg
);
558 ssize_t
drm_dp_dpcd_read(struct drm_dp_aux
*aux
, unsigned int offset
,
559 void *buffer
, size_t size
);
560 ssize_t
drm_dp_dpcd_write(struct drm_dp_aux
*aux
, unsigned int offset
,
561 void *buffer
, size_t size
);
564 * drm_dp_dpcd_readb() - read a single byte from the DPCD
565 * @aux: DisplayPort AUX channel
566 * @offset: address of the register to read
567 * @valuep: location where the value of the register will be stored
569 * Returns the number of bytes transferred (1) on success, or a negative
570 * error code on failure.
572 static inline ssize_t
drm_dp_dpcd_readb(struct drm_dp_aux
*aux
,
573 unsigned int offset
, u8
*valuep
)
575 return drm_dp_dpcd_read(aux
, offset
, valuep
, 1);
579 * drm_dp_dpcd_writeb() - write a single byte to the DPCD
580 * @aux: DisplayPort AUX channel
581 * @offset: address of the register to write
582 * @value: value to write to the register
584 * Returns the number of bytes transferred (1) on success, or a negative
585 * error code on failure.
587 static inline ssize_t
drm_dp_dpcd_writeb(struct drm_dp_aux
*aux
,
588 unsigned int offset
, u8 value
)
590 return drm_dp_dpcd_write(aux
, offset
, &value
, 1);
593 int drm_dp_dpcd_read_link_status(struct drm_dp_aux
*aux
,
594 u8 status
[DP_LINK_STATUS_SIZE
]);
599 #define DP_LINK_CAP_ENHANCED_FRAMING (1 << 0)
602 unsigned char revision
;
604 unsigned int num_lanes
;
605 unsigned long capabilities
;
608 int drm_dp_link_probe(struct drm_dp_aux
*aux
, struct drm_dp_link
*link
);
609 int drm_dp_link_power_up(struct drm_dp_aux
*aux
, struct drm_dp_link
*link
);
610 int drm_dp_link_configure(struct drm_dp_aux
*aux
, struct drm_dp_link
*link
);
612 int drm_dp_aux_register(struct drm_dp_aux
*aux
);
613 void drm_dp_aux_unregister(struct drm_dp_aux
*aux
);
615 #endif /* _DRM_DP_HELPER_H_ */