2 * Copyright © 2008,2010 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
24 * Eric Anholt <eric@anholt.net>
25 * Chris Wilson <chris@chris-wilson.co.uk>
30 #include <drm/i915_drm.h>
32 #include "i915_trace.h"
33 #include "intel_drv.h"
34 #include <linux/pagemap.h>
36 #define __EXEC_OBJECT_HAS_PIN (1<<31)
37 #define __EXEC_OBJECT_HAS_FENCE (1<<30)
38 #define __EXEC_OBJECT_NEEDS_BIAS (1<<28)
40 #define BATCH_OFFSET_BIAS (256*1024)
43 struct list_head vmas
;
46 struct i915_vma
*lut
[0];
47 struct hlist_head buckets
[0];
51 static struct eb_vmas
*
52 eb_create(struct drm_i915_gem_execbuffer2
*args
)
54 struct eb_vmas
*eb
= NULL
;
56 if (args
->flags
& I915_EXEC_HANDLE_LUT
) {
57 unsigned size
= args
->buffer_count
;
58 size
*= sizeof(struct i915_vma
*);
59 size
+= sizeof(struct eb_vmas
);
60 eb
= kmalloc(size
, M_DRM
, M_NOWAIT
);
64 unsigned size
= args
->buffer_count
;
65 unsigned count
= PAGE_SIZE
/ sizeof(struct hlist_head
) / 2;
66 BUILD_BUG_ON_NOT_POWER_OF_2(PAGE_SIZE
/ sizeof(struct hlist_head
));
67 while (count
> 2*size
)
69 eb
= kzalloc(count
*sizeof(struct hlist_head
) +
70 sizeof(struct eb_vmas
),
77 eb
->and = -args
->buffer_count
;
79 INIT_LIST_HEAD(&eb
->vmas
);
84 eb_reset(struct eb_vmas
*eb
)
87 memset(eb
->buckets
, 0, (eb
->and+1)*sizeof(struct hlist_head
));
91 eb_lookup_vmas(struct eb_vmas
*eb
,
92 struct drm_i915_gem_exec_object2
*exec
,
93 const struct drm_i915_gem_execbuffer2
*args
,
94 struct i915_address_space
*vm
,
95 struct drm_file
*file
)
97 struct drm_i915_private
*dev_priv
= vm
->dev
->dev_private
;
98 struct drm_i915_gem_object
*obj
;
99 struct list_head objects
;
102 INIT_LIST_HEAD(&objects
);
103 lockmgr(&file
->table_lock
, LK_EXCLUSIVE
);
104 /* Grab a reference to the object and release the lock so we can lookup
105 * or create the VMA without using GFP_ATOMIC */
106 for (i
= 0; i
< args
->buffer_count
; i
++) {
107 obj
= to_intel_bo(idr_find(&file
->object_idr
, exec
[i
].handle
));
109 lockmgr(&file
->table_lock
, LK_RELEASE
);
110 DRM_DEBUG("Invalid object handle %d at index %d\n",
116 if (!list_empty(&obj
->obj_exec_link
)) {
117 lockmgr(&file
->table_lock
, LK_RELEASE
);
118 DRM_DEBUG("Object %p [handle %d, index %d] appears more than once in object list\n",
119 obj
, exec
[i
].handle
, i
);
124 drm_gem_object_reference(&obj
->base
);
125 list_add_tail(&obj
->obj_exec_link
, &objects
);
127 lockmgr(&file
->table_lock
, LK_RELEASE
);
130 while (!list_empty(&objects
)) {
131 struct i915_vma
*vma
;
132 struct i915_address_space
*bind_vm
= vm
;
134 if (exec
[i
].flags
& EXEC_OBJECT_NEEDS_GTT
&&
135 USES_FULL_PPGTT(vm
->dev
)) {
140 /* If we have secure dispatch, or the userspace assures us that
141 * they know what they're doing, use the GGTT VM.
143 if (((args
->flags
& I915_EXEC_SECURE
) &&
144 (i
== (args
->buffer_count
- 1))))
145 bind_vm
= &dev_priv
->gtt
.base
;
147 obj
= list_first_entry(&objects
,
148 struct drm_i915_gem_object
,
152 * NOTE: We can leak any vmas created here when something fails
153 * later on. But that's no issue since vma_unbind can deal with
154 * vmas which are not actually bound. And since only
155 * lookup_or_create exists as an interface to get at the vma
156 * from the (obj, vm) we don't run the risk of creating
157 * duplicated vmas for the same vm.
159 vma
= i915_gem_obj_lookup_or_create_vma(obj
, bind_vm
);
161 DRM_DEBUG("Failed to lookup VMA\n");
166 /* Transfer ownership from the objects list to the vmas list. */
167 list_add_tail(&vma
->exec_list
, &eb
->vmas
);
168 list_del_init(&obj
->obj_exec_link
);
170 vma
->exec_entry
= &exec
[i
];
174 uint32_t handle
= args
->flags
& I915_EXEC_HANDLE_LUT
? i
: exec
[i
].handle
;
175 vma
->exec_handle
= handle
;
176 hlist_add_head(&vma
->exec_node
,
177 &eb
->buckets
[handle
& eb
->and]);
186 while (!list_empty(&objects
)) {
187 obj
= list_first_entry(&objects
,
188 struct drm_i915_gem_object
,
190 list_del_init(&obj
->obj_exec_link
);
191 drm_gem_object_unreference(&obj
->base
);
194 * Objects already transfered to the vmas list will be unreferenced by
201 static struct i915_vma
*eb_get_vma(struct eb_vmas
*eb
, unsigned long handle
)
204 if (handle
>= -eb
->and)
206 return eb
->lut
[handle
];
208 struct hlist_head
*head
;
209 struct hlist_node
*node
;
211 head
= &eb
->buckets
[handle
& eb
->and];
212 hlist_for_each(node
, head
) {
213 struct i915_vma
*vma
;
215 vma
= hlist_entry(node
, struct i915_vma
, exec_node
);
216 if (vma
->exec_handle
== handle
)
224 i915_gem_execbuffer_unreserve_vma(struct i915_vma
*vma
)
226 struct drm_i915_gem_exec_object2
*entry
;
227 struct drm_i915_gem_object
*obj
= vma
->obj
;
229 if (!drm_mm_node_allocated(&vma
->node
))
232 entry
= vma
->exec_entry
;
234 if (entry
->flags
& __EXEC_OBJECT_HAS_FENCE
)
235 i915_gem_object_unpin_fence(obj
);
237 if (entry
->flags
& __EXEC_OBJECT_HAS_PIN
)
240 entry
->flags
&= ~(__EXEC_OBJECT_HAS_FENCE
| __EXEC_OBJECT_HAS_PIN
);
243 static void eb_destroy(struct eb_vmas
*eb
)
245 while (!list_empty(&eb
->vmas
)) {
246 struct i915_vma
*vma
;
248 vma
= list_first_entry(&eb
->vmas
,
251 list_del_init(&vma
->exec_list
);
252 i915_gem_execbuffer_unreserve_vma(vma
);
253 drm_gem_object_unreference(&vma
->obj
->base
);
258 static inline int use_cpu_reloc(struct drm_i915_gem_object
*obj
)
260 return (HAS_LLC(obj
->base
.dev
) ||
261 obj
->base
.write_domain
== I915_GEM_DOMAIN_CPU
||
262 !obj
->map_and_fenceable
||
263 obj
->cache_level
!= I915_CACHE_NONE
);
267 relocate_entry_cpu(struct drm_i915_gem_object
*obj
,
268 struct drm_i915_gem_relocation_entry
*reloc
,
269 uint64_t target_offset
)
271 struct drm_device
*dev
= obj
->base
.dev
;
272 uint32_t page_offset
= offset_in_page(reloc
->offset
);
273 uint64_t delta
= reloc
->delta
+ target_offset
;
277 ret
= i915_gem_object_set_to_cpu_domain(obj
, true);
281 vaddr
= kmap_atomic(i915_gem_object_get_page(obj
,
282 reloc
->offset
>> PAGE_SHIFT
));
283 *(uint32_t *)(vaddr
+ page_offset
) = lower_32_bits(delta
);
285 if (INTEL_INFO(dev
)->gen
>= 8) {
286 page_offset
= offset_in_page(page_offset
+ sizeof(uint32_t));
288 if (page_offset
== 0) {
289 kunmap_atomic(vaddr
);
290 vaddr
= kmap_atomic(i915_gem_object_get_page(obj
,
291 (reloc
->offset
+ sizeof(uint32_t)) >> PAGE_SHIFT
));
294 *(uint32_t *)(vaddr
+ page_offset
) = upper_32_bits(delta
);
297 kunmap_atomic(vaddr
);
303 relocate_entry_gtt(struct drm_i915_gem_object
*obj
,
304 struct drm_i915_gem_relocation_entry
*reloc
,
305 uint64_t target_offset
)
307 struct drm_device
*dev
= obj
->base
.dev
;
308 uint64_t delta
= reloc
->delta
+ target_offset
;
309 uint32_t __iomem
*reloc_entry
;
310 void __iomem
*reloc_page
;
313 ret
= i915_gem_object_set_to_gtt_domain(obj
, true);
317 ret
= i915_gem_object_put_fence(obj
);
321 /* Map the page containing the relocation we're going to perform. */
322 reloc
->offset
+= i915_gem_obj_ggtt_offset(obj
);
323 reloc_page
= pmap_mapdev_attr(dev
->agp
->base
+ (reloc
->offset
&
324 ~PAGE_MASK
), PAGE_SIZE
, PAT_WRITE_COMBINING
);
325 reloc_entry
= (uint32_t __iomem
*)
326 ((char *)reloc_page
+ offset_in_page(reloc
->offset
));
327 iowrite32(lower_32_bits(delta
), reloc_entry
);
329 if (INTEL_INFO(dev
)->gen
>= 8) {
332 if (offset_in_page(reloc
->offset
+ sizeof(uint32_t)) == 0) {
333 pmap_unmapdev((vm_offset_t
)reloc_page
, PAGE_SIZE
);
334 reloc_page
= pmap_mapdev_attr(
336 reloc
->offset
+ sizeof(uint32_t),
337 PAGE_SIZE
, PAT_WRITE_COMBINING
);
338 reloc_entry
= reloc_page
;
341 iowrite32(upper_32_bits(delta
), reloc_entry
);
344 pmap_unmapdev((vm_offset_t
)reloc_page
, PAGE_SIZE
);
350 i915_gem_execbuffer_relocate_entry(struct drm_i915_gem_object
*obj
,
352 struct drm_i915_gem_relocation_entry
*reloc
)
354 struct drm_device
*dev
= obj
->base
.dev
;
355 struct drm_gem_object
*target_obj
;
356 struct drm_i915_gem_object
*target_i915_obj
;
357 struct i915_vma
*target_vma
;
358 uint64_t target_offset
;
361 /* we've already hold a reference to all valid objects */
362 target_vma
= eb_get_vma(eb
, reloc
->target_handle
);
363 if (unlikely(target_vma
== NULL
))
365 target_i915_obj
= target_vma
->obj
;
366 target_obj
= &target_vma
->obj
->base
;
368 target_offset
= target_vma
->node
.start
;
370 /* Sandybridge PPGTT errata: We need a global gtt mapping for MI and
371 * pipe_control writes because the gpu doesn't properly redirect them
372 * through the ppgtt for non_secure batchbuffers. */
373 if (unlikely(IS_GEN6(dev
) &&
374 reloc
->write_domain
== I915_GEM_DOMAIN_INSTRUCTION
&&
375 !target_i915_obj
->has_global_gtt_mapping
)) {
376 struct i915_vma
*vma
=
377 list_first_entry(&target_i915_obj
->vma_list
,
378 typeof(*vma
), vma_link
);
379 vma
->bind_vma(vma
, target_i915_obj
->cache_level
, GLOBAL_BIND
);
382 /* Validate that the target is in a valid r/w GPU domain */
383 if (unlikely(reloc
->write_domain
& (reloc
->write_domain
- 1))) {
384 DRM_DEBUG("reloc with multiple write domains: "
385 "obj %p target %d offset %d "
386 "read %08x write %08x",
387 obj
, reloc
->target_handle
,
390 reloc
->write_domain
);
393 if (unlikely((reloc
->write_domain
| reloc
->read_domains
)
394 & ~I915_GEM_GPU_DOMAINS
)) {
395 DRM_DEBUG("reloc with read/write non-GPU domains: "
396 "obj %p target %d offset %d "
397 "read %08x write %08x",
398 obj
, reloc
->target_handle
,
401 reloc
->write_domain
);
405 target_obj
->pending_read_domains
|= reloc
->read_domains
;
406 target_obj
->pending_write_domain
|= reloc
->write_domain
;
408 /* If the relocation already has the right value in it, no
409 * more work needs to be done.
411 if (target_offset
== reloc
->presumed_offset
)
414 /* Check that the relocation address is valid... */
415 if (unlikely(reloc
->offset
>
416 obj
->base
.size
- (INTEL_INFO(dev
)->gen
>= 8 ? 8 : 4))) {
417 DRM_DEBUG("Relocation beyond object bounds: "
418 "obj %p target %d offset %d size %d.\n",
419 obj
, reloc
->target_handle
,
421 (int) obj
->base
.size
);
424 if (unlikely(reloc
->offset
& 3)) {
425 DRM_DEBUG("Relocation not 4-byte aligned: "
426 "obj %p target %d offset %d.\n",
427 obj
, reloc
->target_handle
,
428 (int) reloc
->offset
);
432 /* We can't wait for rendering with pagefaults disabled */
433 if (obj
->active
&& (curthread
->td_flags
& TDF_NOFAULT
))
436 if (use_cpu_reloc(obj
))
437 ret
= relocate_entry_cpu(obj
, reloc
, target_offset
);
439 ret
= relocate_entry_gtt(obj
, reloc
, target_offset
);
444 /* and update the user's relocation entry */
445 reloc
->presumed_offset
= target_offset
;
451 i915_gem_execbuffer_relocate_vma(struct i915_vma
*vma
,
454 #define N_RELOC(x) ((x) / sizeof(struct drm_i915_gem_relocation_entry))
455 struct drm_i915_gem_relocation_entry stack_reloc
[N_RELOC(512)];
456 struct drm_i915_gem_relocation_entry __user
*user_relocs
;
457 struct drm_i915_gem_exec_object2
*entry
= vma
->exec_entry
;
460 user_relocs
= to_user_ptr(entry
->relocs_ptr
);
462 remain
= entry
->relocation_count
;
464 struct drm_i915_gem_relocation_entry
*r
= stack_reloc
;
466 if (count
> ARRAY_SIZE(stack_reloc
))
467 count
= ARRAY_SIZE(stack_reloc
);
470 if (__copy_from_user_inatomic(r
, user_relocs
, count
*sizeof(r
[0])))
474 u64 offset
= r
->presumed_offset
;
476 ret
= i915_gem_execbuffer_relocate_entry(vma
->obj
, eb
, r
);
480 if (r
->presumed_offset
!= offset
&&
481 __copy_to_user_inatomic(&user_relocs
->presumed_offset
,
483 sizeof(r
->presumed_offset
))) {
497 i915_gem_execbuffer_relocate_vma_slow(struct i915_vma
*vma
,
499 struct drm_i915_gem_relocation_entry
*relocs
)
501 const struct drm_i915_gem_exec_object2
*entry
= vma
->exec_entry
;
504 for (i
= 0; i
< entry
->relocation_count
; i
++) {
505 ret
= i915_gem_execbuffer_relocate_entry(vma
->obj
, eb
, &relocs
[i
]);
514 i915_gem_execbuffer_relocate(struct eb_vmas
*eb
)
516 struct i915_vma
*vma
;
519 /* This is the fast path and we cannot handle a pagefault whilst
520 * holding the struct mutex lest the user pass in the relocations
521 * contained within a mmaped bo. For in such a case we, the page
522 * fault handler would call i915_gem_fault() and we would try to
523 * acquire the struct mutex again. Obviously this is bad and so
524 * lockdep complains vehemently.
527 list_for_each_entry(vma
, &eb
->vmas
, exec_list
) {
528 ret
= i915_gem_execbuffer_relocate_vma(vma
, eb
);
538 need_reloc_mappable(struct i915_vma
*vma
)
540 struct drm_i915_gem_exec_object2
*entry
= vma
->exec_entry
;
541 return entry
->relocation_count
&& !use_cpu_reloc(vma
->obj
) &&
542 i915_is_ggtt(vma
->vm
);
546 i915_gem_execbuffer_reserve_vma(struct i915_vma
*vma
,
547 struct intel_engine_cs
*ring
,
550 struct drm_i915_gem_object
*obj
= vma
->obj
;
551 struct drm_i915_gem_exec_object2
*entry
= vma
->exec_entry
;
552 bool has_fenced_gpu_access
= INTEL_INFO(ring
->dev
)->gen
< 4;
560 has_fenced_gpu_access
&&
561 entry
->flags
& EXEC_OBJECT_NEEDS_FENCE
&&
562 obj
->tiling_mode
!= I915_TILING_NONE
;
563 if (need_fence
|| need_reloc_mappable(vma
))
564 flags
|= PIN_MAPPABLE
;
566 if (entry
->flags
& EXEC_OBJECT_NEEDS_GTT
)
568 if (entry
->flags
& __EXEC_OBJECT_NEEDS_BIAS
)
569 flags
|= BATCH_OFFSET_BIAS
| PIN_OFFSET_BIAS
;
571 ret
= i915_gem_object_pin(obj
, vma
->vm
, entry
->alignment
, flags
);
575 entry
->flags
|= __EXEC_OBJECT_HAS_PIN
;
577 if (has_fenced_gpu_access
) {
578 if (entry
->flags
& EXEC_OBJECT_NEEDS_FENCE
) {
579 ret
= i915_gem_object_get_fence(obj
);
583 if (i915_gem_object_pin_fence(obj
))
584 entry
->flags
|= __EXEC_OBJECT_HAS_FENCE
;
586 obj
->pending_fenced_gpu_access
= true;
590 if (entry
->offset
!= vma
->node
.start
) {
591 entry
->offset
= vma
->node
.start
;
595 if (entry
->flags
& EXEC_OBJECT_WRITE
) {
596 obj
->base
.pending_read_domains
= I915_GEM_DOMAIN_RENDER
;
597 obj
->base
.pending_write_domain
= I915_GEM_DOMAIN_RENDER
;
604 eb_vma_misplaced(struct i915_vma
*vma
, bool has_fenced_gpu_access
)
606 struct drm_i915_gem_exec_object2
*entry
= vma
->exec_entry
;
607 struct drm_i915_gem_object
*obj
= vma
->obj
;
608 bool need_fence
, need_mappable
;
611 has_fenced_gpu_access
&&
612 entry
->flags
& EXEC_OBJECT_NEEDS_FENCE
&&
613 obj
->tiling_mode
!= I915_TILING_NONE
;
614 need_mappable
= need_fence
|| need_reloc_mappable(vma
);
616 WARN_ON((need_mappable
|| need_fence
) &&
617 !i915_is_ggtt(vma
->vm
));
619 if (entry
->alignment
&&
620 vma
->node
.start
& (entry
->alignment
- 1))
623 if (need_mappable
&& !obj
->map_and_fenceable
)
626 if (entry
->flags
& __EXEC_OBJECT_NEEDS_BIAS
&&
627 vma
->node
.start
< BATCH_OFFSET_BIAS
)
634 i915_gem_execbuffer_reserve(struct intel_engine_cs
*ring
,
635 struct list_head
*vmas
,
638 struct drm_i915_gem_object
*obj
;
639 struct i915_vma
*vma
;
640 struct i915_address_space
*vm
;
641 struct list_head ordered_vmas
;
642 bool has_fenced_gpu_access
= INTEL_INFO(ring
->dev
)->gen
< 4;
645 if (list_empty(vmas
))
648 i915_gem_retire_requests_ring(ring
);
650 vm
= list_first_entry(vmas
, struct i915_vma
, exec_list
)->vm
;
652 INIT_LIST_HEAD(&ordered_vmas
);
653 while (!list_empty(vmas
)) {
654 struct drm_i915_gem_exec_object2
*entry
;
655 bool need_fence
, need_mappable
;
657 vma
= list_first_entry(vmas
, struct i915_vma
, exec_list
);
659 entry
= vma
->exec_entry
;
662 has_fenced_gpu_access
&&
663 entry
->flags
& EXEC_OBJECT_NEEDS_FENCE
&&
664 obj
->tiling_mode
!= I915_TILING_NONE
;
665 need_mappable
= need_fence
|| need_reloc_mappable(vma
);
668 list_move(&vma
->exec_list
, &ordered_vmas
);
670 list_move_tail(&vma
->exec_list
, &ordered_vmas
);
672 obj
->base
.pending_read_domains
= I915_GEM_GPU_DOMAINS
& ~I915_GEM_DOMAIN_COMMAND
;
673 obj
->base
.pending_write_domain
= 0;
674 obj
->pending_fenced_gpu_access
= false;
676 list_splice(&ordered_vmas
, vmas
);
678 /* Attempt to pin all of the buffers into the GTT.
679 * This is done in 3 phases:
681 * 1a. Unbind all objects that do not match the GTT constraints for
682 * the execbuffer (fenceable, mappable, alignment etc).
683 * 1b. Increment pin count for already bound objects.
684 * 2. Bind new objects.
685 * 3. Decrement pin count.
687 * This avoid unnecessary unbinding of later objects in order to make
688 * room for the earlier objects *unless* we need to defragment.
694 /* Unbind any ill-fitting objects or pin. */
695 list_for_each_entry(vma
, vmas
, exec_list
) {
696 if (!drm_mm_node_allocated(&vma
->node
))
699 if (eb_vma_misplaced(vma
, has_fenced_gpu_access
))
700 ret
= i915_vma_unbind(vma
);
702 ret
= i915_gem_execbuffer_reserve_vma(vma
, ring
, need_relocs
);
707 /* Bind fresh objects */
708 list_for_each_entry(vma
, vmas
, exec_list
) {
709 if (drm_mm_node_allocated(&vma
->node
))
712 ret
= i915_gem_execbuffer_reserve_vma(vma
, ring
, need_relocs
);
718 if (ret
!= -ENOSPC
|| retry
++)
721 /* Decrement pin count for bound objects */
722 list_for_each_entry(vma
, vmas
, exec_list
)
723 i915_gem_execbuffer_unreserve_vma(vma
);
725 ret
= i915_gem_evict_vm(vm
, true);
732 i915_gem_execbuffer_relocate_slow(struct drm_device
*dev
,
733 struct drm_i915_gem_execbuffer2
*args
,
734 struct drm_file
*file
,
735 struct intel_engine_cs
*ring
,
737 struct drm_i915_gem_exec_object2
*exec
)
739 struct drm_i915_gem_relocation_entry
*reloc
;
740 struct i915_address_space
*vm
;
741 struct i915_vma
*vma
;
745 unsigned count
= args
->buffer_count
;
747 if (WARN_ON(list_empty(&eb
->vmas
)))
750 vm
= list_first_entry(&eb
->vmas
, struct i915_vma
, exec_list
)->vm
;
752 /* We may process another execbuffer during the unlock... */
753 while (!list_empty(&eb
->vmas
)) {
754 vma
= list_first_entry(&eb
->vmas
, struct i915_vma
, exec_list
);
755 list_del_init(&vma
->exec_list
);
756 i915_gem_execbuffer_unreserve_vma(vma
);
757 drm_gem_object_unreference(&vma
->obj
->base
);
760 mutex_unlock(&dev
->struct_mutex
);
763 for (i
= 0; i
< count
; i
++)
764 total
+= exec
[i
].relocation_count
;
766 reloc_offset
= drm_malloc_ab(count
, sizeof(*reloc_offset
));
767 reloc
= drm_malloc_ab(total
, sizeof(*reloc
));
768 if (reloc
== NULL
|| reloc_offset
== NULL
) {
769 drm_free_large(reloc
);
770 drm_free_large(reloc_offset
);
771 mutex_lock(&dev
->struct_mutex
);
776 for (i
= 0; i
< count
; i
++) {
777 struct drm_i915_gem_relocation_entry __user
*user_relocs
;
778 u64 invalid_offset
= (u64
)-1;
781 user_relocs
= to_user_ptr(exec
[i
].relocs_ptr
);
783 if (copy_from_user(reloc
+total
, user_relocs
,
784 exec
[i
].relocation_count
* sizeof(*reloc
))) {
786 mutex_lock(&dev
->struct_mutex
);
790 /* As we do not update the known relocation offsets after
791 * relocating (due to the complexities in lock handling),
792 * we need to mark them as invalid now so that we force the
793 * relocation processing next time. Just in case the target
794 * object is evicted and then rebound into its old
795 * presumed_offset before the next execbuffer - if that
796 * happened we would make the mistake of assuming that the
797 * relocations were valid.
799 for (j
= 0; j
< exec
[i
].relocation_count
; j
++) {
800 if (__copy_to_user(&user_relocs
[j
].presumed_offset
,
802 sizeof(invalid_offset
))) {
804 mutex_lock(&dev
->struct_mutex
);
809 reloc_offset
[i
] = total
;
810 total
+= exec
[i
].relocation_count
;
813 ret
= i915_mutex_lock_interruptible(dev
);
815 mutex_lock(&dev
->struct_mutex
);
819 /* reacquire the objects */
821 ret
= eb_lookup_vmas(eb
, exec
, args
, vm
, file
);
825 need_relocs
= (args
->flags
& I915_EXEC_NO_RELOC
) == 0;
826 ret
= i915_gem_execbuffer_reserve(ring
, &eb
->vmas
, &need_relocs
);
830 list_for_each_entry(vma
, &eb
->vmas
, exec_list
) {
831 int offset
= vma
->exec_entry
- exec
;
832 ret
= i915_gem_execbuffer_relocate_vma_slow(vma
, eb
,
833 reloc
+ reloc_offset
[offset
]);
838 /* Leave the user relocations as are, this is the painfully slow path,
839 * and we want to avoid the complication of dropping the lock whilst
840 * having buffers reserved in the aperture and so causing spurious
841 * ENOSPC for random operations.
845 drm_free_large(reloc
);
846 drm_free_large(reloc_offset
);
851 i915_gem_execbuffer_move_to_gpu(struct intel_engine_cs
*ring
,
852 struct list_head
*vmas
)
854 struct i915_vma
*vma
;
855 uint32_t flush_domains
= 0;
856 bool flush_chipset
= false;
859 list_for_each_entry(vma
, vmas
, exec_list
) {
860 struct drm_i915_gem_object
*obj
= vma
->obj
;
861 ret
= i915_gem_object_sync(obj
, ring
);
865 if (obj
->base
.write_domain
& I915_GEM_DOMAIN_CPU
)
866 flush_chipset
|= i915_gem_clflush_object(obj
, false);
868 flush_domains
|= obj
->base
.write_domain
;
872 i915_gem_chipset_flush(ring
->dev
);
874 if (flush_domains
& I915_GEM_DOMAIN_GTT
)
877 /* Unconditionally invalidate gpu caches and ensure that we do flush
878 * any residual writes from the previous batch.
880 return intel_ring_invalidate_all_caches(ring
);
884 i915_gem_check_execbuffer(struct drm_i915_gem_execbuffer2
*exec
)
886 if (exec
->flags
& __I915_EXEC_UNKNOWN_FLAGS
)
889 return ((exec
->batch_start_offset
| exec
->batch_len
) & 0x7) == 0;
893 validate_exec_list(struct drm_i915_gem_exec_object2
*exec
,
897 unsigned relocs_total
= 0;
898 unsigned relocs_max
= UINT_MAX
/ sizeof(struct drm_i915_gem_relocation_entry
);
900 for (i
= 0; i
< count
; i
++) {
901 char __user
*ptr
= to_user_ptr(exec
[i
].relocs_ptr
);
902 int length
; /* limited by fault_in_pages_readable() */
904 if (exec
[i
].flags
& __EXEC_OBJECT_UNKNOWN_FLAGS
)
907 /* First check for malicious input causing overflow in
908 * the worst case where we need to allocate the entire
909 * relocation tree as a single array.
911 if (exec
[i
].relocation_count
> relocs_max
- relocs_total
)
913 relocs_total
+= exec
[i
].relocation_count
;
915 length
= exec
[i
].relocation_count
*
916 sizeof(struct drm_i915_gem_relocation_entry
);
918 * We must check that the entire relocation array is safe
919 * to read, but since we may need to update the presumed
920 * offsets during execution, check for full write access.
923 if (!access_ok(VERIFY_WRITE
, ptr
, length
))
927 if (likely(!i915
.prefault_disable
)) {
928 if (fault_in_multipages_readable(ptr
, length
))
936 static struct intel_context
*
937 i915_gem_validate_context(struct drm_device
*dev
, struct drm_file
*file
,
938 struct intel_engine_cs
*ring
, const u32 ctx_id
)
940 struct intel_context
*ctx
= NULL
;
941 struct i915_ctx_hang_stats
*hs
;
943 if (ring
->id
!= RCS
&& ctx_id
!= DEFAULT_CONTEXT_ID
)
944 return ERR_PTR(-EINVAL
);
946 ctx
= i915_gem_context_get(file
->driver_priv
, ctx_id
);
950 hs
= &ctx
->hang_stats
;
952 DRM_DEBUG("Context %u tried to submit while banned\n", ctx_id
);
953 return ERR_PTR(-EIO
);
960 i915_gem_execbuffer_move_to_active(struct list_head
*vmas
,
961 struct intel_engine_cs
*ring
)
963 struct i915_vma
*vma
;
965 list_for_each_entry(vma
, vmas
, exec_list
) {
966 struct drm_i915_gem_object
*obj
= vma
->obj
;
967 u32 old_read
= obj
->base
.read_domains
;
968 u32 old_write
= obj
->base
.write_domain
;
970 obj
->base
.write_domain
= obj
->base
.pending_write_domain
;
971 if (obj
->base
.write_domain
== 0)
972 obj
->base
.pending_read_domains
|= obj
->base
.read_domains
;
973 obj
->base
.read_domains
= obj
->base
.pending_read_domains
;
974 obj
->fenced_gpu_access
= obj
->pending_fenced_gpu_access
;
976 i915_vma_move_to_active(vma
, ring
);
977 if (obj
->base
.write_domain
) {
979 obj
->last_write_seqno
= intel_ring_get_seqno(ring
);
980 /* check for potential scanout */
981 if (i915_gem_obj_ggtt_bound(obj
) &&
982 i915_gem_obj_to_ggtt(obj
)->pin_count
)
983 intel_mark_fb_busy(obj
, ring
);
985 /* update for the implicit flush after a batch */
986 obj
->base
.write_domain
&= ~I915_GEM_GPU_DOMAINS
;
989 trace_i915_gem_object_change_domain(obj
, old_read
, old_write
);
994 i915_gem_execbuffer_retire_commands(struct drm_device
*dev
,
995 struct drm_file
*file
,
996 struct intel_engine_cs
*ring
,
997 struct drm_i915_gem_object
*obj
)
999 /* Unconditionally force add_request to emit a full flush. */
1000 ring
->gpu_caches_dirty
= true;
1002 /* Add a breadcrumb for the completion of the batch buffer */
1003 (void)__i915_add_request(ring
, file
, obj
, NULL
);
1007 i915_reset_gen7_sol_offsets(struct drm_device
*dev
,
1008 struct intel_engine_cs
*ring
)
1010 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1013 if (!IS_GEN7(dev
) || ring
!= &dev_priv
->ring
[RCS
]) {
1014 DRM_DEBUG("sol reset is gen7/rcs only\n");
1018 ret
= intel_ring_begin(ring
, 4 * 3);
1022 for (i
= 0; i
< 4; i
++) {
1023 intel_ring_emit(ring
, MI_LOAD_REGISTER_IMM(1));
1024 intel_ring_emit(ring
, GEN7_SO_WRITE_OFFSET(i
));
1025 intel_ring_emit(ring
, 0);
1028 intel_ring_advance(ring
);
1034 * Find one BSD ring to dispatch the corresponding BSD command.
1035 * The Ring ID is returned.
1037 static int gen8_dispatch_bsd_ring(struct drm_device
*dev
,
1038 struct drm_file
*file
)
1040 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1041 struct drm_i915_file_private
*file_priv
= file
->driver_priv
;
1043 /* Check whether the file_priv is using one ring */
1044 if (file_priv
->bsd_ring
)
1045 return file_priv
->bsd_ring
->id
;
1047 /* If no, use the ping-pong mechanism to select one ring */
1050 mutex_lock(&dev
->struct_mutex
);
1051 if (dev_priv
->mm
.bsd_ring_dispatch_index
== 0) {
1053 dev_priv
->mm
.bsd_ring_dispatch_index
= 1;
1056 dev_priv
->mm
.bsd_ring_dispatch_index
= 0;
1058 file_priv
->bsd_ring
= &dev_priv
->ring
[ring_id
];
1059 mutex_unlock(&dev
->struct_mutex
);
1064 static struct drm_i915_gem_object
*
1065 eb_get_batch(struct eb_vmas
*eb
)
1067 struct i915_vma
*vma
= list_entry(eb
->vmas
.prev
, typeof(*vma
), exec_list
);
1070 * SNA is doing fancy tricks with compressing batch buffers, which leads
1071 * to negative relocation deltas. Usually that works out ok since the
1072 * relocate address is still positive, except when the batch is placed
1073 * very low in the GTT. Ensure this doesn't happen.
1075 * Note that actual hangs have only been observed on gen7, but for
1076 * paranoia do it everywhere.
1078 vma
->exec_entry
->flags
|= __EXEC_OBJECT_NEEDS_BIAS
;
1084 i915_gem_do_execbuffer(struct drm_device
*dev
, void *data
,
1085 struct drm_file
*file
,
1086 struct drm_i915_gem_execbuffer2
*args
,
1087 struct drm_i915_gem_exec_object2
*exec
)
1089 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1091 struct drm_i915_gem_object
*batch_obj
;
1092 struct drm_clip_rect
*cliprects
= NULL
;
1093 struct intel_engine_cs
*ring
;
1094 struct intel_context
*ctx
;
1095 struct i915_address_space
*vm
;
1096 const u32 ctx_id
= i915_execbuffer2_get_context_id(*args
);
1097 u64 exec_start
= args
->batch_start_offset
, exec_len
;
1102 if (!i915_gem_check_execbuffer(args
))
1105 ret
= validate_exec_list(exec
, args
->buffer_count
);
1110 if (args
->flags
& I915_EXEC_SECURE
) {
1111 flags
|= I915_DISPATCH_SECURE
;
1113 if (args
->flags
& I915_EXEC_IS_PINNED
)
1114 flags
|= I915_DISPATCH_PINNED
;
1116 if ((args
->flags
& I915_EXEC_RING_MASK
) > LAST_USER_RING
) {
1117 DRM_DEBUG("execbuf with unknown ring: %d\n",
1118 (int)(args
->flags
& I915_EXEC_RING_MASK
));
1122 if ((args
->flags
& I915_EXEC_RING_MASK
) == I915_EXEC_DEFAULT
)
1123 ring
= &dev_priv
->ring
[RCS
];
1124 else if ((args
->flags
& I915_EXEC_RING_MASK
) == I915_EXEC_BSD
) {
1125 if (HAS_BSD2(dev
)) {
1127 ring_id
= gen8_dispatch_bsd_ring(dev
, file
);
1128 ring
= &dev_priv
->ring
[ring_id
];
1130 ring
= &dev_priv
->ring
[VCS
];
1132 ring
= &dev_priv
->ring
[(args
->flags
& I915_EXEC_RING_MASK
) - 1];
1134 if (!intel_ring_initialized(ring
)) {
1135 DRM_DEBUG("execbuf with invalid ring: %d\n",
1136 (int)(args
->flags
& I915_EXEC_RING_MASK
));
1140 mode
= args
->flags
& I915_EXEC_CONSTANTS_MASK
;
1141 mask
= I915_EXEC_CONSTANTS_MASK
;
1143 case I915_EXEC_CONSTANTS_REL_GENERAL
:
1144 case I915_EXEC_CONSTANTS_ABSOLUTE
:
1145 case I915_EXEC_CONSTANTS_REL_SURFACE
:
1146 if (mode
!= 0 && ring
!= &dev_priv
->ring
[RCS
]) {
1147 DRM_DEBUG("non-0 rel constants mode on non-RCS\n");
1151 if (mode
!= dev_priv
->relative_constants_mode
) {
1152 if (INTEL_INFO(dev
)->gen
< 4) {
1153 DRM_DEBUG("no rel constants on pre-gen4\n");
1157 if (INTEL_INFO(dev
)->gen
> 5 &&
1158 mode
== I915_EXEC_CONSTANTS_REL_SURFACE
) {
1159 DRM_DEBUG("rel surface constants mode invalid on gen5+\n");
1163 /* The HW changed the meaning on this bit on gen6 */
1164 if (INTEL_INFO(dev
)->gen
>= 6)
1165 mask
&= ~I915_EXEC_CONSTANTS_REL_SURFACE
;
1169 DRM_DEBUG("execbuf with unknown constants: %d\n", mode
);
1173 if (args
->buffer_count
< 1) {
1174 DRM_DEBUG("execbuf with %d buffers\n", args
->buffer_count
);
1178 if (args
->num_cliprects
!= 0) {
1179 if (ring
!= &dev_priv
->ring
[RCS
]) {
1180 DRM_DEBUG("clip rectangles are only valid with the render ring\n");
1184 if (INTEL_INFO(dev
)->gen
>= 5) {
1185 DRM_DEBUG("clip rectangles are only valid on pre-gen5\n");
1189 if (args
->num_cliprects
> UINT_MAX
/ sizeof(*cliprects
)) {
1190 DRM_DEBUG("execbuf with %u cliprects\n",
1191 args
->num_cliprects
);
1195 cliprects
= kcalloc(args
->num_cliprects
,
1198 if (cliprects
== NULL
) {
1203 if (copy_from_user(cliprects
,
1204 to_user_ptr(args
->cliprects_ptr
),
1205 sizeof(*cliprects
)*args
->num_cliprects
)) {
1210 if (args
->DR4
== 0xffffffff) {
1211 DRM_DEBUG("UXA submitting garbage DR4, fixing up\n");
1215 if (args
->DR1
|| args
->DR4
|| args
->cliprects_ptr
) {
1216 DRM_DEBUG("0 cliprects but dirt in cliprects fields\n");
1221 intel_runtime_pm_get(dev_priv
);
1223 ret
= i915_mutex_lock_interruptible(dev
);
1227 if (dev_priv
->ums
.mm_suspended
) {
1228 mutex_unlock(&dev
->struct_mutex
);
1233 ctx
= i915_gem_validate_context(dev
, file
, ring
, ctx_id
);
1235 mutex_unlock(&dev
->struct_mutex
);
1240 i915_gem_context_reference(ctx
);
1243 if (!USES_FULL_PPGTT(dev
))
1244 vm
= &dev_priv
->gtt
.base
;
1246 eb
= eb_create(args
);
1248 i915_gem_context_unreference(ctx
);
1249 mutex_unlock(&dev
->struct_mutex
);
1254 /* Look up object handles */
1255 ret
= eb_lookup_vmas(eb
, exec
, args
, vm
, file
);
1259 /* take note of the batch buffer before we might reorder the lists */
1260 batch_obj
= eb_get_batch(eb
);
1262 /* Move the objects en-masse into the GTT, evicting if necessary. */
1263 need_relocs
= (args
->flags
& I915_EXEC_NO_RELOC
) == 0;
1264 ret
= i915_gem_execbuffer_reserve(ring
, &eb
->vmas
, &need_relocs
);
1268 /* The objects are in their final locations, apply the relocations. */
1270 ret
= i915_gem_execbuffer_relocate(eb
);
1272 if (ret
== -EFAULT
) {
1273 ret
= i915_gem_execbuffer_relocate_slow(dev
, args
, file
, ring
,
1275 BUG_ON(!mutex_is_locked(&dev
->struct_mutex
));
1281 /* Set the pending read domains for the batch buffer to COMMAND */
1282 if (batch_obj
->base
.pending_write_domain
) {
1283 DRM_DEBUG("Attempting to use self-modifying batch buffer\n");
1287 batch_obj
->base
.pending_read_domains
|= I915_GEM_DOMAIN_COMMAND
;
1289 if (i915_needs_cmd_parser(ring
)) {
1290 ret
= i915_parse_cmds(ring
,
1292 args
->batch_start_offset
,
1298 * XXX: Actually do this when enabling batch copy...
1300 * Set the DISPATCH_SECURE bit to remove the NON_SECURE bit
1301 * from MI_BATCH_BUFFER_START commands issued in the
1302 * dispatch_execbuffer implementations. We specifically don't
1303 * want that set when the command parser is enabled.
1307 /* snb/ivb/vlv conflate the "batch in ppgtt" bit with the "non-secure
1308 * batch" bit. Hence we need to pin secure batches into the global gtt.
1309 * hsw should have this fixed, but bdw mucks it up again. */
1310 if (flags
& I915_DISPATCH_SECURE
&&
1311 !batch_obj
->has_global_gtt_mapping
) {
1312 /* When we have multiple VMs, we'll need to make sure that we
1313 * allocate space first */
1314 struct i915_vma
*vma
= i915_gem_obj_to_ggtt(batch_obj
);
1316 vma
->bind_vma(vma
, batch_obj
->cache_level
, GLOBAL_BIND
);
1319 if (flags
& I915_DISPATCH_SECURE
)
1320 exec_start
+= i915_gem_obj_ggtt_offset(batch_obj
);
1322 exec_start
+= i915_gem_obj_offset(batch_obj
, vm
);
1324 ret
= i915_gem_execbuffer_move_to_gpu(ring
, &eb
->vmas
);
1328 ret
= i915_switch_context(ring
, ctx
);
1332 if (ring
== &dev_priv
->ring
[RCS
] &&
1333 mode
!= dev_priv
->relative_constants_mode
) {
1334 ret
= intel_ring_begin(ring
, 4);
1338 intel_ring_emit(ring
, MI_NOOP
);
1339 intel_ring_emit(ring
, MI_LOAD_REGISTER_IMM(1));
1340 intel_ring_emit(ring
, INSTPM
);
1341 intel_ring_emit(ring
, mask
<< 16 | mode
);
1342 intel_ring_advance(ring
);
1344 dev_priv
->relative_constants_mode
= mode
;
1347 if (args
->flags
& I915_EXEC_GEN7_SOL_RESET
) {
1348 ret
= i915_reset_gen7_sol_offsets(dev
, ring
);
1354 exec_len
= args
->batch_len
;
1356 for (i
= 0; i
< args
->num_cliprects
; i
++) {
1357 ret
= i915_emit_box(dev
, &cliprects
[i
],
1358 args
->DR1
, args
->DR4
);
1362 ret
= ring
->dispatch_execbuffer(ring
,
1363 exec_start
, exec_len
,
1369 ret
= ring
->dispatch_execbuffer(ring
,
1370 exec_start
, exec_len
,
1376 trace_i915_gem_ring_dispatch(ring
, intel_ring_get_seqno(ring
), flags
);
1378 i915_gem_execbuffer_move_to_active(&eb
->vmas
, ring
);
1379 i915_gem_execbuffer_retire_commands(dev
, file
, ring
, batch_obj
);
1382 /* the request owns the ref now */
1383 i915_gem_context_unreference(ctx
);
1386 mutex_unlock(&dev
->struct_mutex
);
1391 /* intel_gpu_busy should also get a ref, so it will free when the device
1392 * is really idle. */
1393 intel_runtime_pm_put(dev_priv
);
1398 * Legacy execbuffer just creates an exec2 list from the original exec object
1399 * list array and passes it to the real function.
1402 i915_gem_execbuffer(struct drm_device
*dev
, void *data
,
1403 struct drm_file
*file
)
1405 struct drm_i915_gem_execbuffer
*args
= data
;
1406 struct drm_i915_gem_execbuffer2 exec2
;
1407 struct drm_i915_gem_exec_object
*exec_list
= NULL
;
1408 struct drm_i915_gem_exec_object2
*exec2_list
= NULL
;
1411 if (args
->buffer_count
< 1) {
1412 DRM_DEBUG("execbuf with %d buffers\n", args
->buffer_count
);
1416 /* Copy in the exec list from userland */
1417 exec_list
= drm_malloc_ab(sizeof(*exec_list
), args
->buffer_count
);
1418 exec2_list
= drm_malloc_ab(sizeof(*exec2_list
), args
->buffer_count
);
1419 if (exec_list
== NULL
|| exec2_list
== NULL
) {
1420 DRM_DEBUG("Failed to allocate exec list for %d buffers\n",
1421 args
->buffer_count
);
1422 drm_free_large(exec_list
);
1423 drm_free_large(exec2_list
);
1426 ret
= copy_from_user(exec_list
,
1427 to_user_ptr(args
->buffers_ptr
),
1428 sizeof(*exec_list
) * args
->buffer_count
);
1430 DRM_DEBUG("copy %d exec entries failed %d\n",
1431 args
->buffer_count
, ret
);
1432 drm_free_large(exec_list
);
1433 drm_free_large(exec2_list
);
1437 for (i
= 0; i
< args
->buffer_count
; i
++) {
1438 exec2_list
[i
].handle
= exec_list
[i
].handle
;
1439 exec2_list
[i
].relocation_count
= exec_list
[i
].relocation_count
;
1440 exec2_list
[i
].relocs_ptr
= exec_list
[i
].relocs_ptr
;
1441 exec2_list
[i
].alignment
= exec_list
[i
].alignment
;
1442 exec2_list
[i
].offset
= exec_list
[i
].offset
;
1443 if (INTEL_INFO(dev
)->gen
< 4)
1444 exec2_list
[i
].flags
= EXEC_OBJECT_NEEDS_FENCE
;
1446 exec2_list
[i
].flags
= 0;
1449 exec2
.buffers_ptr
= args
->buffers_ptr
;
1450 exec2
.buffer_count
= args
->buffer_count
;
1451 exec2
.batch_start_offset
= args
->batch_start_offset
;
1452 exec2
.batch_len
= args
->batch_len
;
1453 exec2
.DR1
= args
->DR1
;
1454 exec2
.DR4
= args
->DR4
;
1455 exec2
.num_cliprects
= args
->num_cliprects
;
1456 exec2
.cliprects_ptr
= args
->cliprects_ptr
;
1457 exec2
.flags
= I915_EXEC_RENDER
;
1458 i915_execbuffer2_set_context_id(exec2
, 0);
1460 ret
= i915_gem_do_execbuffer(dev
, data
, file
, &exec2
, exec2_list
);
1462 struct drm_i915_gem_exec_object __user
*user_exec_list
=
1463 to_user_ptr(args
->buffers_ptr
);
1465 /* Copy the new buffer offsets back to the user's exec list. */
1466 for (i
= 0; i
< args
->buffer_count
; i
++) {
1467 ret
= __copy_to_user(&user_exec_list
[i
].offset
,
1468 &exec2_list
[i
].offset
,
1469 sizeof(user_exec_list
[i
].offset
));
1472 DRM_DEBUG("failed to copy %d exec entries "
1473 "back to user (%d)\n",
1474 args
->buffer_count
, ret
);
1480 drm_free_large(exec_list
);
1481 drm_free_large(exec2_list
);
1486 i915_gem_execbuffer2(struct drm_device
*dev
, void *data
,
1487 struct drm_file
*file
)
1489 struct drm_i915_gem_execbuffer2
*args
= data
;
1490 struct drm_i915_gem_exec_object2
*exec2_list
= NULL
;
1493 if (args
->buffer_count
< 1 ||
1494 args
->buffer_count
> UINT_MAX
/ sizeof(*exec2_list
)) {
1495 DRM_DEBUG("execbuf2 with %d buffers\n", args
->buffer_count
);
1499 if (args
->rsvd2
!= 0) {
1500 DRM_DEBUG("dirty rvsd2 field\n");
1504 exec2_list
= kmalloc(sizeof(*exec2_list
)*args
->buffer_count
,
1506 if (exec2_list
== NULL
)
1507 exec2_list
= drm_malloc_ab(sizeof(*exec2_list
),
1508 args
->buffer_count
);
1509 if (exec2_list
== NULL
) {
1510 DRM_DEBUG("Failed to allocate exec list for %d buffers\n",
1511 args
->buffer_count
);
1514 ret
= copy_from_user(exec2_list
,
1515 to_user_ptr(args
->buffers_ptr
),
1516 sizeof(*exec2_list
) * args
->buffer_count
);
1518 DRM_DEBUG("copy %d exec entries failed %d\n",
1519 args
->buffer_count
, ret
);
1520 drm_free_large(exec2_list
);
1524 ret
= i915_gem_do_execbuffer(dev
, data
, file
, args
, exec2_list
);
1526 /* Copy the new buffer offsets back to the user's exec list. */
1527 struct drm_i915_gem_exec_object2
*user_exec_list
=
1528 to_user_ptr(args
->buffers_ptr
);
1531 for (i
= 0; i
< args
->buffer_count
; i
++) {
1532 ret
= __copy_to_user(&user_exec_list
[i
].offset
,
1533 &exec2_list
[i
].offset
,
1534 sizeof(user_exec_list
[i
].offset
));
1537 DRM_DEBUG("failed to copy %d exec entries "
1539 args
->buffer_count
);
1545 drm_free_large(exec2_list
);