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drm/i915: Update to Linux 3.16
[dragonfly.git] / sys / dev / drm / i915 / i915_dma.c
blob57d51ca8c66a112b14a40258f3ae09a6934b5276
1 /* i915_dma.c -- DMA support for the I915 -*- linux-c -*-
2 */
3 /*
4 * Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas.
5 * All Rights Reserved.
6 *
7 * Permission is hereby granted, free of charge, to any person obtaining a
8 * copy of this software and associated documentation files (the
9 * "Software"), to deal in the Software without restriction, including
10 * without limitation the rights to use, copy, modify, merge, publish,
11 * distribute, sub license, and/or sell copies of the Software, and to
12 * permit persons to whom the Software is furnished to do so, subject to
13 * the following conditions:
14 *
15 * The above copyright notice and this permission notice (including the
16 * next paragraph) shall be included in all copies or substantial portions
17 * of the Software.
18 *
19 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
20 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
21 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
22 * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR
23 * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
24 * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
25 * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
26 *
27 */
28
29 #include <drm/drmP.h>
30 #include <drm/i915_drm.h>
31 #include "i915_drv.h"
32 #include "intel_drv.h"
33 #include "intel_ringbuffer.h"
34 #include <linux/workqueue.h>
35
36 extern struct drm_i915_private *i915_mch_dev;
37
38 #define LP_RING(d) (&((struct drm_i915_private *)(d))->ring[RCS])
39
40 #define BEGIN_LP_RING(n) \
41 intel_ring_begin(LP_RING(dev_priv), (n))
42
43 #define OUT_RING(x) \
44 intel_ring_emit(LP_RING(dev_priv), x)
45
46 #define ADVANCE_LP_RING() \
47 __intel_ring_advance(LP_RING(dev_priv))
48
49 /**
50 * Lock test for when it's just for synchronization of ring access.
51 *
52 * In that case, we don't need to do it when GEM is initialized as nobody else
53 * has access to the ring.
54 */
55 #define RING_LOCK_TEST_WITH_RETURN(dev, file) do { \
56 if (LP_RING(dev->dev_private)->buffer->obj == NULL) \
57 LOCK_TEST_WITH_RETURN(dev, file); \
58 } while (0)
59
60 static inline u32
61 intel_read_legacy_status_page(struct drm_i915_private *dev_priv, int reg)
62 {
63 if (I915_NEED_GFX_HWS(dev_priv->dev))
64 return ioread32(dev_priv->dri1.gfx_hws_cpu_addr + reg);
65 else
66 return intel_read_status_page(LP_RING(dev_priv), reg);
67 }
68
69 #define READ_HWSP(dev_priv, reg) intel_read_legacy_status_page(dev_priv, reg)
70 #define READ_BREADCRUMB(dev_priv) READ_HWSP(dev_priv, I915_BREADCRUMB_INDEX)
71 #define I915_BREADCRUMB_INDEX 0x21
72
73 void i915_update_dri1_breadcrumb(struct drm_device *dev)
74 {
75 /* XXX: We don't care about dri1 */
76 return;
77 }
78
79 static void i915_write_hws_pga(struct drm_device *dev)
80 {
81 struct drm_i915_private *dev_priv = dev->dev_private;
82 u32 addr;
83
84 addr = dev_priv->status_page_dmah->busaddr;
85 if (INTEL_INFO(dev)->gen >= 4)
86 addr |= (dev_priv->status_page_dmah->busaddr >> 28) & 0xf0;
87 I915_WRITE(HWS_PGA, addr);
88 }
89
90 /**
91 * Frees the hardware status page, whether it's a physical address or a virtual
92 * address set up by the X Server.
93 */
94 static void i915_free_hws(struct drm_device *dev)
95 {
96 struct drm_i915_private *dev_priv = dev->dev_private;
97 struct intel_engine_cs *ring = LP_RING(dev_priv);
98
99 if (dev_priv->status_page_dmah) {
100 drm_pci_free(dev, dev_priv->status_page_dmah);
101 dev_priv->status_page_dmah = NULL;
102 }
103
104 if (ring->status_page.gfx_addr) {
105 ring->status_page.gfx_addr = 0;
106 #if 0 /* We don't care about dri1 */
107 iounmap(dev_priv->dri1.gfx_hws_cpu_addr);
108 #endif
109 }
110
111 /* Need to rewrite hardware status page */
112 I915_WRITE(HWS_PGA, 0x1ffff000);
113 }
114
115 void i915_kernel_lost_context(struct drm_device * dev)
116 {
117 struct drm_i915_private *dev_priv = dev->dev_private;
118 struct drm_i915_private *master_priv = dev_priv;
119 struct intel_engine_cs *ring = LP_RING(dev_priv);
120 struct intel_ringbuffer *ringbuf = ring->buffer;
121
122 /*
123 * We should never lose context on the ring with modesetting
124 * as we don't expose it to userspace
125 */
126 if (drm_core_check_feature(dev, DRIVER_MODESET))
127 return;
128
129 ringbuf->head = I915_READ_HEAD(ring) & HEAD_ADDR;
130 ringbuf->tail = I915_READ_TAIL(ring) & TAIL_ADDR;
131 ringbuf->space = ringbuf->head - (ringbuf->tail + I915_RING_FREE_SPACE);
132 if (ringbuf->space < 0)
133 ringbuf->space += ringbuf->size;
134
135 #if 0
136 if (!dev->primary->master)
137 return;
138
139 master_priv = dev->primary->master->driver_priv;
140 #endif
141 if (ringbuf->head == ringbuf->tail && master_priv->sarea_priv)
142 master_priv->sarea_priv->perf_boxes |= I915_BOX_RING_EMPTY;
143 }
144
145 static int i915_dma_cleanup(struct drm_device * dev)
146 {
147 struct drm_i915_private *dev_priv = dev->dev_private;
148 int i;
149
150 /* Make sure interrupts are disabled here because the uninstall ioctl
151 * may not have been called from userspace and after dev_private
152 * is freed, it's too late.
153 */
154 if (dev->irq_enabled)
155 drm_irq_uninstall(dev);
156
157 mutex_lock(&dev->struct_mutex);
158 for (i = 0; i < I915_NUM_RINGS; i++)
159 intel_cleanup_ring_buffer(&dev_priv->ring[i]);
160 mutex_unlock(&dev->struct_mutex);
161
162 /* Clear the HWS virtual address at teardown */
163 if (I915_NEED_GFX_HWS(dev))
164 i915_free_hws(dev);
165
166 return 0;
167 }
168
169 static int i915_initialize(struct drm_device * dev, drm_i915_init_t * init)
170 {
171 struct drm_i915_private *dev_priv = dev->dev_private;
172 int ret;
173
174 dev_priv->sarea = drm_getsarea(dev);
175 if (!dev_priv->sarea) {
176 DRM_ERROR("can not find sarea!\n");
177 i915_dma_cleanup(dev);
178 return -EINVAL;
179 }
180
181 dev_priv->sarea_priv = (drm_i915_sarea_t *)
182 ((u8 *) dev_priv->sarea->handle + init->sarea_priv_offset);
183
184 if (init->ring_size != 0) {
185 if (LP_RING(dev_priv)->buffer->obj != NULL) {
186 i915_dma_cleanup(dev);
187 DRM_ERROR("Client tried to initialize ringbuffer in "
188 "GEM mode\n");
189 return -EINVAL;
190 }
191
192 ret = intel_render_ring_init_dri(dev,
193 init->ring_start,
194 init->ring_size);
195 if (ret) {
196 i915_dma_cleanup(dev);
197 return ret;
198 }
199 }
200
201 dev_priv->dri1.cpp = init->cpp;
202 dev_priv->dri1.back_offset = init->back_offset;
203 dev_priv->dri1.front_offset = init->front_offset;
204 dev_priv->dri1.current_page = 0;
205 dev_priv->sarea_priv->pf_current_page = 0;
206
207
208 /* Allow hardware batchbuffers unless told otherwise.
209 */
210 dev_priv->dri1.allow_batchbuffer = 1;
211
212 return 0;
213 }
214
215 static int i915_dma_resume(struct drm_device * dev)
216 {
217 struct drm_i915_private *dev_priv = dev->dev_private;
218 struct intel_engine_cs *ring = LP_RING(dev_priv);
219
220 DRM_DEBUG_DRIVER("%s\n", __func__);
221
222 if (ring->buffer->virtual_start == NULL) {
223 DRM_ERROR("can not ioremap virtual address for"
224 " ring buffer\n");
225 return -ENOMEM;
226 }
227
228 /* Program Hardware Status Page */
229 if (!ring->status_page.page_addr) {
230 DRM_ERROR("Can not find hardware status page\n");
231 return -EINVAL;
232 }
233 DRM_DEBUG_DRIVER("hw status page @ %p\n",
234 ring->status_page.page_addr);
235 if (ring->status_page.gfx_addr != 0)
236 intel_ring_setup_status_page(ring);
237 else
238 i915_write_hws_pga(dev);
239
240 DRM_DEBUG_DRIVER("Enabled hardware status page\n");
241
242 return 0;
243 }
244
245 static int i915_dma_init(struct drm_device *dev, void *data,
246 struct drm_file *file_priv)
247 {
248 drm_i915_init_t *init = data;
249 int retcode = 0;
250
251 if (drm_core_check_feature(dev, DRIVER_MODESET))
252 return -ENODEV;
253
254 switch (init->func) {
255 case I915_INIT_DMA:
256 retcode = i915_initialize(dev, init);
257 break;
258 case I915_CLEANUP_DMA:
259 retcode = i915_dma_cleanup(dev);
260 break;
261 case I915_RESUME_DMA:
262 retcode = i915_dma_resume(dev);
263 break;
264 default:
265 retcode = -EINVAL;
266 break;
267 }
268
269 return retcode;
270 }
271
272 /* Implement basically the same security restrictions as hardware does
273 * for MI_BATCH_NON_SECURE. These can be made stricter at any time.
274 *
275 * Most of the calculations below involve calculating the size of a
276 * particular instruction. It's important to get the size right as
277 * that tells us where the next instruction to check is. Any illegal
278 * instruction detected will be given a size of zero, which is a
279 * signal to abort the rest of the buffer.
280 */
281 static int validate_cmd(int cmd)
282 {
283 switch (((cmd >> 29) & 0x7)) {
284 case 0x0:
285 switch ((cmd >> 23) & 0x3f) {
286 case 0x0:
287 return 1; /* MI_NOOP */
288 case 0x4:
289 return 1; /* MI_FLUSH */
290 default:
291 return 0; /* disallow everything else */
292 }
293 break;
294 case 0x1:
295 return 0; /* reserved */
296 case 0x2:
297 return (cmd & 0xff) + 2; /* 2d commands */
298 case 0x3:
299 if (((cmd >> 24) & 0x1f) <= 0x18)
300 return 1;
301
302 switch ((cmd >> 24) & 0x1f) {
303 case 0x1c:
304 return 1;
305 case 0x1d:
306 switch ((cmd >> 16) & 0xff) {
307 case 0x3:
308 return (cmd & 0x1f) + 2;
309 case 0x4:
310 return (cmd & 0xf) + 2;
311 default:
312 return (cmd & 0xffff) + 2;
313 }
314 case 0x1e:
315 if (cmd & (1 << 23))
316 return (cmd & 0xffff) + 1;
317 else
318 return 1;
319 case 0x1f:
320 if ((cmd & (1 << 23)) == 0) /* inline vertices */
321 return (cmd & 0x1ffff) + 2;
322 else if (cmd & (1 << 17)) /* indirect random */
323 if ((cmd & 0xffff) == 0)
324 return 0; /* unknown length, too hard */
325 else
326 return (((cmd & 0xffff) + 1) / 2) + 1;
327 else
328 return 2; /* indirect sequential */
329 default:
330 return 0;
331 }
332 default:
333 return 0;
334 }
335
336 return 0;
337 }
338
339 static int i915_emit_cmds(struct drm_device * dev, int *buffer, int dwords)
340 {
341 struct drm_i915_private *dev_priv = dev->dev_private;
342 int i, ret;
343
344 if ((dwords+1) * sizeof(int) >= LP_RING(dev_priv)->buffer->size - 8)
345 return -EINVAL;
346
347 for (i = 0; i < dwords;) {
348 int sz = validate_cmd(buffer[i]);
349 if (sz == 0 || i + sz > dwords)
350 return -EINVAL;
351 i += sz;
352 }
353
354 ret = BEGIN_LP_RING((dwords+1)&~1);
355 if (ret)
356 return ret;
357
358 for (i = 0; i < dwords; i++)
359 OUT_RING(buffer[i]);
360 if (dwords & 1)
361 OUT_RING(0);
362
363 ADVANCE_LP_RING();
364
365 return 0;
366 }
367
368 int
369 i915_emit_box(struct drm_device *dev,
370 struct drm_clip_rect *box,
371 int DR1, int DR4)
372 {
373 struct drm_i915_private *dev_priv = dev->dev_private;
374 int ret;
375
376 if (box->y2 <= box->y1 || box->x2 <= box->x1 ||
377 box->y2 <= 0 || box->x2 <= 0) {
378 DRM_ERROR("Bad box %d,%d..%d,%d\n",
379 box->x1, box->y1, box->x2, box->y2);
380 return -EINVAL;
381 }
382
383 if (INTEL_INFO(dev)->gen >= 4) {
384 ret = BEGIN_LP_RING(4);
385 if (ret)
386 return ret;
387
388 OUT_RING(GFX_OP_DRAWRECT_INFO_I965);
389 OUT_RING((box->x1 & 0xffff) | (box->y1 << 16));
390 OUT_RING(((box->x2 - 1) & 0xffff) | ((box->y2 - 1) << 16));
391 OUT_RING(DR4);
392 } else {
393 ret = BEGIN_LP_RING(6);
394 if (ret)
395 return ret;
396
397 OUT_RING(GFX_OP_DRAWRECT_INFO);
398 OUT_RING(DR1);
399 OUT_RING((box->x1 & 0xffff) | (box->y1 << 16));
400 OUT_RING(((box->x2 - 1) & 0xffff) | ((box->y2 - 1) << 16));
401 OUT_RING(DR4);
402 OUT_RING(0);
403 }
404 ADVANCE_LP_RING();
405
406 return 0;
407 }
408
409 /* XXX: Emitting the counter should really be moved to part of the IRQ
410 * emit. For now, do it in both places:
411 */
412
413 static void i915_emit_breadcrumb(struct drm_device *dev)
414 {
415 struct drm_i915_private *dev_priv = dev->dev_private;
416
417 dev_priv->dri1.counter++;
418 if (dev_priv->dri1.counter > 0x7FFFFFFFUL)
419 dev_priv->dri1.counter = 0;
420 if (dev_priv->sarea_priv)
421 dev_priv->sarea_priv->last_enqueue = dev_priv->dri1.counter;
422
423 if (BEGIN_LP_RING(4) == 0) {
424 OUT_RING(MI_STORE_DWORD_INDEX);
425 OUT_RING(I915_BREADCRUMB_INDEX << MI_STORE_DWORD_INDEX_SHIFT);
426 OUT_RING(dev_priv->dri1.counter);
427 OUT_RING(0);
428 ADVANCE_LP_RING();
429 }
430 }
431
432 static int i915_dispatch_cmdbuffer(struct drm_device * dev,
433 drm_i915_cmdbuffer_t *cmd,
434 struct drm_clip_rect *cliprects,
435 void *cmdbuf)
436 {
437 int nbox = cmd->num_cliprects;
438 int i = 0, count, ret;
439
440 if (cmd->sz & 0x3) {
441 DRM_ERROR("alignment");
442 return -EINVAL;
443 }
444
445 i915_kernel_lost_context(dev);
446
447 count = nbox ? nbox : 1;
448
449 for (i = 0; i < count; i++) {
450 if (i < nbox) {
451 ret = i915_emit_box(dev, &cliprects[i],
452 cmd->DR1, cmd->DR4);
453 if (ret)
454 return ret;
455 }
456
457 ret = i915_emit_cmds(dev, cmdbuf, cmd->sz / 4);
458 if (ret)
459 return ret;
460 }
461
462 i915_emit_breadcrumb(dev);
463 return 0;
464 }
465
466 static int i915_dispatch_batchbuffer(struct drm_device * dev,
467 drm_i915_batchbuffer_t * batch,
468 struct drm_clip_rect *cliprects)
469 {
470 struct drm_i915_private *dev_priv = dev->dev_private;
471 int nbox = batch->num_cliprects;
472 int i, count, ret;
473
474 if ((batch->start | batch->used) & 0x7) {
475 DRM_ERROR("alignment");
476 return -EINVAL;
477 }
478
479 i915_kernel_lost_context(dev);
480
481 count = nbox ? nbox : 1;
482 for (i = 0; i < count; i++) {
483 if (i < nbox) {
484 ret = i915_emit_box(dev, &cliprects[i],
485 batch->DR1, batch->DR4);
486 if (ret)
487 return ret;
488 }
489
490 if (!IS_I830(dev) && !IS_845G(dev)) {
491 ret = BEGIN_LP_RING(2);
492 if (ret)
493 return ret;
494
495 if (INTEL_INFO(dev)->gen >= 4) {
496 OUT_RING(MI_BATCH_BUFFER_START | (2 << 6) | MI_BATCH_NON_SECURE_I965);
497 OUT_RING(batch->start);
498 } else {
499 OUT_RING(MI_BATCH_BUFFER_START | (2 << 6));
500 OUT_RING(batch->start | MI_BATCH_NON_SECURE);
501 }
502 } else {
503 ret = BEGIN_LP_RING(4);
504 if (ret)
505 return ret;
506
507 OUT_RING(MI_BATCH_BUFFER);
508 OUT_RING(batch->start | MI_BATCH_NON_SECURE);
509 OUT_RING(batch->start + batch->used - 4);
510 OUT_RING(0);
511 }
512 ADVANCE_LP_RING();
513 }
514
515
516 if (IS_G4X(dev) || IS_GEN5(dev)) {
517 if (BEGIN_LP_RING(2) == 0) {
518 OUT_RING(MI_FLUSH | MI_NO_WRITE_FLUSH | MI_INVALIDATE_ISP);
519 OUT_RING(MI_NOOP);
520 ADVANCE_LP_RING();
521 }
522 }
523
524 i915_emit_breadcrumb(dev);
525 return 0;
526 }
527
528 static int i915_dispatch_flip(struct drm_device * dev)
529 {
530 struct drm_i915_private *dev_priv = dev->dev_private;
531 int ret;
532
533 if (!dev_priv->sarea_priv)
534 return -EINVAL;
535
536 DRM_DEBUG_DRIVER("%s: page=%d pfCurrentPage=%d\n",
537 __func__,
538 dev_priv->dri1.current_page,
539 dev_priv->sarea_priv->pf_current_page);
540
541 i915_kernel_lost_context(dev);
542
543 ret = BEGIN_LP_RING(10);
544 if (ret)
545 return ret;
546
547 OUT_RING(MI_FLUSH | MI_READ_FLUSH);
548 OUT_RING(0);
549
550 OUT_RING(CMD_OP_DISPLAYBUFFER_INFO | ASYNC_FLIP);
551 OUT_RING(0);
552 if (dev_priv->dri1.current_page == 0) {
553 OUT_RING(dev_priv->dri1.back_offset);
554 dev_priv->dri1.current_page = 1;
555 } else {
556 OUT_RING(dev_priv->dri1.front_offset);
557 dev_priv->dri1.current_page = 0;
558 }
559 OUT_RING(0);
560
561 OUT_RING(MI_WAIT_FOR_EVENT | MI_WAIT_FOR_PLANE_A_FLIP);
562 OUT_RING(0);
563
564 ADVANCE_LP_RING();
565
566 dev_priv->sarea_priv->last_enqueue = dev_priv->dri1.counter++;
567
568 if (BEGIN_LP_RING(4) == 0) {
569 OUT_RING(MI_STORE_DWORD_INDEX);
570 OUT_RING(I915_BREADCRUMB_INDEX << MI_STORE_DWORD_INDEX_SHIFT);
571 OUT_RING(dev_priv->dri1.counter);
572 OUT_RING(0);
573 ADVANCE_LP_RING();
574 }
575
576 dev_priv->sarea_priv->pf_current_page = dev_priv->dri1.current_page;
577 return 0;
578 }
579
580 static int i915_quiescent(struct drm_device *dev)
581 {
582 i915_kernel_lost_context(dev);
583 return intel_ring_idle(LP_RING(dev->dev_private));
584 }
585
586 static int i915_flush_ioctl(struct drm_device *dev, void *data,
587 struct drm_file *file_priv)
588 {
589 int ret;
590
591 if (drm_core_check_feature(dev, DRIVER_MODESET))
592 return -ENODEV;
593
594 RING_LOCK_TEST_WITH_RETURN(dev, file_priv);
595
596 mutex_lock(&dev->struct_mutex);
597 ret = i915_quiescent(dev);
598 mutex_unlock(&dev->struct_mutex);
599
600 return ret;
601 }
602
603 static int i915_batchbuffer(struct drm_device *dev, void *data,
604 struct drm_file *file_priv)
605 {
606 struct drm_i915_private *dev_priv = dev->dev_private;
607 drm_i915_sarea_t *sarea_priv;
608 drm_i915_batchbuffer_t *batch = data;
609 int ret;
610 struct drm_clip_rect *cliprects = NULL;
611
612 if (drm_core_check_feature(dev, DRIVER_MODESET))
613 return -ENODEV;
614
615 sarea_priv = (drm_i915_sarea_t *) dev_priv->sarea_priv;
616
617 if (!dev_priv->dri1.allow_batchbuffer) {
618 DRM_ERROR("Batchbuffer ioctl disabled\n");
619 return -EINVAL;
620 }
621
622 DRM_DEBUG_DRIVER("i915 batchbuffer, start %x used %d cliprects %d\n",
623 batch->start, batch->used, batch->num_cliprects);
624
625 RING_LOCK_TEST_WITH_RETURN(dev, file_priv);
626
627 if (batch->num_cliprects < 0)
628 return -EINVAL;
629
630 if (batch->num_cliprects) {
631 cliprects = kcalloc(batch->num_cliprects,
632 sizeof(*cliprects),
633 GFP_KERNEL);
634 if (cliprects == NULL)
635 return -ENOMEM;
636
637 ret = copy_from_user(cliprects, batch->cliprects,
638 batch->num_cliprects *
639 sizeof(struct drm_clip_rect));
640 if (ret != 0) {
641 ret = -EFAULT;
642 goto fail_free;
643 }
644 }
645
646 mutex_lock(&dev->struct_mutex);
647 ret = i915_dispatch_batchbuffer(dev, batch, cliprects);
648 mutex_unlock(&dev->struct_mutex);
649
650 if (sarea_priv)
651 sarea_priv->last_dispatch = READ_BREADCRUMB(dev_priv);
652
653 fail_free:
654 kfree(cliprects);
655
656 return ret;
657 }
658
659 static int i915_cmdbuffer(struct drm_device *dev, void *data,
660 struct drm_file *file_priv)
661 {
662 struct drm_i915_private *dev_priv = dev->dev_private;
663 drm_i915_sarea_t *sarea_priv;
664 drm_i915_cmdbuffer_t *cmdbuf = data;
665 struct drm_clip_rect *cliprects = NULL;
666 void *batch_data;
667 int ret;
668
669 DRM_DEBUG_DRIVER("i915 cmdbuffer, buf %p sz %d cliprects %d\n",
670 cmdbuf->buf, cmdbuf->sz, cmdbuf->num_cliprects);
671
672 if (drm_core_check_feature(dev, DRIVER_MODESET))
673 return -ENODEV;
674
675 sarea_priv = (drm_i915_sarea_t *) dev_priv->sarea_priv;
676
677 RING_LOCK_TEST_WITH_RETURN(dev, file_priv);
678
679 if (cmdbuf->num_cliprects < 0)
680 return -EINVAL;
681
682 batch_data = kmalloc(cmdbuf->sz, M_DRM, M_WAITOK);
683 if (batch_data == NULL)
684 return -ENOMEM;
685
686 ret = copy_from_user(batch_data, cmdbuf->buf, cmdbuf->sz);
687 if (ret != 0) {
688 ret = -EFAULT;
689 goto fail_batch_free;
690 }
691
692 if (cmdbuf->num_cliprects) {
693 cliprects = kcalloc(cmdbuf->num_cliprects,
694 sizeof(*cliprects), GFP_KERNEL);
695 if (cliprects == NULL) {
696 ret = -ENOMEM;
697 goto fail_batch_free;
698 }
699
700 ret = copy_from_user(cliprects, cmdbuf->cliprects,
701 cmdbuf->num_cliprects *
702 sizeof(struct drm_clip_rect));
703 if (ret != 0) {
704 ret = -EFAULT;
705 goto fail_clip_free;
706 }
707 }
708
709 mutex_lock(&dev->struct_mutex);
710 ret = i915_dispatch_cmdbuffer(dev, cmdbuf, cliprects, batch_data);
711 mutex_unlock(&dev->struct_mutex);
712 if (ret) {
713 DRM_ERROR("i915_dispatch_cmdbuffer failed\n");
714 goto fail_clip_free;
715 }
716
717 if (sarea_priv)
718 sarea_priv->last_dispatch = READ_BREADCRUMB(dev_priv);
719
720 fail_clip_free:
721 kfree(cliprects);
722 fail_batch_free:
723 kfree(batch_data);
724
725 return ret;
726 }
727
728 static int i915_emit_irq(struct drm_device * dev)
729 {
730 struct drm_i915_private *dev_priv = dev->dev_private;
731 #if 0
732 struct drm_i915_master_private *master_priv = dev->primary->master->driver_priv;
733 #endif
734
735 i915_kernel_lost_context(dev);
736
737 DRM_DEBUG_DRIVER("\n");
738
739 dev_priv->dri1.counter++;
740 if (dev_priv->dri1.counter > 0x7FFFFFFFUL)
741 dev_priv->dri1.counter = 1;
742 if (dev_priv->sarea_priv)
743 dev_priv->sarea_priv->last_enqueue = dev_priv->dri1.counter;
744
745 if (BEGIN_LP_RING(4) == 0) {
746 OUT_RING(MI_STORE_DWORD_INDEX);
747 OUT_RING(I915_BREADCRUMB_INDEX << MI_STORE_DWORD_INDEX_SHIFT);
748 OUT_RING(dev_priv->dri1.counter);
749 OUT_RING(MI_USER_INTERRUPT);
750 ADVANCE_LP_RING();
751 }
752
753 return dev_priv->dri1.counter;
754 }
755
756 static int i915_wait_irq(struct drm_device * dev, int irq_nr)
757 {
758 struct drm_i915_private *dev_priv = dev->dev_private;
759 #if 0
760 struct drm_i915_master_private *master_priv = dev->primary->master->driver_priv;
761 #endif
762 int ret = 0;
763 struct intel_engine_cs *ring = LP_RING(dev_priv);
764
765 DRM_DEBUG_DRIVER("irq_nr=%d breadcrumb=%d\n", irq_nr,
766 READ_BREADCRUMB(dev_priv));
767
768 #if 0
769 if (READ_BREADCRUMB(dev_priv) >= irq_nr) {
770 if (master_priv->sarea_priv)
771 master_priv->sarea_priv->last_dispatch = READ_BREADCRUMB(dev_priv);
772 return 0;
773 }
774
775 if (master_priv->sarea_priv)
776 master_priv->sarea_priv->perf_boxes |= I915_BOX_WAIT;
777 #else
778 if (READ_BREADCRUMB(dev_priv) >= irq_nr) {
779 if (dev_priv->sarea_priv) {
780 dev_priv->sarea_priv->last_dispatch =
781 READ_BREADCRUMB(dev_priv);
782 }
783 return 0;
784 }
785
786 if (dev_priv->sarea_priv)
787 dev_priv->sarea_priv->perf_boxes |= I915_BOX_WAIT;
788 #endif
789
790 if (ring->irq_get(ring)) {
791 DRM_WAIT_ON(ret, ring->irq_queue, 3 * HZ,
792 READ_BREADCRUMB(dev_priv) >= irq_nr);
793 ring->irq_put(ring);
794 } else if (wait_for(READ_BREADCRUMB(dev_priv) >= irq_nr, 3000))
795 ret = -EBUSY;
796
797 if (ret == -EBUSY) {
798 DRM_ERROR("EBUSY -- rec: %d emitted: %d\n",
799 READ_BREADCRUMB(dev_priv), (int)dev_priv->dri1.counter);
800 }
801
802 return ret;
803 }
804
805 /* Needs the lock as it touches the ring.
806 */
807 static int i915_irq_emit(struct drm_device *dev, void *data,
808 struct drm_file *file_priv)
809 {
810 struct drm_i915_private *dev_priv = dev->dev_private;
811 drm_i915_irq_emit_t *emit = data;
812 int result;
813
814 if (drm_core_check_feature(dev, DRIVER_MODESET))
815 return -ENODEV;
816
817 if (!dev_priv || !LP_RING(dev_priv)->buffer->virtual_start) {
818 DRM_ERROR("called with no initialization\n");
819 return -EINVAL;
820 }
821
822 RING_LOCK_TEST_WITH_RETURN(dev, file_priv);
823
824 mutex_lock(&dev->struct_mutex);
825 result = i915_emit_irq(dev);
826 mutex_unlock(&dev->struct_mutex);
827
828 if (copy_to_user(emit->irq_seq, &result, sizeof(int))) {
829 DRM_ERROR("copy_to_user\n");
830 return -EFAULT;
831 }
832
833 return 0;
834 }
835
836 /* Doesn't need the hardware lock.
837 */
838 static int i915_irq_wait(struct drm_device *dev, void *data,
839 struct drm_file *file_priv)
840 {
841 struct drm_i915_private *dev_priv = dev->dev_private;
842 drm_i915_irq_wait_t *irqwait = data;
843
844 if (drm_core_check_feature(dev, DRIVER_MODESET))
845 return -ENODEV;
846
847 if (!dev_priv) {
848 DRM_ERROR("called with no initialization\n");
849 return -EINVAL;
850 }
851
852 return i915_wait_irq(dev, irqwait->irq_seq);
853 }
854
855 static int i915_vblank_pipe_get(struct drm_device *dev, void *data,
856 struct drm_file *file_priv)
857 {
858 struct drm_i915_private *dev_priv = dev->dev_private;
859 drm_i915_vblank_pipe_t *pipe = data;
860
861 if (drm_core_check_feature(dev, DRIVER_MODESET))
862 return -ENODEV;
863
864 if (!dev_priv) {
865 DRM_ERROR("called with no initialization\n");
866 return -EINVAL;
867 }
868
869 pipe->pipe = DRM_I915_VBLANK_PIPE_A | DRM_I915_VBLANK_PIPE_B;
870
871 return 0;
872 }
873
874 /**
875 * Schedule buffer swap at given vertical blank.
876 */
877 static int i915_vblank_swap(struct drm_device *dev, void *data,
878 struct drm_file *file_priv)
879 {
880 /* The delayed swap mechanism was fundamentally racy, and has been
881 * removed. The model was that the client requested a delayed flip/swap
882 * from the kernel, then waited for vblank before continuing to perform
883 * rendering. The problem was that the kernel might wake the client
884 * up before it dispatched the vblank swap (since the lock has to be
885 * held while touching the ringbuffer), in which case the client would
886 * clear and start the next frame before the swap occurred, and
887 * flicker would occur in addition to likely missing the vblank.
888 *
889 * In the absence of this ioctl, userland falls back to a correct path
890 * of waiting for a vblank, then dispatching the swap on its own.
891 * Context switching to userland and back is plenty fast enough for
892 * meeting the requirements of vblank swapping.
893 */
894 return -EINVAL;
895 }
896
897 static int i915_flip_bufs(struct drm_device *dev, void *data,
898 struct drm_file *file_priv)
899 {
900 int ret;
901
902 if (drm_core_check_feature(dev, DRIVER_MODESET))
903 return -ENODEV;
904
905 DRM_DEBUG_DRIVER("%s\n", __func__);
906
907 RING_LOCK_TEST_WITH_RETURN(dev, file_priv);
908
909 mutex_lock(&dev->struct_mutex);
910 ret = i915_dispatch_flip(dev);
911 mutex_unlock(&dev->struct_mutex);
912
913 return ret;
914 }
915
916 static int i915_getparam(struct drm_device *dev, void *data,
917 struct drm_file *file_priv)
918 {
919 struct drm_i915_private *dev_priv = dev->dev_private;
920 drm_i915_getparam_t *param = data;
921 int value;
922
923 if (!dev_priv) {
924 DRM_ERROR("called with no initialization\n");
925 return -EINVAL;
926 }
927
928 switch (param->param) {
929 case I915_PARAM_IRQ_ACTIVE:
930 value = dev->irq_enabled ? 1 : 0;
931 break;
932 case I915_PARAM_ALLOW_BATCHBUFFER:
933 value = dev_priv->dri1.allow_batchbuffer ? 1 : 0;
934 break;
935 case I915_PARAM_LAST_DISPATCH:
936 value = READ_BREADCRUMB(dev_priv);
937 break;
938 case I915_PARAM_CHIPSET_ID:
939 value = dev->pdev->device;
940 break;
941 case I915_PARAM_HAS_GEM:
942 value = 1;
943 break;
944 case I915_PARAM_NUM_FENCES_AVAIL:
945 value = dev_priv->num_fence_regs - dev_priv->fence_reg_start;
946 break;
947 case I915_PARAM_HAS_OVERLAY:
948 value = dev_priv->overlay ? 1 : 0;
949 break;
950 case I915_PARAM_HAS_PAGEFLIPPING:
951 value = 1;
952 break;
953 case I915_PARAM_HAS_EXECBUF2:
954 /* depends on GEM */
955 value = 1;
956 break;
957 case I915_PARAM_HAS_BSD:
958 value = intel_ring_initialized(&dev_priv->ring[VCS]);
959 break;
960 case I915_PARAM_HAS_BLT:
961 value = intel_ring_initialized(&dev_priv->ring[BCS]);
962 break;
963 case I915_PARAM_HAS_VEBOX:
964 value = intel_ring_initialized(&dev_priv->ring[VECS]);
965 break;
966 case I915_PARAM_HAS_RELAXED_FENCING:
967 value = 1;
968 break;
969 case I915_PARAM_HAS_COHERENT_RINGS:
970 value = 1;
971 break;
972 case I915_PARAM_HAS_EXEC_CONSTANTS:
973 value = INTEL_INFO(dev)->gen >= 4;
974 break;
975 case I915_PARAM_HAS_RELAXED_DELTA:
976 value = 1;
977 break;
978 case I915_PARAM_HAS_GEN7_SOL_RESET:
979 value = 1;
980 break;
981 case I915_PARAM_HAS_LLC:
982 value = HAS_LLC(dev);
983 break;
984 case I915_PARAM_HAS_WT:
985 value = HAS_WT(dev);
986 break;
987 case I915_PARAM_HAS_ALIASING_PPGTT:
988 value = dev_priv->mm.aliasing_ppgtt || USES_FULL_PPGTT(dev);
989 break;
990 case I915_PARAM_HAS_WAIT_TIMEOUT:
991 value = 1;
992 break;
993 case I915_PARAM_HAS_SEMAPHORES:
994 value = i915_semaphore_is_enabled(dev);
995 break;
996 case I915_PARAM_HAS_PINNED_BATCHES:
997 value = 1;
998 break;
999 case I915_PARAM_HAS_EXEC_NO_RELOC:
1000 value = 1;
1001 break;
1002 case I915_PARAM_HAS_EXEC_HANDLE_LUT:
1003 value = 1;
1004 break;
1005 case I915_PARAM_CMD_PARSER_VERSION:
1006 value = i915_cmd_parser_get_version();
1007 break;
1008 default:
1009 DRM_DEBUG("Unknown parameter %d\n", param->param);
1010 return -EINVAL;
1011 }
1012
1013 if (copy_to_user(param->value, &value, sizeof(int))) {
1014 DRM_ERROR("copy_to_user failed\n");
1015 return -EFAULT;
1016 }
1017
1018 return 0;
1019 }
1020
1021 static int i915_setparam(struct drm_device *dev, void *data,
1022 struct drm_file *file_priv)
1023 {
1024 struct drm_i915_private *dev_priv = dev->dev_private;
1025 drm_i915_setparam_t *param = data;
1026
1027 if (!dev_priv) {
1028 DRM_ERROR("called with no initialization\n");
1029 return -EINVAL;
1030 }
1031
1032 switch (param->param) {
1033 case I915_SETPARAM_USE_MI_BATCHBUFFER_START:
1034 break;
1035 case I915_SETPARAM_TEX_LRU_LOG_GRANULARITY:
1036 break;
1037 case I915_SETPARAM_ALLOW_BATCHBUFFER:
1038 dev_priv->dri1.allow_batchbuffer = param->value ? 1 : 0;
1039 break;
1040 case I915_SETPARAM_NUM_USED_FENCES:
1041 if (param->value > dev_priv->num_fence_regs ||
1042 param->value < 0)
1043 return -EINVAL;
1044 /* Userspace can use first N regs */
1045 dev_priv->fence_reg_start = param->value;
1046 break;
1047 default:
1048 DRM_DEBUG_DRIVER("unknown parameter %d\n",
1049 param->param);
1050 return -EINVAL;
1051 }
1052
1053 return 0;
1054 }
1055
1056 static int i915_set_status_page(struct drm_device *dev, void *data,
1057 struct drm_file *file_priv)
1058 {
1059 #if 0 /* We don't care about dri1 */
1060 struct drm_i915_private *dev_priv = dev->dev_private;
1061 drm_i915_hws_addr_t *hws = data;
1062 struct intel_engine_cs *ring;
1063
1064 if (drm_core_check_feature(dev, DRIVER_MODESET))
1065 return -ENODEV;
1066
1067 if (!I915_NEED_GFX_HWS(dev))
1068 return -EINVAL;
1069
1070 if (!dev_priv) {
1071 DRM_ERROR("called with no initialization\n");
1072 return -EINVAL;
1073 }
1074
1075 if (drm_core_check_feature(dev, DRIVER_MODESET)) {
1076 WARN(1, "tried to set status page when mode setting active\n");
1077 return 0;
1078 }
1079
1080 DRM_DEBUG_DRIVER("set status page addr 0x%08x\n", (u32)hws->addr);
1081
1082 ring = LP_RING(dev_priv);
1083 ring->status_page.gfx_addr = hws->addr & (0x1ffff<<12);
1084
1085 dev_priv->dri1.gfx_hws_cpu_addr =
1086 ioremap_wc(dev_priv->gtt.mappable_base + hws->addr, 4096);
1087 if (dev_priv->dri1.gfx_hws_cpu_addr == NULL) {
1088 i915_dma_cleanup(dev);
1089 ring->status_page.gfx_addr = 0;
1090 DRM_ERROR("can not ioremap virtual address for"
1091 " G33 hw status page\n");
1092 return -ENOMEM;
1093 }
1094
1095 memset_io(dev_priv->dri1.gfx_hws_cpu_addr, 0, PAGE_SIZE);
1096 I915_WRITE(HWS_PGA, ring->status_page.gfx_addr);
1097
1098 DRM_DEBUG_DRIVER("load hws HWS_PGA with gfx mem 0x%x\n",
1099 ring->status_page.gfx_addr);
1100 DRM_DEBUG_DRIVER("load hws at %p\n",
1101 ring->status_page.page_addr);
1102 return 0;
1103 #endif
1104 return -EINVAL;
1105 }
1106
1107 static int i915_get_bridge_dev(struct drm_device *dev)
1108 {
1109 struct drm_i915_private *dev_priv = dev->dev_private;
1110 static struct pci_dev i915_bridge_dev;
1111
1112 i915_bridge_dev.dev = pci_find_dbsf(0, 0, 0, 0);
1113 if (!i915_bridge_dev.dev) {
1114 DRM_ERROR("bridge device not found\n");
1115 return -1;
1116 }
1117
1118 dev_priv->bridge_dev = &i915_bridge_dev;
1119 return 0;
1120 }
1121
1122 #define MCHBAR_I915 0x44
1123 #define MCHBAR_I965 0x48
1124 #define MCHBAR_SIZE (4*4096)
1125
1126 #define DEVEN_REG 0x54
1127 #define DEVEN_MCHBAR_EN (1 << 28)
1128
1129 /* Allocate space for the MCH regs if needed, return nonzero on error */
1130 static int
1131 intel_alloc_mchbar_resource(struct drm_device *dev)
1132 {
1133 struct drm_i915_private *dev_priv = dev->dev_private;
1134 int reg = INTEL_INFO(dev)->gen >= 4 ? MCHBAR_I965 : MCHBAR_I915;
1135 device_t vga;
1136 u32 temp_lo, temp_hi = 0;
1137 u64 mchbar_addr;
1138
1139 if (INTEL_INFO(dev)->gen >= 4)
1140 pci_read_config_dword(dev_priv->bridge_dev, reg + 4, &temp_hi);
1141 pci_read_config_dword(dev_priv->bridge_dev, reg, &temp_lo);
1142 mchbar_addr = ((u64)temp_hi << 32) | temp_lo;
1143
1144 /* If ACPI doesn't have it, assume we need to allocate it ourselves */
1145 #ifdef CONFIG_PNP
1146 if (mchbar_addr &&
1147 pnp_range_reserved(mchbar_addr, mchbar_addr + MCHBAR_SIZE))
1148 return 0;
1149 #endif
1150
1151 /* Get some space for it */
1152 vga = device_get_parent(dev->dev);
1153 dev_priv->mch_res_rid = 0x100;
1154 dev_priv->mch_res = BUS_ALLOC_RESOURCE(device_get_parent(vga),
1155 dev->dev, SYS_RES_MEMORY, &dev_priv->mch_res_rid, 0, ~0UL,
1156 MCHBAR_SIZE, RF_ACTIVE | RF_SHAREABLE, -1);
1157 if (dev_priv->mch_res == NULL) {
1158 DRM_ERROR("failed mchbar resource alloc\n");
1159 return (-ENOMEM);
1160 }
1161
1162 if (INTEL_INFO(dev)->gen >= 4)
1163 pci_write_config_dword(dev_priv->bridge_dev, reg + 4,
1164 upper_32_bits(rman_get_start(dev_priv->mch_res)));
1165
1166 pci_write_config_dword(dev_priv->bridge_dev, reg,
1167 lower_32_bits(rman_get_start(dev_priv->mch_res)));
1168 return 0;
1169 }
1170
1171 /* Setup MCHBAR if possible, return true if we should disable it again */
1172 static void
1173 intel_setup_mchbar(struct drm_device *dev)
1174 {
1175 struct drm_i915_private *dev_priv = dev->dev_private;
1176 int mchbar_reg = INTEL_INFO(dev)->gen >= 4 ? MCHBAR_I965 : MCHBAR_I915;
1177 u32 temp;
1178 bool enabled;
1179
1180 if (IS_VALLEYVIEW(dev))
1181 return;
1182
1183 dev_priv->mchbar_need_disable = false;
1184
1185 if (IS_I915G(dev) || IS_I915GM(dev)) {
1186 pci_read_config_dword(dev_priv->bridge_dev, DEVEN_REG, &temp);
1187 enabled = !!(temp & DEVEN_MCHBAR_EN);
1188 } else {
1189 pci_read_config_dword(dev_priv->bridge_dev, mchbar_reg, &temp);
1190 enabled = temp & 1;
1191 }
1192
1193 /* If it's already enabled, don't have to do anything */
1194 if (enabled)
1195 return;
1196
1197 if (intel_alloc_mchbar_resource(dev))
1198 return;
1199
1200 dev_priv->mchbar_need_disable = true;
1201
1202 /* Space is allocated or reserved, so enable it. */
1203 if (IS_I915G(dev) || IS_I915GM(dev)) {
1204 pci_write_config_dword(dev_priv->bridge_dev, DEVEN_REG,
1205 temp | DEVEN_MCHBAR_EN);
1206 } else {
1207 pci_read_config_dword(dev_priv->bridge_dev, mchbar_reg, &temp);
1208 pci_write_config_dword(dev_priv->bridge_dev, mchbar_reg, temp | 1);
1209 }
1210 }
1211
1212 static void
1213 intel_teardown_mchbar(struct drm_device *dev)
1214 {
1215 struct drm_i915_private *dev_priv = dev->dev_private;
1216 int mchbar_reg = INTEL_INFO(dev)->gen >= 4 ? MCHBAR_I965 : MCHBAR_I915;
1217 device_t vga;
1218 u32 temp;
1219
1220 if (dev_priv->mchbar_need_disable) {
1221 if (IS_I915G(dev) || IS_I915GM(dev)) {
1222 pci_read_config_dword(dev_priv->bridge_dev, DEVEN_REG, &temp);
1223 temp &= ~DEVEN_MCHBAR_EN;
1224 pci_write_config_dword(dev_priv->bridge_dev, DEVEN_REG, temp);
1225 } else {
1226 pci_read_config_dword(dev_priv->bridge_dev, mchbar_reg, &temp);
1227 temp &= ~1;
1228 pci_write_config_dword(dev_priv->bridge_dev, mchbar_reg, temp);
1229 }
1230 }
1231
1232 if (dev_priv->mch_res != NULL) {
1233 vga = device_get_parent(dev->dev);
1234 BUS_DEACTIVATE_RESOURCE(device_get_parent(vga), dev->dev,
1235 SYS_RES_MEMORY, dev_priv->mch_res_rid, dev_priv->mch_res);
1236 BUS_RELEASE_RESOURCE(device_get_parent(vga), dev->dev,
1237 SYS_RES_MEMORY, dev_priv->mch_res_rid, dev_priv->mch_res);
1238 dev_priv->mch_res = NULL;
1239 }
1240 }
1241
1242 #if 0
1243 /* true = enable decode, false = disable decoder */
1244 static unsigned int i915_vga_set_decode(void *cookie, bool state)
1245 {
1246 struct drm_device *dev = cookie;
1247
1248 intel_modeset_vga_set_state(dev, state);
1249 if (state)
1250 return VGA_RSRC_LEGACY_IO | VGA_RSRC_LEGACY_MEM |
1251 VGA_RSRC_NORMAL_IO | VGA_RSRC_NORMAL_MEM;
1252 else
1253 return VGA_RSRC_NORMAL_IO | VGA_RSRC_NORMAL_MEM;
1254 }
1255
1256 static void i915_switcheroo_set_state(struct pci_dev *pdev, enum vga_switcheroo_state state)
1257 {
1258 struct drm_device *dev = pci_get_drvdata(pdev);
1259 pm_message_t pmm = { .event = PM_EVENT_SUSPEND };
1260 if (state == VGA_SWITCHEROO_ON) {
1261 pr_info("switched on\n");
1262 dev->switch_power_state = DRM_SWITCH_POWER_CHANGING;
1263 /* i915 resume handler doesn't set to D0 */
1264 pci_set_power_state(dev->pdev, PCI_D0);
1265 i915_resume(dev);
1266 dev->switch_power_state = DRM_SWITCH_POWER_ON;
1267 } else {
1268 pr_err("switched off\n");
1269 dev->switch_power_state = DRM_SWITCH_POWER_CHANGING;
1270 i915_suspend(dev, pmm);
1271 dev->switch_power_state = DRM_SWITCH_POWER_OFF;
1272 }
1273 }
1274
1275 static bool i915_switcheroo_can_switch(struct pci_dev *pdev)
1276 {
1277 struct drm_device *dev = pci_get_drvdata(pdev);
1278
1279 /*
1280 * FIXME: open_count is protected by drm_global_mutex but that would lead to
1281 * locking inversion with the driver load path. And the access here is
1282 * completely racy anyway. So don't bother with locking for now.
1283 */
1284 return dev->open_count == 0;
1285 }
1286
1287 static const struct vga_switcheroo_client_ops i915_switcheroo_ops = {
1288 .set_gpu_state = i915_switcheroo_set_state,
1289 .reprobe = NULL,
1290 .can_switch = i915_switcheroo_can_switch,
1291 };
1292 #endif
1293
1294 static int i915_load_modeset_init(struct drm_device *dev)
1295 {
1296 struct drm_i915_private *dev_priv = dev->dev_private;
1297 int ret;
1298
1299 ret = intel_parse_bios(dev);
1300 if (ret)
1301 DRM_INFO("failed to find VBIOS tables\n");
1302
1303 #if 0
1304 /* If we have > 1 VGA cards, then we need to arbitrate access
1305 * to the common VGA resources.
1306 *
1307 * If we are a secondary display controller (!PCI_DISPLAY_CLASS_VGA),
1308 * then we do not take part in VGA arbitration and the
1309 * vga_client_register() fails with -ENODEV.
1310 */
1311 ret = vga_client_register(dev->pdev, dev, NULL, i915_vga_set_decode);
1312 if (ret && ret != -ENODEV)
1313 goto out;
1314
1315 intel_register_dsm_handler();
1316
1317 ret = vga_switcheroo_register_client(dev->pdev, &i915_switcheroo_ops, false);
1318 if (ret)
1319 goto cleanup_vga_client;
1320
1321 /* Initialise stolen first so that we may reserve preallocated
1322 * objects for the BIOS to KMS transition.
1323 */
1324 ret = i915_gem_init_stolen(dev);
1325 if (ret)
1326 goto cleanup_vga_switcheroo;
1327 #endif
1328
1329 intel_power_domains_init_hw(dev_priv);
1330
1331 ret = drm_irq_install(dev, dev->irq);
1332 if (ret)
1333 goto cleanup_gem_stolen;
1334
1335 /* Important: The output setup functions called by modeset_init need
1336 * working irqs for e.g. gmbus and dp aux transfers. */
1337 intel_modeset_init(dev);
1338
1339 ret = i915_gem_init(dev);
1340 if (ret)
1341 goto cleanup_irq;
1342
1343 #if 0
1344 INIT_WORK(&dev_priv->console_resume_work, intel_console_resume);
1345 #endif
1346
1347 intel_modeset_gem_init(dev);
1348
1349 /* Always safe in the mode setting case. */
1350 /* FIXME: do pre/post-mode set stuff in core KMS code */
1351 dev->vblank_disable_allowed = 1;
1352 if (INTEL_INFO(dev)->num_pipes == 0) {
1353 return 0;
1354 }
1355
1356 ret = intel_fbdev_init(dev);
1357 if (ret)
1358 goto cleanup_gem;
1359
1360 /* Only enable hotplug handling once the fbdev is fully set up. */
1361 intel_hpd_init(dev);
1362
1363 /*
1364 * Some ports require correctly set-up hpd registers for detection to
1365 * work properly (leading to ghost connected connector status), e.g. VGA
1366 * on gm45. Hence we can only set up the initial fbdev config after hpd
1367 * irqs are fully enabled. Now we should scan for the initial config
1368 * only once hotplug handling is enabled, but due to screwed-up locking
1369 * around kms/fbdev init we can't protect the fdbev initial config
1370 * scanning against hotplug events. Hence do this first and ignore the
1371 * tiny window where we will loose hotplug notifactions.
1372 */
1373 intel_fbdev_initial_config(dev);
1374
1375 /* Only enable hotplug handling once the fbdev is fully set up. */
1376 dev_priv->enable_hotplug_processing = true;
1377
1378 drm_kms_helper_poll_init(dev);
1379
1380 return 0;
1381
1382 cleanup_gem:
1383 mutex_lock(&dev->struct_mutex);
1384 i915_gem_cleanup_ringbuffer(dev);
1385 i915_gem_context_fini(dev);
1386 mutex_unlock(&dev->struct_mutex);
1387 WARN_ON(dev_priv->mm.aliasing_ppgtt);
1388 cleanup_irq:
1389 drm_irq_uninstall(dev);
1390 cleanup_gem_stolen:
1391 #if 0
1392 i915_gem_cleanup_stolen(dev);
1393 cleanup_vga_switcheroo:
1394 vga_switcheroo_unregister_client(dev->pdev);
1395 cleanup_vga_client:
1396 vga_client_register(dev->pdev, NULL, NULL, NULL);
1397 out:
1398 #endif
1399 return ret;
1400 }
1401
1402 #if 0
1403 int i915_master_create(struct drm_device *dev, struct drm_master *master)
1404 {
1405 struct drm_i915_master_private *master_priv;
1406
1407 master_priv = kzalloc(sizeof(*master_priv), GFP_KERNEL);
1408 if (!master_priv)
1409 return -ENOMEM;
1410
1411 master->driver_priv = master_priv;
1412 return 0;
1413 }
1414
1415 void i915_master_destroy(struct drm_device *dev, struct drm_master *master)
1416 {
1417 struct drm_i915_master_private *master_priv = master->driver_priv;
1418
1419 if (!master_priv)
1420 return;
1421
1422 kfree(master_priv);
1423
1424 master->driver_priv = NULL;
1425 }
1426 #endif
1427
1428 #if IS_ENABLED(CONFIG_FB)
1429 static void i915_kick_out_firmware_fb(struct drm_i915_private *dev_priv)
1430 {
1431 struct apertures_struct *ap;
1432 struct pci_dev *pdev = dev_priv->dev->pdev;
1433 bool primary;
1434
1435 ap = alloc_apertures(1);
1436 if (!ap)
1437 return;
1438
1439 ap->ranges[0].base = dev_priv->gtt.mappable_base;
1440 ap->ranges[0].size = dev_priv->gtt.mappable_end;
1441
1442 primary =
1443 pdev->resource[PCI_ROM_RESOURCE].flags & IORESOURCE_ROM_SHADOW;
1444
1445 remove_conflicting_framebuffers(ap, "inteldrmfb", primary);
1446
1447 kfree(ap);
1448 }
1449 #else
1450 static void i915_kick_out_firmware_fb(struct drm_i915_private *dev_priv)
1451 {
1452 }
1453 #endif
1454
1455 #if !defined(CONFIG_VGA_CONSOLE)
1456 static int i915_kick_out_vgacon(struct drm_i915_private *dev_priv)
1457 {
1458 return 0;
1459 }
1460 #elif !defined(CONFIG_DUMMY_CONSOLE)
1461 static int i915_kick_out_vgacon(struct drm_i915_private *dev_priv)
1462 {
1463 return -ENODEV;
1464 }
1465 #else
1466 static int i915_kick_out_vgacon(struct drm_i915_private *dev_priv)
1467 {
1468 int ret = 0;
1469
1470 DRM_INFO("Replacing VGA console driver\n");
1471
1472 console_lock();
1473 if (con_is_bound(&vga_con))
1474 ret = do_take_over_console(&dummy_con, 0, MAX_NR_CONSOLES - 1, 1);
1475 if (ret == 0) {
1476 ret = do_unregister_con_driver(&vga_con);
1477
1478 /* Ignore "already unregistered". */
1479 if (ret == -ENODEV)
1480 ret = 0;
1481 }
1482 console_unlock();
1483
1484 return ret;
1485 }
1486 #endif
1487
1488 static void i915_dump_device_info(struct drm_i915_private *dev_priv)
1489 {
1490 #if 0
1491 const struct intel_device_info *info = &dev_priv->info;
1492
1493 #define PRINT_S(name) "%s"
1494 #define SEP_EMPTY
1495 #define PRINT_FLAG(name) info->name ? #name "," : ""
1496 #define SEP_COMMA ,
1497 DRM_DEBUG_DRIVER("i915 device info: gen=%i, pciid=0x%04x flags="
1498 DEV_INFO_FOR_EACH_FLAG(PRINT_S, SEP_EMPTY),
1499 info->gen,
1500 dev_priv->dev->pdev->device,
1501 DEV_INFO_FOR_EACH_FLAG(PRINT_FLAG, SEP_COMMA));
1502 #undef PRINT_S
1503 #undef SEP_EMPTY
1504 #undef PRINT_FLAG
1505 #undef SEP_COMMA
1506 #endif
1507 }
1508
1509 /*
1510 * Determine various intel_device_info fields at runtime.
1511 *
1512 * Use it when either:
1513 * - it's judged too laborious to fill n static structures with the limit
1514 * when a simple if statement does the job,
1515 * - run-time checks (eg read fuse/strap registers) are needed.
1516 *
1517 * This function needs to be called:
1518 * - after the MMIO has been setup as we are reading registers,
1519 * - after the PCH has been detected,
1520 * - before the first usage of the fields it can tweak.
1521 */
1522 static void intel_device_info_runtime_init(struct drm_device *dev)
1523 {
1524 struct drm_i915_private *dev_priv = dev->dev_private;
1525 struct intel_device_info *info;
1526 enum i915_pipe pipe;
1527
1528 info = (struct intel_device_info *)&dev_priv->info;
1529
1530 if (IS_VALLEYVIEW(dev))
1531 for_each_pipe(pipe)
1532 info->num_sprites[pipe] = 2;
1533 else
1534 for_each_pipe(pipe)
1535 info->num_sprites[pipe] = 1;
1536
1537 if (i915.disable_display) {
1538 DRM_INFO("Display disabled (module parameter)\n");
1539 info->num_pipes = 0;
1540 } else if (info->num_pipes > 0 &&
1541 (INTEL_INFO(dev)->gen == 7 || INTEL_INFO(dev)->gen == 8) &&
1542 !IS_VALLEYVIEW(dev)) {
1543 u32 fuse_strap = I915_READ(FUSE_STRAP);
1544 u32 sfuse_strap = I915_READ(SFUSE_STRAP);
1545
1546 /*
1547 * SFUSE_STRAP is supposed to have a bit signalling the display
1548 * is fused off. Unfortunately it seems that, at least in
1549 * certain cases, fused off display means that PCH display
1550 * reads don't land anywhere. In that case, we read 0s.
1551 *
1552 * On CPT/PPT, we can detect this case as SFUSE_STRAP_FUSE_LOCK
1553 * should be set when taking over after the firmware.
1554 */
1555 if (fuse_strap & ILK_INTERNAL_DISPLAY_DISABLE ||
1556 sfuse_strap & SFUSE_STRAP_DISPLAY_DISABLED ||
1557 (dev_priv->pch_type == PCH_CPT &&
1558 !(sfuse_strap & SFUSE_STRAP_FUSE_LOCK))) {
1559 DRM_INFO("Display fused off, disabling\n");
1560 info->num_pipes = 0;
1561 }
1562 }
1563 }
1564
1565 /**
1566 * i915_driver_load - setup chip and create an initial config
1567 * @dev: DRM device
1568 * @flags: startup flags
1569 *
1570 * The driver load routine has to do several things:
1571 * - drive output discovery via intel_modeset_init()
1572 * - initialize the memory manager
1573 * - allocate initial config memory
1574 * - setup the DRM framebuffer with the allocated memory
1575 */
1576 int i915_driver_load(struct drm_device *dev, unsigned long flags)
1577 {
1578 struct drm_i915_private *dev_priv = dev->dev_private;
1579 struct intel_device_info *info, *device_info;
1580 unsigned long base, size;
1581 int ret = 0, mmio_bar, mmio_size;
1582 uint32_t aperture_size;
1583 static struct pci_dev i915_pdev;
1584
1585 /* XXX: dev->pci_device not present in Linux drm */
1586 info = i915_get_device_id(dev->pci_device);
1587
1588 /* XXX: struct pci_dev */
1589 i915_pdev.dev = dev->dev;
1590 dev->pdev = &i915_pdev;
1591 dev->pdev->device = dev->pci_device;
1592
1593 /* Refuse to load on gen6+ without kms enabled. */
1594 if (info->gen >= 6 && !drm_core_check_feature(dev, DRIVER_MODESET)) {
1595 DRM_INFO("Your hardware requires kernel modesetting (KMS)\n");
1596 DRM_INFO("See CONFIG_DRM_I915_KMS, nomodeset, and i915.modeset parameters\n");
1597 return -ENODEV;
1598 }
1599
1600 dev_priv = kzalloc(sizeof(*dev_priv), GFP_KERNEL);
1601 if (dev_priv == NULL)
1602 return -ENOMEM;
1603
1604 dev->dev_private = (void *)dev_priv;
1605 dev_priv->dev = dev;
1606
1607 /* copy initial configuration to dev_priv->info */
1608 device_info = (struct intel_device_info *)&dev_priv->info;
1609 *device_info = *info;
1610
1611 lockinit(&dev_priv->irq_lock, "userirq", 0, LK_CANRECURSE);
1612 lockinit(&dev_priv->gpu_error.lock, "915err", 0, LK_CANRECURSE);
1613 spin_init(&dev_priv->backlight_lock, "i915bl");
1614 lockinit(&dev_priv->uncore.lock, "915gt", 0, LK_CANRECURSE);
1615 spin_init(&dev_priv->mm.object_stat_lock, "i915osl");
1616 lockinit(&dev_priv->dpio_lock, "i915dpio", 0, LK_CANRECURSE);
1617 lockinit(&dev_priv->modeset_restore_lock, "i915mrl", 0, LK_CANRECURSE);
1618
1619 intel_pm_setup(dev);
1620
1621 intel_display_crc_init(dev);
1622
1623 i915_dump_device_info(dev_priv);
1624
1625 /* Not all pre-production machines fall into this category, only the
1626 * very first ones. Almost everything should work, except for maybe
1627 * suspend/resume. And we don't implement workarounds that affect only
1628 * pre-production machines. */
1629 if (IS_HSW_EARLY_SDV(dev))
1630 DRM_INFO("This is an early pre-production Haswell machine. "
1631 "It may not be fully functional.\n");
1632
1633 if (i915_get_bridge_dev(dev)) {
1634 ret = -EIO;
1635 goto free_priv;
1636 }
1637
1638 mmio_bar = IS_GEN2(dev) ? 1 : 0;
1639 /* Before gen4, the registers and the GTT are behind different BARs.
1640 * However, from gen4 onwards, the registers and the GTT are shared
1641 * in the same BAR, so we want to restrict this ioremap from
1642 * clobbering the GTT which we want ioremap_wc instead. Fortunately,
1643 * the register BAR remains the same size for all the earlier
1644 * generations up to Ironlake.
1645 */
1646 if (info->gen < 5)
1647 mmio_size = 512*1024;
1648 else
1649 mmio_size = 2*1024*1024;
1650
1651 #if 0
1652 dev_priv->regs = pci_iomap(dev->pdev, mmio_bar, mmio_size);
1653 if (!dev_priv->regs) {
1654 DRM_ERROR("failed to map registers\n");
1655 ret = -EIO;
1656 goto put_bridge;
1657 }
1658 #else
1659 base = drm_get_resource_start(dev, mmio_bar);
1660 size = drm_get_resource_len(dev, mmio_bar);
1661
1662 ret = drm_addmap(dev, base, size, _DRM_REGISTERS,
1663 _DRM_KERNEL | _DRM_DRIVER, &dev_priv->mmio_map);
1664 #endif
1665
1666 /* This must be called before any calls to HAS_PCH_* */
1667 intel_detect_pch(dev);
1668
1669 intel_uncore_init(dev);
1670
1671 ret = i915_gem_gtt_init(dev);
1672 if (ret)
1673 goto out_regs;
1674
1675 if (drm_core_check_feature(dev, DRIVER_MODESET)) {
1676 ret = i915_kick_out_vgacon(dev_priv);
1677 if (ret) {
1678 DRM_ERROR("failed to remove conflicting VGA console\n");
1679 goto out_gtt;
1680 }
1681
1682 i915_kick_out_firmware_fb(dev_priv);
1683 }
1684
1685 #if 0
1686 pci_set_master(dev->pdev);
1687
1688 /* overlay on gen2 is broken and can't address above 1G */
1689 if (IS_GEN2(dev))
1690 dma_set_coherent_mask(&dev->pdev->dev, DMA_BIT_MASK(30));
1691
1692 /* 965GM sometimes incorrectly writes to hardware status page (HWS)
1693 * using 32bit addressing, overwriting memory if HWS is located
1694 * above 4GB.
1695 *
1696 * The documentation also mentions an issue with undefined
1697 * behaviour if any general state is accessed within a page above 4GB,
1698 * which also needs to be handled carefully.
1699 */
1700 if (IS_BROADWATER(dev) || IS_CRESTLINE(dev))
1701 dma_set_coherent_mask(&dev->pdev->dev, DMA_BIT_MASK(32));
1702 #endif
1703
1704 aperture_size = dev_priv->gtt.mappable_end;
1705
1706 dev_priv->gtt.mappable =
1707 io_mapping_create_wc(dev_priv->gtt.mappable_base,
1708 aperture_size);
1709 if (dev_priv->gtt.mappable == NULL) {
1710 ret = -EIO;
1711 goto out_gtt;
1712 }
1713
1714 dev_priv->gtt.mtrr = arch_phys_wc_add(dev_priv->gtt.mappable_base,
1715 aperture_size);
1716
1717 /* The i915 workqueue is primarily used for batched retirement of
1718 * requests (and thus managing bo) once the task has been completed
1719 * by the GPU. i915_gem_retire_requests() is called directly when we
1720 * need high-priority retirement, such as waiting for an explicit
1721 * bo.
1722 *
1723 * It is also used for periodic low-priority events, such as
1724 * idle-timers and recording error state.
1725 *
1726 * All tasks on the workqueue are expected to acquire the dev mutex
1727 * so there is no point in running more than one instance of the
1728 * workqueue at any time. Use an ordered one.
1729 */
1730 dev_priv->wq = alloc_ordered_workqueue("i915", 0);
1731 if (dev_priv->wq == NULL) {
1732 DRM_ERROR("Failed to create our workqueue.\n");
1733 ret = -ENOMEM;
1734 goto out_mtrrfree;
1735 }
1736
1737 intel_irq_init(dev);
1738 intel_uncore_sanitize(dev);
1739
1740 /* Try to make sure MCHBAR is enabled before poking at it */
1741 intel_setup_mchbar(dev);
1742 intel_setup_gmbus(dev);
1743 intel_opregion_setup(dev);
1744
1745 intel_setup_bios(dev);
1746
1747 i915_gem_load(dev);
1748
1749 /* On the 945G/GM, the chipset reports the MSI capability on the
1750 * integrated graphics even though the support isn't actually there
1751 * according to the published specs. It doesn't appear to function
1752 * correctly in testing on 945G.
1753 * This may be a side effect of MSI having been made available for PEG
1754 * and the registers being closely associated.
1755 *
1756 * According to chipset errata, on the 965GM, MSI interrupts may
1757 * be lost or delayed, but we use them anyways to avoid
1758 * stuck interrupts on some machines.
1759 */
1760 #if 0
1761 if (!IS_I945G(dev) && !IS_I945GM(dev))
1762 pci_enable_msi(dev->pdev);
1763 #endif
1764
1765 intel_device_info_runtime_init(dev);
1766
1767 if (INTEL_INFO(dev)->num_pipes) {
1768 ret = drm_vblank_init(dev, INTEL_INFO(dev)->num_pipes);
1769 if (ret)
1770 goto out_gem_unload;
1771 }
1772
1773 intel_power_domains_init(dev_priv);
1774
1775 if (drm_core_check_feature(dev, DRIVER_MODESET)) {
1776 ret = i915_load_modeset_init(dev);
1777 if (ret < 0) {
1778 DRM_ERROR("failed to init modeset\n");
1779 goto out_power_well;
1780 }
1781 } else {
1782 /* Start out suspended in ums mode. */
1783 dev_priv->ums.mm_suspended = 1;
1784 }
1785
1786 #if 0
1787 i915_setup_sysfs(dev);
1788 #endif
1789
1790 if (INTEL_INFO(dev)->num_pipes) {
1791 /* Must be done after probing outputs */
1792 intel_opregion_init(dev);
1793 #if 0
1794 acpi_video_register();
1795 #endif
1796 }
1797
1798 if (IS_GEN5(dev))
1799 intel_gpu_ips_init(dev_priv);
1800
1801 intel_init_runtime_pm(dev_priv);
1802
1803 return 0;
1804
1805 out_power_well:
1806 intel_power_domains_remove(dev_priv);
1807 drm_vblank_cleanup(dev);
1808 out_gem_unload:
1809
1810 intel_teardown_gmbus(dev);
1811 intel_teardown_mchbar(dev);
1812 pm_qos_remove_request(&dev_priv->pm_qos);
1813 destroy_workqueue(dev_priv->wq);
1814 out_mtrrfree:
1815 arch_phys_wc_del(dev_priv->gtt.mtrr);
1816 #if 0
1817 io_mapping_free(dev_priv->gtt.mappable);
1818 #endif
1819 out_gtt:
1820 dev_priv->gtt.base.cleanup(&dev_priv->gtt.base);
1821 out_regs:
1822 intel_uncore_fini(dev);
1823 free_priv:
1824 kfree(dev_priv);
1825 return ret;
1826 }
1827
1828 int i915_driver_unload(struct drm_device *dev)
1829 {
1830 struct drm_i915_private *dev_priv = dev->dev_private;
1831 int ret;
1832
1833 ret = i915_gem_suspend(dev);
1834 if (ret) {
1835 DRM_ERROR("failed to idle hardware: %d\n", ret);
1836 return ret;
1837 }
1838
1839 intel_fini_runtime_pm(dev_priv);
1840
1841 intel_gpu_ips_teardown();
1842
1843 /* The i915.ko module is still not prepared to be loaded when
1844 * the power well is not enabled, so just enable it in case
1845 * we're going to unload/reload. */
1846 intel_display_set_init_power(dev_priv, true);
1847 intel_power_domains_remove(dev_priv);
1848
1849 #if 0
1850 i915_teardown_sysfs(dev);
1851
1852 WARN_ON(unregister_oom_notifier(&dev_priv->mm.oom_notifier));
1853 unregister_shrinker(&dev_priv->mm.shrinker);
1854
1855 io_mapping_free(dev_priv->gtt.mappable);
1856 #endif
1857 arch_phys_wc_del(dev_priv->gtt.mtrr);
1858
1859 #if 0
1860 acpi_video_unregister();
1861 #endif
1862
1863 if (drm_core_check_feature(dev, DRIVER_MODESET)) {
1864 intel_fbdev_fini(dev);
1865 intel_modeset_cleanup(dev);
1866 #if 0
1867 cancel_work_sync(&dev_priv->console_resume_work);
1868 #endif
1869
1870 /*
1871 * free the memory space allocated for the child device
1872 * config parsed from VBT
1873 */
1874 if (dev_priv->vbt.child_dev && dev_priv->vbt.child_dev_num) {
1875 kfree(dev_priv->vbt.child_dev);
1876 dev_priv->vbt.child_dev = NULL;
1877 dev_priv->vbt.child_dev_num = 0;
1878 }
1879
1880 }
1881
1882 /* Free error state after interrupts are fully disabled. */
1883 del_timer_sync(&dev_priv->gpu_error.hangcheck_timer);
1884 cancel_work_sync(&dev_priv->gpu_error.work);
1885 #if 0
1886 i915_destroy_error_state(dev);
1887 #endif
1888
1889 intel_opregion_fini(dev);
1890
1891 if (drm_core_check_feature(dev, DRIVER_MODESET)) {
1892 /* Flush any outstanding unpin_work. */
1893 flush_workqueue(dev_priv->wq);
1894
1895 mutex_lock(&dev->struct_mutex);
1896 i915_gem_cleanup_ringbuffer(dev);
1897 i915_gem_context_fini(dev);
1898 WARN_ON(dev_priv->mm.aliasing_ppgtt);
1899 mutex_unlock(&dev->struct_mutex);
1900 #if 0
1901 i915_gem_cleanup_stolen(dev);
1902 #endif
1903
1904 if (!I915_NEED_GFX_HWS(dev))
1905 i915_free_hws(dev);
1906 }
1907
1908 WARN_ON(!list_empty(&dev_priv->vm_list));
1909
1910 drm_vblank_cleanup(dev);
1911
1912 intel_teardown_gmbus(dev);
1913 intel_teardown_mchbar(dev);
1914
1915 bus_generic_detach(dev->dev);
1916 drm_rmmap(dev, dev_priv->mmio_map);
1917
1918 destroy_workqueue(dev_priv->wq);
1919 pm_qos_remove_request(&dev_priv->pm_qos);
1920
1921 dev_priv->gtt.base.cleanup(&dev_priv->gtt.base);
1922
1923 intel_uncore_fini(dev);
1924 #if 0
1925 if (dev_priv->regs != NULL)
1926 pci_iounmap(dev->pdev, dev_priv->regs);
1927 #endif
1928
1929 pci_dev_put(dev_priv->bridge_dev);
1930 kfree(dev_priv);
1931
1932 return 0;
1933 }
1934
1935 int i915_driver_open(struct drm_device *dev, struct drm_file *file)
1936 {
1937 int ret;
1938
1939 ret = i915_gem_open(dev, file);
1940 if (ret)
1941 return ret;
1942
1943 return 0;
1944 }
1945
1946 /**
1947 * i915_driver_lastclose - clean up after all DRM clients have exited
1948 * @dev: DRM device
1949 *
1950 * Take care of cleaning up after all DRM clients have exited. In the
1951 * mode setting case, we want to restore the kernel's initial mode (just
1952 * in case the last client left us in a bad state).
1953 *
1954 * Additionally, in the non-mode setting case, we'll tear down the GTT
1955 * and DMA structures, since the kernel won't be using them, and clea
1956 * up any GEM state.
1957 */
1958 void i915_driver_lastclose(struct drm_device * dev)
1959 {
1960 struct drm_i915_private *dev_priv = dev->dev_private;
1961
1962 /* On gen6+ we refuse to init without kms enabled, but then the drm core
1963 * goes right around and calls lastclose. Check for this and don't clean
1964 * up anything. */
1965 if (!dev_priv)
1966 return;
1967
1968 if (drm_core_check_feature(dev, DRIVER_MODESET)) {
1969 #if 0
1970 intel_fbdev_restore_mode(dev);
1971 vga_switcheroo_process_delayed_switch();
1972 #endif
1973 return;
1974 }
1975
1976 i915_gem_lastclose(dev);
1977
1978 i915_dma_cleanup(dev);
1979 }
1980
1981 void i915_driver_preclose(struct drm_device * dev, struct drm_file *file_priv)
1982 {
1983 mutex_lock(&dev->struct_mutex);
1984 i915_gem_context_close(dev, file_priv);
1985 i915_gem_release(dev, file_priv);
1986 mutex_unlock(&dev->struct_mutex);
1987 }
1988
1989 void i915_driver_postclose(struct drm_device *dev, struct drm_file *file)
1990 {
1991 struct drm_i915_file_private *file_priv = file->driver_priv;
1992
1993 if (file_priv && file_priv->bsd_ring)
1994 file_priv->bsd_ring = NULL;
1995 kfree(file_priv);
1996 }
1997
1998 struct drm_ioctl_desc i915_ioctls[] = {
1999 DRM_IOCTL_DEF_DRV(I915_INIT, i915_dma_init, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
2000 DRM_IOCTL_DEF_DRV(I915_FLUSH, i915_flush_ioctl, DRM_AUTH),
2001 DRM_IOCTL_DEF_DRV(I915_FLIP, i915_flip_bufs, DRM_AUTH),
2002 DRM_IOCTL_DEF_DRV(I915_BATCHBUFFER, i915_batchbuffer, DRM_AUTH),
2003 DRM_IOCTL_DEF_DRV(I915_IRQ_EMIT, i915_irq_emit, DRM_AUTH),
2004 DRM_IOCTL_DEF_DRV(I915_IRQ_WAIT, i915_irq_wait, DRM_AUTH),
2005 DRM_IOCTL_DEF_DRV(I915_GETPARAM, i915_getparam, DRM_AUTH|DRM_RENDER_ALLOW),
2006 DRM_IOCTL_DEF_DRV(I915_SETPARAM, i915_setparam, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
2007 DRM_IOCTL_DEF_DRV(I915_ALLOC, drm_noop, DRM_AUTH),
2008 DRM_IOCTL_DEF_DRV(I915_FREE, drm_noop, DRM_AUTH),
2009 DRM_IOCTL_DEF_DRV(I915_INIT_HEAP, drm_noop, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
2010 DRM_IOCTL_DEF_DRV(I915_CMDBUFFER, i915_cmdbuffer, DRM_AUTH),
2011 DRM_IOCTL_DEF_DRV(I915_DESTROY_HEAP, drm_noop, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
2012 DRM_IOCTL_DEF_DRV(I915_SET_VBLANK_PIPE, drm_noop, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
2013 DRM_IOCTL_DEF_DRV(I915_GET_VBLANK_PIPE, i915_vblank_pipe_get, DRM_AUTH),
2014 DRM_IOCTL_DEF_DRV(I915_VBLANK_SWAP, i915_vblank_swap, DRM_AUTH),
2015 DRM_IOCTL_DEF_DRV(I915_HWS_ADDR, i915_set_status_page, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
2016 DRM_IOCTL_DEF_DRV(I915_GEM_INIT, i915_gem_init_ioctl, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY|DRM_UNLOCKED),
2017 DRM_IOCTL_DEF_DRV(I915_GEM_EXECBUFFER, i915_gem_execbuffer, DRM_AUTH|DRM_UNLOCKED),
2018 DRM_IOCTL_DEF_DRV(I915_GEM_EXECBUFFER2, i915_gem_execbuffer2, DRM_AUTH|DRM_UNLOCKED),
2019 DRM_IOCTL_DEF_DRV(I915_GEM_PIN, i915_gem_pin_ioctl, DRM_AUTH|DRM_ROOT_ONLY|DRM_UNLOCKED),
2020 DRM_IOCTL_DEF_DRV(I915_GEM_UNPIN, i915_gem_unpin_ioctl, DRM_AUTH|DRM_ROOT_ONLY|DRM_UNLOCKED),
2021 DRM_IOCTL_DEF_DRV(I915_GEM_BUSY, i915_gem_busy_ioctl, DRM_AUTH|DRM_UNLOCKED),
2022 DRM_IOCTL_DEF_DRV(I915_GEM_SET_CACHING, i915_gem_set_caching_ioctl, DRM_UNLOCKED),
2023 DRM_IOCTL_DEF_DRV(I915_GEM_GET_CACHING, i915_gem_get_caching_ioctl, DRM_UNLOCKED),
2024 DRM_IOCTL_DEF_DRV(I915_GEM_THROTTLE, i915_gem_throttle_ioctl, DRM_AUTH|DRM_UNLOCKED),
2025 DRM_IOCTL_DEF_DRV(I915_GEM_ENTERVT, i915_gem_entervt_ioctl, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY|DRM_UNLOCKED),
2026 DRM_IOCTL_DEF_DRV(I915_GEM_LEAVEVT, i915_gem_leavevt_ioctl, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY|DRM_UNLOCKED),
2027 DRM_IOCTL_DEF_DRV(I915_GEM_CREATE, i915_gem_create_ioctl, DRM_UNLOCKED),
2028 DRM_IOCTL_DEF_DRV(I915_GEM_PREAD, i915_gem_pread_ioctl, DRM_UNLOCKED),
2029 DRM_IOCTL_DEF_DRV(I915_GEM_PWRITE, i915_gem_pwrite_ioctl, DRM_UNLOCKED),
2030 DRM_IOCTL_DEF_DRV(I915_GEM_MMAP, i915_gem_mmap_ioctl, DRM_UNLOCKED),
2031 DRM_IOCTL_DEF_DRV(I915_GEM_MMAP_GTT, i915_gem_mmap_gtt_ioctl, DRM_UNLOCKED),
2032 DRM_IOCTL_DEF_DRV(I915_GEM_SET_DOMAIN, i915_gem_set_domain_ioctl, DRM_UNLOCKED),
2033 DRM_IOCTL_DEF_DRV(I915_GEM_SW_FINISH, i915_gem_sw_finish_ioctl, DRM_UNLOCKED),
2034 DRM_IOCTL_DEF_DRV(I915_GEM_SET_TILING, i915_gem_set_tiling, DRM_UNLOCKED),
2035 DRM_IOCTL_DEF_DRV(I915_GEM_GET_TILING, i915_gem_get_tiling, DRM_UNLOCKED),
2036 DRM_IOCTL_DEF_DRV(I915_GEM_GET_APERTURE, i915_gem_get_aperture_ioctl, DRM_UNLOCKED),
2037 DRM_IOCTL_DEF_DRV(I915_GET_PIPE_FROM_CRTC_ID, intel_get_pipe_from_crtc_id, DRM_UNLOCKED),
2038 DRM_IOCTL_DEF_DRV(I915_GEM_MADVISE, i915_gem_madvise_ioctl, DRM_UNLOCKED),
2039 DRM_IOCTL_DEF_DRV(I915_OVERLAY_PUT_IMAGE, intel_overlay_put_image, DRM_MASTER|DRM_CONTROL_ALLOW|DRM_UNLOCKED),
2040 DRM_IOCTL_DEF_DRV(I915_OVERLAY_ATTRS, intel_overlay_attrs, DRM_MASTER|DRM_CONTROL_ALLOW|DRM_UNLOCKED),
2041 DRM_IOCTL_DEF_DRV(I915_SET_SPRITE_COLORKEY, intel_sprite_set_colorkey, DRM_MASTER|DRM_CONTROL_ALLOW|DRM_UNLOCKED),
2042 DRM_IOCTL_DEF_DRV(I915_GET_SPRITE_COLORKEY, intel_sprite_get_colorkey, DRM_MASTER|DRM_CONTROL_ALLOW|DRM_UNLOCKED),
2043 DRM_IOCTL_DEF_DRV(I915_GEM_WAIT, i915_gem_wait_ioctl, DRM_AUTH|DRM_UNLOCKED),
2044 DRM_IOCTL_DEF_DRV(I915_GEM_CONTEXT_CREATE, i915_gem_context_create_ioctl, DRM_UNLOCKED),
2045 DRM_IOCTL_DEF_DRV(I915_GEM_CONTEXT_DESTROY, i915_gem_context_destroy_ioctl, DRM_UNLOCKED),
2046 DRM_IOCTL_DEF_DRV(I915_REG_READ, i915_reg_read_ioctl, DRM_UNLOCKED),
2047 DRM_IOCTL_DEF_DRV(I915_GET_RESET_STATS, i915_get_reset_stats_ioctl, DRM_UNLOCKED|DRM_RENDER_ALLOW),
2048 #if 0
2049 DRM_IOCTL_DEF_DRV(I915_GEM_USERPTR, i915_gem_userptr_ioctl, DRM_UNLOCKED|DRM_RENDER_ALLOW),
2050 #endif
2051 };
2052
2053 int i915_max_ioctl = ARRAY_SIZE(i915_ioctls);
2054
2055 /*
2056 * This is really ugly: Because old userspace abused the linux agp interface to
2057 * manage the gtt, we need to claim that all intel devices are agp. For
2058 * otherwise the drm core refuses to initialize the agp support code.
2059 */
2060 int i915_driver_device_is_agp(struct drm_device * dev)
2061 {
2062 return 1;
2063 }
DragonFly BSD