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kernel: Move GPL'd kernel files to sys/gnu to have them all in one place.
[dragonfly.git] / sys / dev / sound / pci / maestro3.c
blob587af38b16417a52b2fe66e86494822468cad84e
1 /*-
2 * Copyright (c) 2001 Scott Long <scottl@freebsd.org>
3 * Copyright (c) 2001 Darrell Anderson <anderson@cs.duke.edu>
4 * All rights reserved.
5 *
6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions
8 * are met:
9 * 1. Redistributions of source code must retain the above copyright
10 * notice, this list of conditions and the following disclaimer.
11 * 2. Redistributions in binary form must reproduce the above copyright
12 * notice, this list of conditions and the following disclaimer in the
13 * documentation and/or other materials provided with the distribution.
14 *
15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
16 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
17 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
18 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
19 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
20 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
21 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
22 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
23 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
24 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
25 * SUCH DAMAGE.
26 *
27 * $FreeBSD: src/sys/dev/sound/pci/maestro3.c,v 1.28.2.2 2007/03/12 02:03:25 ariff Exp $
28 */
29
30 /*
31 * Maestro-3/Allegro FreeBSD pcm sound driver
32 *
33 * executive status summary:
34 * (+) /dev/dsp multiple concurrent play channels.
35 * (+) /dev/dsp config (speed, mono/stereo, 8/16 bit).
36 * (+) /dev/mixer sets left/right volumes.
37 * (+) /dev/dsp recording works. Tested successfully with the cdrom channel
38 * (+) apm suspend/resume works, and works properly!.
39 * (-) hardware volme controls don't work =-(
40 * (-) setblocksize() does nothing.
41 *
42 * The real credit goes to:
43 *
44 * Zach Brown for his Linux driver core and helpful technical comments.
45 * <zab@zabbo.net>, http://www.zabbo.net/maestro3
46 *
47 * Cameron Grant created the pcm framework used here nearly verbatim.
48 * <cg@freebsd.org>, http://people.freebsd.org/~cg/template.c
49 *
50 * Taku YAMAMOTO for his Maestro-1/2 FreeBSD driver and sanity reference.
51 * <taku@cent.saitama-u.ac.jp>
52 *
53 * ESS docs explained a few magic registers and numbers.
54 * http://virgo.caltech.edu/~dmoore/maestro3.pdf.gz
55 */
56
57 #include <dev/sound/pcm/sound.h>
58 #include <dev/sound/pcm/ac97.h>
59
60 #include <bus/pci/pcireg.h>
61 #include <bus/pci/pcivar.h>
62
63 #include <gnu/dev/sound/pci/maestro3_reg.h>
64 #include <gnu/dev/sound/pci/maestro3_dsp.h>
65
66 /* -------------------------------------------------------------------- */
67
68 enum {CHANGE=0, CALL=1, INTR=2, BORING=3, NONE=-1};
69 #ifndef M3_DEBUG_LEVEL
70 #define M3_DEBUG_LEVEL NONE
71 #endif
72 #define M3_DEBUG(level, _msg) {if ((level) <= M3_DEBUG_LEVEL) {kprintf _msg;}}
73
74 /* -------------------------------------------------------------------- */
75 enum {
76 ESS_ALLEGRO_1,
77 ESS_MAESTRO3
78 };
79
80 static struct m3_card_type {
81 u_int32_t pci_id; int which; int delay1; int delay2; char *name;
82 } m3_card_types[] = {
83 { 0x1988125d, ESS_ALLEGRO_1, 50, 800, "ESS Technology Allegro-1" },
84 { 0x1998125d, ESS_MAESTRO3, 20, 500, "ESS Technology Maestro3" },
85 { 0x199a125d, ESS_MAESTRO3, 20, 500, "ESS Technology Maestro3" },
86 { 0, 0, 0, 0, NULL }
87 };
88
89 #define M3_BUFSIZE_MIN 4096
90 #define M3_BUFSIZE_MAX 65536
91 #define M3_BUFSIZE_DEFAULT 4096
92 #define M3_PCHANS 4 /* create /dev/dsp0.[0-N] to use more than one */
93 #define M3_RCHANS 1
94 #define M3_MAXADDR ((1 << 27) - 1)
95
96 struct sc_info;
97
98 struct sc_pchinfo {
99 u_int32_t spd;
100 u_int32_t fmt;
101 struct snd_dbuf *buffer;
102 struct pcm_channel *channel;
103 struct sc_info *parent;
104 u_int32_t bufsize;
105 u_int32_t dac_data;
106 u_int32_t dac_idx;
107 u_int32_t active;
108 u_int32_t ptr;
109 u_int32_t prevptr;
110 };
111
112 struct sc_rchinfo {
113 u_int32_t spd;
114 u_int32_t fmt;
115 struct snd_dbuf *buffer;
116 struct pcm_channel *channel;
117 struct sc_info *parent;
118 u_int32_t bufsize;
119 u_int32_t adc_data;
120 u_int32_t adc_idx;
121 u_int32_t active;
122 u_int32_t ptr;
123 u_int32_t prevptr;
124 };
125
126 struct sc_info {
127 device_t dev;
128 u_int32_t type;
129 int which;
130 int delay1;
131 int delay2;
132
133 bus_space_tag_t st;
134 bus_space_handle_t sh;
135 bus_dma_tag_t parent_dmat;
136
137 struct resource *reg;
138 struct resource *irq;
139 int regtype;
140 int regid;
141 int irqid;
142 void *ih;
143
144 struct sc_pchinfo pch[M3_PCHANS];
145 struct sc_rchinfo rch[M3_RCHANS];
146 int pch_cnt;
147 int rch_cnt;
148 int pch_active_cnt;
149 unsigned int bufsz;
150 u_int16_t *savemem;
151
152 sndlock_t sc_lock;
153 };
154
155 #define M3_LOCK(_sc) snd_mtxlock((_sc)->sc_lock)
156 #define M3_UNLOCK(_sc) snd_mtxunlock((_sc)->sc_lock)
157 #define M3_LOCK_ASSERT(_sc) snd_mtxassert((_sc)->sc_lock)
158
159 /* -------------------------------------------------------------------- */
160
161 /* play channel interface */
162 static void *m3_pchan_init(kobj_t, void *, struct snd_dbuf *, struct pcm_channel *, int);
163 static int m3_pchan_free(kobj_t, void *);
164 static int m3_pchan_setformat(kobj_t, void *, u_int32_t);
165 static int m3_pchan_setspeed(kobj_t, void *, u_int32_t);
166 static int m3_pchan_setblocksize(kobj_t, void *, u_int32_t);
167 static int m3_pchan_trigger(kobj_t, void *, int);
168 static int m3_pchan_trigger_locked(kobj_t, void *, int);
169 static u_int32_t m3_pchan_getptr_internal(struct sc_pchinfo *);
170 static u_int32_t m3_pchan_getptr(kobj_t, void *);
171 static struct pcmchan_caps *m3_pchan_getcaps(kobj_t, void *);
172
173 /* record channel interface */
174 static void *m3_rchan_init(kobj_t, void *, struct snd_dbuf *, struct pcm_channel *, int);
175 static int m3_rchan_free(kobj_t, void *);
176 static int m3_rchan_setformat(kobj_t, void *, u_int32_t);
177 static int m3_rchan_setspeed(kobj_t, void *, u_int32_t);
178 static int m3_rchan_setblocksize(kobj_t, void *, u_int32_t);
179 static int m3_rchan_trigger(kobj_t, void *, int);
180 static int m3_rchan_trigger_locked(kobj_t, void *, int);
181 static u_int32_t m3_rchan_getptr_internal(struct sc_rchinfo *);
182 static u_int32_t m3_rchan_getptr(kobj_t, void *);
183 static struct pcmchan_caps *m3_rchan_getcaps(kobj_t, void *);
184
185 static int m3_chan_active(struct sc_info *);
186
187 /* talk to the codec - called from ac97.c */
188 static int m3_initcd(kobj_t, void *);
189 static int m3_rdcd(kobj_t, void *, int);
190 static int m3_wrcd(kobj_t, void *, int, u_int32_t);
191
192 /* stuff */
193 static void m3_intr(void *);
194 static int m3_power(struct sc_info *, int);
195 static int m3_init(struct sc_info *);
196 static int m3_uninit(struct sc_info *);
197 static u_int8_t m3_assp_halt(struct sc_info *);
198 static void m3_config(struct sc_info *);
199 static void m3_amp_enable(struct sc_info *);
200 static void m3_enable_ints(struct sc_info *);
201 static void m3_codec_reset(struct sc_info *);
202
203 /* -------------------------------------------------------------------- */
204 /* Codec descriptor */
205 static kobj_method_t m3_codec_methods[] = {
206 KOBJMETHOD(ac97_init, m3_initcd),
207 KOBJMETHOD(ac97_read, m3_rdcd),
208 KOBJMETHOD(ac97_write, m3_wrcd),
209 { 0, 0 }
210 };
211 AC97_DECLARE(m3_codec);
212
213 /* -------------------------------------------------------------------- */
214 /* channel descriptors */
215
216 static u_int32_t m3_playfmt[] = {
217 AFMT_U8,
218 AFMT_STEREO | AFMT_U8,
219 AFMT_S16_LE,
220 AFMT_STEREO | AFMT_S16_LE,
221 0
222 };
223 static struct pcmchan_caps m3_playcaps = {8000, 48000, m3_playfmt, 0};
224
225 static kobj_method_t m3_pch_methods[] = {
226 KOBJMETHOD(channel_init, m3_pchan_init),
227 KOBJMETHOD(channel_setformat, m3_pchan_setformat),
228 KOBJMETHOD(channel_setspeed, m3_pchan_setspeed),
229 KOBJMETHOD(channel_setblocksize, m3_pchan_setblocksize),
230 KOBJMETHOD(channel_trigger, m3_pchan_trigger),
231 KOBJMETHOD(channel_getptr, m3_pchan_getptr),
232 KOBJMETHOD(channel_getcaps, m3_pchan_getcaps),
233 KOBJMETHOD(channel_free, m3_pchan_free),
234 { 0, 0 }
235 };
236 CHANNEL_DECLARE(m3_pch);
237
238 static u_int32_t m3_recfmt[] = {
239 AFMT_U8,
240 AFMT_STEREO | AFMT_U8,
241 AFMT_S16_LE,
242 AFMT_STEREO | AFMT_S16_LE,
243 0
244 };
245 static struct pcmchan_caps m3_reccaps = {8000, 48000, m3_recfmt, 0};
246
247 static kobj_method_t m3_rch_methods[] = {
248 KOBJMETHOD(channel_init, m3_rchan_init),
249 KOBJMETHOD(channel_setformat, m3_rchan_setformat),
250 KOBJMETHOD(channel_setspeed, m3_rchan_setspeed),
251 KOBJMETHOD(channel_setblocksize, m3_rchan_setblocksize),
252 KOBJMETHOD(channel_trigger, m3_rchan_trigger),
253 KOBJMETHOD(channel_getptr, m3_rchan_getptr),
254 KOBJMETHOD(channel_getcaps, m3_rchan_getcaps),
255 KOBJMETHOD(channel_free, m3_rchan_free),
256 { 0, 0 }
257 };
258 CHANNEL_DECLARE(m3_rch);
259
260 /* -------------------------------------------------------------------- */
261 /* some i/o convenience functions */
262
263 #define m3_rd_1(sc, regno) bus_space_read_1(sc->st, sc->sh, regno)
264 #define m3_rd_2(sc, regno) bus_space_read_2(sc->st, sc->sh, regno)
265 #define m3_rd_4(sc, regno) bus_space_read_4(sc->st, sc->sh, regno)
266 #define m3_wr_1(sc, regno, data) bus_space_write_1(sc->st, sc->sh, regno, data)
267 #define m3_wr_2(sc, regno, data) bus_space_write_2(sc->st, sc->sh, regno, data)
268 #define m3_wr_4(sc, regno, data) bus_space_write_4(sc->st, sc->sh, regno, data)
269 #define m3_rd_assp_code(sc, index) \
270 m3_rd_assp(sc, MEMTYPE_INTERNAL_CODE, index)
271 #define m3_wr_assp_code(sc, index, data) \
272 m3_wr_assp(sc, MEMTYPE_INTERNAL_CODE, index, data)
273 #define m3_rd_assp_data(sc, index) \
274 m3_rd_assp(sc, MEMTYPE_INTERNAL_DATA, index)
275 #define m3_wr_assp_data(sc, index, data) \
276 m3_wr_assp(sc, MEMTYPE_INTERNAL_DATA, index, data)
277
278 static __inline u_int16_t
279 m3_rd_assp(struct sc_info *sc, u_int16_t region, u_int16_t index)
280 {
281 m3_wr_2(sc, DSP_PORT_MEMORY_TYPE, region & MEMTYPE_MASK);
282 m3_wr_2(sc, DSP_PORT_MEMORY_INDEX, index);
283 return m3_rd_2(sc, DSP_PORT_MEMORY_DATA);
284 }
285
286 static __inline void
287 m3_wr_assp(struct sc_info *sc, u_int16_t region, u_int16_t index,
288 u_int16_t data)
289 {
290 m3_wr_2(sc, DSP_PORT_MEMORY_TYPE, region & MEMTYPE_MASK);
291 m3_wr_2(sc, DSP_PORT_MEMORY_INDEX, index);
292 m3_wr_2(sc, DSP_PORT_MEMORY_DATA, data);
293 }
294
295 static __inline int
296 m3_wait(struct sc_info *sc)
297 {
298 int i;
299
300 for (i=0 ; i<20 ; i++) {
301 if ((m3_rd_1(sc, CODEC_STATUS) & 1) == 0) {
302 return 0;
303 }
304 DELAY(2);
305 }
306 return -1;
307 }
308
309 /* -------------------------------------------------------------------- */
310 /* ac97 codec */
311
312 static int
313 m3_initcd(kobj_t kobj, void *devinfo)
314 {
315 struct sc_info *sc = (struct sc_info *)devinfo;
316 u_int32_t data;
317
318 M3_DEBUG(CALL, ("m3_initcd\n"));
319
320 /* init ac-link */
321
322 data = m3_rd_1(sc, CODEC_COMMAND);
323 return ((data & 0x1) ? 0 : 1);
324 }
325
326 static int
327 m3_rdcd(kobj_t kobj, void *devinfo, int regno)
328 {
329 struct sc_info *sc = (struct sc_info *)devinfo;
330 u_int32_t data;
331
332 if (m3_wait(sc)) {
333 device_printf(sc->dev, "m3_rdcd timed out.\n");
334 return -1;
335 }
336 m3_wr_1(sc, CODEC_COMMAND, (regno & 0x7f) | 0x80);
337 DELAY(50); /* ac97 cycle = 20.8 usec */
338 if (m3_wait(sc)) {
339 device_printf(sc->dev, "m3_rdcd timed out.\n");
340 return -1;
341 }
342 data = m3_rd_2(sc, CODEC_DATA);
343 return data;
344 }
345
346 static int
347 m3_wrcd(kobj_t kobj, void *devinfo, int regno, u_int32_t data)
348 {
349 struct sc_info *sc = (struct sc_info *)devinfo;
350 if (m3_wait(sc)) {
351 device_printf(sc->dev, "m3_wrcd timed out.\n");
352 return -1;;
353 }
354 m3_wr_2(sc, CODEC_DATA, data);
355 m3_wr_1(sc, CODEC_COMMAND, regno & 0x7f);
356 DELAY(50); /* ac97 cycle = 20.8 usec */
357 return 0;
358 }
359
360 /* -------------------------------------------------------------------- */
361 /* play channel interface */
362
363 #define LO(x) (((x) & 0x0000ffff) )
364 #define HI(x) (((x) & 0xffff0000) >> 16)
365
366 static void *
367 m3_pchan_init(kobj_t kobj, void *devinfo, struct snd_dbuf *b, struct pcm_channel *c, int dir)
368 {
369 struct sc_info *sc = devinfo;
370 struct sc_pchinfo *ch;
371 u_int32_t bus_addr, i;
372 int idx, data_bytes, dac_data;
373 int dsp_in_size, dsp_out_size, dsp_in_buf, dsp_out_buf;
374
375 M3_LOCK(sc);
376 idx = sc->pch_cnt; /* dac instance number, no active reuse! */
377 M3_DEBUG(CHANGE, ("m3_pchan_init(dac=%d)\n", idx));
378
379 if (dir != PCMDIR_PLAY) {
380 M3_UNLOCK(sc);
381 device_printf(sc->dev, "m3_pchan_init not PCMDIR_PLAY\n");
382 return (NULL);
383 }
384
385 data_bytes = (((MINISRC_TMP_BUFFER_SIZE & ~1) +
386 (MINISRC_IN_BUFFER_SIZE & ~1) +
387 (MINISRC_OUT_BUFFER_SIZE & ~1) + 4) + 255) &~ 255;
388 dac_data = 0x1100 + (data_bytes * idx);
389
390 dsp_in_size = MINISRC_IN_BUFFER_SIZE - (0x20 * 2);
391 dsp_out_size = MINISRC_OUT_BUFFER_SIZE - (0x20 * 2);
392 dsp_in_buf = dac_data + (MINISRC_TMP_BUFFER_SIZE/2);
393 dsp_out_buf = dsp_in_buf + (dsp_in_size/2) + 1;
394
395 ch = &sc->pch[idx];
396 ch->dac_idx = idx;
397 ch->dac_data = dac_data;
398 if (ch->dac_data + data_bytes/2 >= 0x1c00) {
399 M3_UNLOCK(sc);
400 device_printf(sc->dev, "m3_pchan_init: revb mem exhausted\n");
401 return (NULL);
402 }
403
404 ch->buffer = b;
405 ch->parent = sc;
406 ch->channel = c;
407 ch->fmt = AFMT_U8;
408 ch->spd = DSP_DEFAULT_SPEED;
409 M3_UNLOCK(sc); /* XXX */
410 if (sndbuf_alloc(ch->buffer, sc->parent_dmat, sc->bufsz) != 0) {
411 device_printf(sc->dev, "m3_pchan_init chn_allocbuf failed\n");
412 return (NULL);
413 }
414 M3_LOCK(sc);
415 ch->bufsize = sndbuf_getsize(ch->buffer);
416
417 /* host dma buffer pointers */
418 bus_addr = sndbuf_getbufaddr(ch->buffer);
419 if (bus_addr & 3) {
420 device_printf(sc->dev, "m3_pchan_init unaligned bus_addr\n");
421 bus_addr = (bus_addr + 4) & ~3;
422 }
423 m3_wr_assp_data(sc, ch->dac_data + CDATA_HOST_SRC_ADDRL, LO(bus_addr));
424 m3_wr_assp_data(sc, ch->dac_data + CDATA_HOST_SRC_ADDRH, HI(bus_addr));
425 m3_wr_assp_data(sc, ch->dac_data + CDATA_HOST_SRC_END_PLUS_1L,
426 LO(bus_addr + ch->bufsize));
427 m3_wr_assp_data(sc, ch->dac_data + CDATA_HOST_SRC_END_PLUS_1H,
428 HI(bus_addr + ch->bufsize));
429 m3_wr_assp_data(sc, ch->dac_data + CDATA_HOST_SRC_CURRENTL,
430 LO(bus_addr));
431 m3_wr_assp_data(sc, ch->dac_data + CDATA_HOST_SRC_CURRENTH,
432 HI(bus_addr));
433
434 /* dsp buffers */
435 m3_wr_assp_data(sc, ch->dac_data + CDATA_IN_BUF_BEGIN, dsp_in_buf);
436 m3_wr_assp_data(sc, ch->dac_data + CDATA_IN_BUF_END_PLUS_1,
437 dsp_in_buf + dsp_in_size/2);
438 m3_wr_assp_data(sc, ch->dac_data + CDATA_IN_BUF_HEAD, dsp_in_buf);
439 m3_wr_assp_data(sc, ch->dac_data + CDATA_IN_BUF_TAIL, dsp_in_buf);
440 m3_wr_assp_data(sc, ch->dac_data + CDATA_OUT_BUF_BEGIN, dsp_out_buf);
441 m3_wr_assp_data(sc, ch->dac_data + CDATA_OUT_BUF_END_PLUS_1,
442 dsp_out_buf + dsp_out_size/2);
443 m3_wr_assp_data(sc, ch->dac_data + CDATA_OUT_BUF_HEAD, dsp_out_buf);
444 m3_wr_assp_data(sc, ch->dac_data + CDATA_OUT_BUF_TAIL, dsp_out_buf);
445
446 /* some per client initializers */
447 m3_wr_assp_data(sc, ch->dac_data + SRC3_DIRECTION_OFFSET + 12,
448 ch->dac_data + 40 + 8);
449 m3_wr_assp_data(sc, ch->dac_data + SRC3_DIRECTION_OFFSET + 19,
450 0x400 + MINISRC_COEF_LOC);
451 /* enable or disable low pass filter? (0xff if rate> 45000) */
452 m3_wr_assp_data(sc, ch->dac_data + SRC3_DIRECTION_OFFSET + 22, 0);
453 /* tell it which way dma is going? */
454 m3_wr_assp_data(sc, ch->dac_data + CDATA_DMA_CONTROL,
455 DMACONTROL_AUTOREPEAT + DMAC_PAGE3_SELECTOR +
456 DMAC_BLOCKF_SELECTOR);
457
458 /* set an armload of static initializers */
459 for(i = 0 ; i < NELEM(pv) ; i++) {
460 m3_wr_assp_data(sc, ch->dac_data + pv[i].addr, pv[i].val);
461 }
462
463 /* put us in the packed task lists */
464 m3_wr_assp_data(sc, KDATA_INSTANCE0_MINISRC +
465 (sc->pch_cnt + sc->rch_cnt),
466 ch->dac_data >> DP_SHIFT_COUNT);
467 m3_wr_assp_data(sc, KDATA_DMA_XFER0 + (sc->pch_cnt + sc->rch_cnt),
468 ch->dac_data >> DP_SHIFT_COUNT);
469 m3_wr_assp_data(sc, KDATA_MIXER_XFER0 + sc->pch_cnt,
470 ch->dac_data >> DP_SHIFT_COUNT);
471
472 /* gotta start before stop */
473 m3_pchan_trigger_locked(NULL, ch, PCMTRIG_START);
474 /* silence noise on load */
475 m3_pchan_trigger_locked(NULL, ch, PCMTRIG_STOP);
476
477 sc->pch_cnt++;
478 M3_UNLOCK(sc);
479
480 return (ch);
481 }
482
483 static int
484 m3_pchan_free(kobj_t kobj, void *chdata)
485 {
486 struct sc_pchinfo *ch = chdata;
487 struct sc_info *sc = ch->parent;
488
489 M3_LOCK(sc);
490 M3_DEBUG(CHANGE, ("m3_pchan_free(dac=%d)\n", ch->dac_idx));
491
492 /*
493 * should remove this exact instance from the packed lists, but all
494 * are released at once (and in a stopped state) so this is ok.
495 */
496 m3_wr_assp_data(sc, KDATA_INSTANCE0_MINISRC +
497 (sc->pch_cnt - 1) + sc->rch_cnt, 0);
498 m3_wr_assp_data(sc, KDATA_DMA_XFER0 +
499 (sc->pch_cnt - 1) + sc->rch_cnt, 0);
500 m3_wr_assp_data(sc, KDATA_MIXER_XFER0 + (sc->pch_cnt-1), 0);
501 sc->pch_cnt--;
502 M3_UNLOCK(sc);
503
504 return (0);
505 }
506
507 static int
508 m3_pchan_setformat(kobj_t kobj, void *chdata, u_int32_t format)
509 {
510 struct sc_pchinfo *ch = chdata;
511 struct sc_info *sc = ch->parent;
512 u_int32_t data;
513
514 M3_LOCK(sc);
515 M3_DEBUG(CHANGE,
516 ("m3_pchan_setformat(dac=%d, format=0x%x{%s-%s})\n",
517 ch->dac_idx, format,
518 format & (AFMT_U8|AFMT_S8) ? "8bit":"16bit",
519 format & AFMT_STEREO ? "STEREO":"MONO"));
520
521 /* mono word */
522 data = (format & AFMT_STEREO) ? 0 : 1;
523 m3_wr_assp_data(sc, ch->dac_data + SRC3_MODE_OFFSET, data);
524
525 /* 8bit word */
526 data = ((format & AFMT_U8) || (format & AFMT_S8)) ? 1 : 0;
527 m3_wr_assp_data(sc, ch->dac_data + SRC3_WORD_LENGTH_OFFSET, data);
528
529 ch->fmt = format;
530 M3_UNLOCK(sc);
531
532 return (0);
533 }
534
535 static int
536 m3_pchan_setspeed(kobj_t kobj, void *chdata, u_int32_t speed)
537 {
538 struct sc_pchinfo *ch = chdata;
539 struct sc_info *sc = ch->parent;
540 u_int32_t freq;
541
542 M3_LOCK(sc);
543 M3_DEBUG(CHANGE, ("m3_pchan_setspeed(dac=%d, speed=%d)\n",
544 ch->dac_idx, speed));
545
546 if ((freq = ((speed << 15) + 24000) / 48000) != 0) {
547 freq--;
548 }
549
550 m3_wr_assp_data(sc, ch->dac_data + CDATA_FREQUENCY, freq);
551 ch->spd = speed;
552 M3_UNLOCK(sc);
553
554 /* return closest possible speed */
555 return (speed);
556 }
557
558 static int
559 m3_pchan_setblocksize(kobj_t kobj, void *chdata, u_int32_t blocksize)
560 {
561 struct sc_pchinfo *ch = chdata;
562
563 M3_DEBUG(CHANGE, ("m3_pchan_setblocksize(dac=%d, blocksize=%d)\n",
564 ch->dac_idx, blocksize));
565
566 return (sndbuf_getblksz(ch->buffer));
567 }
568
569 static int
570 m3_pchan_trigger(kobj_t kobj, void *chdata, int go)
571 {
572 struct sc_pchinfo *ch = chdata;
573 struct sc_info *sc = ch->parent;
574 int ret;
575
576 M3_LOCK(sc);
577 ret = m3_pchan_trigger_locked(kobj, chdata, go);
578 M3_UNLOCK(sc);
579
580 return (ret);
581 }
582
583 static int
584 m3_chan_active(struct sc_info *sc)
585 {
586 int i, ret;
587
588 ret = 0;
589
590 for (i = 0; i < sc->pch_cnt; i++)
591 ret += sc->pch[i].active;
592
593 for (i = 0; i < sc->rch_cnt; i++)
594 ret += sc->rch[i].active;
595
596 return (ret);
597 }
598
599 static int
600 m3_pchan_trigger_locked(kobj_t kobj, void *chdata, int go)
601 {
602 struct sc_pchinfo *ch = chdata;
603 struct sc_info *sc = ch->parent;
604 u_int32_t data;
605
606 M3_LOCK_ASSERT(sc);
607 M3_DEBUG(go == PCMTRIG_START ? CHANGE :
608 go == PCMTRIG_STOP ? CHANGE :
609 go == PCMTRIG_ABORT ? CHANGE :
610 CALL,
611 ("m3_pchan_trigger(dac=%d, go=0x%x{%s})\n", ch->dac_idx, go,
612 go == PCMTRIG_START ? "PCMTRIG_START" :
613 go == PCMTRIG_STOP ? "PCMTRIG_STOP" :
614 go == PCMTRIG_ABORT ? "PCMTRIG_ABORT" : "ignore"));
615
616 switch(go) {
617 case PCMTRIG_START:
618 if (ch->active) {
619 return 0;
620 }
621 ch->active = 1;
622 ch->ptr = 0;
623 ch->prevptr = 0;
624 sc->pch_active_cnt++;
625
626 /*[[inc_timer_users]]*/
627 if (m3_chan_active(sc) == 1) {
628 m3_wr_assp_data(sc, KDATA_TIMER_COUNT_RELOAD, 240);
629 m3_wr_assp_data(sc, KDATA_TIMER_COUNT_CURRENT, 240);
630 data = m3_rd_2(sc, HOST_INT_CTRL);
631 m3_wr_2(sc, HOST_INT_CTRL, data | CLKRUN_GEN_ENABLE);
632 }
633
634 m3_wr_assp_data(sc, ch->dac_data + CDATA_INSTANCE_READY, 1);
635 m3_wr_assp_data(sc, KDATA_MIXER_TASK_NUMBER,
636 sc->pch_active_cnt);
637 break;
638
639 case PCMTRIG_STOP:
640 case PCMTRIG_ABORT:
641 if (ch->active == 0) {
642 return 0;
643 }
644 ch->active = 0;
645 sc->pch_active_cnt--;
646
647 /* XXX should the channel be drained? */
648 /*[[dec_timer_users]]*/
649 if (m3_chan_active(sc) == 0) {
650 m3_wr_assp_data(sc, KDATA_TIMER_COUNT_RELOAD, 0);
651 m3_wr_assp_data(sc, KDATA_TIMER_COUNT_CURRENT, 0);
652 data = m3_rd_2(sc, HOST_INT_CTRL);
653 m3_wr_2(sc, HOST_INT_CTRL, data & ~CLKRUN_GEN_ENABLE);
654 }
655
656 m3_wr_assp_data(sc, ch->dac_data + CDATA_INSTANCE_READY, 0);
657 m3_wr_assp_data(sc, KDATA_MIXER_TASK_NUMBER,
658 sc->pch_active_cnt);
659 break;
660
661 case PCMTRIG_EMLDMAWR:
662 /* got play irq, transfer next buffer - ignore if using dma */
663 case PCMTRIG_EMLDMARD:
664 /* got rec irq, transfer next buffer - ignore if using dma */
665 default:
666 break;
667 }
668 return 0;
669 }
670
671 static u_int32_t
672 m3_pchan_getptr_internal(struct sc_pchinfo *ch)
673 {
674 struct sc_info *sc = ch->parent;
675 u_int32_t hi, lo, bus_base, bus_crnt;
676
677 bus_base = sndbuf_getbufaddr(ch->buffer);
678 hi = m3_rd_assp_data(sc, ch->dac_data + CDATA_HOST_SRC_CURRENTH);
679 lo = m3_rd_assp_data(sc, ch->dac_data + CDATA_HOST_SRC_CURRENTL);
680 bus_crnt = lo | (hi << 16);
681
682 M3_DEBUG(CALL, ("m3_pchan_getptr(dac=%d) result=%d\n",
683 ch->dac_idx, bus_crnt - bus_base));
684
685 return (bus_crnt - bus_base); /* current byte offset of channel */
686 }
687
688 static u_int32_t
689 m3_pchan_getptr(kobj_t kobj, void *chdata)
690 {
691 struct sc_pchinfo *ch = chdata;
692 struct sc_info *sc = ch->parent;
693 u_int32_t ptr;
694
695 M3_LOCK(sc);
696 ptr = ch->ptr;
697 M3_UNLOCK(sc);
698
699 return (ptr);
700 }
701
702 static struct pcmchan_caps *
703 m3_pchan_getcaps(kobj_t kobj, void *chdata)
704 {
705 struct sc_pchinfo *ch = chdata;
706
707 M3_DEBUG(CALL, ("m3_pchan_getcaps(dac=%d)\n", ch->dac_idx));
708
709 return &m3_playcaps;
710 }
711
712 /* -------------------------------------------------------------------- */
713 /* rec channel interface */
714
715 static void *
716 m3_rchan_init(kobj_t kobj, void *devinfo, struct snd_dbuf *b, struct pcm_channel *c, int dir)
717 {
718 struct sc_info *sc = devinfo;
719 struct sc_rchinfo *ch;
720 u_int32_t bus_addr, i;
721
722 int idx, data_bytes, adc_data;
723 int dsp_in_size, dsp_out_size, dsp_in_buf, dsp_out_buf;
724
725 M3_LOCK(sc);
726 idx = sc->rch_cnt; /* adc instance number, no active reuse! */
727 M3_DEBUG(CHANGE, ("m3_rchan_init(adc=%d)\n", idx));
728
729 if (dir != PCMDIR_REC) {
730 M3_UNLOCK(sc);
731 device_printf(sc->dev, "m3_pchan_init not PCMDIR_REC\n");
732 return (NULL);
733 }
734
735 data_bytes = (((MINISRC_TMP_BUFFER_SIZE & ~1) +
736 (MINISRC_IN_BUFFER_SIZE & ~1) +
737 (MINISRC_OUT_BUFFER_SIZE & ~1) + 4) + 255) &~ 255;
738 adc_data = 0x1100 + (data_bytes * idx) + data_bytes/2;
739 dsp_in_size = MINISRC_IN_BUFFER_SIZE + (0x10 * 2);
740 dsp_out_size = MINISRC_OUT_BUFFER_SIZE - (0x10 * 2);
741 dsp_in_buf = adc_data + (MINISRC_TMP_BUFFER_SIZE / 2);
742 dsp_out_buf = dsp_in_buf + (dsp_in_size / 2) + 1;
743
744 ch = &sc->rch[idx];
745 ch->adc_idx = idx;
746 ch->adc_data = adc_data;
747 if (ch->adc_data + data_bytes/2 >= 0x1c00) {
748 M3_UNLOCK(sc);
749 device_printf(sc->dev, "m3_rchan_init: revb mem exhausted\n");
750 return (NULL);
751 }
752
753 ch->buffer = b;
754 ch->parent = sc;
755 ch->channel = c;
756 ch->fmt = AFMT_U8;
757 ch->spd = DSP_DEFAULT_SPEED;
758 M3_UNLOCK(sc); /* XXX */
759 if (sndbuf_alloc(ch->buffer, sc->parent_dmat, sc->bufsz) != 0) {
760 device_printf(sc->dev, "m3_rchan_init chn_allocbuf failed\n");
761 return (NULL);
762 }
763 M3_LOCK(sc);
764 ch->bufsize = sndbuf_getsize(ch->buffer);
765
766 /* host dma buffer pointers */
767 bus_addr = sndbuf_getbufaddr(ch->buffer);
768 if (bus_addr & 3) {
769 device_printf(sc->dev, "m3_rchan_init unaligned bus_addr\n");
770 bus_addr = (bus_addr + 4) & ~3;
771 }
772 m3_wr_assp_data(sc, ch->adc_data + CDATA_HOST_SRC_ADDRL, LO(bus_addr));
773 m3_wr_assp_data(sc, ch->adc_data + CDATA_HOST_SRC_ADDRH, HI(bus_addr));
774 m3_wr_assp_data(sc, ch->adc_data + CDATA_HOST_SRC_END_PLUS_1L,
775 LO(bus_addr + ch->bufsize));
776 m3_wr_assp_data(sc, ch->adc_data + CDATA_HOST_SRC_END_PLUS_1H,
777 HI(bus_addr + ch->bufsize));
778 m3_wr_assp_data(sc, ch->adc_data + CDATA_HOST_SRC_CURRENTL,
779 LO(bus_addr));
780 m3_wr_assp_data(sc, ch->adc_data + CDATA_HOST_SRC_CURRENTH,
781 HI(bus_addr));
782
783 /* dsp buffers */
784 m3_wr_assp_data(sc, ch->adc_data + CDATA_IN_BUF_BEGIN, dsp_in_buf);
785 m3_wr_assp_data(sc, ch->adc_data + CDATA_IN_BUF_END_PLUS_1,
786 dsp_in_buf + dsp_in_size/2);
787 m3_wr_assp_data(sc, ch->adc_data + CDATA_IN_BUF_HEAD, dsp_in_buf);
788 m3_wr_assp_data(sc, ch->adc_data + CDATA_IN_BUF_TAIL, dsp_in_buf);
789 m3_wr_assp_data(sc, ch->adc_data + CDATA_OUT_BUF_BEGIN, dsp_out_buf);
790 m3_wr_assp_data(sc, ch->adc_data + CDATA_OUT_BUF_END_PLUS_1,
791 dsp_out_buf + dsp_out_size/2);
792 m3_wr_assp_data(sc, ch->adc_data + CDATA_OUT_BUF_HEAD, dsp_out_buf);
793 m3_wr_assp_data(sc, ch->adc_data + CDATA_OUT_BUF_TAIL, dsp_out_buf);
794
795 /* some per client initializers */
796 m3_wr_assp_data(sc, ch->adc_data + SRC3_DIRECTION_OFFSET + 12,
797 ch->adc_data + 40 + 8);
798 m3_wr_assp_data(sc, ch->adc_data + CDATA_DMA_CONTROL,
799 DMACONTROL_DIRECTION + DMACONTROL_AUTOREPEAT +
800 DMAC_PAGE3_SELECTOR + DMAC_BLOCKF_SELECTOR);
801
802 /* set an armload of static initializers */
803 for(i = 0 ; i < NELEM(rv) ; i++) {
804 m3_wr_assp_data(sc, ch->adc_data + rv[i].addr, rv[i].val);
805 }
806
807 /* put us in the packed task lists */
808 m3_wr_assp_data(sc, KDATA_INSTANCE0_MINISRC +
809 (sc->pch_cnt + sc->rch_cnt),
810 ch->adc_data >> DP_SHIFT_COUNT);
811 m3_wr_assp_data(sc, KDATA_DMA_XFER0 + (sc->pch_cnt + sc->rch_cnt),
812 ch->adc_data >> DP_SHIFT_COUNT);
813 m3_wr_assp_data(sc, KDATA_ADC1_XFER0 + sc->rch_cnt,
814 ch->adc_data >> DP_SHIFT_COUNT);
815
816 /* gotta start before stop */
817 m3_rchan_trigger_locked(NULL, ch, PCMTRIG_START);
818 /* stop on init */
819 m3_rchan_trigger_locked(NULL, ch, PCMTRIG_STOP);
820
821 sc->rch_cnt++;
822 M3_UNLOCK(sc);
823
824 return (ch);
825 }
826
827 static int
828 m3_rchan_free(kobj_t kobj, void *chdata)
829 {
830 struct sc_rchinfo *ch = chdata;
831 struct sc_info *sc = ch->parent;
832
833 M3_LOCK(sc);
834 M3_DEBUG(CHANGE, ("m3_rchan_free(adc=%d)\n", ch->adc_idx));
835
836 /*
837 * should remove this exact instance from the packed lists, but all
838 * are released at once (and in a stopped state) so this is ok.
839 */
840 m3_wr_assp_data(sc, KDATA_INSTANCE0_MINISRC +
841 (sc->rch_cnt - 1) + sc->pch_cnt, 0);
842 m3_wr_assp_data(sc, KDATA_DMA_XFER0 +
843 (sc->rch_cnt - 1) + sc->pch_cnt, 0);
844 m3_wr_assp_data(sc, KDATA_ADC1_XFER0 + (sc->rch_cnt - 1), 0);
845 sc->rch_cnt--;
846 M3_UNLOCK(sc);
847
848 return (0);
849 }
850
851 static int
852 m3_rchan_setformat(kobj_t kobj, void *chdata, u_int32_t format)
853 {
854 struct sc_rchinfo *ch = chdata;
855 struct sc_info *sc = ch->parent;
856 u_int32_t data;
857
858 M3_LOCK(sc);
859 M3_DEBUG(CHANGE,
860 ("m3_rchan_setformat(dac=%d, format=0x%x{%s-%s})\n",
861 ch->adc_idx, format,
862 format & (AFMT_U8|AFMT_S8) ? "8bit":"16bit",
863 format & AFMT_STEREO ? "STEREO":"MONO"));
864
865 /* mono word */
866 data = (format & AFMT_STEREO) ? 0 : 1;
867 m3_wr_assp_data(sc, ch->adc_data + SRC3_MODE_OFFSET, data);
868
869 /* 8bit word */
870 data = ((format & AFMT_U8) || (format & AFMT_S8)) ? 1 : 0;
871 m3_wr_assp_data(sc, ch->adc_data + SRC3_WORD_LENGTH_OFFSET, data);
872 ch->fmt = format;
873 M3_UNLOCK(sc);
874
875 return (0);
876 }
877
878 static int
879 m3_rchan_setspeed(kobj_t kobj, void *chdata, u_int32_t speed)
880 {
881 struct sc_rchinfo *ch = chdata;
882 struct sc_info *sc = ch->parent;
883 u_int32_t freq;
884
885 M3_LOCK(sc);
886 M3_DEBUG(CHANGE, ("m3_rchan_setspeed(adc=%d, speed=%d)\n",
887 ch->adc_idx, speed));
888
889 if ((freq = ((speed << 15) + 24000) / 48000) != 0) {
890 freq--;
891 }
892
893 m3_wr_assp_data(sc, ch->adc_data + CDATA_FREQUENCY, freq);
894 ch->spd = speed;
895 M3_UNLOCK(sc);
896
897 /* return closest possible speed */
898 return (speed);
899 }
900
901 static int
902 m3_rchan_setblocksize(kobj_t kobj, void *chdata, u_int32_t blocksize)
903 {
904 struct sc_rchinfo *ch = chdata;
905
906 M3_DEBUG(CHANGE, ("m3_rchan_setblocksize(adc=%d, blocksize=%d)\n",
907 ch->adc_idx, blocksize));
908
909 return (sndbuf_getblksz(ch->buffer));
910 }
911
912 static int
913 m3_rchan_trigger(kobj_t kobj, void *chdata, int go)
914 {
915 struct sc_rchinfo *ch = chdata;
916 struct sc_info *sc = ch->parent;
917 int ret;
918
919 M3_LOCK(sc);
920 ret = m3_rchan_trigger_locked(kobj, chdata, go);
921 M3_UNLOCK(sc);
922
923 return (ret);
924 }
925
926 static int
927 m3_rchan_trigger_locked(kobj_t kobj, void *chdata, int go)
928 {
929 struct sc_rchinfo *ch = chdata;
930 struct sc_info *sc = ch->parent;
931 u_int32_t data;
932
933 M3_LOCK_ASSERT(sc);
934 M3_DEBUG(go == PCMTRIG_START ? CHANGE :
935 go == PCMTRIG_STOP ? CHANGE :
936 go == PCMTRIG_ABORT ? CHANGE :
937 CALL,
938 ("m3_rchan_trigger(adc=%d, go=0x%x{%s})\n", ch->adc_idx, go,
939 go == PCMTRIG_START ? "PCMTRIG_START" :
940 go == PCMTRIG_STOP ? "PCMTRIG_STOP" :
941 go == PCMTRIG_ABORT ? "PCMTRIG_ABORT" : "ignore"));
942
943 switch(go) {
944 case PCMTRIG_START:
945 if (ch->active) {
946 return 0;
947 }
948 ch->active = 1;
949 ch->ptr = 0;
950 ch->prevptr = 0;
951
952 /*[[inc_timer_users]]*/
953 if (m3_chan_active(sc) == 1) {
954 m3_wr_assp_data(sc, KDATA_TIMER_COUNT_RELOAD, 240);
955 m3_wr_assp_data(sc, KDATA_TIMER_COUNT_CURRENT, 240);
956 data = m3_rd_2(sc, HOST_INT_CTRL);
957 m3_wr_2(sc, HOST_INT_CTRL, data | CLKRUN_GEN_ENABLE);
958 }
959
960 m3_wr_assp_data(sc, KDATA_ADC1_REQUEST, 1);
961 m3_wr_assp_data(sc, ch->adc_data + CDATA_INSTANCE_READY, 1);
962 break;
963
964 case PCMTRIG_STOP:
965 case PCMTRIG_ABORT:
966 if (ch->active == 0) {
967 return 0;
968 }
969 ch->active = 0;
970
971 /*[[dec_timer_users]]*/
972 if (m3_chan_active(sc) == 0) {
973 m3_wr_assp_data(sc, KDATA_TIMER_COUNT_RELOAD, 0);
974 m3_wr_assp_data(sc, KDATA_TIMER_COUNT_CURRENT, 0);
975 data = m3_rd_2(sc, HOST_INT_CTRL);
976 m3_wr_2(sc, HOST_INT_CTRL, data & ~CLKRUN_GEN_ENABLE);
977 }
978
979 m3_wr_assp_data(sc, ch->adc_data + CDATA_INSTANCE_READY, 0);
980 m3_wr_assp_data(sc, KDATA_ADC1_REQUEST, 0);
981 break;
982
983 case PCMTRIG_EMLDMAWR:
984 /* got play irq, transfer next buffer - ignore if using dma */
985 case PCMTRIG_EMLDMARD:
986 /* got rec irq, transfer next buffer - ignore if using dma */
987 default:
988 break;
989 }
990 return 0;
991 }
992
993 static u_int32_t
994 m3_rchan_getptr_internal(struct sc_rchinfo *ch)
995 {
996 struct sc_info *sc = ch->parent;
997 u_int32_t hi, lo, bus_base, bus_crnt;
998
999 bus_base = sndbuf_getbufaddr(ch->buffer);
1000 hi = m3_rd_assp_data(sc, ch->adc_data + CDATA_HOST_SRC_CURRENTH);
1001 lo = m3_rd_assp_data(sc, ch->adc_data + CDATA_HOST_SRC_CURRENTL);
1002 bus_crnt = lo | (hi << 16);
1003
1004 M3_DEBUG(CALL, ("m3_rchan_getptr(adc=%d) result=%d\n",
1005 ch->adc_idx, bus_crnt - bus_base));
1006
1007 return (bus_crnt - bus_base); /* current byte offset of channel */
1008 }
1009
1010 static u_int32_t
1011 m3_rchan_getptr(kobj_t kobj, void *chdata)
1012 {
1013 struct sc_rchinfo *ch = chdata;
1014 struct sc_info *sc = ch->parent;
1015 u_int32_t ptr;
1016
1017 M3_LOCK(sc);
1018 ptr = ch->ptr;
1019 M3_UNLOCK(sc);
1020
1021 return (ptr);
1022 }
1023
1024 static struct pcmchan_caps *
1025 m3_rchan_getcaps(kobj_t kobj, void *chdata)
1026 {
1027 struct sc_rchinfo *ch = chdata;
1028
1029 M3_DEBUG(CALL, ("m3_rchan_getcaps(adc=%d)\n", ch->adc_idx));
1030
1031 return &m3_reccaps;
1032 }
1033
1034 /* -------------------------------------------------------------------- */
1035 /* The interrupt handler */
1036
1037 static void
1038 m3_intr(void *p)
1039 {
1040 struct sc_info *sc = (struct sc_info *)p;
1041 struct sc_pchinfo *pch;
1042 struct sc_rchinfo *rch;
1043 u_int32_t status, ctl, i, delta;
1044
1045 M3_DEBUG(INTR, ("m3_intr\n"));
1046
1047 M3_LOCK(sc);
1048 status = m3_rd_1(sc, HOST_INT_STATUS);
1049 if (!status) {
1050 M3_UNLOCK(sc);
1051 return;
1052 }
1053
1054 m3_wr_1(sc, HOST_INT_STATUS, 0xff); /* ack the int? */
1055
1056 if (status & HV_INT_PENDING) {
1057 u_int8_t event;
1058
1059 event = m3_rd_1(sc, HW_VOL_COUNTER_MASTER);
1060 switch (event) {
1061 case 0x99:
1062 mixer_hwvol_mute(sc->dev);
1063 break;
1064 case 0xaa:
1065 mixer_hwvol_step(sc->dev, 1, 1);
1066 break;
1067 case 0x66:
1068 mixer_hwvol_step(sc->dev, -1, -1);
1069 break;
1070 case 0x88:
1071 break;
1072 default:
1073 device_printf(sc->dev, "Unknown HWVOL event\n");
1074 }
1075 m3_wr_1(sc, HW_VOL_COUNTER_MASTER, 0x88);
1076
1077 }
1078
1079 if (status & ASSP_INT_PENDING) {
1080 ctl = m3_rd_1(sc, ASSP_CONTROL_B);
1081 if (!(ctl & STOP_ASSP_CLOCK)) {
1082 ctl = m3_rd_1(sc, ASSP_HOST_INT_STATUS);
1083 if (ctl & DSP2HOST_REQ_TIMER) {
1084 m3_wr_1(sc, ASSP_HOST_INT_STATUS,
1085 DSP2HOST_REQ_TIMER);
1086 /*[[ess_update_ptr]]*/
1087 goto m3_handle_channel_intr;
1088 }
1089 }
1090 }
1091
1092 goto m3_handle_channel_intr_out;
1093
1094 m3_handle_channel_intr:
1095 for (i=0 ; i<sc->pch_cnt ; i++) {
1096 pch = &sc->pch[i];
1097 if (pch->active) {
1098 pch->ptr = m3_pchan_getptr_internal(pch);
1099 delta = pch->bufsize + pch->ptr - pch->prevptr;
1100 delta %= pch->bufsize;
1101 if (delta < sndbuf_getblksz(pch->buffer))
1102 continue;
1103 pch->prevptr = pch->ptr;
1104 M3_UNLOCK(sc);
1105 chn_intr(pch->channel);
1106 M3_LOCK(sc);
1107 }
1108 }
1109 for (i=0 ; i<sc->rch_cnt ; i++) {
1110 rch = &sc->rch[i];
1111 if (rch->active) {
1112 rch->ptr = m3_rchan_getptr_internal(rch);
1113 delta = rch->bufsize + rch->ptr - rch->prevptr;
1114 delta %= rch->bufsize;
1115 if (delta < sndbuf_getblksz(rch->buffer))
1116 continue;
1117 rch->prevptr = rch->ptr;
1118 M3_UNLOCK(sc);
1119 chn_intr(rch->channel);
1120 M3_LOCK(sc);
1121 }
1122 }
1123
1124 m3_handle_channel_intr_out:
1125 M3_UNLOCK(sc);
1126 }
1127
1128 /* -------------------------------------------------------------------- */
1129 /* stuff */
1130
1131 static int
1132 m3_power(struct sc_info *sc, int state)
1133 {
1134 u_int32_t data;
1135
1136 M3_DEBUG(CHANGE, ("m3_power(%d)\n", state));
1137 M3_LOCK_ASSERT(sc);
1138
1139 data = pci_read_config(sc->dev, 0x34, 1);
1140 if (pci_read_config(sc->dev, data, 1) == 1) {
1141 pci_write_config(sc->dev, data + 4, state, 1);
1142 }
1143
1144 return 0;
1145 }
1146
1147 static int
1148 m3_init(struct sc_info *sc)
1149 {
1150 u_int32_t data, i, size;
1151 u_int8_t reset_state;
1152
1153 M3_LOCK_ASSERT(sc);
1154 M3_DEBUG(CHANGE, ("m3_init\n"));
1155
1156 /* diable legacy emulations. */
1157 data = pci_read_config(sc->dev, PCI_LEGACY_AUDIO_CTRL, 2);
1158 data |= DISABLE_LEGACY;
1159 pci_write_config(sc->dev, PCI_LEGACY_AUDIO_CTRL, data, 2);
1160
1161 m3_config(sc);
1162
1163 reset_state = m3_assp_halt(sc);
1164
1165 m3_codec_reset(sc);
1166
1167 /* [m3_assp_init] */
1168 /* zero kernel data */
1169 size = REV_B_DATA_MEMORY_UNIT_LENGTH * NUM_UNITS_KERNEL_DATA;
1170 for(i = 0 ; i < size / 2 ; i++) {
1171 m3_wr_assp_data(sc, KDATA_BASE_ADDR + i, 0);
1172 }
1173 /* zero mixer data? */
1174 size = REV_B_DATA_MEMORY_UNIT_LENGTH * NUM_UNITS_KERNEL_DATA;
1175 for(i = 0 ; i < size / 2 ; i++) {
1176 m3_wr_assp_data(sc, KDATA_BASE_ADDR2 + i, 0);
1177 }
1178 /* init dma pointer */
1179 m3_wr_assp_data(sc, KDATA_CURRENT_DMA,
1180 KDATA_DMA_XFER0);
1181 /* write kernel into code memory */
1182 size = sizeof(assp_kernel_image);
1183 for(i = 0 ; i < size / 2; i++) {
1184 m3_wr_assp_code(sc, REV_B_CODE_MEMORY_BEGIN + i,
1185 assp_kernel_image[i]);
1186 }
1187 /*
1188 * We only have this one client and we know that 0x400 is kfree in
1189 * our kernel's mem map, so lets just drop it there. It seems that
1190 * the minisrc doesn't need vectors, so we won't bother with them..
1191 */
1192 size = sizeof(assp_minisrc_image);
1193 for(i = 0 ; i < size / 2; i++) {
1194 m3_wr_assp_code(sc, 0x400 + i, assp_minisrc_image[i]);
1195 }
1196 /* write the coefficients for the low pass filter? */
1197 size = sizeof(minisrc_lpf_image);
1198 for(i = 0; i < size / 2 ; i++) {
1199 m3_wr_assp_code(sc,0x400 + MINISRC_COEF_LOC + i,
1200 minisrc_lpf_image[i]);
1201 }
1202 m3_wr_assp_code(sc, 0x400 + MINISRC_COEF_LOC + size, 0x8000);
1203 /* the minisrc is the only thing on our task list */
1204 m3_wr_assp_data(sc, KDATA_TASK0, 0x400);
1205 /* init the mixer number */
1206 m3_wr_assp_data(sc, KDATA_MIXER_TASK_NUMBER, 0);
1207 /* extreme kernel master volume */
1208 m3_wr_assp_data(sc, KDATA_DAC_LEFT_VOLUME, ARB_VOLUME);
1209 m3_wr_assp_data(sc, KDATA_DAC_RIGHT_VOLUME, ARB_VOLUME);
1210
1211 m3_amp_enable(sc);
1212
1213 /* [m3_assp_client_init] (only one client at index 0) */
1214 for (i=0x1100 ; i<0x1c00 ; i++) {
1215 m3_wr_assp_data(sc, i, 0); /* zero entire dac/adc area */
1216 }
1217
1218 /* [m3_assp_continue] */
1219 m3_wr_1(sc, DSP_PORT_CONTROL_REG_B, reset_state | REGB_ENABLE_RESET);
1220
1221 return 0;
1222 }
1223
1224 static int
1225 m3_uninit(struct sc_info *sc)
1226 {
1227 M3_DEBUG(CHANGE, ("m3_uninit\n"));
1228 return 0;
1229 }
1230
1231 /* -------------------------------------------------------------------- */
1232 /* Probe and attach the card */
1233
1234 static int
1235 m3_pci_probe(device_t dev)
1236 {
1237 struct m3_card_type *card;
1238
1239 M3_DEBUG(CALL, ("m3_pci_probe(0x%x)\n", pci_get_devid(dev)));
1240
1241 for (card = m3_card_types ; card->pci_id ; card++) {
1242 if (pci_get_devid(dev) == card->pci_id) {
1243 device_set_desc(dev, card->name);
1244 return BUS_PROBE_DEFAULT;
1245 }
1246 }
1247 return ENXIO;
1248 }
1249
1250 static int
1251 m3_pci_attach(device_t dev)
1252 {
1253 struct sc_info *sc;
1254 struct ac97_info *codec = NULL;
1255 u_int32_t data;
1256 char status[SND_STATUSLEN];
1257 struct m3_card_type *card;
1258 int i, len, dacn, adcn;
1259
1260 M3_DEBUG(CALL, ("m3_pci_attach\n"));
1261
1262 sc = kmalloc(sizeof(*sc), M_DEVBUF, M_WAITOK | M_ZERO);
1263 sc->dev = dev;
1264 sc->type = pci_get_devid(dev);
1265 sc->sc_lock = snd_mtxcreate(device_get_nameunit(dev),
1266 "sound softc");
1267 if (sc->sc_lock == NULL) {
1268 device_printf(dev, "cannot create mutex\n");
1269 kfree(sc, M_DEVBUF);
1270 return (ENXIO);
1271 }
1272 for (card = m3_card_types ; card->pci_id ; card++) {
1273 if (sc->type == card->pci_id) {
1274 sc->which = card->which;
1275 sc->delay1 = card->delay1;
1276 sc->delay2 = card->delay2;
1277 break;
1278 }
1279 }
1280
1281 if (resource_int_value(device_get_name(dev), device_get_unit(dev),
1282 "dac", &i) == 0) {
1283 if (i < 1)
1284 dacn = 1;
1285 else if (i > M3_PCHANS)
1286 dacn = M3_PCHANS;
1287 else
1288 dacn = i;
1289 } else
1290 dacn = M3_PCHANS;
1291
1292 adcn = M3_RCHANS;
1293
1294 data = pci_read_config(dev, PCIR_COMMAND, 2);
1295 data |= (PCIM_CMD_PORTEN | PCIM_CMD_MEMEN | PCIM_CMD_BUSMASTEREN);
1296 pci_write_config(dev, PCIR_COMMAND, data, 2);
1297
1298 sc->regid = PCIR_BAR(0);
1299 sc->regtype = SYS_RES_MEMORY;
1300 sc->reg = bus_alloc_resource_any(dev, sc->regtype, &sc->regid,
1301 RF_ACTIVE);
1302 if (!sc->reg) {
1303 sc->regtype = SYS_RES_IOPORT;
1304 sc->reg = bus_alloc_resource_any(dev, sc->regtype, &sc->regid,
1305 RF_ACTIVE);
1306 }
1307 if (!sc->reg) {
1308 device_printf(dev, "unable to allocate register space\n");
1309 goto bad;
1310 }
1311 sc->st = rman_get_bustag(sc->reg);
1312 sc->sh = rman_get_bushandle(sc->reg);
1313
1314 sc->irqid = 0;
1315 sc->irq = bus_alloc_resource_any(dev, SYS_RES_IRQ, &sc->irqid,
1316 RF_ACTIVE | RF_SHAREABLE);
1317 if (!sc->irq) {
1318 device_printf(dev, "unable to allocate interrupt\n");
1319 goto bad;
1320 }
1321
1322 if (snd_setup_intr(dev, sc->irq, INTR_MPSAFE, m3_intr, sc, &sc->ih)) {
1323 device_printf(dev, "unable to setup interrupt\n");
1324 goto bad;
1325 }
1326
1327 sc->bufsz = pcm_getbuffersize(dev, M3_BUFSIZE_MIN, M3_BUFSIZE_DEFAULT,
1328 M3_BUFSIZE_MAX);
1329
1330 if (bus_dma_tag_create(
1331 NULL, /* parent */
1332 2, 0, /* alignment, boundary */
1333 M3_MAXADDR, /* lowaddr */
1334 BUS_SPACE_MAXADDR, /* highaddr */
1335 NULL, NULL, /* filtfunc, filtfuncarg */
1336 sc->bufsz, /* maxsize */
1337 1, /* nsegments */
1338 0x3ffff, /* maxsegz */
1339 0, /* flags */
1340 &sc->parent_dmat) != 0) {
1341 device_printf(dev, "unable to create dma tag\n");
1342 goto bad;
1343 }
1344
1345 M3_LOCK(sc);
1346 m3_power(sc, 0); /* power up */
1347 /* init chip */
1348 i = m3_init(sc);
1349 M3_UNLOCK(sc);
1350 if (i == -1) {
1351 device_printf(dev, "unable to initialize the card\n");
1352 goto bad;
1353 }
1354
1355 /* create/init mixer */
1356 codec = AC97_CREATE(dev, sc, m3_codec);
1357 if (codec == NULL) {
1358 device_printf(dev, "ac97_create error\n");
1359 goto bad;
1360 }
1361 if (mixer_init(dev, ac97_getmixerclass(), codec)) {
1362 device_printf(dev, "mixer_init error\n");
1363 goto bad;
1364 }
1365
1366 m3_enable_ints(sc);
1367
1368 if (pcm_register(dev, sc, dacn, adcn)) {
1369 device_printf(dev, "pcm_register error\n");
1370 goto bad;
1371 }
1372 for (i=0 ; i<dacn ; i++) {
1373 if (pcm_addchan(dev, PCMDIR_PLAY, &m3_pch_class, sc)) {
1374 device_printf(dev, "pcm_addchan (play) error\n");
1375 goto bad;
1376 }
1377 }
1378 for (i=0 ; i<adcn ; i++) {
1379 if (pcm_addchan(dev, PCMDIR_REC, &m3_rch_class, sc)) {
1380 device_printf(dev, "pcm_addchan (rec) error\n");
1381 goto bad;
1382 }
1383 }
1384 ksnprintf(status, SND_STATUSLEN, "at %s 0x%lx irq %ld %s",
1385 (sc->regtype == SYS_RES_IOPORT)? "io" : "memory",
1386 rman_get_start(sc->reg), rman_get_start(sc->irq),
1387 PCM_KLDSTRING(snd_maestro3));
1388 if (pcm_setstatus(dev, status)) {
1389 device_printf(dev, "attach: pcm_setstatus error\n");
1390 goto bad;
1391 }
1392
1393 mixer_hwvol_init(dev);
1394
1395 /* Create the buffer for saving the card state during suspend */
1396 len = sizeof(u_int16_t) * (REV_B_CODE_MEMORY_LENGTH +
1397 REV_B_DATA_MEMORY_LENGTH);
1398 sc->savemem = kmalloc(len, M_DEVBUF, M_WAITOK | M_ZERO);
1399
1400 return 0;
1401
1402 bad:
1403 if (codec)
1404 ac97_destroy(codec);
1405 if (sc->ih)
1406 bus_teardown_intr(dev, sc->irq, sc->ih);
1407 if (sc->irq)
1408 bus_release_resource(dev, SYS_RES_IRQ, sc->irqid, sc->irq);
1409 if (sc->reg)
1410 bus_release_resource(dev, sc->regtype, sc->regid, sc->reg);
1411 if (sc->parent_dmat)
1412 bus_dma_tag_destroy(sc->parent_dmat);
1413 if (sc->sc_lock)
1414 snd_mtxfree(sc->sc_lock);
1415 kfree(sc, M_DEVBUF);
1416 return ENXIO;
1417 }
1418
1419 static int
1420 m3_pci_detach(device_t dev)
1421 {
1422 struct sc_info *sc = pcm_getdevinfo(dev);
1423 int r;
1424
1425 M3_DEBUG(CALL, ("m3_pci_detach\n"));
1426
1427 if ((r = pcm_unregister(dev)) != 0) {
1428 return r;
1429 }
1430
1431 M3_LOCK(sc);
1432 m3_uninit(sc); /* shutdown chip */
1433 m3_power(sc, 3); /* power off */
1434 M3_UNLOCK(sc);
1435
1436 bus_teardown_intr(dev, sc->irq, sc->ih);
1437 bus_release_resource(dev, SYS_RES_IRQ, sc->irqid, sc->irq);
1438 bus_release_resource(dev, sc->regtype, sc->regid, sc->reg);
1439 bus_dma_tag_destroy(sc->parent_dmat);
1440
1441 kfree(sc->savemem, M_DEVBUF);
1442 snd_mtxfree(sc->sc_lock);
1443 kfree(sc, M_DEVBUF);
1444 return 0;
1445 }
1446
1447 static int
1448 m3_pci_suspend(device_t dev)
1449 {
1450 struct sc_info *sc = pcm_getdevinfo(dev);
1451 int i, index = 0;
1452
1453 M3_DEBUG(CHANGE, ("m3_pci_suspend\n"));
1454
1455 M3_LOCK(sc);
1456 for (i=0 ; i<sc->pch_cnt ; i++) {
1457 if (sc->pch[i].active) {
1458 m3_pchan_trigger_locked(NULL, &sc->pch[i],
1459 PCMTRIG_STOP);
1460 }
1461 }
1462 for (i=0 ; i<sc->rch_cnt ; i++) {
1463 if (sc->rch[i].active) {
1464 m3_rchan_trigger_locked(NULL, &sc->rch[i],
1465 PCMTRIG_STOP);
1466 }
1467 }
1468 DELAY(10 * 1000); /* give things a chance to stop */
1469
1470 /* Disable interrupts */
1471 m3_wr_2(sc, HOST_INT_CTRL, 0);
1472 m3_wr_1(sc, ASSP_CONTROL_C, 0);
1473
1474 m3_assp_halt(sc);
1475
1476 /* Save the state of the ASSP */
1477 for (i = REV_B_CODE_MEMORY_BEGIN; i <= REV_B_CODE_MEMORY_END; i++)
1478 sc->savemem[index++] = m3_rd_assp_code(sc, i);
1479 for (i = REV_B_DATA_MEMORY_BEGIN; i <= REV_B_DATA_MEMORY_END; i++)
1480 sc->savemem[index++] = m3_rd_assp_data(sc, i);
1481
1482 /* Power down the card to D3 state */
1483 m3_power(sc, 3);
1484 M3_UNLOCK(sc);
1485
1486 return 0;
1487 }
1488
1489 static int
1490 m3_pci_resume(device_t dev)
1491 {
1492 struct sc_info *sc = pcm_getdevinfo(dev);
1493 int i, index = 0;
1494 u_int8_t reset_state;
1495
1496 M3_DEBUG(CHANGE, ("m3_pci_resume\n"));
1497
1498 M3_LOCK(sc);
1499 /* Power the card back to D0 */
1500 m3_power(sc, 0);
1501
1502 m3_config(sc);
1503
1504 reset_state = m3_assp_halt(sc);
1505
1506 m3_codec_reset(sc);
1507
1508 /* Restore the ASSP state */
1509 for (i = REV_B_CODE_MEMORY_BEGIN; i <= REV_B_CODE_MEMORY_END; i++)
1510 m3_wr_assp_code(sc, i, sc->savemem[index++]);
1511 for (i = REV_B_DATA_MEMORY_BEGIN; i <= REV_B_DATA_MEMORY_END; i++)
1512 m3_wr_assp_data(sc, i, sc->savemem[index++]);
1513
1514 /* Restart the DMA engine */
1515 m3_wr_assp_data(sc, KDATA_DMA_ACTIVE, 0);
1516
1517 /* [m3_assp_continue] */
1518 m3_wr_1(sc, DSP_PORT_CONTROL_REG_B, reset_state | REGB_ENABLE_RESET);
1519
1520 m3_amp_enable(sc);
1521
1522 m3_enable_ints(sc);
1523
1524 M3_UNLOCK(sc); /* XXX */
1525 if (mixer_reinit(dev) == -1) {
1526 device_printf(dev, "unable to reinitialize the mixer\n");
1527 return (ENXIO);
1528 }
1529 M3_LOCK(sc);
1530
1531 /* Turn the channels back on */
1532 for (i=0 ; i<sc->pch_cnt ; i++) {
1533 if (sc->pch[i].active) {
1534 m3_pchan_trigger_locked(NULL, &sc->pch[i],
1535 PCMTRIG_START);
1536 }
1537 }
1538 for (i=0 ; i<sc->rch_cnt ; i++) {
1539 if (sc->rch[i].active) {
1540 m3_rchan_trigger_locked(NULL, &sc->rch[i],
1541 PCMTRIG_START);
1542 }
1543 }
1544
1545 M3_UNLOCK(sc);
1546 return 0;
1547 }
1548
1549 static int
1550 m3_pci_shutdown(device_t dev)
1551 {
1552 struct sc_info *sc = pcm_getdevinfo(dev);
1553
1554 M3_DEBUG(CALL, ("m3_pci_shutdown\n"));
1555
1556 M3_LOCK(sc);
1557 m3_power(sc, 3); /* power off */
1558 M3_UNLOCK(sc);
1559
1560 return 0;
1561 }
1562
1563 static u_int8_t
1564 m3_assp_halt(struct sc_info *sc)
1565 {
1566 u_int8_t data, reset_state;
1567
1568 M3_LOCK_ASSERT(sc);
1569
1570 data = m3_rd_1(sc, DSP_PORT_CONTROL_REG_B);
1571 reset_state = data & ~REGB_STOP_CLOCK; /* remember for continue */
1572 DELAY(10 * 1000);
1573 m3_wr_1(sc, DSP_PORT_CONTROL_REG_B, reset_state & ~REGB_ENABLE_RESET);
1574 DELAY(10 * 1000); /* necessary? */
1575
1576 return reset_state;
1577 }
1578
1579 static void
1580 m3_config(struct sc_info *sc)
1581 {
1582 u_int32_t data, hv_cfg;
1583 int hint;
1584
1585 M3_LOCK_ASSERT(sc);
1586
1587 M3_UNLOCK(sc);
1588 /*
1589 * The volume buttons can be wired up via two different sets of pins.
1590 * This presents a problem since we can't tell which way it's
1591 * configured. Allow the user to set a hint in order to twiddle
1592 * the proper bits.
1593 */
1594 if (resource_int_value(device_get_name(sc->dev),
1595 device_get_unit(sc->dev),
1596 "hwvol_config", &hint) == 0)
1597 hv_cfg = (hint > 0) ? HV_BUTTON_FROM_GD : 0;
1598 else
1599 hv_cfg = HV_BUTTON_FROM_GD;
1600 M3_LOCK(sc);
1601
1602 data = pci_read_config(sc->dev, PCI_ALLEGRO_CONFIG, 4);
1603 data &= ~HV_BUTTON_FROM_GD;
1604 data |= REDUCED_DEBOUNCE | HV_CTRL_ENABLE | hv_cfg;
1605 data |= PM_CTRL_ENABLE | CLK_DIV_BY_49 | USE_PCI_TIMING;
1606 pci_write_config(sc->dev, PCI_ALLEGRO_CONFIG, data, 4);
1607
1608 m3_wr_1(sc, ASSP_CONTROL_B, RESET_ASSP);
1609 data = pci_read_config(sc->dev, PCI_ALLEGRO_CONFIG, 4);
1610 data &= ~INT_CLK_SELECT;
1611 if (sc->which == ESS_MAESTRO3) {
1612 data &= ~INT_CLK_MULT_ENABLE;
1613 data |= INT_CLK_SRC_NOT_PCI;
1614 }
1615 data &= ~(CLK_MULT_MODE_SELECT | CLK_MULT_MODE_SELECT_2);
1616 pci_write_config(sc->dev, PCI_ALLEGRO_CONFIG, data, 4);
1617
1618 if (sc->which == ESS_ALLEGRO_1) {
1619 data = pci_read_config(sc->dev, PCI_USER_CONFIG, 4);
1620 data |= IN_CLK_12MHZ_SELECT;
1621 pci_write_config(sc->dev, PCI_USER_CONFIG, data, 4);
1622 }
1623
1624 data = m3_rd_1(sc, ASSP_CONTROL_A);
1625 data &= ~(DSP_CLK_36MHZ_SELECT | ASSP_CLK_49MHZ_SELECT);
1626 data |= ASSP_CLK_49MHZ_SELECT; /*XXX assumes 49MHZ dsp XXX*/
1627 data |= ASSP_0_WS_ENABLE;
1628 m3_wr_1(sc, ASSP_CONTROL_A, data);
1629
1630 m3_wr_1(sc, ASSP_CONTROL_B, RUN_ASSP);
1631 }
1632
1633 static void
1634 m3_enable_ints(struct sc_info *sc)
1635 {
1636 u_int8_t data;
1637
1638 m3_wr_2(sc, HOST_INT_CTRL, ASSP_INT_ENABLE | HV_INT_ENABLE);
1639 data = m3_rd_1(sc, ASSP_CONTROL_C);
1640 m3_wr_1(sc, ASSP_CONTROL_C, data | ASSP_HOST_INT_ENABLE);
1641 }
1642
1643 static void
1644 m3_amp_enable(struct sc_info *sc)
1645 {
1646 u_int32_t gpo, polarity_port, polarity;
1647 u_int16_t data;
1648
1649 M3_LOCK_ASSERT(sc);
1650
1651 switch (sc->which) {
1652 case ESS_ALLEGRO_1:
1653 polarity_port = 0x1800;
1654 break;
1655 case ESS_MAESTRO3:
1656 polarity_port = 0x1100;
1657 break;
1658 default:
1659 panic("bad sc->which");
1660 }
1661 gpo = (polarity_port >> 8) & 0x0f;
1662 polarity = polarity_port >> 12;
1663 polarity = !polarity; /* enable */
1664 polarity = polarity << gpo;
1665 gpo = 1 << gpo;
1666 m3_wr_2(sc, GPIO_MASK, ~gpo);
1667 data = m3_rd_2(sc, GPIO_DIRECTION);
1668 m3_wr_2(sc, GPIO_DIRECTION, data | gpo);
1669 data = GPO_SECONDARY_AC97 | GPO_PRIMARY_AC97 | polarity;
1670 m3_wr_2(sc, GPIO_DATA, data);
1671 m3_wr_2(sc, GPIO_MASK, ~0);
1672 }
1673
1674 static void
1675 m3_codec_reset(struct sc_info *sc)
1676 {
1677 u_int16_t data, dir;
1678 int retry = 0;
1679
1680 M3_LOCK_ASSERT(sc);
1681 do {
1682 data = m3_rd_2(sc, GPIO_DIRECTION);
1683 dir = data | 0x10; /* assuming pci bus master? */
1684
1685 /* [[remote_codec_config]] */
1686 data = m3_rd_2(sc, RING_BUS_CTRL_B);
1687 m3_wr_2(sc, RING_BUS_CTRL_B, data & ~SECOND_CODEC_ID_MASK);
1688 data = m3_rd_2(sc, SDO_OUT_DEST_CTRL);
1689 m3_wr_2(sc, SDO_OUT_DEST_CTRL, data & ~COMMAND_ADDR_OUT);
1690 data = m3_rd_2(sc, SDO_IN_DEST_CTRL);
1691 m3_wr_2(sc, SDO_IN_DEST_CTRL, data & ~STATUS_ADDR_IN);
1692
1693 m3_wr_2(sc, RING_BUS_CTRL_A, IO_SRAM_ENABLE);
1694 DELAY(20);
1695
1696 m3_wr_2(sc, GPIO_DIRECTION, dir & ~GPO_PRIMARY_AC97);
1697 m3_wr_2(sc, GPIO_MASK, ~GPO_PRIMARY_AC97);
1698 m3_wr_2(sc, GPIO_DATA, 0);
1699 m3_wr_2(sc, GPIO_DIRECTION, dir | GPO_PRIMARY_AC97);
1700 DELAY(sc->delay1 * 1000); /*delay1 (ALLEGRO:50, MAESTRO3:20)*/
1701 m3_wr_2(sc, GPIO_DATA, GPO_PRIMARY_AC97);
1702 DELAY(5);
1703 m3_wr_2(sc, RING_BUS_CTRL_A, IO_SRAM_ENABLE |
1704 SERIAL_AC_LINK_ENABLE);
1705 m3_wr_2(sc, GPIO_MASK, ~0);
1706 DELAY(sc->delay2 * 1000); /*delay2 (ALLEGRO:800, MAESTRO3:500)*/
1707
1708 /* [[try read vendor]] */
1709 data = m3_rdcd(NULL, sc, 0x7c);
1710 if ((data == 0) || (data == 0xffff)) {
1711 retry++;
1712 if (retry > 3) {
1713 device_printf(sc->dev, "Codec reset failed\n");
1714 break;
1715 }
1716 device_printf(sc->dev, "Codec reset retry\n");
1717 } else retry = 0;
1718 } while (retry);
1719 }
1720
1721 static device_method_t m3_methods[] = {
1722 DEVMETHOD(device_probe, m3_pci_probe),
1723 DEVMETHOD(device_attach, m3_pci_attach),
1724 DEVMETHOD(device_detach, m3_pci_detach),
1725 DEVMETHOD(device_suspend, m3_pci_suspend),
1726 DEVMETHOD(device_resume, m3_pci_resume),
1727 DEVMETHOD(device_shutdown, m3_pci_shutdown),
1728 { 0, 0 }
1729 };
1730
1731 static driver_t m3_driver = {
1732 "pcm",
1733 m3_methods,
1734 PCM_SOFTC_SIZE,
1735 };
1736
1737 DRIVER_MODULE(snd_maestro3, pci, m3_driver, pcm_devclass, NULL, NULL);
1738 MODULE_DEPEND(snd_maestro3, sound, SOUND_MINVER, SOUND_PREFVER, SOUND_MAXVER);
1739 MODULE_VERSION(snd_maestro3, 1);
DragonFly BSD