2 * Copyright (c) 2002-2004 M. Warner Losh.
3 * Copyright (c) 2000-2001 Jonathan Chen.
6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions
9 * 1. Redistributions of source code must retain the above copyright
10 * notice, this list of conditions and the following disclaimer.
11 * 2. Redistributions in binary form must reproduce the above copyright
12 * notice, this list of conditions and the following disclaimer in the
13 * documentation and/or other materials provided with the distribution.
15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
16 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
17 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
18 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
19 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
20 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
21 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
22 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
23 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
24 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
27 * $FreeBSD: src/sys/dev/pccbb/pccbb_pci.c,v 1.15 2005/10/08 06:58:51 imp Exp $
28 * $DragonFly: src/sys/dev/pccard/pccbb/pccbb_pci.c,v 1.2 2007/08/14 14:58:44 sephe Exp $
32 * Copyright (c) 1998, 1999 and 2000
33 * HAYAKAWA Koichi. All rights reserved.
35 * Redistribution and use in source and binary forms, with or without
36 * modification, are permitted provided that the following conditions
38 * 1. Redistributions of source code must retain the above copyright
39 * notice, this list of conditions and the following disclaimer.
40 * 2. Redistributions in binary form must reproduce the above copyright
41 * notice, this list of conditions and the following disclaimer in the
42 * documentation and/or other materials provided with the distribution.
43 * 3. All advertising materials mentioning features or use of this software
44 * must display the following acknowledgement:
45 * This product includes software developed by HAYAKAWA Koichi.
46 * 4. The name of the author may not be used to endorse or promote products
47 * derived from this software without specific prior written permission.
49 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
50 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
51 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
52 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
53 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
54 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
55 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
56 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
57 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
58 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
62 * Driver for PCI to CardBus Bridge chips
66 * http://www-s.ti.com/cgi-bin/sc/generic2.cgi?family=PCI+CARDBUS+CONTROLLERS
68 * Written by Jonathan Chen <jon@freebsd.org>
69 * The author would like to acknowledge:
70 * * HAYAKAWA Koichi: Author of the NetBSD code for the same thing
71 * * Warner Losh: Newbus/newcard guru and author of the pccard side of things
72 * * YAMAMOTO Shigeru: Author of another FreeBSD cardbus driver
73 * * David Cross: Author of the initial ugly hack for a specific cardbus card
78 #include <sys/param.h>
79 #include <sys/systm.h>
81 #include <sys/errno.h>
82 #include <sys/kernel.h>
84 #include <sys/malloc.h>
85 #include <sys/sysctl.h>
86 #include <sys/kthread.h>
89 #include <sys/module.h>
91 #include <bus/pci/pcireg.h>
92 #include <bus/pci/pcivar.h>
93 #include <machine/clock.h>
95 #include <bus/pccard/pccardreg.h>
96 #include <bus/pccard/pccardvar.h>
98 #include <dev/pccard/exca/excareg.h>
99 #include <dev/pccard/exca/excavar.h>
101 #include <dev/pccard/pccbb/pccbbreg.h>
102 #include <dev/pccard/pccbb/pccbbvar.h>
104 #include "power_if.h"
108 #define DPRINTF(x) do { if (cbb_debug) kprintf x; } while (0)
109 #define DEVPRINTF(x) do { if (cbb_debug) device_printf x; } while (0)
111 #define PCI_MASK_CONFIG(DEV,REG,MASK,SIZE) \
112 pci_write_config(DEV, REG, pci_read_config(DEV, REG, SIZE) MASK, SIZE)
113 #define PCI_MASK2_CONFIG(DEV,REG,MASK1,MASK2,SIZE) \
114 pci_write_config(DEV, REG, ( \
115 pci_read_config(DEV, REG, SIZE) MASK1) MASK2, SIZE)
117 static void cbb_chipinit(struct cbb_softc
*sc
);
119 static struct yenta_chipinfo
{
124 /* Texas Instruments chips */
125 {PCIC_ID_TI1031
, "TI1031 PCI-PC Card Bridge", CB_TI113X
},
126 {PCIC_ID_TI1130
, "TI1130 PCI-CardBus Bridge", CB_TI113X
},
127 {PCIC_ID_TI1131
, "TI1131 PCI-CardBus Bridge", CB_TI113X
},
129 {PCIC_ID_TI1210
, "TI1210 PCI-CardBus Bridge", CB_TI12XX
},
130 {PCIC_ID_TI1211
, "TI1211 PCI-CardBus Bridge", CB_TI12XX
},
131 {PCIC_ID_TI1220
, "TI1220 PCI-CardBus Bridge", CB_TI12XX
},
132 {PCIC_ID_TI1221
, "TI1221 PCI-CardBus Bridge", CB_TI12XX
},
133 {PCIC_ID_TI1225
, "TI1225 PCI-CardBus Bridge", CB_TI12XX
},
134 {PCIC_ID_TI1250
, "TI1250 PCI-CardBus Bridge", CB_TI125X
},
135 {PCIC_ID_TI1251
, "TI1251 PCI-CardBus Bridge", CB_TI125X
},
136 {PCIC_ID_TI1251B
,"TI1251B PCI-CardBus Bridge",CB_TI125X
},
137 {PCIC_ID_TI1260
, "TI1260 PCI-CardBus Bridge", CB_TI12XX
},
138 {PCIC_ID_TI1260B
,"TI1260B PCI-CardBus Bridge",CB_TI12XX
},
139 {PCIC_ID_TI1410
, "TI1410 PCI-CardBus Bridge", CB_TI12XX
},
140 {PCIC_ID_TI1420
, "TI1420 PCI-CardBus Bridge", CB_TI12XX
},
141 {PCIC_ID_TI1421
, "TI1421 PCI-CardBus Bridge", CB_TI12XX
},
142 {PCIC_ID_TI1450
, "TI1450 PCI-CardBus Bridge", CB_TI125X
}, /*SIC!*/
143 {PCIC_ID_TI1451
, "TI1451 PCI-CardBus Bridge", CB_TI12XX
},
144 {PCIC_ID_TI1510
, "TI1510 PCI-CardBus Bridge", CB_TI12XX
},
145 {PCIC_ID_TI1520
, "TI1520 PCI-CardBus Bridge", CB_TI12XX
},
146 {PCIC_ID_TI4410
, "TI4410 PCI-CardBus Bridge", CB_TI12XX
},
147 {PCIC_ID_TI4450
, "TI4450 PCI-CardBus Bridge", CB_TI12XX
},
148 {PCIC_ID_TI4451
, "TI4451 PCI-CardBus Bridge", CB_TI12XX
},
149 {PCIC_ID_TI4510
, "TI4510 PCI-CardBus Bridge", CB_TI12XX
},
150 {PCIC_ID_TI6411
, "TI6411 PCI-CardBus Bridge", CB_TI12XX
},
151 {PCIC_ID_TI6420
, "TI6420 PCI-CardBus Bridge", CB_TI12XX
},
152 {PCIC_ID_TI6420SC
, "TI6420 PCI-CardBus Bridge", CB_TI12XX
},
153 {PCIC_ID_TI7410
, "TI7410 PCI-CardBus Bridge", CB_TI12XX
},
154 {PCIC_ID_TI7510
, "TI7510 PCI-CardBus Bridge", CB_TI12XX
},
155 {PCIC_ID_TI7610
, "TI7610 PCI-CardBus Bridge", CB_TI12XX
},
156 {PCIC_ID_TI7610M
, "TI7610 PCI-CardBus Bridge", CB_TI12XX
},
157 {PCIC_ID_TI7610SD
, "TI7610 PCI-CardBus Bridge", CB_TI12XX
},
158 {PCIC_ID_TI7610MS
, "TI7610 PCI-CardBus Bridge", CB_TI12XX
},
161 {PCIC_ID_ENE_CB710
, "ENE CB710 PCI-CardBus Bridge", CB_TI12XX
},
162 {PCIC_ID_ENE_CB720
, "ENE CB720 PCI-CardBus Bridge", CB_TI12XX
},
163 {PCIC_ID_ENE_CB1211
, "ENE CB1211 PCI-CardBus Bridge", CB_TI12XX
},
164 {PCIC_ID_ENE_CB1225
, "ENE CB1225 PCI-CardBus Bridge", CB_TI12XX
},
165 {PCIC_ID_ENE_CB1410
, "ENE CB1410 PCI-CardBus Bridge", CB_TI12XX
},
166 {PCIC_ID_ENE_CB1420
, "ENE CB1420 PCI-CardBus Bridge", CB_TI12XX
},
169 {PCIC_ID_RICOH_RL5C465
, "RF5C465 PCI-CardBus Bridge", CB_RF5C46X
},
170 {PCIC_ID_RICOH_RL5C466
, "RF5C466 PCI-CardBus Bridge", CB_RF5C46X
},
171 {PCIC_ID_RICOH_RL5C475
, "RF5C475 PCI-CardBus Bridge", CB_RF5C47X
},
172 {PCIC_ID_RICOH_RL5C476
, "RF5C476 PCI-CardBus Bridge", CB_RF5C47X
},
173 {PCIC_ID_RICOH_RL5C477
, "RF5C477 PCI-CardBus Bridge", CB_RF5C47X
},
174 {PCIC_ID_RICOH_RL5C478
, "RF5C478 PCI-CardBus Bridge", CB_RF5C47X
},
176 /* Toshiba products */
177 {PCIC_ID_TOPIC95
, "ToPIC95 PCI-CardBus Bridge", CB_TOPIC95
},
178 {PCIC_ID_TOPIC95B
, "ToPIC95B PCI-CardBus Bridge", CB_TOPIC95
},
179 {PCIC_ID_TOPIC97
, "ToPIC97 PCI-CardBus Bridge", CB_TOPIC97
},
180 {PCIC_ID_TOPIC100
, "ToPIC100 PCI-CardBus Bridge", CB_TOPIC97
},
183 {PCIC_ID_CLPD6832
, "CLPD6832 PCI-CardBus Bridge", CB_CIRRUS
},
184 {PCIC_ID_CLPD6833
, "CLPD6833 PCI-CardBus Bridge", CB_CIRRUS
},
185 {PCIC_ID_CLPD6834
, "CLPD6834 PCI-CardBus Bridge", CB_CIRRUS
},
188 {PCIC_ID_OZ6832
, "O2Micro OZ6832/6833 PCI-CardBus Bridge", CB_O2MICRO
},
189 {PCIC_ID_OZ6860
, "O2Micro OZ6836/6860 PCI-CardBus Bridge", CB_O2MICRO
},
190 {PCIC_ID_OZ6872
, "O2Micro OZ6812/6872 PCI-CardBus Bridge", CB_O2MICRO
},
191 {PCIC_ID_OZ6912
, "O2Micro OZ6912/6972 PCI-CardBus Bridge", CB_O2MICRO
},
192 {PCIC_ID_OZ6922
, "O2Micro OZ6922 PCI-CardBus Bridge", CB_O2MICRO
},
193 {PCIC_ID_OZ6933
, "O2Micro OZ6933 PCI-CardBus Bridge", CB_O2MICRO
},
194 {PCIC_ID_OZ711E1
, "O2Micro OZ711E1 PCI-CardBus Bridge", CB_O2MICRO
},
195 {PCIC_ID_OZ711EC1
, "O2Micro OZ711EC1/M1 PCI-CardBus Bridge", CB_O2MICRO
},
196 {PCIC_ID_OZ711E2
, "O2Micro OZ711E2 PCI-CardBus Bridge", CB_O2MICRO
},
197 {PCIC_ID_OZ711M1
, "O2Micro OZ711M1 PCI-CardBus Bridge", CB_O2MICRO
},
198 {PCIC_ID_OZ711M2
, "O2Micro OZ711M2 PCI-CardBus Bridge", CB_O2MICRO
},
199 {PCIC_ID_OZ711M3
, "O2Micro OZ711M3 PCI-CardBus Bridge", CB_O2MICRO
},
202 {PCIC_ID_SMC_34C90
, "SMC 34C90 PCI-CardBus Bridge", CB_CIRRUS
},
205 {0 /* null id */, "unknown", CB_UNKNOWN
},
208 /************************************************************************/
210 /************************************************************************/
213 cbb_chipset(uint32_t pci_id
, const char **namep
)
215 struct yenta_chipinfo
*ycp
;
217 for (ycp
= yc_chipsets
; ycp
->yc_id
!= 0 && pci_id
!= ycp
->yc_id
; ++ycp
)
220 *namep
= ycp
->yc_name
;
221 return (ycp
->yc_chiptype
);
225 cbb_pci_probe(device_t brdev
)
228 uint8_t progif
, subclass
, class;
231 * Do we know that we support the chipset? If so, then we
234 if (cbb_chipset(pci_get_devid(brdev
), &name
) != CB_UNKNOWN
) {
235 device_set_desc(brdev
, name
);
240 * We do support generic CardBus bridges. All that we've seen
241 * to date have progif 0 (the Yenta spec, and successors mandate
244 class = pci_get_class(brdev
);
245 subclass
= pci_get_subclass(brdev
);
246 progif
= pci_get_progif(brdev
);
247 if (class == PCIC_BRIDGE
&& subclass
== PCIS_BRIDGE_CARDBUS
&&
249 device_set_desc(brdev
, "PCI-CardBus Bridge");
256 * Still need this because the pci code only does power for type 0
260 cbb_powerstate_d0(device_t dev
)
262 u_int32_t membase
, irq
;
264 if (pci_get_powerstate(dev
) != PCI_POWERSTATE_D0
) {
265 /* Save important PCI config data. */
266 membase
= pci_read_config(dev
, CBBR_SOCKBASE
, 4);
267 irq
= pci_read_config(dev
, PCIR_INTLINE
, 4);
269 /* Reset the power state. */
270 device_printf(dev
, "chip is in D%d power mode "
271 "-- setting to D0\n", pci_get_powerstate(dev
));
273 pci_set_powerstate(dev
, PCI_POWERSTATE_D0
);
275 /* Restore PCI config data. */
276 pci_write_config(dev
, CBBR_SOCKBASE
, membase
, 4);
277 pci_write_config(dev
, PCIR_INTLINE
, irq
, 4);
282 * Print out the config space
285 cbb_print_config(device_t dev
)
289 device_printf(dev
, "PCI Configuration space:");
290 for (i
= 0; i
< 256; i
+= 4) {
292 kprintf("\n 0x%02x: ", i
);
293 kprintf("0x%08x ", pci_read_config(dev
, i
, 4));
299 cbb_pci_attach(device_t brdev
)
301 static int curr_bus_number
= 2; /* XXX EVILE BAD (see below) */
302 struct cbb_softc
*sc
= device_get_softc(brdev
);
303 int rid
, bus
, pribus
;
304 device_t parent
, grand_parent
;
306 parent
= device_get_parent(brdev
);
307 grand_parent
= device_get_parent(parent
);
309 sc
->chipset
= cbb_chipset(pci_get_devid(brdev
), NULL
);
312 sc
->exca
[0].pccarddev
= NULL
;
313 sc
->secbus
= pci_read_config(brdev
, PCIR_SECBUS_2
, 1);
314 sc
->subbus
= pci_read_config(brdev
, PCIR_SUBBUS_2
, 1);
316 cbb_powerstate_d0(brdev
);
319 sc
->base_res
= bus_alloc_resource_any(brdev
, SYS_RES_MEMORY
, &rid
,
322 #ifndef PCI_MAP_FIXUP
326 * Generally, the BIOS will assign this memory for us.
327 * However, newer BIOSes do not because the MS design
328 * documents have mandated that this is for the OS
329 * to assign rather than the BIOS. This driver shouldn't
330 * be doing this, but until the pci bus code (or acpi)
331 * does this, we allow CardBus bridges to work on more
334 pci_write_config(brdev
, rid
, 0xffffffff, 4);
335 sockbase
= pci_read_config(brdev
, rid
, 4);
336 sockbase
= (sockbase
& 0xfffffff0) & -(sockbase
& 0xfffffff0);
337 sc
->base_res
= bus_generic_alloc_resource(
338 device_get_parent(brdev
), brdev
, SYS_RES_MEMORY
,
339 &rid
, 0x88000000, ~0, sockbase
,
340 RF_ACTIVE
| rman_make_alignment_flags(sockbase
));
343 "Could not grab register memory\n");
346 pci_write_config(brdev
, CBBR_SOCKBASE
,
347 rman_get_start(sc
->base_res
), 4);
348 #else /* PCI_MAP_FIXUP */
349 device_printf(brdev
, "Could not grab register memory\n");
351 #endif /* !PCI_MAP_FIXUP */
353 DEVPRINTF((brdev
, "Found memory at %08lx\n",
354 rman_get_start(sc
->base_res
)));
357 sc
->bst
= rman_get_bustag(sc
->base_res
);
358 sc
->bsh
= rman_get_bushandle(sc
->base_res
);
359 exca_init(&sc
->exca
[0], brdev
, sc
->bst
, sc
->bsh
, CBB_EXCA_OFFSET
);
360 sc
->exca
[0].flags
|= EXCA_HAS_MEMREG_WIN
;
361 sc
->exca
[0].chipset
= EXCA_CARDBUS
;
362 sc
->chipinit
= cbb_chipinit
;
366 * This is a gross hack. We should be scanning the entire pci
367 * tree, assigning bus numbers in a way such that we (1) can
368 * reserve 1 extra bus just in case and (2) all sub busses
369 * are in an appropriate range.
371 bus
= pci_read_config(brdev
, PCIR_SECBUS_2
, 1);
372 pribus
= pcib_get_bus(grand_parent
);
373 DEVPRINTF((brdev
, "Secondary bus is %d\n", bus
));
375 if (curr_bus_number
<= pribus
)
376 curr_bus_number
= pribus
+ 1;
377 if (pci_read_config(brdev
, PCIR_PRIBUS_2
, 1) != pribus
) {
378 DEVPRINTF((brdev
, "Setting primary bus to %d\n", pribus
));
379 pci_write_config(brdev
, PCIR_PRIBUS_2
, pribus
, 1);
381 bus
= curr_bus_number
;
382 DEVPRINTF((brdev
, "Secondary bus set to %d subbus %d\n", bus
,
385 sc
->subbus
= bus
+ 1;
386 pci_write_config(brdev
, PCIR_SECBUS_2
, bus
, 1);
387 pci_write_config(brdev
, PCIR_SUBBUS_2
, bus
+ 1, 1);
388 curr_bus_number
+= 2;
391 /* attach children */
392 sc
->cbdev
= device_add_child(brdev
, "cardbus", -1);
393 if (sc
->cbdev
== NULL
)
394 DEVPRINTF((brdev
, "WARNING: cannot add cardbus bus.\n"));
395 else if (device_probe_and_attach(sc
->cbdev
) != 0)
396 DEVPRINTF((brdev
, "WARNING: cannot attach cardbus bus!\n"));
398 sc
->exca
[0].pccarddev
= device_add_child(brdev
, "pccard", -1);
399 if (sc
->exca
[0].pccarddev
== NULL
)
400 DEVPRINTF((brdev
, "WARNING: cannot add pccard bus.\n"));
401 else if (device_probe_and_attach(sc
->exca
[0].pccarddev
) != 0)
402 DEVPRINTF((brdev
, "WARNING: cannot attach pccard bus.\n"));
404 /* Map and establish the interrupt. */
406 sc
->irq_res
= bus_alloc_resource_any(brdev
, SYS_RES_IRQ
, &rid
,
407 RF_SHAREABLE
| RF_ACTIVE
);
408 if (sc
->irq_res
== NULL
) {
409 kprintf("cbb: Unable to map IRQ...\n");
413 if (bus_setup_intr(brdev
, sc
->irq_res
, INTR_MPSAFE
, cbb_intr
, sc
,
414 &sc
->intrhand
, NULL
)) {
415 device_printf(brdev
, "couldn't establish interrupt");
419 /* reset 16-bit pcmcia bus */
420 exca_clrb(&sc
->exca
[0], EXCA_INTR
, EXCA_INTR_RESET
);
423 cbb_power(brdev
, CARD_OFF
);
425 /* CSC Interrupt: Card detect interrupt on */
426 cbb_setb(sc
, CBB_SOCKET_MASK
, CBB_SOCKET_MASK_CD
);
428 /* reset interrupt */
429 cbb_set(sc
, CBB_SOCKET_EVENT
, cbb_get(sc
, CBB_SOCKET_EVENT
));
432 cbb_print_config(brdev
);
434 /* Start the thread */
435 if (kthread_create(cbb_event_thread
, sc
, &sc
->event_thread
,
436 "%s", device_get_nameunit(brdev
))) {
437 device_printf(brdev
, "unable to create event thread.\n");
438 panic("cbb_create_event_thread");
443 bus_release_resource(brdev
, SYS_RES_IRQ
, 0, sc
->irq_res
);
445 bus_release_resource(brdev
, SYS_RES_MEMORY
, CBBR_SOCKBASE
,
452 cbb_chipinit(struct cbb_softc
*sc
)
454 uint32_t mux
, sysctrl
, reg
;
456 /* Set CardBus latency timer */
457 if (pci_read_config(sc
->dev
, PCIR_SECLAT_1
, 1) < 0x20)
458 pci_write_config(sc
->dev
, PCIR_SECLAT_1
, 0x20, 1);
460 /* Set PCI latency timer */
461 if (pci_read_config(sc
->dev
, PCIR_LATTIMER
, 1) < 0x20)
462 pci_write_config(sc
->dev
, PCIR_LATTIMER
, 0x20, 1);
464 /* Enable memory access */
465 PCI_MASK_CONFIG(sc
->dev
, PCIR_COMMAND
,
468 | PCIM_CMD_BUSMASTEREN
, 2);
470 /* disable Legacy IO */
471 switch (sc
->chipset
) {
473 PCI_MASK_CONFIG(sc
->dev
, CBBR_BRIDGECTRL
,
474 & ~(CBBM_BRIDGECTRL_RL_3E0_EN
|
475 CBBM_BRIDGECTRL_RL_3E2_EN
), 2);
478 pci_write_config(sc
->dev
, CBBR_LEGACY
, 0x0, 4);
482 /* Use PCI interrupt for interrupt routing */
483 PCI_MASK2_CONFIG(sc
->dev
, CBBR_BRIDGECTRL
,
484 & ~(CBBM_BRIDGECTRL_MASTER_ABORT
|
485 CBBM_BRIDGECTRL_INTR_IREQ_ISA_EN
),
486 | CBBM_BRIDGECTRL_WRITE_POST_EN
,
490 * XXX this should be a function table, ala OLDCARD. This means
491 * that we could more easily support ISA interrupts for pccard
492 * cards if we had to.
494 switch (sc
->chipset
) {
497 * The TI 1031, TI 1130 and TI 1131 all require another bit
498 * be set to enable PCI routing of interrupts, and then
499 * a bit for each of the CSC and Function interrupts we
502 PCI_MASK_CONFIG(sc
->dev
, CBBR_CBCTRL
,
503 | CBBM_CBCTRL_113X_PCI_INTR
|
504 CBBM_CBCTRL_113X_PCI_CSC
| CBBM_CBCTRL_113X_PCI_IRQ_EN
,
506 PCI_MASK_CONFIG(sc
->dev
, CBBR_DEVCTRL
,
507 & ~(CBBM_DEVCTRL_INT_SERIAL
|
508 CBBM_DEVCTRL_INT_PCI
), 1);
512 * Some TI 12xx (and [14][45]xx) based pci cards
513 * sometimes have issues with the MFUNC register not
514 * being initialized due to a bad EEPROM on board.
515 * Laptops that this matters on have this register
516 * properly initialized.
518 * The TI125X parts have a different register.
520 mux
= pci_read_config(sc
->dev
, CBBR_MFUNC
, 4);
521 sysctrl
= pci_read_config(sc
->dev
, CBBR_SYSCTRL
, 4);
523 mux
= (mux
& ~CBBM_MFUNC_PIN0
) |
524 CBBM_MFUNC_PIN0_INTA
;
525 if ((sysctrl
& CBBM_SYSCTRL_INTRTIE
) == 0)
526 mux
= (mux
& ~CBBM_MFUNC_PIN1
) |
527 CBBM_MFUNC_PIN1_INTB
;
528 pci_write_config(sc
->dev
, CBBR_MFUNC
, mux
, 4);
533 * Disable zoom video. Some machines initialize this
534 * improperly and exerpience has shown that this helps
535 * prevent strange behavior.
537 pci_write_config(sc
->dev
, CBBR_MMCTRL
, 0, 4);
541 * Issue #1: INT# generated at the same time as
542 * selected ISA IRQ. When IREQ# or STSCHG# is active,
543 * in addition to the ISA IRQ being generated, INT#
544 * will also be generated at the same time.
546 * Some of the older controllers have an issue in
547 * which the slot's PCI INT# will be asserted whenever
548 * IREQ# or STSCGH# is asserted even if ExCA registers
549 * 03h or 05h have an ISA IRQ selected.
551 * The fix for this issue, which will work for any
552 * controller (old or new), is to set ExCA registers
553 * 3Ah (slot 0) & 7Ah (slot 1) bits 7:4 = 1010b.
554 * These bits are undocumented. By setting this
555 * register (of each slot) to '1010xxxxb' a routing of
556 * IREQ# to INTC# and STSCHG# to INTC# is selected.
557 * Since INTC# isn't connected there will be no
558 * unexpected PCI INT when IREQ# or STSCHG# is active.
559 * However, INTA# (slot 0) or INTB# (slot 1) will
560 * still be correctly generated if NO ISA IRQ is
561 * selected (ExCA regs 03h or 05h are cleared).
563 reg
= exca_getb(&sc
->exca
[0], EXCA_O2MICRO_CTRL_C
);
565 EXCA_O2CC_IREQ_INTC
| EXCA_O2CC_STSCHG_INTC
;
566 exca_putb(&sc
->exca
[0], EXCA_O2MICRO_CTRL_C
, reg
);
571 * Disable Zoom Video, ToPIC 97, 100.
573 pci_write_config(sc
->dev
, CBBR_TOPIC_ZV_CONTROL
, 0, 1);
576 * At offset 0xa1: INTERRUPT CONTROL register
577 * 0x1: Turn on INT interrupts.
579 PCI_MASK_CONFIG(sc
->dev
, CBBR_TOPIC_INTCTRL
,
580 | CBBM_TOPIC_INTCTRL_INTIRQSEL
, 1);
584 * SOCKETCTRL appears to be TOPIC 95/B specific
586 PCI_MASK_CONFIG(sc
->dev
, CBBR_TOPIC_SOCKETCTRL
,
587 | CBBM_TOPIC_SOCKETCTRL_SCR_IRQSEL
, 4);
591 * At offset 0xa0: SLOT CONTROL
592 * 0x80 Enable CardBus Functionality
593 * 0x40 Enable CardBus and PC Card registers
594 * 0x20 Lock ID in exca regs
595 * 0x10 Write protect ID in config regs
596 * Clear the rest of the bits, which defaults the slot
597 * in legacy mode to 0x3e0 and offset 0. (legacy
598 * mode is determined elsewhere)
600 pci_write_config(sc
->dev
, CBBR_TOPIC_SLOTCTRL
,
601 CBBM_TOPIC_SLOTCTRL_SLOTON
|
602 CBBM_TOPIC_SLOTCTRL_SLOTEN
|
603 CBBM_TOPIC_SLOTCTRL_ID_LOCK
|
604 CBBM_TOPIC_SLOTCTRL_ID_WP
, 1);
607 * At offset 0xa3 Card Detect Control Register
608 * 0x80 CARDBUS enbale
609 * 0x01 Cleared for hardware change detect
611 PCI_MASK2_CONFIG(sc
->dev
, CBBR_TOPIC_CDC
,
612 | CBBM_TOPIC_CDC_CARDBUS
,
613 & ~CBBM_TOPIC_CDC_SWDETECT
, 4);
618 * Need to tell ExCA registers to CSC interrupts route via PCI
619 * interrupts. There are two ways to do this. Once is to set
620 * INTR_ENABLE and the other is to set CSC to 0. Since both
621 * methods are mutually compatible, we do both.
623 exca_putb(&sc
->exca
[0], EXCA_INTR
, EXCA_INTR_ENABLE
);
624 exca_putb(&sc
->exca
[0], EXCA_CSC_INTR
, 0);
626 cbb_disable_func_intr(sc
);
628 /* close all memory and io windows */
629 pci_write_config(sc
->dev
, CBBR_MEMBASE0
, 0xffffffff, 4);
630 pci_write_config(sc
->dev
, CBBR_MEMLIMIT0
, 0, 4);
631 pci_write_config(sc
->dev
, CBBR_MEMBASE1
, 0xffffffff, 4);
632 pci_write_config(sc
->dev
, CBBR_MEMLIMIT1
, 0, 4);
633 pci_write_config(sc
->dev
, CBBR_IOBASE0
, 0xffffffff, 4);
634 pci_write_config(sc
->dev
, CBBR_IOLIMIT0
, 0, 4);
635 pci_write_config(sc
->dev
, CBBR_IOBASE1
, 0xffffffff, 4);
636 pci_write_config(sc
->dev
, CBBR_IOLIMIT1
, 0, 4);
640 cbb_route_interrupt(device_t pcib
, device_t dev
, int pin
)
642 struct cbb_softc
*sc
= (struct cbb_softc
*)device_get_softc(pcib
);
644 return (rman_get_start(sc
->irq_res
));
647 static device_method_t cbb_methods
[] = {
648 /* Device interface */
649 DEVMETHOD(device_probe
, cbb_pci_probe
),
650 DEVMETHOD(device_attach
, cbb_pci_attach
),
651 DEVMETHOD(device_detach
, cbb_detach
),
652 DEVMETHOD(device_shutdown
, cbb_shutdown
),
653 DEVMETHOD(device_suspend
, cbb_suspend
),
654 DEVMETHOD(device_resume
, cbb_resume
),
657 DEVMETHOD(bus_print_child
, bus_generic_print_child
),
658 DEVMETHOD(bus_read_ivar
, cbb_read_ivar
),
659 DEVMETHOD(bus_write_ivar
, cbb_write_ivar
),
660 DEVMETHOD(bus_alloc_resource
, cbb_alloc_resource
),
661 DEVMETHOD(bus_release_resource
, cbb_release_resource
),
662 DEVMETHOD(bus_activate_resource
, cbb_activate_resource
),
663 DEVMETHOD(bus_deactivate_resource
, cbb_deactivate_resource
),
664 DEVMETHOD(bus_driver_added
, cbb_driver_added
),
665 DEVMETHOD(bus_child_detached
, cbb_child_detached
),
666 DEVMETHOD(bus_setup_intr
, cbb_setup_intr
),
667 DEVMETHOD(bus_teardown_intr
, cbb_teardown_intr
),
668 DEVMETHOD(bus_child_present
, cbb_child_present
),
670 /* 16-bit card interface */
671 DEVMETHOD(card_set_res_flags
, cbb_pcic_set_res_flags
),
672 DEVMETHOD(card_set_memory_offset
, cbb_pcic_set_memory_offset
),
674 /* power interface */
675 DEVMETHOD(power_enable_socket
, cbb_power_enable_socket
),
676 DEVMETHOD(power_disable_socket
, cbb_power_disable_socket
),
678 /* pcib compatibility interface */
679 DEVMETHOD(pcib_maxslots
, cbb_maxslots
),
680 DEVMETHOD(pcib_read_config
, cbb_read_config
),
681 DEVMETHOD(pcib_write_config
, cbb_write_config
),
682 DEVMETHOD(pcib_route_interrupt
, cbb_route_interrupt
),
687 static driver_t cbb_driver
= {
690 sizeof(struct cbb_softc
)
693 DRIVER_MODULE(cbb
, pci
, cbb_driver
, cbb_devclass
, 0, 0);
694 MODULE_DEPEND(cbb
, exca
, 1, 1, 1);