sys/bus/pci/pcivar.h

   1 /*-
   2  * Copyright (c) 1997, Stefan Esser <se@freebsd.org>
   3  * All rights reserved.
   4  *
   5  * Redistribution and use in source and binary forms, with or without
   6  * modification, are permitted provided that the following conditions
   7  * are met:
   8  * 1. Redistributions of source code must retain the above copyright
   9  *    notice unmodified, this list of conditions, and the following
  10  *    disclaimer.
  11  * 2. Redistributions in binary form must reproduce the above copyright
  12  *    notice, this list of conditions and the following disclaimer in the
  13  *    documentation and/or other materials provided with the distribution.
  14  *
  15  * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
  16  * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
  17  * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
  18  * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
  19  * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
  20  * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  21  * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  22  * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  23  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
  24  * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  25  *
  26  * $FreeBSD: src/sys/dev/pci/pcivar.h,v 1.80.2.1.4.1 2009/04/15 03:14:26 kensmith Exp $
  27  */
  28
  29 #ifndef _PCIVAR_H_
  30 #define _PCIVAR_H_
  31
  32 #ifndef _SYS_QUEUE_H_
  33 #include <sys/queue.h>
  34 #endif
  35
  36 /* some PCI bus constants */
  37
  38 #define PCI_DOMAINMAX   65535   /* highest supported domain number */
  39 #define PCI_BUSMAX      255     /* highest supported bus number */
  40 #define PCI_SLOTMAX     31      /* highest supported slot number */
  41 #define PCI_FUNCMAX     7       /* highest supported function number */
  42 #define PCI_REGMAX      255     /* highest supported config register addr. */
  43
  44 #define PCI_MAXMAPS_0   6       /* max. no. of memory/port maps */
  45 #define PCI_MAXMAPS_1   2       /* max. no. of maps for PCI to PCI bridge */
  46 #define PCI_MAXMAPS_2   1       /* max. no. of maps for CardBus bridge */
  47
  48 typedef uint64_t pci_addr_t;
  49
  50 /* Interesting values for PCI power management */
  51 struct pcicfg_pp {
  52     uint16_t    pp_cap;         /* PCI power management capabilities */
  53     uint8_t     pp_status;      /* config space address of PCI power status reg */
  54     uint8_t     pp_pmcsr;       /* config space address of PMCSR reg */
  55     uint8_t     pp_data;        /* config space address of PCI power data reg */
  56 };
  57
  58 struct vpd_readonly {
  59     char        keyword[2];
  60     char        *value;
  61 };
  62
  63 struct vpd_write {
  64     char        keyword[2];
  65     char        *value;
  66     int         start;
  67     int         len;
  68 };
  69
  70 struct pcicfg_vpd {
  71     uint8_t     vpd_reg;        /* base register, + 2 for addr, + 4 data */
  72     char        vpd_cached;
  73     char        *vpd_ident;     /* string identifier */
  74     int         vpd_rocnt;
  75     struct vpd_readonly *vpd_ros;
  76     int         vpd_wcnt;
  77     struct vpd_write *vpd_w;
  78 };
  79
  80 /* Interesting values for PCI MSI */
  81 struct pcicfg_msi {
  82     uint16_t    msi_ctrl;       /* Message Control */
  83     uint8_t     msi_location;   /* Offset of MSI capability registers. */
  84     uint8_t     msi_msgnum;     /* Number of messages */
  85     int         msi_alloc;      /* Number of allocated messages. */
  86     uint64_t    msi_addr;       /* Contents of address register. */
  87     uint16_t    msi_data;       /* Contents of data register. */
  88     u_int       msi_handlers;
  89 };
  90
  91 /* Interesting values for PCI MSI-X */
  92 struct msix_vector {
  93     TAILQ_ENTRY(msix_vector) mv_link;
  94     uint64_t    mv_address;     /* Contents of address register. */
  95     uint32_t    mv_data;        /* Contents of data register. */
  96     int         mv_rid;
  97 };
  98 TAILQ_HEAD(msix_vectorlist, msix_vector);
  99
 100 struct pcicfg_msix {
 101     uint16_t    msix_ctrl;      /* Message Control */
 102     uint16_t    msix_msgnum;    /* Number of messages */
 103     uint8_t     msix_location;  /* Offset of MSI-X capability registers. */
 104     uint8_t     msix_table_bar; /* BAR containing vector table. */
 105     uint8_t     msix_pba_bar;   /* BAR containing PBA. */
 106     uint32_t    msix_table_offset;
 107     uint32_t    msix_pba_offset;
 108     int         msix_alloc;     /* Number of allocated vectors. */
 109     struct resource *msix_table_res;    /* Resource containing vector table. */
 110     struct resource *msix_pba_res;      /* Resource containing PBA. */
 111     struct msix_vectorlist msix_vectors;
 112 };
 113
 114 /* Interesting values for HyperTransport */
 115 struct pcicfg_ht {
 116     uint8_t     ht_slave;       /* Non-zero if device is an HT slave. */
 117     uint8_t     ht_msimap;      /* Offset of MSI mapping cap registers. */
 118     uint16_t    ht_msictrl;     /* MSI mapping control */
 119     uint64_t    ht_msiaddr;     /* MSI mapping base address */
 120 };
 121
 122 /* Interesting values for PCI Express capability */
 123 struct pcicfg_expr {
 124     uint8_t     expr_ptr;       /* capability ptr */
 125     uint16_t    expr_cap;       /* capabilities */
 126     uint32_t    expr_slotcap;   /* slot capabilities */
 127 };
 128
 129 /* Interesting values for PCI-X */
 130 struct pcicfg_pcix {
 131     uint8_t     pcix_ptr;
 132 };
 133
 134 /* config header information common to all header types */
 135 typedef struct pcicfg {
 136     device_t    dev;            /* device which owns this */
 137
 138     uint32_t    bar[PCI_MAXMAPS_0]; /* BARs */
 139     uint32_t    bios;           /* BIOS mapping */
 140
 141     uint16_t    subvendor;      /* card vendor ID */
 142     uint16_t    subdevice;      /* card device ID, assigned by card vendor */
 143     uint16_t    vendor;         /* chip vendor ID */
 144     uint16_t    device;         /* chip device ID, assigned by chip vendor */
 145
 146     uint16_t    cmdreg;         /* disable/enable chip and PCI options */
 147     uint16_t    statreg;        /* supported PCI features and error state */
 148
 149     uint8_t     baseclass;      /* chip PCI class */
 150     uint8_t     subclass;       /* chip PCI subclass */
 151     uint8_t     progif;         /* chip PCI programming interface */
 152     uint8_t     revid;          /* chip revision ID */
 153
 154     uint8_t     hdrtype;        /* chip config header type */
 155     uint8_t     cachelnsz;      /* cache line size in 4byte units */
 156     uint8_t     intpin;         /* PCI interrupt pin */
 157     uint8_t     intline;        /* interrupt line (IRQ for PC arch) */
 158
 159     uint8_t     mingnt;         /* min. useful bus grant time in 250ns units */
 160     uint8_t     maxlat;         /* max. tolerated bus grant latency in 250ns */
 161     uint8_t     lattimer;       /* latency timer in units of 30ns bus cycles */
 162
 163     uint8_t     mfdev;          /* multi-function device (from hdrtype reg) */
 164     uint8_t     nummaps;        /* actual number of PCI maps used */
 165
 166     uint32_t    domain;         /* PCI domain */
 167     uint8_t     bus;            /* config space bus address */
 168     uint8_t     slot;           /* config space slot address */
 169     uint8_t     func;           /* config space function number */
 170
 171     uint8_t     dummy;
 172
 173     struct pcicfg_pp pp;        /* pci power management */
 174     struct pcicfg_vpd vpd;      /* pci vital product data */
 175     struct pcicfg_msi msi;      /* pci msi */
 176     struct pcicfg_msix msix;    /* pci msi-x */
 177     struct pcicfg_ht ht;        /* HyperTransport */
 178     struct pcicfg_expr expr;    /* PCI Express */
 179     struct pcicfg_pcix pcix;    /* PCI-X */
 180 } pcicfgregs;
 181
 182 /* additional type 1 device config header information (PCI to PCI bridge) */
 183
 184 typedef struct {
 185     pci_addr_t  pmembase;       /* base address of prefetchable memory */
 186     pci_addr_t  pmemlimit;      /* topmost address of prefetchable memory */
 187     uint32_t    membase;        /* base address of memory window */
 188     uint32_t    memlimit;       /* topmost address of memory window */
 189     uint32_t    iobase;         /* base address of port window */
 190     uint32_t    iolimit;        /* topmost address of port window */
 191     uint16_t    secstat;        /* secondary bus status register */
 192     uint16_t    bridgectl;      /* bridge control register */
 193     uint8_t     seclat;         /* CardBus latency timer */
 194 } pcih1cfgregs;
 195
 196 /* additional type 2 device config header information (CardBus bridge) */
 197
 198 typedef struct {
 199     uint32_t    membase0;       /* base address of memory window */
 200     uint32_t    memlimit0;      /* topmost address of memory window */
 201     uint32_t    membase1;       /* base address of memory window */
 202     uint32_t    memlimit1;      /* topmost address of memory window */
 203     uint32_t    iobase0;        /* base address of port window */
 204     uint32_t    iolimit0;       /* topmost address of port window */
 205     uint32_t    iobase1;        /* base address of port window */
 206     uint32_t    iolimit1;       /* topmost address of port window */
 207     uint32_t    pccardif;       /* PC Card 16bit IF legacy more base addr. */
 208     uint16_t    secstat;        /* secondary bus status register */
 209     uint16_t    bridgectl;      /* bridge control register */
 210     uint8_t     seclat;         /* CardBus latency timer */
 211 } pcih2cfgregs;
 212
 213 extern uint32_t pci_numdevs;
 214
 215 /* Only if the prerequisites are present */
 216 #if defined(_SYS_BUS_H_) && defined(_SYS_PCIIO_H_)
 217 struct pci_devinfo {
 218         STAILQ_ENTRY(pci_devinfo) pci_links;
 219         struct resource_list resources;
 220         pcicfgregs              cfg;
 221         struct pci_conf         conf;
 222 };
 223 #endif
 224
 225 #ifdef _SYS_BUS_H_
 226
 227 #include "pci_if.h"
 228
 229 /*
 230  * Define pci-specific resource flags for accessing memory via dense
 231  * or bwx memory spaces.
 232  */
 233 #define PCI_RF_DENSE    0x10000
 234 #define PCI_RF_BWX      0x20000
 235
 236 enum pci_device_ivars {
 237     PCI_IVAR_SUBVENDOR,
 238     PCI_IVAR_SUBDEVICE,
 239     PCI_IVAR_VENDOR,
 240     PCI_IVAR_DEVICE,
 241     PCI_IVAR_DEVID,
 242     PCI_IVAR_CLASS,
 243     PCI_IVAR_SUBCLASS,
 244     PCI_IVAR_PROGIF,
 245     PCI_IVAR_REVID,
 246     PCI_IVAR_INTPIN,
 247     PCI_IVAR_IRQ,
 248     PCI_IVAR_DOMAIN,
 249     PCI_IVAR_BUS,
 250     PCI_IVAR_SLOT,
 251     PCI_IVAR_FUNCTION,
 252     PCI_IVAR_ETHADDR,
 253     PCI_IVAR_CMDREG,
 254     PCI_IVAR_CACHELNSZ,
 255     PCI_IVAR_MINGNT,
 256     PCI_IVAR_MAXLAT,
 257     PCI_IVAR_LATTIMER,
 258     PCI_IVAR_PCIXCAP_PTR,
 259     PCI_IVAR_PCIECAP_PTR,
 260     PCI_IVAR_VPDCAP_PTR
 261 };
 262
 263 /*
 264  * Simplified accessors for pci devices
 265  */
 266 #define PCI_ACCESSOR(var, ivar, type)                                   \
 267         __BUS_ACCESSOR(pci, var, PCI, ivar, type)
 268
 269 PCI_ACCESSOR(subvendor,         SUBVENDOR,      uint16_t)
 270 PCI_ACCESSOR(subdevice,         SUBDEVICE,      uint16_t)
 271 PCI_ACCESSOR(vendor,            VENDOR,         uint16_t)
 272 PCI_ACCESSOR(device,            DEVICE,         uint16_t)
 273 PCI_ACCESSOR(devid,             DEVID,          uint32_t)
 274 PCI_ACCESSOR(class,             CLASS,          uint8_t)
 275 PCI_ACCESSOR(subclass,          SUBCLASS,       uint8_t)
 276 PCI_ACCESSOR(progif,            PROGIF,         uint8_t)
 277 PCI_ACCESSOR(revid,             REVID,          uint8_t)
 278 PCI_ACCESSOR(intpin,            INTPIN,         uint8_t)
 279 PCI_ACCESSOR(irq,               IRQ,            uint8_t)
 280 PCI_ACCESSOR(domain,            DOMAIN,         uint32_t)
 281 PCI_ACCESSOR(bus,               BUS,            uint8_t)
 282 PCI_ACCESSOR(slot,              SLOT,           uint8_t)
 283 PCI_ACCESSOR(function,          FUNCTION,       uint8_t)
 284 PCI_ACCESSOR(ether,             ETHADDR,        uint8_t *)
 285 PCI_ACCESSOR(cmdreg,            CMDREG,         uint8_t)
 286 PCI_ACCESSOR(cachelnsz,         CACHELNSZ,      uint8_t)
 287 PCI_ACCESSOR(mingnt,            MINGNT,         uint8_t)
 288 PCI_ACCESSOR(maxlat,            MAXLAT,         uint8_t)
 289 PCI_ACCESSOR(lattimer,          LATTIMER,       uint8_t)
 290 PCI_ACCESSOR(pcixcap_ptr,       PCIXCAP_PTR,    uint8_t)
 291 PCI_ACCESSOR(pciecap_ptr,       PCIECAP_PTR,    uint8_t)
 292 PCI_ACCESSOR(vpdcap_ptr,        VPDCAP_PTR,     uint8_t)
 293
 294 #undef PCI_ACCESSOR
 295
 296 /*
 297  * Operations on configuration space.
 298  */
 299 static __inline uint32_t
 300 pci_read_config(device_t dev, int reg, int width)
 301 {
 302     return PCI_READ_CONFIG(device_get_parent(dev), dev, reg, width);
 303 }
 304
 305 static __inline void
 306 pci_write_config(device_t dev, int reg, uint32_t val, int width)
 307 {
 308     PCI_WRITE_CONFIG(device_get_parent(dev), dev, reg, val, width);
 309 }
 310
 311 /*
 312  * Ivars for pci bridges.
 313  */
 314
 315 /*typedef enum pci_device_ivars pcib_device_ivars;*/
 316 enum pcib_device_ivars {
 317         PCIB_IVAR_DOMAIN,
 318         PCIB_IVAR_BUS
 319 };
 320
 321 #define PCIB_ACCESSOR(var, ivar, type)                                   \
 322     __BUS_ACCESSOR(pcib, var, PCIB, ivar, type)
 323
 324 PCIB_ACCESSOR(domain,           DOMAIN,         uint32_t)
 325 PCIB_ACCESSOR(bus,              BUS,            uint32_t)
 326
 327 #undef PCIB_ACCESSOR
 328
 329 /*
 330  * PCI interrupt validation.  Invalid interrupt values such as 0 or 128
 331  * should be mapped out in the MD pcireadconf code and not here, since
 332  * the only MI invalid IRQ is 255.
 333  */
 334 #define PCI_INVALID_IRQ         255
 335 #define PCI_INTERRUPT_VALID(x)  ((x) != PCI_INVALID_IRQ)
 336
 337 /*
 338  * Convenience functions.
 339  *
 340  * These should be used in preference to manually manipulating
 341  * configuration space.
 342  */
 343 static __inline int
 344 pci_enable_busmaster(device_t dev)
 345 {
 346     return(PCI_ENABLE_BUSMASTER(device_get_parent(dev), dev));
 347 }
 348
 349 static __inline int
 350 pci_disable_busmaster(device_t dev)
 351 {
 352     return(PCI_DISABLE_BUSMASTER(device_get_parent(dev), dev));
 353 }
 354
 355 static __inline int
 356 pci_enable_io(device_t dev, int space)
 357 {
 358     return(PCI_ENABLE_IO(device_get_parent(dev), dev, space));
 359 }
 360
 361 static __inline int
 362 pci_disable_io(device_t dev, int space)
 363 {
 364     return(PCI_DISABLE_IO(device_get_parent(dev), dev, space));
 365 }
 366
 367 static __inline int
 368 pci_get_vpd_ident(device_t dev, const char **identptr)
 369 {
 370     return(PCI_GET_VPD_IDENT(device_get_parent(dev), dev, identptr));
 371 }
 372
 373 static __inline int
 374 pci_get_vpd_readonly(device_t dev, const char *kw, const char **identptr)
 375 {
 376     return(PCI_GET_VPD_READONLY(device_get_parent(dev), dev, kw, identptr));
 377 }
 378
 379 /*
 380  * Check if the address range falls within the VGA defined address range(s)
 381  */
 382 static __inline int
 383 pci_is_vga_ioport_range(u_long start, u_long end)
 384 {
 385
 386         return (((start >= 0x3b0 && end <= 0x3bb) ||
 387             (start >= 0x3c0 && end <= 0x3df)) ? 1 : 0);
 388 }
 389
 390 static __inline int
 391 pci_is_vga_memory_range(u_long start, u_long end)
 392 {
 393
 394         return ((start >= 0xa0000 && end <= 0xbffff) ? 1 : 0);
 395 }
 396
 397 int pcie_slot_implemented(device_t);
 398 void pcie_set_max_readrq(device_t, uint16_t);
 399 uint16_t pcie_get_max_readrq(device_t);
 400
 401 /*
 402  * PCI power states are as defined by ACPI:
 403  *
 404  * D0   State in which device is on and running.  It is receiving full
 405  *      power from the system and delivering full functionality to the user.
 406  * D1   Class-specific low-power state in which device context may or may not
 407  *      be lost.  Buses in D1 cannot do anything to the bus that would force
 408  *      devices on that bus to lose context.
 409  * D2   Class-specific low-power state in which device context may or may
 410  *      not be lost.  Attains greater power savings than D1.  Buses in D2
 411  *      can cause devices on that bus to lose some context.  Devices in D2
 412  *      must be prepared for the bus to be in D2 or higher.
 413  * D3   State in which the device is off and not running.  Device context is
 414  *      lost.  Power can be removed from the device.
 415  */
 416 #define PCI_POWERSTATE_D0       0
 417 #define PCI_POWERSTATE_D1       1
 418 #define PCI_POWERSTATE_D2       2
 419 #define PCI_POWERSTATE_D3       3
 420 #define PCI_POWERSTATE_UNKNOWN  -1
 421
 422 static __inline int
 423 pci_set_powerstate(device_t dev, int state)
 424 {
 425     return PCI_SET_POWERSTATE(device_get_parent(dev), dev, state);
 426 }
 427
 428 static __inline int
 429 pci_get_powerstate(device_t dev)
 430 {
 431     return PCI_GET_POWERSTATE(device_get_parent(dev), dev);
 432 }
 433
 434 static __inline int
 435 pci_find_extcap(device_t dev, int capability, int *capreg)
 436 {
 437     return PCI_FIND_EXTCAP(device_get_parent(dev), dev, capability, capreg);
 438 }
 439
 440 static __inline int
 441 pci_is_pcie(device_t dev)
 442 {
 443         return (pci_get_pciecap_ptr(dev) != 0);
 444 }
 445
 446 static __inline int
 447 pci_is_pcix(device_t dev)
 448 {
 449         return (pci_get_pcixcap_ptr(dev) != 0);
 450 }
 451
 452 static __inline int
 453 pci_alloc_msi(device_t dev, int *rid, int count, int cpuid)
 454 {
 455     return (PCI_ALLOC_MSI(device_get_parent(dev), dev, rid, count, cpuid));
 456 }
 457
 458 static __inline int
 459 pci_release_msi(device_t dev)
 460 {
 461     return (PCI_RELEASE_MSI(device_get_parent(dev), dev));
 462 }
 463
 464 static __inline int
 465 pci_alloc_msix_vector(device_t dev, u_int vector, int *rid, int cpuid)
 466 {
 467     return (PCI_ALLOC_MSIX_VECTOR(device_get_parent(dev), dev, vector, rid,
 468         cpuid));
 469 }
 470
 471 static __inline int
 472 pci_release_msix_vector(device_t dev, int rid)
 473 {
 474         return PCI_RELEASE_MSIX_VECTOR(device_get_parent(dev), dev, rid);
 475 }
 476
 477 static __inline int
 478 pci_msi_count(device_t dev)
 479 {
 480     return (PCI_MSI_COUNT(device_get_parent(dev), dev));
 481 }
 482
 483 static __inline int
 484 pci_msix_count(device_t dev)
 485 {
 486     return (PCI_MSIX_COUNT(device_get_parent(dev), dev));
 487 }
 488
 489 device_t pci_find_bsf(uint8_t, uint8_t, uint8_t);
 490 device_t pci_find_dbsf(uint32_t, uint8_t, uint8_t, uint8_t);
 491 device_t pci_find_device(uint16_t, uint16_t);
 492 device_t pci_find_class(uint8_t class, uint8_t subclass);
 493 #if defined(_SYS_BUS_H_) && defined(_SYS_PCIIO_H_)
 494 device_t pci_iterate_class(struct pci_devinfo **dinfop,
 495                         uint8_t class, uint8_t subclass);
 496 #endif
 497
 498 /* Can be used by drivers to manage the MSI-X table. */
 499 int     pci_pending_msix_vector(device_t dev, u_int index);
 500 int     pci_setup_msix(device_t dev);
 501 void    pci_teardown_msix(device_t dev);
 502 void    pci_enable_msix(device_t dev);
 503 void    pci_disable_msix(device_t dev);
 504
 505 int     pci_msi_device_blacklisted(device_t dev);
 506
 507 void    pci_ht_map_msi(device_t dev, uint64_t addr);
 508
 509 void    pci_restore_state(device_t dev);
 510 void    pci_save_state(device_t dev);
 511
 512 /* Returns PCI_INTR_TYPE_ */
 513 int     pci_alloc_1intr(device_t dev, int msi_enable, int *rid, u_int *flags);
 514
 515 #define PCI_INTR_TYPE_LEGACY    0
 516 #define PCI_INTR_TYPE_MSI       1
 517 #define PCI_INTR_TYPE_MSIX      2       /* not yet */
 518
 519 #endif  /* _SYS_BUS_H_ */
 520
 521 /*
 522  * device operations for control device, initialised in generic PCI code
 523  */
 524 extern struct dev_ops pci_ops;
 525
 526 /*
 527  * List of all PCI devices, generation count for the list.
 528  */
 529 STAILQ_HEAD(devlist, pci_devinfo);
 530
 531 extern struct devlist   pci_devq;
 532 extern uint32_t pci_generation;
 533
 534 #define VGA_PCI_BIOS_SHADOW_ADDR        0xC0000
 535 #define VGA_PCI_BIOS_SHADOW_SIZE        131072
 536
 537 int     vga_pci_is_boot_display(device_t dev);
 538 void *  vga_pci_map_bios(device_t dev, size_t *size);
 539 void    vga_pci_unmap_bios(device_t dev, void *bios);
 540
 541 #endif /* _PCIVAR_H_ */