sys/dev/drm/mach64_drm.h

   1 /* mach64_drm.h -- Public header for the mach64 driver -*- linux-c -*-
   2  * Created: Thu Nov 30 20:04:32 2000 by gareth@valinux.com
   3  */
   4 /*-
   5  * Copyright 2000 Gareth Hughes
   6  * Copyright 2002 Frank C. Earl
   7  * Copyright 2002-2003 Leif Delgass
   8  * All Rights Reserved.
   9  *
  10  * Permission is hereby granted, free of charge, to any person obtaining a
  11  * copy of this software and associated documentation files (the "Software"),
  12  * to deal in the Software without restriction, including without limitation
  13  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
  14  * and/or sell copies of the Software, and to permit persons to whom the
  15  * Software is furnished to do so, subject to the following conditions:
  16  *
  17  * The above copyright notice and this permission notice (including the next
  18  * paragraph) shall be included in all copies or substantial portions of the
  19  * Software.
  20  *
  21  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  22  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  23  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  24  * THE COPYRIGHT OWNER(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
  25  * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
  26  * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
  27  *
  28  * Authors:
  29  *    Gareth Hughes <gareth@valinux.com>
  30  *    Frank C. Earl <fearl@airmail.net>
  31  *    Leif Delgass <ldelgass@retinalburn.net>
  32  */
  33
  34 #ifndef __MACH64_DRM_H__
  35 #define __MACH64_DRM_H__
  36
  37 /* WARNING: If you change any of these defines, make sure to change the
  38  * defines in the Xserver file (mach64_sarea.h)
  39  */
  40 #ifndef __MACH64_SAREA_DEFINES__
  41 #define __MACH64_SAREA_DEFINES__
  42
  43 /* What needs to be changed for the current vertex buffer?
  44  * GH: We're going to be pedantic about this.  We want the card to do as
  45  * little as possible, so let's avoid having it fetch a whole bunch of
  46  * register values that don't change all that often, if at all.
  47  */
  48 #define MACH64_UPLOAD_DST_OFF_PITCH     0x0001
  49 #define MACH64_UPLOAD_Z_OFF_PITCH       0x0002
  50 #define MACH64_UPLOAD_Z_ALPHA_CNTL      0x0004
  51 #define MACH64_UPLOAD_SCALE_3D_CNTL     0x0008
  52 #define MACH64_UPLOAD_DP_FOG_CLR        0x0010
  53 #define MACH64_UPLOAD_DP_WRITE_MASK     0x0020
  54 #define MACH64_UPLOAD_DP_PIX_WIDTH      0x0040
  55 #define MACH64_UPLOAD_SETUP_CNTL        0x0080
  56 #define MACH64_UPLOAD_MISC              0x0100
  57 #define MACH64_UPLOAD_TEXTURE           0x0200
  58 #define MACH64_UPLOAD_TEX0IMAGE         0x0400
  59 #define MACH64_UPLOAD_TEX1IMAGE         0x0800
  60 #define MACH64_UPLOAD_CLIPRECTS         0x1000  /* handled client-side */
  61 #define MACH64_UPLOAD_CONTEXT           0x00ff
  62 #define MACH64_UPLOAD_ALL               0x1fff
  63
  64 /* DMA buffer size
  65  */
  66 #define MACH64_BUFFER_SIZE              16384
  67
  68 /* Max number of swaps allowed on the ring
  69  * before the client must wait
  70  */
  71 #define MACH64_MAX_QUEUED_FRAMES        3U
  72
  73 /* Byte offsets for host blit buffer data
  74  */
  75 #define MACH64_HOSTDATA_BLIT_OFFSET     104
  76
  77 /* Keep these small for testing.
  78  */
  79 #define MACH64_NR_SAREA_CLIPRECTS       8
  80
  81 #define MACH64_CARD_HEAP                0
  82 #define MACH64_AGP_HEAP                 1
  83 #define MACH64_NR_TEX_HEAPS             2
  84 #define MACH64_NR_TEX_REGIONS           64
  85 #define MACH64_LOG_TEX_GRANULARITY      16
  86
  87 #define MACH64_TEX_MAXLEVELS            1
  88
  89 #define MACH64_NR_CONTEXT_REGS          15
  90 #define MACH64_NR_TEXTURE_REGS          4
  91
  92 #endif                          /* __MACH64_SAREA_DEFINES__ */
  93
  94 typedef struct {
  95         unsigned int dst_off_pitch;
  96
  97         unsigned int z_off_pitch;
  98         unsigned int z_cntl;
  99         unsigned int alpha_tst_cntl;
 100
 101         unsigned int scale_3d_cntl;
 102
 103         unsigned int sc_left_right;
 104         unsigned int sc_top_bottom;
 105
 106         unsigned int dp_fog_clr;
 107         unsigned int dp_write_mask;
 108         unsigned int dp_pix_width;
 109         unsigned int dp_mix;
 110         unsigned int dp_src;
 111
 112         unsigned int clr_cmp_cntl;
 113         unsigned int gui_traj_cntl;
 114
 115         unsigned int setup_cntl;
 116
 117         unsigned int tex_size_pitch;
 118         unsigned int tex_cntl;
 119         unsigned int secondary_tex_off;
 120         unsigned int tex_offset;
 121 } drm_mach64_context_regs_t;
 122
 123 typedef struct drm_mach64_sarea {
 124         /* The channel for communication of state information to the kernel
 125          * on firing a vertex dma buffer.
 126          */
 127         drm_mach64_context_regs_t context_state;
 128         unsigned int dirty;
 129         unsigned int vertsize;
 130
 131         /* The current cliprects, or a subset thereof.
 132          */
 133         struct drm_clip_rect boxes[MACH64_NR_SAREA_CLIPRECTS];
 134         unsigned int nbox;
 135
 136         /* Counters for client-side throttling of rendering clients.
 137          */
 138         unsigned int frames_queued;
 139
 140         /* Texture memory LRU.
 141          */
 142         struct drm_tex_region tex_list[MACH64_NR_TEX_HEAPS][MACH64_NR_TEX_REGIONS +
 143                                                        1];
 144         unsigned int tex_age[MACH64_NR_TEX_HEAPS];
 145         int ctx_owner;
 146 } drm_mach64_sarea_t;
 147
 148 /* WARNING: If you change any of these defines, make sure to change the
 149  * defines in the Xserver file (mach64_common.h)
 150  */
 151
 152 /* Mach64 specific ioctls
 153  * The device specific ioctl range is 0x40 to 0x79.
 154  */
 155
 156 #define DRM_MACH64_INIT           0x00
 157 #define DRM_MACH64_IDLE           0x01
 158 #define DRM_MACH64_RESET          0x02
 159 #define DRM_MACH64_SWAP           0x03
 160 #define DRM_MACH64_CLEAR          0x04
 161 #define DRM_MACH64_VERTEX         0x05
 162 #define DRM_MACH64_BLIT           0x06
 163 #define DRM_MACH64_FLUSH          0x07
 164 #define DRM_MACH64_GETPARAM       0x08
 165
 166 #define DRM_IOCTL_MACH64_INIT           DRM_IOW( DRM_COMMAND_BASE + DRM_MACH64_INIT, drm_mach64_init_t)
 167 #define DRM_IOCTL_MACH64_IDLE           DRM_IO(  DRM_COMMAND_BASE + DRM_MACH64_IDLE )
 168 #define DRM_IOCTL_MACH64_RESET          DRM_IO(  DRM_COMMAND_BASE + DRM_MACH64_RESET )
 169 #define DRM_IOCTL_MACH64_SWAP           DRM_IO(  DRM_COMMAND_BASE + DRM_MACH64_SWAP )
 170 #define DRM_IOCTL_MACH64_CLEAR          DRM_IOW( DRM_COMMAND_BASE + DRM_MACH64_CLEAR, drm_mach64_clear_t)
 171 #define DRM_IOCTL_MACH64_VERTEX         DRM_IOW( DRM_COMMAND_BASE + DRM_MACH64_VERTEX, drm_mach64_vertex_t)
 172 #define DRM_IOCTL_MACH64_BLIT           DRM_IOW( DRM_COMMAND_BASE + DRM_MACH64_BLIT, drm_mach64_blit_t)
 173 #define DRM_IOCTL_MACH64_FLUSH          DRM_IO(  DRM_COMMAND_BASE + DRM_MACH64_FLUSH )
 174 #define DRM_IOCTL_MACH64_GETPARAM       DRM_IOWR( DRM_COMMAND_BASE + DRM_MACH64_GETPARAM, drm_mach64_getparam_t)
 175
 176 /* Buffer flags for clears
 177  */
 178 #define MACH64_FRONT                    0x1
 179 #define MACH64_BACK                     0x2
 180 #define MACH64_DEPTH                    0x4
 181
 182 /* Primitive types for vertex buffers
 183  */
 184 #define MACH64_PRIM_POINTS              0x00000000
 185 #define MACH64_PRIM_LINES               0x00000001
 186 #define MACH64_PRIM_LINE_LOOP           0x00000002
 187 #define MACH64_PRIM_LINE_STRIP          0x00000003
 188 #define MACH64_PRIM_TRIANGLES           0x00000004
 189 #define MACH64_PRIM_TRIANGLE_STRIP      0x00000005
 190 #define MACH64_PRIM_TRIANGLE_FAN        0x00000006
 191 #define MACH64_PRIM_QUADS               0x00000007
 192 #define MACH64_PRIM_QUAD_STRIP          0x00000008
 193 #define MACH64_PRIM_POLYGON             0x00000009
 194
 195 typedef enum _drm_mach64_dma_mode_t {
 196         MACH64_MODE_DMA_ASYNC,
 197         MACH64_MODE_DMA_SYNC,
 198         MACH64_MODE_MMIO
 199 } drm_mach64_dma_mode_t;
 200
 201 typedef struct drm_mach64_init {
 202         enum {
 203                 DRM_MACH64_INIT_DMA = 0x01,
 204                 DRM_MACH64_CLEANUP_DMA = 0x02
 205         } func;
 206
 207         unsigned long sarea_priv_offset;
 208         int is_pci;
 209         drm_mach64_dma_mode_t dma_mode;
 210
 211         unsigned int fb_bpp;
 212         unsigned int front_offset, front_pitch;
 213         unsigned int back_offset, back_pitch;
 214
 215         unsigned int depth_bpp;
 216         unsigned int depth_offset, depth_pitch;
 217
 218         unsigned long fb_offset;
 219         unsigned long mmio_offset;
 220         unsigned long ring_offset;
 221         unsigned long buffers_offset;
 222         unsigned long agp_textures_offset;
 223 } drm_mach64_init_t;
 224
 225 typedef struct drm_mach64_clear {
 226         unsigned int flags;
 227         int x, y, w, h;
 228         unsigned int clear_color;
 229         unsigned int clear_depth;
 230 } drm_mach64_clear_t;
 231
 232 typedef struct drm_mach64_vertex {
 233         int prim;
 234         void *buf;              /* Address of vertex buffer */
 235         unsigned long used;     /* Number of bytes in buffer */
 236         int discard;            /* Client finished with buffer? */
 237 } drm_mach64_vertex_t;
 238
 239 typedef struct drm_mach64_blit {
 240         void *buf;
 241         int pitch;
 242         int offset;
 243         int format;
 244         unsigned short x, y;
 245         unsigned short width, height;
 246 } drm_mach64_blit_t;
 247
 248 typedef struct drm_mach64_getparam {
 249         enum {
 250                 MACH64_PARAM_FRAMES_QUEUED = 0x01,
 251                 MACH64_PARAM_IRQ_NR = 0x02
 252         } param;
 253         void *value;
 254 } drm_mach64_getparam_t;
 255
 256 #endif