sys/bus/pci/pci_isab.c

   1 /*
   2  * Copyright (c) 2004, Joerg Sonnenberger <joerg@bec.de>
   3  * All rights reserved.
   4  * Copyright (c) 1994,1995 Stefan Esser.  All rights reserved.
   5  *
   6  * Redistribution and use in source and binary forms, with or without
   7  * modification, are permitted provided that the following conditions
   8  * are met:
   9  * 1. Redistributions of source code must retain the above copyright
  10  *    notice unmodified, this list of conditions, and the following
  11  *    disclaimer.
  12  * 2. Redistributions in binary form must reproduce the above copyright
  13  *    notice, this list of conditions and the following disclaimer in the
  14  *    documentation and/or other materials provided with the distribution.
  15  * 3. The name of the author may not be used to endorse or promote products
  16  *    derived from this software without specific prior written permission.
  17  *
  18  * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
  19  * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
  20  * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
  21  * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
  22  * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
  23  * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  24  * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  25  * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  26  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
  27  * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  28  *
  29  * $DragonFly: src/sys/bus/pci/pci_isab.c,v 1.8 2006/12/22 23:12:17 swildner Exp $
  30  */
  31
  32 #include "opt_pci.h"
  33
  34 #include <sys/param.h>
  35 #include <sys/bus.h>
  36 #include <sys/kernel.h>
  37 #include <sys/malloc.h>
  38 #include <sys/module.h>
  39 #include <sys/rman.h>
  40 #include <sys/systm.h>
  41
  42 #include <bus/isa/isavar.h>
  43 #include <bus/pci/pcivar.h>
  44 #include <bus/pci/pcireg.h>
  45
  46 #include "pcib_private.h"
  47
  48 static  void    chipset_attach(device_t dev, int unit);
  49
  50 #ifndef PCI_QUIET
  51
  52 struct condmsg {
  53     unsigned char       port;
  54     unsigned char       mask;
  55     unsigned char       value;
  56     char                flags;
  57     const char          *text;
  58 };
  59
  60 #define M_XX 0  /* end of list */
  61 #define M_EQ 1  /* mask and return true if equal */
  62 #define M_NE 2  /* mask and return true if not equal */
  63 #define M_TR 3  /* don't read config, always true */
  64 #define M_EN 4  /* mask and print "enabled" if true, "disabled" if false */
  65 #define M_NN 5  /* opposite sense of M_EN */
  66
  67 static const struct condmsg conf82425ex[] =
  68 {
  69     { 0x00, 0x00, 0x00, M_TR, "\tClock " },
  70     { 0x50, 0x06, 0x00, M_EQ, "25" },
  71     { 0x50, 0x06, 0x02, M_EQ, "33" },
  72     { 0x50, 0x04, 0x04, M_EQ, "??", },
  73     { 0x00, 0x00, 0x00, M_TR, "MHz, L1 Cache " },
  74     { 0x50, 0x01, 0x00, M_EQ, "Disabled\n" },
  75     { 0x50, 0x09, 0x01, M_EQ, "Write-through\n" },
  76     { 0x50, 0x09, 0x09, M_EQ, "Write-back\n" },
  77
  78     { 0x00, 0x00, 0x00, M_TR, "\tL2 Cache " },
  79     { 0x52, 0x07, 0x00, M_EQ, "Disabled" },
  80     { 0x52, 0x0f, 0x01, M_EQ, "64KB Write-through" },
  81     { 0x52, 0x0f, 0x02, M_EQ, "128KB Write-through" },
  82     { 0x52, 0x0f, 0x03, M_EQ, "256KB Write-through" },
  83     { 0x52, 0x0f, 0x04, M_EQ, "512KB Write-through" },
  84     { 0x52, 0x0f, 0x01, M_EQ, "64KB Write-back" },
  85     { 0x52, 0x0f, 0x02, M_EQ, "128KB Write-back" },
  86     { 0x52, 0x0f, 0x03, M_EQ, "256KB Write-back" },
  87     { 0x52, 0x0f, 0x04, M_EQ, "512KB Write-back" },
  88     { 0x53, 0x01, 0x00, M_EQ, ", 3-" },
  89     { 0x53, 0x01, 0x01, M_EQ, ", 2-" },
  90     { 0x53, 0x06, 0x00, M_EQ, "3-3-3" },
  91     { 0x53, 0x06, 0x02, M_EQ, "2-2-2" },
  92     { 0x53, 0x06, 0x04, M_EQ, "1-1-1" },
  93     { 0x53, 0x06, 0x06, M_EQ, "?-?-?" },
  94     { 0x53, 0x18, 0x00, M_EQ, "/4-2-2-2\n" },
  95     { 0x53, 0x18, 0x08, M_EQ, "/3-2-2-2\n" },
  96     { 0x53, 0x18, 0x10, M_EQ, "/?-?-?-?\n" },
  97     { 0x53, 0x18, 0x18, M_EQ, "/2-1-1-1\n" },
  98
  99     { 0x56, 0x00, 0x00, M_TR, "\tDRAM: " },
 100     { 0x56, 0x02, 0x02, M_EQ, "Fast Code Read, " },
 101     { 0x56, 0x04, 0x04, M_EQ, "Fast Data Read, " },
 102     { 0x56, 0x08, 0x08, M_EQ, "Fast Write, " },
 103     { 0x57, 0x20, 0x20, M_EQ, "Pipelined CAS" },
 104     { 0x57, 0x2e, 0x00, M_NE, "\n\t" },
 105     { 0x57, 0x00, 0x00, M_TR, "Timing: RAS: " },
 106     { 0x57, 0x07, 0x00, M_EQ, "4" },
 107     { 0x57, 0x07, 0x01, M_EQ, "3" },
 108     { 0x57, 0x07, 0x02, M_EQ, "2" },
 109     { 0x57, 0x07, 0x04, M_EQ, "1.5" },
 110     { 0x57, 0x07, 0x05, M_EQ, "1" },
 111     { 0x57, 0x00, 0x00, M_TR, " Clocks, CAS Read: " },
 112     { 0x57, 0x18, 0x00, M_EQ, "3/1", },
 113     { 0x57, 0x18, 0x00, M_EQ, "2/1", },
 114     { 0x57, 0x18, 0x00, M_EQ, "1.5/0.5", },
 115     { 0x57, 0x18, 0x00, M_EQ, "1/1", },
 116     { 0x57, 0x00, 0x00, M_TR, ", CAS Write: " },
 117     { 0x57, 0x20, 0x00, M_EQ, "2/1", },
 118     { 0x57, 0x20, 0x20, M_EQ, "1/1", },
 119     { 0x57, 0x00, 0x00, M_TR, "\n" },
 120
 121     { 0x40, 0x01, 0x01, M_EQ, "\tCPU-to-PCI Byte Merging\n" },
 122     { 0x40, 0x02, 0x02, M_EQ, "\tCPU-to-PCI Bursting\n" },
 123     { 0x40, 0x04, 0x04, M_EQ, "\tPCI Posted Writes\n" },
 124     { 0x40, 0x20, 0x00, M_EQ, "\tDRAM Parity Disabled\n" },
 125
 126     { 0x48, 0x03, 0x01, M_EQ, "\tPCI IDE controller: Primary (1F0h-1F7h,3F6h,3F7h)" },
 127     { 0x48, 0x03, 0x02, M_EQ, "\tPCI IDE controller: Secondary (170h-177h,376h,377h)" },
 128     { 0x4d, 0x01, 0x01, M_EQ, "\tRTC (70-77h)\n" },
 129     { 0x4d, 0x02, 0x02, M_EQ, "\tKeyboard (60,62,64,66h)\n" },
 130     { 0x4d, 0x08, 0x08, M_EQ, "\tIRQ12/M Mouse Function\n" },
 131
 132 /* end marker */
 133     { 0 }
 134 };
 135
 136 static const struct condmsg conf82424zx[] =
 137 {
 138     { 0x00, 0x00, 0x00, M_TR, "\tCPU: " },
 139     { 0x50, 0xe0, 0x00, M_EQ, "486DX" },
 140     { 0x50, 0xe0, 0x20, M_EQ, "486SX" },
 141     { 0x50, 0xe0, 0x40, M_EQ, "486DX2 or 486DX4" },
 142     { 0x50, 0xe0, 0x80, M_EQ, "Overdrive (writeback)" },
 143
 144     { 0x00, 0x00, 0x00, M_TR, ", bus=" },
 145     { 0x50, 0x03, 0x00, M_EQ, "25MHz" },
 146     { 0x50, 0x03, 0x01, M_EQ, "33MHz" },
 147     { 0x53, 0x01, 0x01, M_TR, ", CPU->Memory posting "},
 148     { 0x53, 0x01, 0x00, M_EQ, "OFF" },
 149     { 0x53, 0x01, 0x01, M_EQ, "ON" },
 150
 151     { 0x56, 0x30, 0x00, M_NE, "\n\tWarning:" },
 152     { 0x56, 0x20, 0x00, M_NE, " NO cache parity!" },
 153     { 0x56, 0x10, 0x00, M_NE, " NO DRAM parity!" },
 154     { 0x55, 0x04, 0x04, M_EQ, "\n\tWarning: refresh OFF! " },
 155
 156     { 0x00, 0x00, 0x00, M_TR, "\n\tCache: " },
 157     { 0x52, 0x01, 0x00, M_EQ, "None" },
 158     { 0x52, 0xc1, 0x01, M_EQ, "64KB" },
 159     { 0x52, 0xc1, 0x41, M_EQ, "128KB" },
 160     { 0x52, 0xc1, 0x81, M_EQ, "256KB" },
 161     { 0x52, 0xc1, 0xc1, M_EQ, "512KB" },
 162     { 0x52, 0x03, 0x01, M_EQ, " writethrough" },
 163     { 0x52, 0x03, 0x03, M_EQ, " writeback" },
 164
 165     { 0x52, 0x01, 0x01, M_EQ, ", cache clocks=" },
 166     { 0x52, 0x05, 0x01, M_EQ, "3-1-1-1" },
 167     { 0x52, 0x05, 0x05, M_EQ, "2-1-1-1" },
 168
 169     { 0x00, 0x00, 0x00, M_TR, "\n\tDRAM:" },
 170     { 0x55, 0x43, 0x00, M_NE, " page mode" },
 171     { 0x55, 0x02, 0x02, M_EQ, " code fetch" },
 172     { 0x55, 0x43, 0x43, M_EQ, "," },
 173     { 0x55, 0x43, 0x42, M_EQ, " and" },
 174     { 0x55, 0x40, 0x40, M_EQ, " read" },
 175     { 0x55, 0x03, 0x03, M_EQ, " and" },
 176     { 0x55, 0x43, 0x41, M_EQ, " and" },
 177     { 0x55, 0x01, 0x01, M_EQ, " write" },
 178     { 0x55, 0x43, 0x00, M_NE, "," },
 179
 180     { 0x00, 0x00, 0x00, M_TR, " memory clocks=" },
 181     { 0x55, 0x20, 0x00, M_EQ, "X-2-2-2" },
 182     { 0x55, 0x20, 0x20, M_EQ, "X-1-2-1" },
 183
 184     { 0x00, 0x00, 0x00, M_TR, "\n\tCPU->PCI: posting " },
 185     { 0x53, 0x02, 0x00, M_NE, "ON" },
 186     { 0x53, 0x02, 0x00, M_EQ, "OFF" },
 187     { 0x00, 0x00, 0x00, M_TR, ", burst mode " },
 188     { 0x54, 0x02, 0x00, M_NE, "ON" },
 189     { 0x54, 0x02, 0x00, M_EQ, "OFF" },
 190     { 0x00, 0x00, 0x00, M_TR, "\n\tPCI->Memory: posting " },
 191     { 0x54, 0x01, 0x00, M_NE, "ON" },
 192     { 0x54, 0x01, 0x00, M_EQ, "OFF" },
 193
 194     { 0x00, 0x00, 0x00, M_TR, "\n" },
 195
 196 /* end marker */
 197     { 0 }
 198 };
 199
 200 static const struct condmsg conf82434lx[] =
 201 {
 202     { 0x00, 0x00, 0x00, M_TR, "\tCPU: " },
 203     { 0x50, 0xe3, 0x82, M_EQ, "Pentium, 60MHz" },
 204     { 0x50, 0xe3, 0x83, M_EQ, "Pentium, 66MHz" },
 205     { 0x50, 0xe3, 0xa2, M_EQ, "Pentium, 90MHz" },
 206     { 0x50, 0xe3, 0xa3, M_EQ, "Pentium, 100MHz" },
 207     { 0x50, 0xc2, 0x82, M_NE, "(unknown)" },
 208     { 0x50, 0x04, 0x00, M_EQ, " (primary cache OFF)" },
 209
 210     { 0x53, 0x01, 0x01, M_TR, ", CPU->Memory posting "},
 211     { 0x53, 0x01, 0x01, M_NE, "OFF" },
 212     { 0x53, 0x01, 0x01, M_EQ, "ON" },
 213
 214     { 0x53, 0x08, 0x00, M_NE, ", read around write"},
 215
 216     { 0x70, 0x04, 0x00, M_EQ, "\n\tWarning: Cache parity disabled!" },
 217     { 0x57, 0x20, 0x00, M_NE, "\n\tWarning: DRAM parity mask!" },
 218     { 0x57, 0x01, 0x00, M_EQ, "\n\tWarning: refresh OFF! " },
 219
 220     { 0x00, 0x00, 0x00, M_TR, "\n\tCache: " },
 221     { 0x52, 0x01, 0x00, M_EQ, "None" },
 222     { 0x52, 0x81, 0x01, M_EQ, "" },
 223     { 0x52, 0xc1, 0x81, M_EQ, "256KB" },
 224     { 0x52, 0xc1, 0xc1, M_EQ, "512KB" },
 225     { 0x52, 0x03, 0x01, M_EQ, " writethrough" },
 226     { 0x52, 0x03, 0x03, M_EQ, " writeback" },
 227
 228     { 0x52, 0x01, 0x01, M_EQ, ", cache clocks=" },
 229     { 0x52, 0x21, 0x01, M_EQ, "3-2-2-2/4-2-2-2" },
 230     { 0x52, 0x21, 0x21, M_EQ, "3-1-1-1" },
 231
 232     { 0x52, 0x01, 0x01, M_EQ, "\n\tCache flags: " },
 233     { 0x52, 0x11, 0x11, M_EQ, " cache-all" },
 234     { 0x52, 0x09, 0x09, M_EQ, " byte-control" },
 235     { 0x52, 0x05, 0x05, M_EQ, " powersaver" },
 236
 237     { 0x00, 0x00, 0x00, M_TR, "\n\tDRAM:" },
 238     { 0x57, 0x10, 0x00, M_EQ, " page mode" },
 239
 240     { 0x00, 0x00, 0x00, M_TR, " memory clocks=" },
 241     { 0x57, 0xc0, 0x00, M_EQ, "X-4-4-4 (70ns)" },
 242     { 0x57, 0xc0, 0x40, M_EQ, "X-4-4-4/X-3-3-3 (60ns)" },
 243     { 0x57, 0xc0, 0x80, M_EQ, "???" },
 244     { 0x57, 0xc0, 0xc0, M_EQ, "X-3-3-3 (50ns)" },
 245     { 0x58, 0x02, 0x02, M_EQ, ", RAS-wait" },
 246     { 0x58, 0x01, 0x01, M_EQ, ", CAS-wait" },
 247
 248     { 0x00, 0x00, 0x00, M_TR, "\n\tCPU->PCI: posting " },
 249     { 0x53, 0x02, 0x02, M_EQ, "ON" },
 250     { 0x53, 0x02, 0x00, M_EQ, "OFF" },
 251     { 0x00, 0x00, 0x00, M_TR, ", burst mode " },
 252     { 0x54, 0x02, 0x00, M_NE, "ON" },
 253     { 0x54, 0x02, 0x00, M_EQ, "OFF" },
 254     { 0x54, 0x04, 0x00, M_TR, ", PCI clocks=" },
 255     { 0x54, 0x04, 0x00, M_EQ, "2-2-2-2" },
 256     { 0x54, 0x04, 0x00, M_NE, "2-1-1-1" },
 257     { 0x00, 0x00, 0x00, M_TR, "\n\tPCI->Memory: posting " },
 258     { 0x54, 0x01, 0x00, M_NE, "ON" },
 259     { 0x54, 0x01, 0x00, M_EQ, "OFF" },
 260
 261     { 0x57, 0x01, 0x01, M_EQ, "\n\tRefresh:" },
 262     { 0x57, 0x03, 0x03, M_EQ, " CAS#/RAS#(Hidden)" },
 263     { 0x57, 0x03, 0x01, M_EQ, " RAS#Only" },
 264     { 0x57, 0x05, 0x05, M_EQ, " BurstOf4" },
 265
 266     { 0x00, 0x00, 0x00, M_TR, "\n" },
 267
 268 /* end marker */
 269     { 0 }
 270 };
 271
 272 static const struct condmsg conf82378[] =
 273 {
 274     { 0x00, 0x00, 0x00, M_TR, "\tBus Modes:" },
 275     { 0x41, 0x04, 0x04, M_EQ, " Bus Park," },
 276     { 0x41, 0x02, 0x02, M_EQ, " Bus Lock," },
 277     { 0x41, 0x02, 0x00, M_EQ, " Resource Lock," },
 278     { 0x41, 0x01, 0x01, M_EQ, " GAT" },
 279     { 0x4d, 0x20, 0x20, M_EQ, "\n\tCoprocessor errors enabled" },
 280     { 0x4d, 0x10, 0x10, M_EQ, "\n\tMouse function enabled" },
 281
 282     { 0x4e, 0x30, 0x10, M_EQ, "\n\tIDE controller: Primary (1F0h-1F7h,3F6h,3F7h)" },
 283     { 0x4e, 0x30, 0x30, M_EQ, "\n\tIDE controller: Secondary (170h-177h,376h,377h)" },
 284     { 0x4e, 0x28, 0x08, M_EQ, "\n\tFloppy controller: 3F0h,3F1h " },
 285     { 0x4e, 0x24, 0x04, M_EQ, "\n\tFloppy controller: 3F2h-3F7h " },
 286     { 0x4e, 0x28, 0x28, M_EQ, "\n\tFloppy controller: 370h,371h " },
 287     { 0x4e, 0x24, 0x24, M_EQ, "\n\tFloppy controller: 372h-377h " },
 288     { 0x4e, 0x02, 0x02, M_EQ, "\n\tKeyboard controller: 60h,62h,64h,66h" },
 289     { 0x4e, 0x01, 0x01, M_EQ, "\n\tRTC: 70h-77h" },
 290
 291     { 0x4f, 0x80, 0x80, M_EQ, "\n\tConfiguration RAM: 0C00h,0800h-08FFh" },
 292     { 0x4f, 0x40, 0x40, M_EQ, "\n\tPort 92: enabled" },
 293     { 0x4f, 0x03, 0x00, M_EQ, "\n\tSerial Port A: COM1 (3F8h-3FFh)" },
 294     { 0x4f, 0x03, 0x01, M_EQ, "\n\tSerial Port A: COM2 (2F8h-2FFh)" },
 295     { 0x4f, 0x0c, 0x00, M_EQ, "\n\tSerial Port B: COM1 (3F8h-3FFh)" },
 296     { 0x4f, 0x0c, 0x04, M_EQ, "\n\tSerial Port B: COM2 (2F8h-2FFh)" },
 297     { 0x4f, 0x30, 0x00, M_EQ, "\n\tParallel Port: LPT1 (3BCh-3BFh)" },
 298     { 0x4f, 0x30, 0x04, M_EQ, "\n\tParallel Port: LPT2 (378h-37Fh)" },
 299     { 0x4f, 0x30, 0x20, M_EQ, "\n\tParallel Port: LPT3 (278h-27Fh)" },
 300     { 0x00, 0x00, 0x00, M_TR, "\n" },
 301
 302 /* end marker */
 303     { 0 }
 304 };
 305
 306 static const struct condmsg conf82437fx[] =
 307 {
 308     /* PCON -- PCI Control Register */
 309     { 0x00, 0x00, 0x00, M_TR, "\tCPU Inactivity timer: " },
 310     { 0x50, 0xe0, 0xe0, M_EQ, "8" },
 311     { 0x50, 0xe0, 0xd0, M_EQ, "7" },
 312     { 0x50, 0xe0, 0xc0, M_EQ, "6" },
 313     { 0x50, 0xe0, 0xb0, M_EQ, "5" },
 314     { 0x50, 0xe0, 0xa0, M_EQ, "4" },
 315     { 0x50, 0xe0, 0x90, M_EQ, "3" },
 316     { 0x50, 0xe0, 0x80, M_EQ, "2" },
 317     { 0x50, 0xe0, 0x00, M_EQ, "1" },
 318     { 0x00, 0x00, 0x00, M_TR, " clocks\n\tPeer Concurrency: " },
 319     { 0x50, 0x08, 0x08, M_EN, 0 },
 320     { 0x00, 0x00, 0x00, M_TR, "\n\tCPU-to-PCI Write Bursting: " },
 321     { 0x50, 0x04, 0x00, M_NN, 0 },
 322     { 0x00, 0x00, 0x00, M_TR, "\n\tPCI Streaming: " },
 323     { 0x50, 0x02, 0x00, M_NN, 0 },
 324     { 0x00, 0x00, 0x00, M_TR, "\n\tBus Concurrency: " },
 325     { 0x50, 0x01, 0x00, M_NN, 0 },
 326
 327     /* CC -- Cache Control Regsiter */
 328     { 0x00, 0x00, 0x00, M_TR, "\n\tCache:" },
 329     { 0x52, 0xc0, 0x80, M_EQ, " 512K" },
 330     { 0x52, 0xc0, 0x40, M_EQ, " 256K" },
 331     { 0x52, 0xc0, 0x00, M_EQ, " NO" },
 332     { 0x52, 0x30, 0x00, M_EQ, " pipelined-burst" },
 333     { 0x52, 0x30, 0x10, M_EQ, " burst" },
 334     { 0x52, 0x30, 0x20, M_EQ, " asynchronous" },
 335     { 0x52, 0x30, 0x30, M_EQ, " dual-bank pipelined-burst" },
 336     { 0x00, 0x00, 0x00, M_TR, " secondary; L1 " },
 337     { 0x52, 0x01, 0x00, M_EN, 0 },
 338     { 0x00, 0x00, 0x00, M_TR, "\n" },
 339
 340     /* DRAMC -- DRAM Control Register */
 341     { 0x57, 0x07, 0x00, M_EQ, "Warning: refresh OFF!\n" },
 342     { 0x00, 0x00, 0x00, M_TR, "\tDRAM:" },
 343     { 0x57, 0xc0, 0x00, M_EQ, " no memory hole" },
 344     { 0x57, 0xc0, 0x40, M_EQ, " 512K-640K memory hole" },
 345     { 0x57, 0xc0, 0x80, M_EQ, " 15M-16M memory hole" },
 346     { 0x57, 0x07, 0x01, M_EQ, ", 50 MHz refresh" },
 347     { 0x57, 0x07, 0x02, M_EQ, ", 60 MHz refresh" },
 348     { 0x57, 0x07, 0x03, M_EQ, ", 66 MHz refresh" },
 349
 350     /* DRAMT = DRAM Timing Register */
 351     { 0x00, 0x00, 0x00, M_TR, "\n\tRead burst timing: " },
 352     { 0x58, 0x60, 0x00, M_EQ, "x-4-4-4/x-4-4-4" },
 353     { 0x58, 0x60, 0x20, M_EQ, "x-3-3-3/x-4-4-4" },
 354     { 0x58, 0x60, 0x40, M_EQ, "x-2-2-2/x-3-3-3" },
 355     { 0x58, 0x60, 0x60, M_EQ, "???" },
 356     { 0x00, 0x00, 0x00, M_TR, "\n\tWrite burst timing: " },
 357     { 0x58, 0x18, 0x00, M_EQ, "x-4-4-4" },
 358     { 0x58, 0x18, 0x08, M_EQ, "x-3-3-3" },
 359     { 0x58, 0x18, 0x10, M_EQ, "x-2-2-2" },
 360     { 0x58, 0x18, 0x18, M_EQ, "???" },
 361     { 0x00, 0x00, 0x00, M_TR, "\n\tRAS-CAS delay: " },
 362     { 0x58, 0x04, 0x00, M_EQ, "3" },
 363     { 0x58, 0x04, 0x04, M_EQ, "2" },
 364     { 0x00, 0x00, 0x00, M_TR, " clocks\n" },
 365
 366     /* end marker */
 367     { 0 }
 368 };
 369
 370 static const struct condmsg conf82437vx[] =
 371 {
 372     /* PCON -- PCI Control Register */
 373     { 0x00, 0x00, 0x00, M_TR, "\n\tPCI Concurrency: " },
 374     { 0x50, 0x08, 0x08, M_EN, 0 },
 375
 376     /* CC -- Cache Control Regsiter */
 377     { 0x00, 0x00, 0x00, M_TR, "\n\tCache:" },
 378     { 0x52, 0xc0, 0x80, M_EQ, " 512K" },
 379     { 0x52, 0xc0, 0x40, M_EQ, " 256K" },
 380     { 0x52, 0xc0, 0x00, M_EQ, " NO" },
 381     { 0x52, 0x30, 0x00, M_EQ, " pipelined-burst" },
 382     { 0x52, 0x30, 0x10, M_EQ, " burst" },
 383     { 0x52, 0x30, 0x20, M_EQ, " asynchronous" },
 384     { 0x52, 0x30, 0x30, M_EQ, " dual-bank pipelined-burst" },
 385     { 0x00, 0x00, 0x00, M_TR, " secondary; L1 " },
 386     { 0x52, 0x01, 0x00, M_EN, 0 },
 387     { 0x00, 0x00, 0x00, M_TR, "\n" },
 388
 389     /* DRAMC -- DRAM Control Register */
 390     { 0x57, 0x07, 0x00, M_EQ, "Warning: refresh OFF!\n" },
 391     { 0x00, 0x00, 0x00, M_TR, "\tDRAM:" },
 392     { 0x57, 0xc0, 0x00, M_EQ, " no memory hole" },
 393     { 0x57, 0xc0, 0x40, M_EQ, " 512K-640K memory hole" },
 394     { 0x57, 0xc0, 0x80, M_EQ, " 15M-16M memory hole" },
 395     { 0x57, 0x07, 0x01, M_EQ, ", 50 MHz refresh" },
 396     { 0x57, 0x07, 0x02, M_EQ, ", 60 MHz refresh" },
 397     { 0x57, 0x07, 0x03, M_EQ, ", 66 MHz refresh" },
 398
 399     /* DRAMT = DRAM Timing Register */
 400     { 0x00, 0x00, 0x00, M_TR, "\n\tRead burst timing: " },
 401     { 0x58, 0x60, 0x00, M_EQ, "x-4-4-4/x-4-4-4" },
 402     { 0x58, 0x60, 0x20, M_EQ, "x-3-3-3/x-4-4-4" },
 403     { 0x58, 0x60, 0x40, M_EQ, "x-2-2-2/x-3-3-3" },
 404     { 0x58, 0x60, 0x60, M_EQ, "???" },
 405     { 0x00, 0x00, 0x00, M_TR, "\n\tWrite burst timing: " },
 406     { 0x58, 0x18, 0x00, M_EQ, "x-4-4-4" },
 407     { 0x58, 0x18, 0x08, M_EQ, "x-3-3-3" },
 408     { 0x58, 0x18, 0x10, M_EQ, "x-2-2-2" },
 409     { 0x58, 0x18, 0x18, M_EQ, "???" },
 410     { 0x00, 0x00, 0x00, M_TR, "\n\tRAS-CAS delay: " },
 411     { 0x58, 0x04, 0x00, M_EQ, "3" },
 412     { 0x58, 0x04, 0x04, M_EQ, "2" },
 413     { 0x00, 0x00, 0x00, M_TR, " clocks\n" },
 414
 415     /* end marker */
 416     { 0 }
 417 };
 418
 419 static const struct condmsg conf82371fb[] =
 420 {
 421     /* IORT -- ISA I/O Recovery Timer Register */
 422     { 0x00, 0x00, 0x00, M_TR, "\tI/O Recovery Timing: 8-bit " },
 423     { 0x4c, 0x40, 0x00, M_EQ, "3.5" },
 424     { 0x4c, 0x78, 0x48, M_EQ, "1" },
 425     { 0x4c, 0x78, 0x50, M_EQ, "2" },
 426     { 0x4c, 0x78, 0x58, M_EQ, "3" },
 427     { 0x4c, 0x78, 0x60, M_EQ, "4" },
 428     { 0x4c, 0x78, 0x68, M_EQ, "5" },
 429     { 0x4c, 0x78, 0x70, M_EQ, "6" },
 430     { 0x4c, 0x78, 0x78, M_EQ, "7" },
 431     { 0x4c, 0x78, 0x40, M_EQ, "8" },
 432     { 0x00, 0x00, 0x00, M_TR, " clocks, 16-bit " },
 433     { 0x4c, 0x04, 0x00, M_EQ, "3.5" },
 434     { 0x4c, 0x07, 0x05, M_EQ, "1" },
 435     { 0x4c, 0x07, 0x06, M_EQ, "2" },
 436     { 0x4c, 0x07, 0x07, M_EQ, "3" },
 437     { 0x4c, 0x07, 0x04, M_EQ, "4" },
 438     { 0x00, 0x00, 0x00, M_TR, " clocks\n" },
 439
 440     /* XBCS -- X-Bus Chip Select Register */
 441     { 0x00, 0x00, 0x00, M_TR, "\tExtended BIOS: " },
 442     { 0x4e, 0x80, 0x80, M_EN, 0 },
 443     { 0x00, 0x00, 0x00, M_TR, "\n\tLower BIOS: " },
 444     { 0x4e, 0x40, 0x40, M_EN, 0 },
 445     { 0x00, 0x00, 0x00, M_TR, "\n\tCoprocessor IRQ13: " },
 446     { 0x4e, 0x20, 0x20, M_EN, 0 },
 447     { 0x00, 0x00, 0x00, M_TR, "\n\tMouse IRQ12: " },
 448     { 0x4e, 0x10, 0x10, M_EN, 0 },
 449     { 0x00, 0x00, 0x00, M_TR, "\n" },
 450
 451     { 0x00, 0x00, 0x00, M_TR, "\tInterrupt Routing: " },
 452 #define PIRQ(x, n) \
 453     { 0x00, 0x00, 0x00, M_TR, n ": " }, \
 454     { x, 0x80, 0x80, M_EQ, "disabled" }, \
 455     { x, 0xc0, 0x40, M_EQ, "[shared] " }, \
 456     { x, 0x8f, 0x03, M_EQ, "IRQ3" }, \
 457     { x, 0x8f, 0x04, M_EQ, "IRQ4" }, \
 458     { x, 0x8f, 0x05, M_EQ, "IRQ5" }, \
 459     { x, 0x8f, 0x06, M_EQ, "IRQ6" }, \
 460     { x, 0x8f, 0x07, M_EQ, "IRQ7" }, \
 461     { x, 0x8f, 0x09, M_EQ, "IRQ9" }, \
 462     { x, 0x8f, 0x0a, M_EQ, "IRQ10" }, \
 463     { x, 0x8f, 0x0b, M_EQ, "IRQ11" }, \
 464     { x, 0x8f, 0x0c, M_EQ, "IRQ12" }, \
 465     { x, 0x8f, 0x0e, M_EQ, "IRQ14" }, \
 466     { x, 0x8f, 0x0f, M_EQ, "IRQ15" }
 467
 468     /* Interrupt routing */
 469     PIRQ(0x60, "A"),
 470     PIRQ(0x61, ", B"),
 471     PIRQ(0x62, ", C"),
 472     PIRQ(0x63, ", D"),
 473     PIRQ(0x70, "\n\t\tMB0"),
 474     PIRQ(0x71, ", MB1"),
 475
 476     { 0x00, 0x00, 0x00, M_TR, "\n" },
 477
 478 #undef PIRQ
 479
 480     /* XXX - do DMA routing, too? */
 481     { 0 }
 482 };
 483
 484 static const struct condmsg conf82371fb2[] =
 485 {
 486     /* IDETM -- IDE Timing Register */
 487     { 0x00, 0x00, 0x00, M_TR, "\tPrimary IDE: " },
 488     { 0x41, 0x80, 0x80, M_EN, 0 },
 489     { 0x00, 0x00, 0x00, M_TR, "\n\tSecondary IDE: " },
 490     { 0x43, 0x80, 0x80, M_EN, 0 },
 491     { 0x00, 0x00, 0x00, M_TR, "\n" },
 492
 493     /* end of list */
 494     { 0 }
 495 };
 496
 497 static void
 498 writeconfig (device_t dev, const struct condmsg *tbl)
 499 {
 500     while (tbl->flags != M_XX) {
 501         const char *text = 0;
 502
 503         if (tbl->flags == M_TR) {
 504             text = tbl->text;
 505         } else {
 506             unsigned char v = pci_read_config(dev, tbl->port, 1);
 507             switch (tbl->flags) {
 508     case M_EQ:
 509                 if ((v & tbl->mask) == tbl->value) text = tbl->text;
 510                 break;
 511     case M_NE:
 512                 if ((v & tbl->mask) != tbl->value) text = tbl->text;
 513                 break;
 514     case M_EN:
 515                 text = (v & tbl->mask) ? "enabled" : "disabled";
 516                 break;
 517     case M_NN:
 518                 text = (v & tbl->mask) ? "disabled" : "enabled";
 519             }
 520         }
 521         if (text) kprintf ("%s", text);
 522         tbl++;
 523     }
 524 }
 525
 526 #endif /* PCI_QUIET */
 527
 528 static void
 529 chipset_attach (device_t dev, int unit)
 530 {
 531 #ifndef PCI_QUIET
 532         if (!bootverbose)
 533                 return;
 534
 535         switch (pci_get_devid(dev)) {
 536         case 0x04868086:
 537                 writeconfig (dev, conf82425ex);
 538                 break;
 539         case 0x04838086:
 540                 writeconfig (dev, conf82424zx);
 541                 break;
 542         case 0x04a38086:
 543                 writeconfig (dev, conf82434lx);
 544                 break;
 545         case 0x04848086:
 546                 writeconfig (dev, conf82378);
 547                 break;
 548         case 0x122d8086:
 549                 writeconfig (dev, conf82437fx);
 550                 break;
 551         case 0x70308086:
 552                 writeconfig (dev, conf82437vx);
 553                 break;
 554         case 0x70008086:
 555         case 0x122e8086:
 556                 writeconfig (dev, conf82371fb);
 557                 break;
 558         case 0x70108086:
 559         case 0x12308086:
 560                 writeconfig (dev, conf82371fb2);
 561                 break;
 562 #if 0
 563         case 0x00011011: /* DEC 21050 */
 564         case 0x00221014: /* IBM xxx */
 565                 writeconfig (dev, conf_pci2pci);
 566                 break;
 567 #endif
 568         };
 569 #endif /* PCI_QUIET */
 570 }
 571
 572 static const char *
 573 eisab_match(device_t dev)
 574 {
 575         switch (pci_get_devid(dev)) {
 576         case 0x04828086:
 577                 /* Recognize this specifically, it has PCI-HOST class (!) */
 578                 return ("Intel 82375EB PCI-EISA bridge");
 579         }
 580         if (pci_get_class(dev) == PCIC_BRIDGE
 581             && pci_get_subclass(dev) == PCIS_BRIDGE_EISA)
 582                 return pci_bridge_type(dev);
 583
 584         return NULL;
 585 }
 586
 587 static const char *
 588 isab_match(device_t dev)
 589 {
 590         unsigned        rev;
 591
 592         switch (pci_get_devid(dev)) {
 593         case 0x04848086:
 594                 rev = pci_get_revid(dev);
 595                 if (rev == 3)
 596                     return ("Intel 82378ZB PCI to ISA bridge");
 597                 return ("Intel 82378IB PCI to ISA bridge");
 598         case 0x122e8086:
 599                 return ("Intel 82371FB PCI to ISA bridge");
 600         case 0x70008086:
 601                 return ("Intel 82371SB PCI to ISA bridge");
 602         case 0x71108086:
 603                 return ("Intel 82371AB PCI to ISA bridge");
 604         case 0x71988086:
 605                 return ("Intel 82443MX PCI to ISA bridge");
 606         case 0x24108086:
 607                 return ("Intel 82801AA (ICH) PCI to LPC bridge");
 608         case 0x24208086:
 609                 return ("Intel 82801AB (ICH0) PCI to LPC bridge");
 610         case 0x24408086:
 611                 return ("Intel 82801BA/BAM (ICH2) PCI to LPC bridge");
 612         case 0x26408086:
 613                 return ("Intel 82801FB/FBW (ICH6) PCI to LPC bridge");
 614         case 0x26428086:
 615                 return ("Intel 82801FR/FRW (ICH6) PCI to LPC bridge");
 616
 617         /* NVIDIA -- vendor 0x10de */
 618         case 0x006010de:
 619                 return ("NVIDIA nForce2 PCI to ISA bridge");
 620
 621         /* VLSI -- vendor 0x1004 */
 622         case 0x00061004:
 623                 return ("VLSI 82C593 PCI to ISA bridge");
 624
 625         /* VIA Technologies -- vendor 0x1106 */
 626         case 0x05861106: /* south bridge section */
 627                 return ("VIA 82C586 PCI-ISA bridge");
 628         case 0x05961106:
 629                 return ("VIA 82C596B PCI-ISA bridge");
 630         case 0x06861106:
 631                 return ("VIA 82C686 PCI-ISA bridge");
 632
 633         /* AcerLabs -- vendor 0x10b9 */
 634         /* Funny : The datasheet told me vendor id is "10b8",sub-vendor */
 635         /* id is '10b9" but the register always shows "10b9". -Foxfair  */
 636         case 0x153310b9:
 637                 return ("AcerLabs M1533 portable PCI-ISA bridge");
 638         case 0x154310b9:
 639                 return ("AcerLabs M1543 desktop PCI-ISA bridge");
 640
 641         /* SiS -- vendor 0x1039 */
 642         case 0x00081039:
 643                 return ("SiS 85c503 PCI-ISA bridge");
 644
 645         /* Cyrix -- vendor 0x1078 */
 646         case 0x00001078:
 647                 return ("Cyrix Cx5510 PCI-ISA bridge");
 648         case 0x01001078:
 649                 return ("Cyrix Cx5530 PCI-ISA bridge");
 650
 651         /* UMC United Microelectronics 0x1060 */
 652         case 0x886a1060:
 653                 return ("UMC UM8886 ISA Bridge with EIDE");
 654
 655         /* Cypress -- vendor 0x1080 */
 656         case 0xc6931080:
 657                 if (pci_get_class(dev) == PCIC_BRIDGE
 658                     && pci_get_subclass(dev) == PCIS_BRIDGE_ISA)
 659                         return ("Cypress 82C693 PCI-ISA bridge");
 660                 break;
 661
 662         /* ServerWorks -- vendor 0x1166 */
 663         case 0x02001166:
 664                 return ("ServerWorks IB6566 PCI to ISA bridge");
 665         }
 666
 667         if (pci_get_class(dev) == PCIC_BRIDGE
 668             && pci_get_subclass(dev) == PCIS_BRIDGE_ISA)
 669                 return pci_bridge_type(dev);
 670
 671         return NULL;
 672 }
 673
 674 static int
 675 isab_probe(device_t dev)
 676 {
 677         const char *desc;
 678         int     is_eisa;
 679
 680         is_eisa = 0;
 681         desc = eisab_match(dev);
 682         if (desc)
 683                 is_eisa = 1;
 684         else
 685                 desc = isab_match(dev);
 686         if (desc) {
 687                 /*
 688                  * For a PCI-EISA bridge, add both eisa and isa.
 689                  * Only add one instance of eisa or isa for now.
 690                  */
 691                 device_set_desc_copy(dev, desc);
 692                 if (is_eisa && !devclass_get_device(devclass_find("eisa"), 0))
 693                         device_add_child(dev, "eisa", -1);
 694
 695                 if (!devclass_get_device(devclass_find("isa"), 0))
 696                         device_add_child(dev, "isa", -1);
 697                 return -1000;
 698         }
 699         return ENXIO;
 700 }
 701
 702 int
 703 isab_attach(device_t dev)
 704 {
 705         chipset_attach(dev, device_get_unit(dev));
 706         return bus_generic_attach(dev);
 707 }
 708
 709 static device_method_t isab_methods[] = {
 710         /* Device interface */
 711         DEVMETHOD(device_probe,         isab_probe),
 712         DEVMETHOD(device_attach,        isab_attach),
 713         DEVMETHOD(device_shutdown,      bus_generic_shutdown),
 714         DEVMETHOD(device_suspend,       bus_generic_suspend),
 715         DEVMETHOD(device_resume,        bus_generic_resume),
 716
 717         /* Bus interface */
 718         DEVMETHOD(bus_print_child,      bus_generic_print_child),
 719         DEVMETHOD(bus_alloc_resource,   bus_generic_alloc_resource),
 720         DEVMETHOD(bus_release_resource, bus_generic_release_resource),
 721         DEVMETHOD(bus_activate_resource, bus_generic_activate_resource),
 722         DEVMETHOD(bus_deactivate_resource, bus_generic_deactivate_resource),
 723         DEVMETHOD(bus_setup_intr,       bus_generic_setup_intr),
 724         DEVMETHOD(bus_teardown_intr,    bus_generic_teardown_intr),
 725
 726         { 0, 0 }
 727 };
 728
 729 static driver_t isab_driver = {
 730         "isab",
 731         isab_methods,
 732         1,
 733 };
 734
 735 devclass_t isab_devclass;
 736
 737 DRIVER_MODULE(isab, pci, isab_driver, isab_devclass, 0, 0);