sys/dev/netif/pdq_layer/pdqreg.h

   1 /*-
   2  * Copyright (c) 1995, 1996 Matt Thomas <matt@3am-software.com>
   3  * All rights reserved.
   4  *
   5  * Redistribution and use in source and binary forms, with or without
   6  * modification, are permitted provided that the following conditions
   7  * are met:
   8  * 1. Redistributions of source code must retain the above copyright
   9  *    notice, this list of conditions and the following disclaimer.
  10  * 2. The name of the author may not be used to endorse or promote products
  11  *    derived from this software withough specific prior written permission
  12  *
  13  * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
  14  * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
  15  * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
  16  * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
  17  * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
  18  * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  19  * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  20  * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  21  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
  22  * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  23  *
  24  * $FreeBSD: src/sys/dev/pdq/pdqreg.h,v 1.2 1999/08/28 00:42:20 peter Exp $
  25  * $DragonFly: src/sys/dev/netif/pdq_layer/Attic/pdqreg.h,v 1.4 2005/05/05 22:57:44 swildner Exp $
  26  *
  27  */
  28
  29 /*
  30  * DEC PDQ FDDI Controller; PDQ port driver definitions
  31  *
  32  */
  33
  34 #ifndef _PDQREG_H
  35 #define _PDQREG_H
  36
  37 #if defined(PDQTEST) && !defined(PDQ_NDEBUG)
  38 #include <assert.h>
  39 #define PDQ_ASSERT      assert
  40 #else
  41 #define PDQ_ASSERT(x)   do { } while(0)
  42 #endif
  43
  44 #define PDQ_RING_SIZE(array)    ((sizeof(array) / sizeof(array[0])))
  45 #define PDQ_ARRAY_SIZE(array)   ((sizeof(array) / sizeof(array[0])))
  46 #define PDQ_RING_MASK(array)    (PDQ_RING_SIZE(array) - 1)
  47 #define PDQ_BITMASK(n)          (1L << (pdq_uint32_t) (n))
  48
  49 #define PDQ_FDDI_MAX            4495
  50 #define PDQ_FDDI_LLC_MIN        20
  51 #define PDQ_FDDI_SMT_MIN        37
  52
  53 #define PDQ_FDDI_SMT            0x40
  54 #define PDQ_FDDI_LLC_ASYNC      0x50
  55 #define PDQ_FDDI_LLC_SYNC       0xD0
  56 #define PDQ_FDDI_IMP_ASYNC      0x60
  57 #define PDQ_FDDI_IMP_SYNC       0xE0
  58
  59 #define PDQ_FDDIFC_C            0x80
  60 #define PDQ_FDDIFC_L            0x40
  61 #define PDQ_FDDIFC_F            0x30
  62 #define PDQ_FDDIFC_Z            0x0F
  63
  64 #define PDQ_FDDI_PH0            0x20
  65 #define PDQ_FDDI_PH1            0x38
  66 #define PDQ_FDDI_PH2            0x00
  67
  68 typedef pdq_uint32_t pdq_physaddr_t;
  69
  70 struct _pdq_lanaddr_t {
  71     pdq_uint8_t lanaddr_bytes[8];
  72 };
  73
  74 typedef struct {
  75     pdq_uint8_t fwrev_bytes[4];
  76 } pdq_fwrev_t;
  77
  78 enum _pdq_state_t {
  79     PDQS_RESET=0,
  80     PDQS_UPGRADE=1,
  81     PDQS_DMA_UNAVAILABLE=2,
  82     PDQS_DMA_AVAILABLE=3,
  83     PDQS_LINK_AVAILABLE=4,
  84     PDQS_LINK_UNAVAILABLE=5,
  85     PDQS_HALTED=6,
  86     PDQS_RING_MEMBER=7
  87 };
  88
  89 struct _pdq_csrs_t {
  90     pdq_bus_memoffset_t csr_port_reset;                 /* 0x00 [RW] */
  91     pdq_bus_memoffset_t csr_host_data;                  /* 0x04 [R]  */
  92     pdq_bus_memoffset_t csr_port_control;               /* 0x08 [RW] */
  93     pdq_bus_memoffset_t csr_port_data_a;                /* 0x0C [RW] */
  94     pdq_bus_memoffset_t csr_port_data_b;                /* 0x10 [RW] */
  95     pdq_bus_memoffset_t csr_port_status;                /* 0x14 [R]  */
  96     pdq_bus_memoffset_t csr_host_int_type_0;            /* 0x18 [RW] */
  97     pdq_bus_memoffset_t csr_host_int_enable;            /* 0x1C [RW] */
  98     pdq_bus_memoffset_t csr_type_2_producer;            /* 0x20 [RW] */
  99     pdq_bus_memoffset_t csr_cmd_response_producer;      /* 0x28 [RW] */
 100     pdq_bus_memoffset_t csr_cmd_request_producer;       /* 0x2C [RW] */
 101     pdq_bus_memoffset_t csr_host_smt_producer;          /* 0x30 [RW] */
 102     pdq_bus_memoffset_t csr_unsolicited_producer;       /* 0x34 [RW] */
 103     pdq_bus_t csr_bus;
 104     pdq_bus_memaddr_t csr_base;
 105 };
 106
 107 struct _pdq_pci_csrs_t {
 108     pdq_bus_memoffset_t csr_pfi_mode_control;           /* 0x40 [RW] */
 109     pdq_bus_memoffset_t csr_pfi_status;                 /* 0x44 [RW] */
 110     pdq_bus_memoffset_t csr_fifo_write;                 /* 0x48 [RW] */
 111     pdq_bus_memoffset_t csr_fifo_read;                  /* 0x4C [RW] */
 112     pdq_bus_t csr_bus;
 113     pdq_bus_memaddr_t csr_base;
 114 };
 115
 116 #define PDQ_PFI_MODE_DMA_ENABLE         0x01    /* DMA Enable */
 117 #define PDQ_PFI_MODE_PFI_PCI_INTR       0x02    /* PFI-to-PCI Int Enable */
 118 #define PDQ_PFI_MODE_PDQ_PCI_INTR       0x04    /* PDQ-to-PCI Int Enable */
 119
 120 #define PDQ_PFI_STATUS_PDQ_INTR         0x10    /* PDQ Int received */
 121 #define PDQ_PFI_STATUS_DMA_ABORT        0x08    /* PDQ DMA Abort asserted */
 122
 123 #define PDQ_EISA_BURST_HOLDOFF                  0x0040
 124 #define PDQ_EISA_SLOT_ID                        0x0C80
 125 #define PDQ_EISA_SLOT_CTRL                      0x0C84
 126 #define PDQ_EISA_MEM_ADD_CMP_0                  0x0C85
 127 #define PDQ_EISA_MEM_ADD_CMP_1                  0x0C86
 128 #define PDQ_EISA_MEM_ADD_CMP_2                  0x0C87
 129 #define PDQ_EISA_MEM_ADD_HI_CMP_0               0x0C88
 130 #define PDQ_EISA_MEM_ADD_HI_CMP_1               0x0C89
 131 #define PDQ_EISA_MEM_ADD_HI_CMP_2               0x0C8A
 132 #define PDQ_EISA_MEM_ADD_MASK_0                 0x0C8B
 133 #define PDQ_EISA_MEM_ADD_MASK_1                 0x0C8C
 134 #define PDQ_EISA_MEM_ADD_MASK_2                 0x0C8D
 135 #define PDQ_EISA_MEM_ADD_LO_CMP_0               0x0C8E
 136 #define PDQ_EISA_MEM_ADD_LO_CMP_1               0x0C8F
 137 #define PDQ_EISA_MEM_ADD_LO_CMP_2               0x0C90
 138 #define PDQ_EISA_IO_CMP_0_0                     0x0C91
 139 #define PDQ_EISA_IO_CMP_0_1                     0x0C92
 140 #define PDQ_EISA_IO_CMP_1_0                     0x0C93
 141 #define PDQ_EISA_IO_CMP_1_1                     0x0C94
 142 #define PDQ_EISA_IO_CMP_2_0                     0x0C95
 143 #define PDQ_EISA_IO_CMP_2_1                     0x0C96
 144 #define PDQ_EISA_IO_CMP_3_0                     0x0C97
 145 #define PDQ_EISA_IO_CMP_3_1                     0x0C98
 146 #define PDQ_EISA_IO_ADD_MASK_0_0                0x0C99
 147 #define PDQ_EISA_IO_ADD_MASK_0_1                0x0C9A
 148 #define PDQ_EISA_IO_ADD_MASK_1_0                0x0C9B
 149 #define PDQ_EISA_IO_ADD_MASK_1_1                0x0C9C
 150 #define PDQ_EISA_IO_ADD_MASK_2_0                0x0C9D
 151 #define PDQ_EISA_IO_ADD_MASK_2_1                0x0C9E
 152 #define PDQ_EISA_IO_ADD_MASK_3_0                0x0C9F
 153 #define PDQ_EISA_IO_ADD_MASK_3_1                0x0CA0
 154 #define PDQ_EISA_MOD_CONFIG_1                   0x0CA1
 155 #define PDQ_EISA_MOD_CONFIG_2                   0x0CA2
 156 #define PDQ_EISA_MOD_CONFIG_3                   0x0CA3
 157 #define PDQ_EISA_MOD_CONFIG_4                   0x0CA4
 158 #define PDQ_EISA_MOD_CONFIG_5                   0x0CA5
 159 #define PDQ_EISA_MOD_CONFIG_6                   0x0CA6
 160 #define PDQ_EISA_MOD_CONFIG_7                   0x0CA7
 161 #define PDQ_EISA_DIP_SWITCH                     0x0CA8
 162 #define PDQ_EISA_IO_CONFIG_STAT_0               0x0CA9
 163 #define PDQ_EISA_IO_CONFIG_STAT_1               0x0CAA
 164 #define PDQ_EISA_DMA_CONFIG                     0x0CAB
 165 #define PDQ_EISA_INPUT_PORT                     0x0CAC
 166 #define PDQ_EISA_OUTPUT_PORT                    0x0CAD
 167 #define PDQ_EISA_FUNCTION_CTRL                  0x0CAE
 168
 169 #define PDQ_TC_CSR_OFFSET                       0x00100000
 170 #define PDQ_TC_CSR_SPACE                        0x0040
 171 #define PDQ_FBUS_CSR_OFFSET                     0x00200000
 172 #define PDQ_FBUS_CSR_SPACE                      0x0080
 173
 174 /*
 175  * Port Reset Data A Definitions
 176  */
 177 #define PDQ_PRESET_SKIP_SELFTEST        0x0004
 178 #define PDQ_PRESET_SOFT_RESET           0x0002
 179 #define PDQ_PRESET_UPGRADE              0x0001
 180 /*
 181  * Port Control Register Definitions
 182  */
 183 #define PDQ_PCTL_CMD_ERROR              0x8000
 184 #define PDQ_PCTL_FLASH_BLAST            0x4000
 185 #define PDQ_PCTL_HALT                   0x2000
 186 #define PDQ_PCTL_COPY_DATA              0x1000
 187 #define PDQ_PCTL_ERROR_LOG_START        0x0800
 188 #define PDQ_PCTL_ERROR_LOG_READ         0x0400
 189 #define PDQ_PCTL_XMT_DATA_FLUSH_DONE    0x0200
 190 #define PDQ_PCTL_DMA_INIT               0x0100
 191 #define PDQ_DMA_INIT_LW_BSWAP_DATA      0x02
 192 #define PDQ_DMA_INIT_LW_BSWAP_LITERAL   0x01
 193 #define PDQ_PCTL_INIT_START             0x0080
 194 #define PDQ_PCTL_CONSUMER_BLOCK         0x0040
 195 #define PDQ_PCTL_DMA_UNINIT             0x0020
 196 #define PDQ_PCTL_RING_MEMBER            0x0010
 197 #define PDQ_PCTL_MLA_READ               0x0008
 198 #define PDQ_PCTL_FW_REV_READ            0x0004
 199 #define PDQ_PCTL_DEVICE_SPECIFIC        0x0002
 200 #define PDQ_PCTL_SUB_CMD                0x0001
 201
 202 typedef enum {
 203     PDQ_SUB_CMD_LINK_UNINIT=1,
 204     PDQ_SUB_CMD_DMA_BURST_SIZE_SET=2,
 205     PDQ_SUB_CMD_PDQ_REV_GET=4
 206 } pdq_sub_cmd_t;
 207
 208 typedef enum {
 209     PDQ_DMA_BURST_4LW=0,
 210     PDQ_DMA_BURST_8LW=1,
 211     PDQ_DMA_BURST_16LW=2,
 212     PDQ_DMA_BURST_32LW=3
 213 } pdq_dma_burst_size_t;
 214
 215 typedef enum {
 216     PDQ_CHIP_REV_A_B_OR_C=0,
 217     PDQ_CHIP_REV_D=2,
 218     PDQ_CHIP_REV_E=4
 219 } pdq_chip_rev_t;
 220 /*
 221  * Port Status Register Definitions
 222  */
 223 #define PDQ_PSTS_RCV_DATA_PENDING       0x80000000ul
 224 #define PDQ_PSTS_XMT_DATA_PENDING       0x40000000ul
 225 #define PDQ_PSTS_HOST_SMT_PENDING       0x20000000ul
 226 #define PDQ_PSTS_UNSOL_PENDING          0x10000000ul
 227 #define PDQ_PSTS_CMD_RSP_PENDING        0x08000000ul
 228 #define PDQ_PSTS_CMD_REQ_PENDING        0x04000000ul
 229 #define PDQ_PSTS_TYPE_0_PENDING         0x02000000ul
 230 #define PDQ_PSTS_INTR_PENDING           0xFE000000ul
 231 #define PDQ_PSTS_ADAPTER_STATE(sts)     ((pdq_state_t) (((sts) >> 8) & 0x07))
 232 #define PDQ_PSTS_HALT_ID(sts)           ((pdq_halt_code_t) ((sts) & 0xFF))
 233 /*
 234  * Host Interrupt Register Definitions
 235  */
 236 #define PDQ_HOST_INT_TX_ENABLE                  0x80000000ul
 237 #define PDQ_HOST_INT_RX_ENABLE                  0x40000000ul
 238 #define PDQ_HOST_INT_UNSOL_ENABLE               0x20000000ul
 239 #define PDQ_HOST_INT_HOST_SMT_ENABLE            0x10000000ul
 240 #define PDQ_HOST_INT_CMD_RSP_ENABLE             0x08000000ul
 241 #define PDQ_HOST_INT_CMD_RQST_ENABLE            0x04000000ul
 242
 243 #define PDQ_HOST_INT_1MS                        0x80
 244 #define PDQ_HOST_INT_20MS                       0x40
 245 #define PDQ_HOST_INT_CSR_CMD_DONE               0x20
 246 #define PDQ_HOST_INT_STATE_CHANGE               0x10
 247 #define PDQ_HOST_INT_XMT_DATA_FLUSH             0x08
 248 #define PDQ_HOST_INT_NXM                        0x04
 249 #define PDQ_HOST_INT_PM_PARITY_ERROR            0x02
 250 #define PDQ_HOST_INT_HOST_BUS_PARITY_ERROR      0x01
 251 #define PDQ_HOST_INT_FATAL_ERROR                0x07
 252
 253 typedef enum {
 254     PDQH_SELFTEST_TIMEOUT=0,
 255     PDQH_HOST_BUS_PARITY_ERROR=1,
 256     PDQH_HOST_DIRECTED_HALT=2,
 257     PDQH_SOFTWARE_FAULT=3,
 258     PDQH_HARDWARE_FAULT=4,
 259     PDQH_PC_TRACE_PATH_TEST=5,
 260     PDQH_DMA_ERROR=6,
 261     PDQH_IMAGE_CRC_ERROR=7,
 262     PDQH_ADAPTER_PROCESSOR_ERROR=8,
 263     PDQH_MAX=9
 264 } pdq_halt_code_t;
 265
 266 typedef struct {
 267     pdq_uint16_t pdqcb_receives;
 268     pdq_uint16_t pdqcb_transmits;
 269     pdq_uint32_t pdqcb__filler1;
 270     pdq_uint32_t pdqcb_host_smt;
 271     pdq_uint32_t pdqcb__filler2;
 272     pdq_uint32_t pdqcb_unsolicited_event;
 273     pdq_uint32_t pdqcb__filler3;
 274     pdq_uint32_t pdqcb_command_response;
 275     pdq_uint32_t pdqcb__filler4;
 276     pdq_uint32_t pdqcb_command_request;
 277     pdq_uint32_t pdqcb__filler5[7];
 278 } pdq_consumer_block_t;
 279
 280 #if defined(BYTE_ORDER) && BYTE_ORDER == BIG_ENDIAN
 281 #define PDQ_BITFIELD2(a, b)                      b, a
 282 #define PDQ_BITFIELD3(a, b, c)                c, b, a
 283 #define PDQ_BITFIELD4(a, b, c, d)          d, c, b, a
 284 #define PDQ_BITFIELD5(a, b, c, d, e)    e, d, c, b, a
 285 #define PDQ_BITFIELD12(a, b, c, d, e, f, g, h, i, j, k, l)      \
 286                                         l, k, j, i, h, g, f, e, d, c, b, a
 287 #else
 288 #define PDQ_BITFIELD2(a, b)             a, b
 289 #define PDQ_BITFIELD3(a, b, c)          a, b, c
 290 #define PDQ_BITFIELD4(a, b, c, d)       a, b, c, d
 291 #define PDQ_BITFIELD5(a, b, c, d, e)    a, b, c, d, e
 292 #define PDQ_BITFIELD12(a, b, c, d, e, f, g, h, i, j, k, l)      \
 293                                         a, b, c, d, e, f, g, h, i, j, k, l
 294 #endif
 295
 296 typedef struct {
 297     pdq_uint32_t PDQ_BITFIELD5(rxd_pa_hi : 16,
 298                                rxd_seg_cnt : 4,
 299                                rxd_seg_len_hi : 9,
 300                                rxd_seg_len_lo : 2,
 301                                rxd_sop : 1);
 302     pdq_uint32_t rxd_pa_lo;
 303 } pdq_rxdesc_t;
 304
 305 typedef union {
 306     pdq_uint32_t rxs_status;
 307     pdq_uint32_t PDQ_BITFIELD12(rxs_len : 13,
 308                                 rxs_rcc_ss : 2,
 309                                 rxs_rcc_dd : 2,
 310                                 rxs_rcc_reason : 3,
 311                                 rxs_rcc_badcrc : 1,
 312                                 rxs_rcc_badpdu : 1,
 313                                 rxs_fsb__reserved : 2,
 314                                 rxs_fsb_c : 1,
 315                                 rxs_fsb_a : 1,
 316                                 rxs_fsb_e : 1,
 317                                 rxs_fsc : 3,
 318                                 rxs__reserved : 2);
 319 } pdq_rxstatus_t;
 320
 321 typedef struct {
 322     pdq_uint32_t PDQ_BITFIELD5(txd_pa_hi : 16,
 323                                txd_seg_len : 13,
 324                                txd_mbz : 1,
 325                                txd_eop : 1,
 326                                txd_sop : 1);
 327     pdq_uint32_t txd_pa_lo;
 328 } pdq_txdesc_t;
 329
 330 typedef struct {
 331     pdq_rxdesc_t pdqdb_receives[256];           /* 2048;        0x0000..0x07FF */
 332     pdq_txdesc_t pdqdb_transmits[256];          /* 2048;        0x0800..0x0FFF */
 333     pdq_rxdesc_t pdqdb_host_smt[64];            /*  512;        0x1000..0x11FF */
 334     pdq_rxdesc_t pdqdb_unsolicited_events[16];  /*  128;        0x1200..0x127F */
 335     pdq_rxdesc_t pdqdb_command_responses[16];   /*  128;        0x1280..0x12FF */
 336     pdq_txdesc_t pdqdb_command_requests[16];    /*  128;        0x1300..0x137F */
 337     /*
 338      * The rest of the descriptor block is unused.
 339      * As such we could use it for other things.
 340      */
 341     pdq_consumer_block_t pdqdb_consumer;        /*   64;        0x1380..0x13BF */
 342     void *pdqdb_receive_buffers[256];           /* 1024/2048;   0x13C0..0x17BF 0x13C0..0x1BBF */
 343     void *pdqdb_host_smt_buffers[64];           /*  256/ 512;   0x17C0..0x18BF 0x1BC0..0x1DBF */
 344     /*
 345      * The maximum command size is 512 so as long as thes
 346      * command is at least that long all will be fine.
 347      */
 348     pdq_uint32_t pdqdb_command_pool[464];
 349 } pdq_descriptor_block_t;
 350
 351 typedef struct {
 352     /*
 353      * These value manage the available space in command/response
 354      * buffer area.
 355      */
 356     pdq_physaddr_t ci_pa_bufstart;
 357     pdq_uint8_t *ci_bufstart;
 358     /*
 359      * Bitmask of commands to sent to the PDQ
 360      */
 361     pdq_uint32_t ci_pending_commands;
 362     /*
 363      * Variables to maintain the PDQ queues.
 364      */
 365     pdq_uint32_t ci_command_active;
 366     pdq_uint32_t ci_request_producer;
 367     pdq_uint32_t ci_response_producer;
 368     pdq_uint32_t ci_request_completion;
 369     pdq_uint32_t ci_response_completion;
 370 } pdq_command_info_t;
 371
 372 #define PDQ_SIZE_UNSOLICITED_EVENT      512
 373 #define PDQ_NUM_UNSOLICITED_EVENTS      (PDQ_OS_PAGESIZE / PDQ_SIZE_UNSOLICITED_EVENT)
 374
 375 typedef struct _pdq_unsolicited_event_t pdq_unsolicited_event_t;
 376
 377 typedef struct {
 378     pdq_physaddr_t ui_pa_bufstart;
 379     pdq_unsolicited_event_t *ui_events;
 380
 381     pdq_uint32_t ui_free;
 382     pdq_uint32_t ui_producer;
 383     pdq_uint32_t ui_completion;
 384 } pdq_unsolicited_info_t;
 385
 386 #define PDQ_RX_FC_OFFSET        (sizeof(pdq_rxstatus_t) + 3)
 387 #define PDQ_RX_SEGCNT           ((PDQ_FDDI_MAX + PDQ_OS_DATABUF_SIZE - 1) / PDQ_OS_DATABUF_SIZE)
 388 #define PDQ_DO_TYPE2_PRODUCER(pdq) \
 389     PDQ_CSR_WRITE(&(pdq)->pdq_csrs, csr_type_2_producer, \
 390           ((pdq)->pdq_rx_info.rx_producer << 0) \
 391         | ((pdq)->pdq_tx_info.tx_producer << 8) \
 392         | ((pdq)->pdq_rx_info.rx_completion << 16) \
 393         | ((pdq)->pdq_tx_info.tx_completion << 24))
 394
 395 #define PDQ_DO_HOST_SMT_PRODUCER(pdq) \
 396     PDQ_CSR_WRITE(&(pdq)->pdq_csrs, csr_host_smt_producer, \
 397           ((pdq)->pdq_host_smt_info.rx_producer   << 0) \
 398         | ((pdq)->pdq_host_smt_info.rx_completion << 8))\
 399
 400 #define PDQ_ADVANCE(n, a, m)    ((n) = ((n) + (a)) & (m))
 401
 402 typedef struct {
 403     void *q_head;
 404     void *q_tail;
 405 } pdq_databuf_queue_t;
 406
 407 typedef struct {
 408     void *rx_buffers;
 409
 410     pdq_uint32_t rx_target;
 411     pdq_uint32_t rx_free;
 412     pdq_uint32_t rx_producer;
 413     pdq_uint32_t rx_completion;
 414 } pdq_rx_info_t;
 415
 416 typedef struct {
 417     pdq_databuf_queue_t tx_txq;
 418     pdq_txdesc_t tx_hdrdesc;
 419     pdq_uint8_t tx_descriptor_count[256];
 420
 421     pdq_uint32_t tx_free;
 422     pdq_uint32_t tx_producer;
 423     pdq_uint32_t tx_completion;
 424 } pdq_tx_info_t;
 425
 426 struct _pdq_t {
 427     pdq_csrs_t pdq_csrs;
 428     pdq_pci_csrs_t pdq_pci_csrs;
 429     pdq_type_t pdq_type;
 430     pdq_chip_rev_t pdq_chip_rev;
 431     pdq_lanaddr_t pdq_hwaddr;
 432     pdq_fwrev_t pdq_fwrev;
 433     pdq_descriptor_block_t *pdq_dbp;
 434     volatile pdq_consumer_block_t *pdq_cbp;
 435     pdq_uint32_t pdq_flags;
 436 #define PDQ_PROMISC     0x0001
 437 #define PDQ_ALLMULTI    0x0002
 438 #define PDQ_PASS_SMT    0x0004
 439 #define PDQ_RUNNING     0x0008
 440 #define PDQ_PRINTCHARS  0x0010
 441 #define PDQ_TXOK        0x0020
 442     const char *pdq_os_name;
 443     void *pdq_os_ctx;
 444     pdq_uint32_t pdq_unit;
 445     pdq_command_info_t pdq_command_info;
 446     pdq_unsolicited_info_t pdq_unsolicited_info;
 447     pdq_tx_info_t pdq_tx_info;
 448     pdq_rx_info_t pdq_rx_info;
 449     pdq_rx_info_t pdq_host_smt_info;
 450     pdq_uint8_t pdq_tx_hdr[3];
 451 };
 452
 453 typedef enum {
 454     PDQC_START=0,
 455     PDQC_FILTER_SET=1,
 456     PDQC_FILTER_GET=2,
 457     PDQC_CHARS_SET=3,
 458     PDQC_STATUS_CHARS_GET=4,
 459     PDQC_COUNTERS_GET=5,
 460     PDQC_COUNTERS_SET=6,
 461     PDQC_ADDR_FILTER_SET=7,
 462     PDQC_ADDR_FILTER_GET=8,
 463     PDQC_ERROR_LOG_CLEAR=9,
 464     PDQC_ERROR_LOG_GET=10,
 465     PDQC_FDDI_MIB_GET=11,
 466     PDQC_DEC_EXT_MIB_GET=12,
 467     PDQC_DEV_SPECIFIC_GET=13,
 468     PDQC_SNMP_SET=14,
 469     PDQC_SMT_MIB_GET=16,
 470     PDQC_SMT_MIB_SET=17
 471 } pdq_cmd_code_t;
 472
 473 typedef enum {
 474     PDQR_SUCCESS=0,
 475     PDQR_FAILURE=1,
 476     PDQR_WARNING=2,
 477     PDQR_LOOP_MODE_BAD=3,
 478     PDQR_ITEM_CODE_BAD=4,
 479     PDQR_TVX_BAD=5,
 480     PDQR_TREQ_BAD=6,
 481     PDQR_RESTRICTED_TOKEN_BAD=7,
 482     PDQR_NO_EOL=12,
 483     PDQR_FILTER_STATE_BAD=13,
 484     PDQR_CMD_TYPE_BAD=14,
 485     PDQR_ADAPTER_STATE_BAD=15,
 486     PDQR_RING_PURGER_BAD=16,
 487     PDQR_LEM_THRESHOLD_BAD=17,
 488     PDQR_LOOP_NOT_SUPPORTED=18,
 489     PDQR_FLUSH_TIME_BAD=19,
 490     PDQR_NOT_YET_IMPLEMENTED=20,
 491     PDQR_CONFIG_POLICY_BAD=21,
 492     PDQR_STATION_ACTION_BAD=22,
 493     PDQR_MAC_ACTION_BAD=23,
 494     PDQR_CON_POLICIES_BAD=24,
 495     PDQR_MAC_LOOP_TIME_BAD=25,
 496     PDQR_TB_MAX_BAD=26,
 497     PDQR_LER_CUTOFF_BAD=27,
 498     PDQR_LER_ALARM_BAD=28,
 499     PDQR_MAC_PATHS_REQ_BAD=29,
 500     PDQR_MAC_T_REQ_BAD=30,
 501     PDQR_EMAC_RING_PURGER_BAD=31,
 502     PDQR_EMAC_RTOKEN_TIMOUT_AD=32,
 503     PDQR_NO_SUCH_ENTRY=33,
 504     PDQR_T_NOTIFY_BAD=34,
 505     PDQR_TR_MAX_EXP_BAD=35,
 506     PDQR_FRAME_ERR_THRESHOLD_BAD=36,
 507     PDQR_MAX_TREQ_BAD=37,
 508     PDQR_FULL_DUPLEX_ENABLE_BAD=38,
 509     PDQR_ITEM_INDEX_BAD=39
 510 } pdq_response_code_t;
 511
 512 typedef enum {
 513     PDQI_EOL=0,
 514     PDQI_T_REQ=1,
 515     PDQI_TVX=2,
 516     PDQI_RESTRICTED_TOKEN=3,
 517     PDQI_LEM_THRESHOLD=4,
 518     PDQI_RING_PURGER=5,
 519     PDQI_COUNTER_INTERVAL=6,
 520     PDQI_IND_GROUP_PROM=7,
 521     PDQI_GROUP_PROM=8,
 522     PDQI_BROADCAST=9,
 523     PDQI_SMT_PROM=10,
 524     PDQI_SMT_USER=11,
 525     PDQI_RESERVED=12,
 526     PDQI_IMPLEMENTOR=13,
 527     PDQI_LOOPBACK_MODE=14,
 528     PDQI_SMT_CONFIG_POLICY=16,
 529     PDQI_SMT_CONNECTION_POLICY=17,
 530     PDQI_SMT_T_NOTIFY=18,
 531     PDQI_SMT_STATION_ACTION=19,
 532     PDQI_MAC_PATHS_REQUESTED=21,
 533     PDQI_MAC_ACTION=23,
 534     PDQI_PORT_CONNECTION_POLICIES=24,
 535     PDQI_PORT_PATHS_REQUESTED=25,
 536     PDQI_PORT_MAC_LOOP_TIME=26,
 537     PDQI_PORT_TB_MAX=27,
 538     PDQI_PORT_LER_CUTOFF=28,
 539     PDQI_PORT_LER_ALARM=29,
 540     PDQI_PORT_ACTION=30,
 541     PDQI_FLUSH_TIME=32,
 542     PDQI_SMT_USER_DATA=33,
 543     PDQI_SMT_STATUS_REPORT_POLICY=34,
 544     PDQI_SMT_TRACE_MAX_EXPIRATION=35,
 545     PDQI_MAC_FRAME_ERR_THRESHOLD=36,
 546     PDQI_MAC_UNIT_DATA_ENABLE=37,
 547     PDQI_PATH_TVX_LOWER_BOUND=38,
 548     PDQI_PATH_TMAX_LOWER_BOUND=39,
 549     PDQI_PATH_MAX_TREQ=40,
 550     PDQI_MAC_TREQ=41,
 551     PDQI_EMAC_RING_PURGER=42,
 552     PDQI_EMAC_RTOKEN_TIMEOUT=43,
 553     PDQI_FULL_DUPLEX_ENABLE=44
 554 } pdq_item_code_t;
 555
 556 enum _pdq_boolean_t {
 557     PDQ_FALSE=0,
 558     PDQ_TRUE=1
 559 };
 560
 561 typedef enum {
 562     PDQ_FILTER_BLOCK=0,
 563     PDQ_FILTER_PASS=1
 564 } pdq_filter_state_t;
 565
 566 typedef enum {
 567     PDQ_STATION_TYPE_SAS=0,
 568     PDQ_STATION_TYPE_DAC=1,
 569     PDQ_STATION_TYPE_SAC=2,
 570     PDQ_STATION_TYPE_NAC=3,
 571     PDQ_STATION_TYPE_DAS=4
 572 } pdq_station_type_t;
 573
 574 typedef enum {
 575     PDQ_STATION_STATE_OFF=0,
 576     PDQ_STATION_STATE_ON=1,
 577     PDQ_STATION_STATE_LOOPBACK=2
 578 } pdq_station_state_t;
 579
 580 typedef enum {
 581     PDQ_LINK_STATE_OFF_READY=1,
 582     PDQ_LINK_STATE_OFF_FAULT_RECOVERY=2,
 583     PDQ_LINK_STATE_ON_RING_INIT=3,
 584     PDQ_LINK_STATE_ON_RING_RUN=4,
 585     PDQ_LINK_STATE_BROKEN=5
 586 } pdq_link_state_t;
 587
 588 typedef enum {
 589     PDQ_DA_TEST_STATE_UNKNOWN=0,
 590     PDQ_DA_TEST_STATE_SUCCESS=1,
 591     PDQ_DA_TEST_STATE_DUPLICATE=2
 592 } pdq_da_test_state_t;
 593
 594 typedef enum {
 595     PDQ_RING_PURGER_STATE_OFF=0,
 596     PDQ_RING_PURGER_STATE_CANDIDATE=1,
 597     PDQ_RING_PURGER_STATE_NON_PURGER=2,
 598     PDQ_RING_PURGER_STATE_PURGER=3
 599 } pdq_ring_purger_state_t;
 600
 601 typedef enum {
 602     PDQ_FRAME_STRING_MODE_SA_MATCH=0,
 603     PDQ_FRAME_STRING_MODE_FCI_STRIP=1
 604 } pdq_frame_strip_mode_t;
 605
 606 typedef enum {
 607     PDQ_RING_ERROR_REASON_NO_ERROR=0,
 608     PDQ_RING_ERROR_REASON_RING_INIT_INITIATED=5,
 609     PDQ_RING_ERROR_REASON_RING_INIT_RECEIVED=6,
 610     PDQ_RING_ERROR_REASON_RING_BEACONING_INITIATED=7,
 611     PDQ_RING_ERROR_REASON_DUPLICATE_ADDRESS_DETECTED=8,
 612     PDQ_RING_ERROR_REASON_DUPLICATE_TOKEN_DETECTED=9,
 613     PDQ_RING_ERROR_REASON_RING_PURGER_ERROR=10,
 614     PDQ_RING_ERROR_REASON_FCI_STRIP_ERROR=11,
 615     PDQ_RING_ERROR_REASON_RING_OP_OSCILLATION=12,
 616     PDQ_RING_ERROR_REASON_DIRECTED_BEACON_RECEVIED=13,
 617     PDQ_RING_ERROR_REASON_PC_TRACE_INITIATED=14,
 618     PDQ_RING_ERROR_REASON_PC_TRACE_RECEVIED=15
 619 } pdq_ring_error_reason_t;
 620
 621 typedef enum {
 622     PDQ_STATION_MODE_NORMAL=0,
 623     PDQ_STATION_MODE_INTERNAL_LOOPBACK=1
 624 } pdq_station_mode_t;
 625
 626 typedef enum {
 627     PDQ_PHY_TYPE_A=0,
 628     PDQ_PHY_TYPE_B=1,
 629     PDQ_PHY_TYPE_S=2,
 630     PDQ_PHY_TYPE_M=3,
 631     PDQ_PHY_TYPE_UNKNOWN=4
 632 } pdq_phy_type_t;
 633
 634 typedef enum {
 635     PDQ_PMD_TYPE_ANSI_MUTLI_MODE=0,
 636     PDQ_PMD_TYPE_ANSI_SINGLE_MODE_TYPE_1=1,
 637     PDQ_PMD_TYPE_ANSI_SIGNLE_MODE_TYPE_2=2,
 638     PDQ_PMD_TYPE_ANSI_SONET=3,
 639     PDQ_PMD_TYPE_LOW_POWER=100,
 640     PDQ_PMD_TYPE_THINWIRE=101,
 641     PDQ_PMD_TYPE_SHIELDED_TWISTED_PAIR=102,
 642     PDQ_PMD_TYPE_UNSHIELDED_TWISTED_PAIR=103
 643 } pdq_pmd_type_t;
 644
 645 typedef enum {
 646     PDQ_PMD_CLASS_ANSI_MULTI_MODE=0,
 647     PDQ_PMD_CLASS_SINGLE_MODE_TYPE_1=1,
 648     PDQ_PMD_CLASS_SINGLE_MODE_TYPE_2=2,
 649     PDQ_PMD_CLASS_SONET=3,
 650     PDQ_PMD_CLASS_LOW_COST_POWER_FIBER=4,
 651     PDQ_PMD_CLASS_TWISTED_PAIR=5,
 652     PDQ_PMD_CLASS_UNKNOWN=6,
 653     PDQ_PMD_CLASS_UNSPECIFIED=7
 654 } pdq_pmd_class_t;
 655
 656 typedef enum {
 657     PDQ_PHY_STATE_INTERNAL_LOOPBACK=0,
 658     PDQ_PHY_STATE_BROKEN=1,
 659     PDQ_PHY_STATE_OFF_READY=2,
 660     PDQ_PHY_STATE_WAITING=3,
 661     PDQ_PHY_STATE_STARTING=4,
 662     PDQ_PHY_STATE_FAILED=5,
 663     PDQ_PHY_STATE_WATCH=6,
 664     PDQ_PHY_STATE_INUSE=7
 665 } pdq_phy_state_t;
 666
 667 typedef enum {
 668     PDQ_REJECT_REASON_NONE=0,
 669     PDQ_REJECT_REASON_LOCAL_LCT=1,
 670     PDQ_REJECT_REASON_REMOTE_LCT=2,
 671     PDQ_REJECT_REASON_LCT_BOTH_SIDES=3,
 672     PDQ_REJECT_REASON_LEM_REJECT=4,
 673     PDQ_REJECT_REASON_TOPOLOGY_ERROR=5,
 674     PDQ_REJECT_REASON_NOISE_REJECT=6,
 675     PDQ_REJECT_REASON_REMOTE_REJECT=7,
 676     PDQ_REJECT_REASON_TRACE_IN_PROGRESS=8,
 677     PDQ_REJECT_REASON_TRACE_RECEIVED_DISABLED=9,
 678     PDQ_REJECT_REASON_STANDBY=10,
 679     PDQ_REJECT_REASON_LCT_PROTOCOL_ERROR=11
 680 } pdq_reject_reason_t;
 681
 682 typedef enum {
 683     PDQ_BROKEN_REASON_NONE=0
 684 } pdq_broken_reason_t;
 685
 686 typedef enum {
 687     PDQ_RI_REASON_TVX_EXPIRED=0,
 688     PDQ_RI_REASON_TRT_EXPIRED=1,
 689     PDQ_RI_REASON_RING_PURGER_ELECTION_ATTEMPT_LIMIT_EXCEEDED=2,
 690     PDQ_RI_REASON_PURGE_ERROR_LIMIT_EXCEEDED=3,
 691     PDQ_RI_REASON_RESTRICTED_TOKEN_TIMEOUT=4
 692 } pdq_ri_reason_t;
 693
 694 typedef enum {
 695     PDQ_LCT_DIRECTION_LOCAL_LCT=0,
 696     PDQ_LCT_DIRECTION_REMOTE_LCT=1,
 697     PDQ_LCT_DIRECTION_LCT_BOTH_SIDES=2
 698 } pdq_lct_direction_t;
 699
 700 typedef enum {
 701     PDQ_PORT_A=0,
 702     PDQ_PORT_B=1
 703 } pdq_port_type_t;
 704
 705 typedef struct {
 706     pdq_uint8_t station_id_bytes[8];
 707 } pdq_station_id_t;
 708
 709 typedef pdq_uint32_t pdq_fdditimer_t;
 710 /*
 711  * Command format for Start, Filter_Get, ... commands
 712  */
 713 typedef struct {
 714     pdq_cmd_code_t generic_op;
 715 } pdq_cmd_generic_t;
 716
 717 /*
 718  * Response format for Start, Filter_Set, ... commands
 719  */
 720 typedef struct {
 721     pdq_uint32_t generic_reserved;
 722     pdq_cmd_code_t generic_op;
 723     pdq_response_code_t generic_status;
 724 } pdq_response_generic_t;
 725
 726 /*
 727  * Command format for Filter_Set command
 728  */
 729 typedef struct {
 730     pdq_cmd_code_t filter_set_op;
 731     struct {
 732         pdq_item_code_t item_code;
 733         pdq_filter_state_t filter_state;
 734     } filter_set_items[7];
 735     pdq_item_code_t filter_set_eol_item_code;
 736 } pdq_cmd_filter_set_t;
 737
 738 /*
 739  * Response format for Filter_Get command.
 740  */
 741 typedef struct {
 742     pdq_uint32_t filter_get_reserved;
 743     pdq_cmd_code_t filter_get_op;
 744     pdq_response_code_t filter_get_status;
 745     pdq_filter_state_t filter_get_ind_group_prom;
 746     pdq_filter_state_t filter_get_group_prom;
 747     pdq_filter_state_t filter_get_broadcast_all;
 748     pdq_filter_state_t filter_get_smt_prom;
 749     pdq_filter_state_t filter_get_smt_user;
 750     pdq_filter_state_t filter_get_reserved_all;
 751     pdq_filter_state_t filter_get_implementor_all;
 752 } pdq_response_filter_get_t;
 753
 754 #define PDQ_SIZE_RESPONSE_FILTER_GET    0x28
 755
 756 typedef struct {
 757     pdq_cmd_code_t chars_set_op;
 758     struct {
 759         pdq_item_code_t item_code;
 760         pdq_uint32_t item_value;
 761         pdq_port_type_t item_port;
 762     } chars_set_items[1];
 763     pdq_item_code_t chars_set_eol_item_code;
 764 } pdq_cmd_chars_set_t;
 765
 766 typedef struct {
 767     pdq_cmd_code_t addr_filter_set_op;
 768     pdq_lanaddr_t addr_filter_set_addresses[62];
 769 } pdq_cmd_addr_filter_set_t;
 770
 771 #define PDQ_SIZE_CMD_ADDR_FILTER_SET    0x1F4
 772
 773 typedef struct {
 774     pdq_uint32_t addr_filter_get_reserved;
 775     pdq_cmd_code_t addr_filter_get_op;
 776     pdq_response_code_t addr_filter_get_status;
 777     pdq_lanaddr_t addr_filter_get_addresses[62];
 778 } pdq_response_addr_filter_get_t;
 779
 780 #define PDQ_SIZE_RESPONSE_ADDR_FILTER_GET       0x1FC
 781
 782 typedef struct {
 783     pdq_uint32_t status_chars_get_reserved;
 784     pdq_cmd_code_t status_chars_get_op;
 785     pdq_response_code_t status_chars_get_status;
 786     struct {
 787         /* Station Characteristic Attributes */
 788         pdq_station_id_t station_id;
 789         pdq_station_type_t station_type;
 790         pdq_uint32_t smt_version_id;
 791         pdq_uint32_t smt_max_version_id;
 792         pdq_uint32_t smt_min_version_id;
 793         /* Station Status Attributes */
 794         pdq_station_state_t station_state;
 795         /* Link Characteristic Attributes */
 796         pdq_lanaddr_t link_address;
 797         pdq_fdditimer_t t_req;
 798         pdq_fdditimer_t tvx;
 799         pdq_fdditimer_t restricted_token_timeout;
 800         pdq_boolean_t ring_purger_enable;
 801         pdq_link_state_t link_state;
 802         pdq_fdditimer_t negotiated_trt;
 803         pdq_da_test_state_t dup_addr_flag;
 804         /* Link Status Attributes */
 805         pdq_lanaddr_t upstream_neighbor;
 806         pdq_lanaddr_t old_upstream_neighbor;
 807         pdq_boolean_t upstream_neighbor_dup_addr_flag;
 808         pdq_lanaddr_t downstream_neighbor;
 809         pdq_lanaddr_t old_downstream_neighbor;
 810         pdq_ring_purger_state_t ring_purger_state;
 811         pdq_frame_strip_mode_t frame_strip_mode;
 812         pdq_ring_error_reason_t ring_error_reason;
 813         pdq_boolean_t loopback;
 814         pdq_fdditimer_t ring_latency;
 815         pdq_lanaddr_t last_dir_beacon_sa;
 816         pdq_lanaddr_t last_dir_beacon_una;
 817         /* Phy Characteristic Attributes */
 818         pdq_phy_type_t phy_type[2];
 819         pdq_pmd_type_t pmd_type[2];
 820         pdq_uint32_t lem_threshold[2];
 821         /* Phy Status Attributes */
 822         pdq_phy_state_t phy_state[2];
 823         pdq_phy_type_t neighbor_phy_type[2];
 824         pdq_uint32_t link_error_estimate[2];
 825         pdq_broken_reason_t broken_reason[2];
 826         pdq_reject_reason_t reject_reason[2];
 827         /* Miscellaneous */
 828         pdq_uint32_t counter_interval;
 829         pdq_fwrev_t module_rev;
 830         pdq_fwrev_t firmware_rev;
 831         pdq_uint32_t mop_device_type;
 832         pdq_uint32_t fddi_led[2];
 833         pdq_uint32_t flush;
 834     } status_chars_get;
 835 } pdq_response_status_chars_get_t;
 836
 837 #define PDQ_SIZE_RESPONSE_STATUS_CHARS_GET      0xF0
 838
 839 typedef struct {
 840     pdq_uint32_t fddi_mib_get_reserved;
 841     pdq_cmd_code_t fddi_mib_get_op;
 842     pdq_response_code_t fddi_mib_get_status;
 843     struct {
 844         /* SMT Objects */
 845         pdq_station_id_t smt_station_id;
 846         pdq_uint32_t smt_op_version_id;
 847         pdq_uint32_t smt_hi_version_id;
 848         pdq_uint32_t smt_lo_version_id;
 849         pdq_uint32_t smt_mac_ct;
 850         pdq_uint32_t smt_non_master_ct;
 851         pdq_uint32_t smt_master_ct;
 852         pdq_uint32_t smt_paths_available;
 853         pdq_uint32_t smt_config_capabilities;
 854         pdq_uint32_t smt_config_policy;
 855         pdq_uint32_t smt_connection_policy;
 856         pdq_uint32_t smt_t_notify;
 857         pdq_uint32_t smt_status_reporting;
 858         pdq_uint32_t smt_ecm_state;
 859         pdq_uint32_t smt_cf_state;
 860         pdq_uint32_t smt_hold_state;
 861         pdq_uint32_t smt_remote_disconnect_flag;
 862         pdq_uint32_t smt_station_action;
 863         /* MAC Objects */
 864         pdq_uint32_t mac_frame_status_capabilities;
 865         pdq_uint32_t mac_t_max_greatest_lower_bound;
 866         pdq_uint32_t mac_tvx_greatest_lower_bound;
 867         pdq_uint32_t mac_paths_available;
 868         pdq_uint32_t mac_current_path;
 869         pdq_lanaddr_t mac_upstream_neighbor;
 870         pdq_lanaddr_t mac_old_upstream_neighbor;
 871         pdq_uint32_t mac_dup_addr_test;
 872         pdq_uint32_t mac_paths_requested;
 873         pdq_uint32_t mac_downstream_port_type;
 874         pdq_lanaddr_t mac_smt_address;
 875         pdq_uint32_t mac_t_req;
 876         pdq_uint32_t mac_t_neg;
 877         pdq_uint32_t mac_t_max;
 878         pdq_uint32_t mac_tvx_value;
 879         pdq_uint32_t mac_t_min;
 880         pdq_uint32_t mac_current_frame_status;
 881         pdq_uint32_t mac_frame_error_threshold;
 882         pdq_uint32_t mac_frame_error_ratio;
 883         pdq_uint32_t mac_rmt_state;
 884         pdq_uint32_t mac_da_flag;
 885         pdq_uint32_t mac_una_da_flag;
 886         pdq_uint32_t mac_frame_condition;
 887         pdq_uint32_t mac_chip_set;
 888         pdq_uint32_t mac_action;
 889         /* Port Objects */
 890         pdq_uint32_t port_pc_type[2];
 891         pdq_uint32_t port_pc_neighbor[2];
 892         pdq_uint32_t port_connection_policies[2];
 893         pdq_uint32_t port_remote_mac_indicated[2];
 894         pdq_uint32_t port_ce_state[2];
 895         pdq_uint32_t port_paths_requested[2];
 896         pdq_uint32_t port_mac_placement[2];
 897         pdq_uint32_t port_available_paths[2];
 898         pdq_uint32_t port_mac_loop_time[2];
 899         pdq_uint32_t port_tb_max[2];
 900         pdq_uint32_t port_bs_flag[2];
 901         pdq_uint32_t port_ler_estimate[2];
 902         pdq_uint32_t port_ler_cutoff[2];
 903         pdq_uint32_t port_ler_alarm[2];
 904         pdq_uint32_t port_connect_state[2];
 905         pdq_uint32_t port_pcm_state[2];
 906         pdq_uint32_t port_pc_withhold[2];
 907         pdq_uint32_t port_ler_condition[2];
 908         pdq_uint32_t port_chip_set[2];
 909         pdq_uint32_t port_action[2];
 910         /* Attachment Objects */
 911         pdq_uint32_t attachment_class;
 912         pdq_uint32_t attachment_optical_bypass_present;
 913         pdq_uint32_t attachment_imax_expiration;
 914         pdq_uint32_t attachment_inserted_status;
 915         pdq_uint32_t attachment_insert_policy;
 916     } fddi_mib_get;
 917 } pdq_response_fddi_mib_get_t;
 918
 919 #define PDQ_SIZE_RESPONSE_FDDI_MIB_GET  0x17C
 920
 921 typedef enum {
 922     PDQ_FDX_STATE_IDLE=0,
 923     PDQ_FDX_STATE_REQUEST=1,
 924     PDQ_FDX_STATE_CONFIRM=2,
 925     PDQ_FDX_STATE_OPERATION=3
 926 } pdq_fdx_state_t;
 927
 928 typedef struct {
 929     pdq_uint32_t dec_ext_mib_get_reserved;
 930     pdq_cmd_code_t dec_ext_mib_get_op;
 931     pdq_response_code_t dec_ext_mib_get_response;
 932     struct {
 933         /* SMT Objects */
 934         pdq_uint32_t esmt_station_type;
 935         /* MAC Objects */
 936         pdq_uint32_t emac_link_state;
 937         pdq_uint32_t emac_ring_purger_state;
 938         pdq_uint32_t emac_ring_purger_enable;
 939         pdq_uint32_t emac_frame_strip_mode;
 940         pdq_uint32_t emac_ring_error_reason;
 941         pdq_uint32_t emac_upstream_nbr_dupl_address_flag;
 942         pdq_uint32_t emac_restricted_token_timeout;
 943         /* Port Objects */
 944         pdq_uint32_t eport_pmd_type[2];
 945         pdq_uint32_t eport_phy_state[2];
 946         pdq_uint32_t eport_reject_reason[2];
 947         /* Full Duplex Objects */
 948         pdq_boolean_t fdx_enable;
 949         pdq_boolean_t fdx_operational;
 950         pdq_fdx_state_t fdx_state;
 951     } dec_ext_mib_get;
 952 } pdq_response_dec_ext_mib_get_t;
 953
 954 #define PDQ_SIZE_RESPONSE_DEC_EXT_MIB_GET       0x50
 955
 956 typedef enum {
 957     PDQ_CALLER_ID_NONE=0,
 958     PDQ_CALLER_ID_SELFTEST=1,
 959     PDQ_CALLER_ID_MFG=2,
 960     PDQ_CALLER_ID_FIRMWARE=5,
 961     PDQ_CALLER_ID_CONSOLE=8
 962 } pdq_caller_id_t;
 963
 964 typedef struct {
 965     pdq_uint32_t error_log_get__reserved;
 966     pdq_cmd_code_t error_log_get_op;
 967     pdq_response_code_t error_log_get_status;
 968     /* Error Header */
 969     pdq_uint32_t error_log_get_event_status;
 970     /* Event Information Block */
 971     pdq_caller_id_t error_log_get_caller_id;
 972     pdq_uint32_t error_log_get_timestamp[2];
 973     pdq_uint32_t error_log_get_write_count;
 974     /* Diagnostic Information */
 975     pdq_uint32_t error_log_get_fru_implication_mask;
 976     pdq_uint32_t error_log_get_test_id;
 977     pdq_uint32_t error_log_get_diag_reserved[6];
 978     /* Firmware Information */
 979     pdq_uint32_t error_log_get_fw_reserved[112];
 980 } pdq_response_error_log_get_t;
 981
 982 \f
 983 /*
 984  * Definitions for the Unsolicited Event Queue.
 985  */
 986 typedef enum {
 987     PDQ_UNSOLICITED_EVENT=0,
 988     PDQ_UNSOLICITED_COUNTERS=1
 989 } pdq_event_t;
 990
 991 typedef enum {
 992     PDQ_ENTITY_STATION=0,
 993     PDQ_ENTITY_LINK=1,
 994     PDQ_ENTITY_PHY_PORT=2
 995 } pdq_entity_t;
 996
 997 typedef enum {
 998     PDQ_STATION_EVENT_TRACE_RECEIVED=1
 999 } pdq_station_event_t;
1000
1001 typedef enum {
1002     PDQ_STATION_EVENT_ARGUMENT_REASON=0,        /* pdq_uint32_t */
1003     PDQ_STATION_EVENT_ARGUMENT_EOL=0xFF
1004 } pdq_station_event_argument_t;
1005
1006 typedef enum {
1007     PDQ_LINK_EVENT_TRANSMIT_UNDERRUN=0,
1008     PDQ_LINK_EVENT_TRANSMIT_FAILED=1,
1009     PDQ_LINK_EVENT_BLOCK_CHECK_ERROR=2,
1010     PDQ_LINK_EVENT_FRAME_STATUS_ERROR=3,
1011     PDQ_LINK_EVENT_PDU_LENGTH_ERROR=4,
1012     PDQ_LINK_EVENT_RECEIVE_DATA_OVERRUN=7,
1013     PDQ_LINK_EVENT_NO_USER_BUFFER=9,
1014     PDQ_LINK_EVENT_RING_INITIALIZATION_INITIATED=10,
1015     PDQ_LINK_EVENT_RING_INITIALIZATION_RECEIVED=11,
1016     PDQ_LINK_EVENT_RING_BEACON_INITIATED=12,
1017     PDQ_LINK_EVENT_DUPLICATE_ADDRESS_FAILURE=13,
1018     PDQ_LINK_EVENT_DUPLICATE_TOKEN_DETECTED=14,
1019     PDQ_LINK_EVENT_RING_PURGE_ERROR=15,
1020     PDQ_LINK_EVENT_FCI_STRIP_ERROR=16,
1021     PDQ_LINK_EVENT_TRACE_INITIATED=17,
1022     PDQ_LINK_EVENT_DIRECTED_BEACON_RECEIVED=18
1023 } pdq_link_event_t;
1024
1025 typedef enum {
1026     PDQ_LINK_EVENT_ARGUMENT_REASON=0,           /* pdq_rireason_t */
1027     PDQ_LINK_EVENT_ARGUMENT_DATA_LINK_HEADER=1, /* pdq_dlhdr_t */
1028     PDQ_LINK_EVENT_ARGUMENT_SOURCE=2,           /* pdq_lanaddr_t */
1029     PDQ_LINK_EVENT_ARGUMENT_UPSTREAM_NEIGHBOR=3,/* pdq_lanaddr_t */
1030     PDQ_LINK_EVENT_ARGUMENT_EOL=0xFF
1031 } pdq_link_event_argument_t;
1032
1033 typedef enum {
1034     PDQ_PHY_EVENT_LEM_ERROR_MONITOR_REJECT=0,
1035     PDQ_PHY_EVENT_ELASTICITY_BUFFER_ERROR=1,
1036     PDQ_PHY_EVENT_LINK_CONFIDENCE_TEST_REJECT=2
1037 } pdq_phy_event_t;
1038
1039 typedef enum {
1040     PDQ_PHY_EVENT_ARGUMENT_DIRECTION=0,         /* pdq_lct_direction_t */
1041     PDQ_PHY_EVENT_ARGUMENT_EOL=0xFF
1042 } pdq_phy_event_arguments;
1043
1044 struct _pdq_unsolicited_event_t {
1045     pdq_uint32_t rvent_reserved;
1046     pdq_event_t event_type;
1047     pdq_entity_t event_entity;
1048     pdq_uint32_t event_index;
1049     union {
1050         pdq_station_event_t station_event;
1051         pdq_link_event_t link_event;
1052         pdq_phy_event_t phy_event;
1053         pdq_uint32_t value;
1054     } event_code;
1055     /*
1056      * The remainder of this event is an argument list.
1057      */
1058     pdq_uint32_t event__filler[123];
1059 };
1060
1061 #endif /* _PDQREG_H */