| blob | 49ab22e05425e659ffa206911163b84b0d9f588e |
1 /*-
2 * Copyright (c) 2000 Doug Rabson
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
7 * are met:
8 * 1. Redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer.
10 * 2. Redistributions in binary form must reproduce the above copyright
11 * notice, this list of conditions and the following disclaimer in the
12 * documentation and/or other materials provided with the distribution.
13 *
14 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
15 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
16 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
17 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
18 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
19 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
20 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
21 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
22 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
23 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
24 * SUCH DAMAGE.
25 *
26 * $FreeBSD: src/sys/pci/agpreg.h,v 1.19 2007/07/13 16:28:12 anholt Exp $
27 * $DragonFly: src/sys/dev/agp/agpreg.h,v 1.7 2008/10/03 08:56:58 hasso Exp $
28 */
30 #ifndef _PCI_AGPREG_H_
31 #define _PCI_AGPREG_H_
33 /*
34 * Offsets for various AGP configuration registers.
35 */
36 #define AGP_APBASE 0x10
37 #define AGP_CAPPTR 0x34
39 /*
40 * Offsets from the AGP Capability pointer.
41 */
42 #define AGP_CAPID 0x0
43 #define AGP_CAPID_GET_MAJOR(x) (((x) & 0x00f00000U) >> 20)
44 #define AGP_CAPID_GET_MINOR(x) (((x) & 0x000f0000U) >> 16)
45 #define AGP_CAPID_GET_NEXT_PTR(x) (((x) & 0x0000ff00U) >> 8)
46 #define AGP_CAPID_GET_CAP_ID(x) (((x) & 0x000000ffU) >> 0)
48 #define AGP_STATUS 0x4
49 #define AGP_COMMAND 0x8
50 #define AGP_STATUS_AGP3 0x0008
51 #define AGP_STATUS_RQ_MASK 0xff000000
52 #define AGP_COMMAND_RQ_MASK 0xff000000
53 #define AGP_STATUS_ARQSZ_MASK 0xe000
54 #define AGP_COMMAND_ARQSZ_MASK 0xe000
55 #define AGP_STATUS_CAL_MASK 0x1c00
56 #define AGP_COMMAND_CAL_MASK 0x1c00
57 #define AGP_STATUS_ISOCH 0x10000
58 #define AGP_STATUS_SBA 0x0200
59 #define AGP_STATUS_ITA_COH 0x0100
60 #define AGP_STATUS_GART64 0x0080
61 #define AGP_STATUS_HTRANS 0x0040
62 #define AGP_STATUS_64BIT 0x0020
63 #define AGP_STATUS_FW 0x0010
64 #define AGP_COMMAND_RQ_MASK 0xff000000
65 #define AGP_COMMAND_ARQSZ_MASK 0xe000
66 #define AGP_COMMAND_CAL_MASK 0x1c00
67 #define AGP_COMMAND_SBA 0x0200
68 #define AGP_COMMAND_AGP 0x0100
69 #define AGP_COMMAND_GART64 0x0080
70 #define AGP_COMMAND_64BIT 0x0020
71 #define AGP_COMMAND_FW 0x0010
73 /*
74 * Config offsets for Intel AGP chipsets.
75 */
76 #define AGP_INTEL_NBXCFG 0x50
77 #define AGP_INTEL_ERRSTS 0x91
78 #define AGP_INTEL_AGPCTRL 0xb0
79 #define AGP_INTEL_APSIZE 0xb4
80 #define AGP_INTEL_ATTBASE 0xb8
82 /*
83 * Config offsets for Intel i8xx/E7xxx AGP chipsets.
84 */
85 #define AGP_INTEL_MCHCFG 0x50
86 #define AGP_INTEL_I820_RDCR 0x51
87 #define AGP_INTEL_I845_AGPM 0x51
88 #define AGP_INTEL_I8XX_ERRSTS 0xc8
90 /*
91 * Config offsets for VIA AGP 2.x chipsets.
92 */
93 #define AGP_VIA_GARTCTRL 0x80
94 #define AGP_VIA_APSIZE 0x84
95 #define AGP_VIA_ATTBASE 0x88
97 /*
98 * Config offsets for VIA AGP 3.0 chipsets.
99 */
100 #define AGP3_VIA_GARTCTRL 0x90
101 #define AGP3_VIA_APSIZE 0x94
102 #define AGP3_VIA_ATTBASE 0x98
103 #define AGP_VIA_AGPSEL 0xfd
105 /*
106 * Config offsets for SiS AGP chipsets.
107 */
108 #define AGP_SIS_ATTBASE 0x90
109 #define AGP_SIS_WINCTRL 0x94
110 #define AGP_SIS_TLBCTRL 0x97
111 #define AGP_SIS_TLBFLUSH 0x98
113 /*
114 * Config offsets for Ali AGP chipsets.
115 */
116 #define AGP_ALI_AGPCTRL 0xb8
117 #define AGP_ALI_ATTBASE 0xbc
118 #define AGP_ALI_TLBCTRL 0xc0
120 /*
121 * Config offsets for the AMD 751 chipset.
122 */
123 #define AGP_AMD751_APBASE 0x10
124 #define AGP_AMD751_REGISTERS 0x14
125 #define AGP_AMD751_APCTRL 0xac
126 #define AGP_AMD751_MODECTRL 0xb0
127 #define AGP_AMD751_MODECTRL_SYNEN 0x80
128 #define AGP_AMD751_MODECTRL2 0xb2
129 #define AGP_AMD751_MODECTRL2_G1LM 0x01
130 #define AGP_AMD751_MODECTRL2_GPDCE 0x02
131 #define AGP_AMD751_MODECTRL2_NGSE 0x08
133 /*
134 * Memory mapped register offsets for AMD 751 chipset.
135 */
136 #define AGP_AMD751_CAPS 0x00
137 #define AGP_AMD751_CAPS_EHI 0x0800
138 #define AGP_AMD751_CAPS_P2P 0x0400
139 #define AGP_AMD751_CAPS_MPC 0x0200
140 #define AGP_AMD751_CAPS_VBE 0x0100
141 #define AGP_AMD751_CAPS_REV 0x00ff
142 #define AGP_AMD751_STATUS 0x02
143 #define AGP_AMD751_STATUS_P2PS 0x0800
144 #define AGP_AMD751_STATUS_GCS 0x0400
145 #define AGP_AMD751_STATUS_MPS 0x0200
146 #define AGP_AMD751_STATUS_VBES 0x0100
147 #define AGP_AMD751_STATUS_P2PE 0x0008
148 #define AGP_AMD751_STATUS_GCE 0x0004
149 #define AGP_AMD751_STATUS_VBEE 0x0001
150 #define AGP_AMD751_ATTBASE 0x04
151 #define AGP_AMD751_TLBCTRL 0x0c
153 /*
154 * Config registers for i810 device 0
155 */
156 #define AGP_I810_SMRAM 0x70
157 #define AGP_I810_SMRAM_GMS 0xc0
158 #define AGP_I810_SMRAM_GMS_DISABLED 0x00
159 #define AGP_I810_SMRAM_GMS_ENABLED_0 0x40
160 #define AGP_I810_SMRAM_GMS_ENABLED_512 0x80
161 #define AGP_I810_SMRAM_GMS_ENABLED_1024 0xc0
162 #define AGP_I810_MISCC 0x72
163 #define AGP_I810_MISCC_WINSIZE 0x0001
164 #define AGP_I810_MISCC_WINSIZE_64 0x0000
165 #define AGP_I810_MISCC_WINSIZE_32 0x0001
166 #define AGP_I810_MISCC_PLCK 0x0008
167 #define AGP_I810_MISCC_PLCK_UNLOCKED 0x0000
168 #define AGP_I810_MISCC_PLCK_LOCKED 0x0008
169 #define AGP_I810_MISCC_WPTC 0x0030
170 #define AGP_I810_MISCC_WPTC_NOLIMIT 0x0000
171 #define AGP_I810_MISCC_WPTC_62 0x0010
172 #define AGP_I810_MISCC_WPTC_50 0x0020
173 #define AGP_I810_MISCC_WPTC_37 0x0030
174 #define AGP_I810_MISCC_RPTC 0x00c0
175 #define AGP_I810_MISCC_RPTC_NOLIMIT 0x0000
176 #define AGP_I810_MISCC_RPTC_62 0x0040
177 #define AGP_I810_MISCC_RPTC_50 0x0080
178 #define AGP_I810_MISCC_RPTC_37 0x00c0
180 /*
181 * Config registers for i810 device 1
182 */
183 #define AGP_I810_GMADR 0x10
184 #define AGP_I810_MMADR 0x14
186 /*
187 * Memory mapped register offsets for i810 chipset.
188 */
189 #define AGP_I810_PGTBL_CTL 0x2020
190 /**
191 * This field determines the actual size of the global GTT on the 965
192 * and G33
193 */
194 #define AGP_I810_PGTBL_SIZE_MASK 0x0000000e
195 #define AGP_I810_PGTBL_SIZE_512KB (0 << 1)
196 #define AGP_I810_PGTBL_SIZE_256KB (1 << 1)
197 #define AGP_I810_PGTBL_SIZE_128KB (2 << 1)
198 #define AGP_I810_DRT 0x3000
199 #define AGP_I810_DRT_UNPOPULATED 0x00
200 #define AGP_I810_DRT_POPULATED 0x01
201 #define AGP_I810_GTT 0x10000
203 /*
204 * Config registers for i830MG device 0
205 */
206 #define AGP_I830_GCC1 0x52
207 #define AGP_I830_GCC1_DEV2 0x08
208 #define AGP_I830_GCC1_DEV2_ENABLED 0x00
209 #define AGP_I830_GCC1_DEV2_DISABLED 0x08
211 #define AGP_I830_GCC1_GMS_STOLEN_512 0x20
212 #define AGP_I830_GCC1_GMS_STOLEN_1024 0x30
213 #define AGP_I830_GCC1_GMS_STOLEN_8192 0x40
214 #define AGP_I830_GCC1_GMASIZE 0x01
215 #define AGP_I830_GCC1_GMASIZE_64 0x01
216 #define AGP_I830_GCC1_GMASIZE_128 0x00
218 /*
219 * Config registers for 852GM/855GM/865G device 0
220 */
221 #define AGP_I855_GCC1 0x52
222 #define AGP_I855_GCC1_DEV2 0x08
223 #define AGP_I855_GCC1_DEV2_ENABLED 0x00
224 #define AGP_I855_GCC1_DEV2_DISABLED 0x08
226 #define AGP_I855_GCC1_GMS_STOLEN_0M 0x00
227 #define AGP_I855_GCC1_GMS_STOLEN_1M 0x10
228 #define AGP_I855_GCC1_GMS_STOLEN_4M 0x20
229 #define AGP_I855_GCC1_GMS_STOLEN_8M 0x30
230 #define AGP_I855_GCC1_GMS_STOLEN_16M 0x40
231 #define AGP_I855_GCC1_GMS_STOLEN_32M 0x50
233 /*
234 * 852GM/855GM variant identification
235 */
236 #define AGP_I85X_CAPID 0x44
237 #define AGP_I85X_VARIANT_MASK 0x7
238 #define AGP_I85X_VARIANT_SHIFT 5
239 #define AGP_I855_GME 0x0
240 #define AGP_I855_GM 0x4
241 #define AGP_I852_GME 0x2
242 #define AGP_I852_GM 0x5
244 /*
245 * 915G registers
246 */
247 #define AGP_I915_GMADR 0x18
248 #define AGP_I915_MMADR 0x10
249 #define AGP_I915_GTTADR 0x1C
250 #define AGP_I915_GCC1_GMS_STOLEN_48M 0x60
251 #define AGP_I915_GCC1_GMS_STOLEN_64M 0x70
252 #define AGP_I915_DEVEN 0x54
253 #define AGP_I915_DEVEN_D2F0 0x08
254 #define AGP_I915_DEVEN_D2F0_ENABLED 0x08
255 #define AGP_I915_DEVEN_D2F0_DISABLED 0x00
256 #define AGP_I915_MSAC 0x62
257 #define AGP_I915_MSAC_GMASIZE 0x02
258 #define AGP_I915_MSAC_GMASIZE_128 0x02
259 #define AGP_I915_MSAC_GMASIZE_256 0x00
261 /*
262 * G965 registers
263 */
264 #define AGP_I965_GTTMMADR 0x10
265 #define AGP_I965_MSAC 0x62
266 #define AGP_I965_MSAC_GMASIZE_128 0x00
267 #define AGP_I965_MSAC_GMASIZE_256 0x02
268 #define AGP_I965_MSAC_GMASIZE_512 0x06
269 #define AGP_I965_PGTBL_SIZE_1MB (3 << 1)
270 #define AGP_I965_PGTBL_SIZE_2MB (4 << 1)
271 #define AGP_I965_PGTBL_SIZE_1_5MB (5 << 1)
273 /*
274 * G33 registers
275 */
276 #define AGP_G33_MGGC_GGMS_MASK (3 << 8)
277 #define AGP_G33_MGGC_GGMS_SIZE_1M (1 << 8)
278 #define AGP_G33_MGGC_GGMS_SIZE_2M (2 << 8)
279 #define AGP_G33_GCC1_GMS_STOLEN_128M 0x80
280 #define AGP_G33_GCC1_GMS_STOLEN_256M 0x90
282 /*
283 * G4X registers
284 */
285 #define AGP_G4X_GCC1_GMS_STOLEN_96M 0xa0
286 #define AGP_G4X_GCC1_GMS_STOLEN_160M 0xb0
287 #define AGP_G4X_GCC1_GMS_STOLEN_224M 0xc0
288 #define AGP_G4X_GCC1_GMS_STOLEN_352M 0xd0
290 /*
291 * NVIDIA nForce/nForce2 registers
292 */
293 #define AGP_NVIDIA_0_APBASE 0x10
294 #define AGP_NVIDIA_0_APSIZE 0x80
295 #define AGP_NVIDIA_1_WBC 0xf0
296 #define AGP_NVIDIA_2_GARTCTRL 0xd0
297 #define AGP_NVIDIA_2_APBASE 0xd8
298 #define AGP_NVIDIA_2_APLIMIT 0xdc
299 #define AGP_NVIDIA_2_ATTBASE(i) (0xe0 + (i) * 4)
300 #define AGP_NVIDIA_3_APBASE 0x50
301 #define AGP_NVIDIA_3_APLIMIT 0x54
303 /*
304 * AMD64 GART registers
305 */
306 #define AGP_AMD64_APCTRL 0x90
307 #define AGP_AMD64_APBASE 0x94
308 #define AGP_AMD64_ATTBASE 0x98
309 #define AGP_AMD64_CACHECTRL 0x9c
310 #define AGP_AMD64_APCTRL_GARTEN 0x00000001
311 #define AGP_AMD64_APCTRL_SIZE_MASK 0x0000000e
312 #define AGP_AMD64_APCTRL_DISGARTCPU 0x00000010
313 #define AGP_AMD64_APCTRL_DISGARTIO 0x00000020
314 #define AGP_AMD64_APCTRL_DISWLKPRB 0x00000040
315 #define AGP_AMD64_APBASE_MASK 0x00007fff
316 #define AGP_AMD64_ATTBASE_MASK 0xfffffff0
317 #define AGP_AMD64_CACHECTRL_INVGART 0x00000001
318 #define AGP_AMD64_CACHECTRL_PTEERR 0x00000002
320 /*
321 * NVIDIA nForce3 registers
322 */
323 #define AGP_AMD64_NVIDIA_0_APBASE 0x10
324 #define AGP_AMD64_NVIDIA_1_APBASE1 0x50
325 #define AGP_AMD64_NVIDIA_1_APLIMIT1 0x54
326 #define AGP_AMD64_NVIDIA_1_APSIZE 0xa8
327 #define AGP_AMD64_NVIDIA_1_APBASE2 0xd8
328 #define AGP_AMD64_NVIDIA_1_APLIMIT2 0xdc
330 /*
331 * ULi M1689 registers
332 */
333 #define AGP_AMD64_ULI_APBASE 0x10
334 #define AGP_AMD64_ULI_HTT_FEATURE 0x50
335 #define AGP_AMD64_ULI_ENU_SCR 0x54
337 /*
338 * ATI IGP registers
339 */
340 #define ATI_GART_MMADDR 0x14
341 #define ATI_RS100_APSIZE 0xac
342 #define ATI_RS100_IG_AGPMODE 0xb0
343 #define ATI_RS300_APSIZE 0xf8
344 #define ATI_RS300_IG_AGPMODE 0xfc
345 #define ATI_GART_FEATURE_ID 0x00
346 #define ATI_GART_BASE 0x04
347 #define ATI_GART_CACHE_CNTRL 0x0c