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[dragonfly.git] / sys / dev / agp / agp_i810.c
bloba63e9b621c483866b3486b3fa3341f2e24655223
1 /*
2 * Copyright (c) 2000 Doug Rabson
3 * Copyright (c) 2000 Ruslan Ermilov
4 * All rights reserved.
5 *
6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions
8 * are met:
9 * 1. Redistributions of source code must retain the above copyright
10 * notice, this list of conditions and the following disclaimer.
11 * 2. Redistributions in binary form must reproduce the above copyright
12 * notice, this list of conditions and the following disclaimer in the
13 * documentation and/or other materials provided with the distribution.
14 *
15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
16 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
17 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
18 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
19 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
20 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
21 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
22 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
23 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
24 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
25 * SUCH DAMAGE.
26 *
27 * $FreeBSD: src/sys/dev/agp/agp_i810.c,v 1.43 2007/11/12 21:51:36 jhb Exp $
28 * $DragonFly: src/sys/dev/agp/agp_i810.c,v 1.19 2008/10/03 08:56:58 hasso Exp $
29 */
30
31 /*
32 * Fixes for 830/845G support: David Dawes <dawes@xfree86.org>
33 * 852GM/855GM/865G support added by David Dawes <dawes@xfree86.org>
34 */
35
36 #include "opt_bus.h"
37
38 #include <sys/param.h>
39 #include <sys/systm.h>
40 #include <sys/malloc.h>
41 #include <sys/kernel.h>
42 #include <sys/bus.h>
43 #include <sys/lock.h>
44 #include <sys/rman.h>
45
46 #include <bus/pci/pcivar.h>
47 #include <bus/pci/pcireg.h>
48 #include "agppriv.h"
49 #include "agpreg.h"
50
51 #include <vm/vm.h>
52 #include <vm/vm_object.h>
53 #include <vm/vm_page.h>
54 #include <vm/vm_pageout.h>
55 #include <vm/pmap.h>
56
57 #include <machine/md_var.h>
58
59 #define bus_read_1(r, o) \
60 bus_space_read_1((r)->r_bustag, (r)->r_bushandle, (o))
61 #define bus_read_4(r, o) \
62 bus_space_read_4((r)->r_bustag, (r)->r_bushandle, (o))
63 #define bus_write_4(r, o, v) \
64 bus_space_write_4((r)->r_bustag, (r)->r_bushandle, (o), (v))
65
66 MALLOC_DECLARE(M_AGP);
67
68 enum {
69 CHIP_I810, /* i810/i815 */
70 CHIP_I830, /* 830M/845G */
71 CHIP_I855, /* 852GM/855GM/865G */
72 CHIP_I915, /* 915G/915GM */
73 CHIP_I965, /* G965 */
74 CHIP_G33, /* G33/Q33/Q35 */
75 CHIP_G4X, /* G45/Q45 */
76 };
77
78 /* The i810 through i855 have the registers at BAR 1, and the GATT gets
79 * allocated by us. The i915 has registers in BAR 0 and the GATT is at the
80 * start of the stolen memory, and should only be accessed by the OS through
81 * BAR 3. The G965 has registers and GATT in the same BAR (0) -- first 512KB
82 * is registers, second 512KB is GATT.
83 */
84 static struct resource_spec agp_i810_res_spec[] = {
85 { SYS_RES_MEMORY, AGP_I810_MMADR, RF_ACTIVE | RF_SHAREABLE },
86 { -1, 0 }
87 };
88
89 static struct resource_spec agp_i915_res_spec[] = {
90 { SYS_RES_MEMORY, AGP_I915_MMADR, RF_ACTIVE | RF_SHAREABLE },
91 { SYS_RES_MEMORY, AGP_I915_GTTADR, RF_ACTIVE | RF_SHAREABLE },
92 { -1, 0 }
93 };
94
95 static struct resource_spec agp_i965_res_spec[] = {
96 { SYS_RES_MEMORY, AGP_I965_GTTMMADR, RF_ACTIVE | RF_SHAREABLE },
97 { -1, 0 }
98 };
99
100 struct agp_i810_softc {
101 struct agp_softc agp;
102 u_int32_t initial_aperture; /* aperture size at startup */
103 struct agp_gatt *gatt;
104 int chiptype; /* i810-like or i830 */
105 u_int32_t dcache_size; /* i810 only */
106 u_int32_t stolen; /* number of i830/845 gtt entries for stolen memory */
107 device_t bdev; /* bridge device */
108
109 void *argb_cursor; /* contigmalloc area for ARGB cursor */
110
111 struct resource_spec * sc_res_spec;
112 struct resource *sc_res[2];
113 };
114
115 /* For adding new devices, devid is the id of the graphics controller
116 * (pci:0:2:0, for example). The placeholder (usually at pci:0:2:1) for the
117 * second head should never be added. The bridge_offset is the offset to
118 * subtract from devid to get the id of the hostb that the device is on.
119 */
120 static const struct agp_i810_match {
121 int devid;
122 int chiptype;
123 int bridge_offset;
124 char *name;
125 } agp_i810_matches[] = {
126 {0x71218086, CHIP_I810, 0x00010000,
127 "Intel 82810 (i810 GMCH) SVGA controller"},
128 {0x71238086, CHIP_I810, 0x00010000,
129 "Intel 82810-DC100 (i810-DC100 GMCH) SVGA controller"},
130 {0x71258086, CHIP_I810, 0x00010000,
131 "Intel 82810E (i810E GMCH) SVGA controller"},
132 {0x11328086, CHIP_I810, 0x00020000,
133 "Intel 82815 (i815 GMCH) SVGA controller"},
134 {0x35778086, CHIP_I830, 0x00020000,
135 "Intel 82830M (830M GMCH) SVGA controller"},
136 {0x25628086, CHIP_I830, 0x00020000,
137 "Intel 82845M (845M GMCH) SVGA controller"},
138 {0x35828086, CHIP_I855, 0x00020000,
139 "Intel 82852/855GM SVGA controller"},
140 {0x25728086, CHIP_I855, 0x00020000,
141 "Intel 82865G (865G GMCH) SVGA controller"},
142 {0x25828086, CHIP_I915, 0x00020000,
143 "Intel 82915G (915G GMCH) SVGA controller"},
144 {0x258A8086, CHIP_I915, 0x00020000,
145 "Intel E7221 SVGA controller"},
146 {0x25928086, CHIP_I915, 0x00020000,
147 "Intel 82915GM (915GM GMCH) SVGA controller"},
148 {0x27728086, CHIP_I915, 0x00020000,
149 "Intel 82945G (945G GMCH) SVGA controller"},
150 {0x27A28086, CHIP_I915, 0x00020000,
151 "Intel 82945GM (945GM GMCH) SVGA controller"},
152 {0x27AE8086, CHIP_I915, 0x00020000,
153 "Intel 945GME SVGA controller"},
154 {0x29728086, CHIP_I965, 0x00020000,
155 "Intel 946GZ SVGA controller"},
156 {0x29828086, CHIP_I965, 0x00020000,
157 "Intel G965 SVGA controller"},
158 {0x29928086, CHIP_I965, 0x00020000,
159 "Intel Q965 SVGA controller"},
160 {0x29A28086, CHIP_I965, 0x00020000,
161 "Intel G965 SVGA controller"},
162 {0x29B28086, CHIP_G33, 0x00020000,
163 "Intel Q35 SVGA controller"},
164 {0x29C28086, CHIP_G33, 0x00020000,
165 "Intel G33 SVGA controller"},
166 {0x29D28086, CHIP_G33, 0x00020000,
167 "Intel Q33 SVGA controller"},
168 {0x2A028086, CHIP_I965, 0x00020000,
169 "Intel GM965 SVGA controller"},
170 {0x2A128086, CHIP_I965, 0x00020000,
171 "Intel GME965 SVGA controller"},
172 {0x2A428086, CHIP_G4X, 0x00020000,
173 "Intel GM45 SVGA controller"},
174 {0x2E028086, CHIP_G4X, 0x00020000,
175 "Intel 4 Series SVGA controller"},
176 {0x2E328086, CHIP_G4X, 0x00020000,
177 "Intel 4 Series SVGA controller"},
178 {0x2E128086, CHIP_G4X, 0x00020000,
179 "Intel Q45 SVGA controller"},
180 {0x2E228086, CHIP_G4X, 0x00020000,
181 "Intel G45 SVGA controller"},
182 {0, 0, 0, NULL}
183 };
184
185 static const struct agp_i810_match*
186 agp_i810_match(device_t dev)
187 {
188 int i, devid;
189
190 if (pci_get_class(dev) != PCIC_DISPLAY
191 || pci_get_subclass(dev) != PCIS_DISPLAY_VGA)
192 return NULL;
193
194 devid = pci_get_devid(dev);
195 for (i = 0; agp_i810_matches[i].devid != 0; i++) {
196 if (agp_i810_matches[i].devid == devid)
197 break;
198 }
199 if (agp_i810_matches[i].devid == 0)
200 return NULL;
201 else
202 return &agp_i810_matches[i];
203 }
204
205 /*
206 * Find bridge device.
207 */
208 static device_t
209 agp_i810_find_bridge(device_t dev)
210 {
211 device_t *children, child;
212 int nchildren, i;
213 u_int32_t devid;
214 const struct agp_i810_match *match;
215
216 match = agp_i810_match(dev);
217 devid = match->devid - match->bridge_offset;
218
219 if (device_get_children(device_get_parent(device_get_parent(dev)),
220 &children, &nchildren))
221 return 0;
222
223 for (i = 0; i < nchildren; i++) {
224 child = children[i];
225
226 if (pci_get_devid(child) == devid) {
227 kfree(children, M_TEMP);
228 return child;
229 }
230 }
231 kfree(children, M_TEMP);
232 return 0;
233 }
234
235 static void
236 agp_i810_identify(driver_t *driver, device_t parent)
237 {
238
239 if (device_find_child(parent, "agp", -1) == NULL &&
240 agp_i810_match(parent))
241 device_add_child(parent, "agp", -1);
242 }
243
244 static int
245 agp_i810_probe(device_t dev)
246 {
247 device_t bdev;
248 const struct agp_i810_match *match;
249 u_int8_t smram;
250 int gcc1, deven;
251
252 if (resource_disabled("agp", device_get_unit(dev)))
253 return (ENXIO);
254 match = agp_i810_match(dev);
255 if (match == NULL)
256 return ENXIO;
257
258 bdev = agp_i810_find_bridge(dev);
259 if (!bdev) {
260 if (bootverbose)
261 kprintf("I810: can't find bridge device\n");
262 return ENXIO;
263 }
264
265 /*
266 * checking whether internal graphics device has been activated.
267 */
268 switch (match->chiptype) {
269 case CHIP_I810:
270 smram = pci_read_config(bdev, AGP_I810_SMRAM, 1);
271 if ((smram & AGP_I810_SMRAM_GMS) ==
272 AGP_I810_SMRAM_GMS_DISABLED) {
273 if (bootverbose)
274 kprintf("I810: disabled, not probing\n");
275 return ENXIO;
276 }
277 break;
278 case CHIP_I830:
279 case CHIP_I855:
280 gcc1 = pci_read_config(bdev, AGP_I830_GCC1, 1);
281 if ((gcc1 & AGP_I830_GCC1_DEV2) ==
282 AGP_I830_GCC1_DEV2_DISABLED) {
283 if (bootverbose)
284 kprintf("I830: disabled, not probing\n");
285 return ENXIO;
286 }
287 break;
288 case CHIP_I915:
289 case CHIP_I965:
290 case CHIP_G33:
291 case CHIP_G4X:
292 deven = pci_read_config(bdev, AGP_I915_DEVEN, 4);
293 if ((deven & AGP_I915_DEVEN_D2F0) ==
294 AGP_I915_DEVEN_D2F0_DISABLED) {
295 if (bootverbose)
296 kprintf("I915: disabled, not probing\n");
297 return ENXIO;
298 }
299 break;
300 }
301
302 device_verbose(dev);
303 if (match->devid == 0x35828086) {
304 switch (pci_read_config(dev, AGP_I85X_CAPID, 1)) {
305 case AGP_I855_GME:
306 device_set_desc(dev,
307 "Intel 82855GME (855GME GMCH) SVGA controller");
308 break;
309 case AGP_I855_GM:
310 device_set_desc(dev,
311 "Intel 82855GM (855GM GMCH) SVGA controller");
312 break;
313 case AGP_I852_GME:
314 device_set_desc(dev,
315 "Intel 82852GME (852GME GMCH) SVGA controller");
316 break;
317 case AGP_I852_GM:
318 device_set_desc(dev,
319 "Intel 82852GM (852GM GMCH) SVGA controller");
320 break;
321 default:
322 device_set_desc(dev,
323 "Intel 8285xM (85xGM GMCH) SVGA controller");
324 break;
325 }
326 } else {
327 device_set_desc(dev, match->name);
328 }
329
330 return BUS_PROBE_DEFAULT;
331 }
332
333 static void
334 agp_i810_dump_regs(device_t dev)
335 {
336 struct agp_i810_softc *sc = device_get_softc(dev);
337
338 device_printf(dev, "AGP_I810_PGTBL_CTL: %08x\n",
339 bus_read_4(sc->sc_res[0], AGP_I810_PGTBL_CTL));
340
341 switch (sc->chiptype) {
342 case CHIP_I810:
343 device_printf(dev, "AGP_I810_MISCC: 0x%04x\n",
344 pci_read_config(sc->bdev, AGP_I810_MISCC, 2));
345 break;
346 case CHIP_I830:
347 device_printf(dev, "AGP_I830_GCC1: 0x%02x\n",
348 pci_read_config(sc->bdev, AGP_I830_GCC1, 1));
349 break;
350 case CHIP_I855:
351 device_printf(dev, "AGP_I855_GCC1: 0x%02x\n",
352 pci_read_config(sc->bdev, AGP_I855_GCC1, 1));
353 break;
354 case CHIP_I915:
355 case CHIP_I965:
356 case CHIP_G33:
357 case CHIP_G4X:
358 device_printf(dev, "AGP_I855_GCC1: 0x%02x\n",
359 pci_read_config(sc->bdev, AGP_I855_GCC1, 1));
360 device_printf(dev, "AGP_I915_MSAC: 0x%02x\n",
361 pci_read_config(sc->bdev, AGP_I915_MSAC, 1));
362 break;
363 }
364 device_printf(dev, "Aperture resource size: %d bytes\n",
365 AGP_GET_APERTURE(dev));
366 }
367
368 static int
369 agp_i810_attach(device_t dev)
370 {
371 struct agp_i810_softc *sc = device_get_softc(dev);
372 struct agp_gatt *gatt;
373 const struct agp_i810_match *match;
374 int error;
375
376 sc->bdev = agp_i810_find_bridge(dev);
377 if (!sc->bdev)
378 return ENOENT;
379
380 match = agp_i810_match(dev);
381 sc->chiptype = match->chiptype;
382
383 switch (sc->chiptype) {
384 case CHIP_I810:
385 case CHIP_I830:
386 case CHIP_I855:
387 sc->sc_res_spec = agp_i810_res_spec;
388 agp_set_aperture_resource(dev, AGP_APBASE);
389 break;
390 case CHIP_I915:
391 case CHIP_G33:
392 sc->sc_res_spec = agp_i915_res_spec;
393 agp_set_aperture_resource(dev, AGP_I915_GMADR);
394 break;
395 case CHIP_I965:
396 case CHIP_G4X:
397 sc->sc_res_spec = agp_i965_res_spec;
398 agp_set_aperture_resource(dev, AGP_I915_GMADR);
399 break;
400 }
401
402 error = agp_generic_attach(dev);
403 if (error)
404 return error;
405
406 if (sc->chiptype != CHIP_I965 && sc->chiptype != CHIP_G33 &&
407 sc->chiptype != CHIP_G4X && ptoa((vm_paddr_t)Maxmem) > 0xfffffffful)
408 {
409 device_printf(dev, "agp_i810.c does not support physical "
410 "memory above 4GB.\n");
411 return ENOENT;
412 }
413
414 if (bus_alloc_resources(dev, sc->sc_res_spec, sc->sc_res)) {
415 agp_generic_detach(dev);
416 return ENODEV;
417 }
418
419 sc->initial_aperture = AGP_GET_APERTURE(dev);
420 if (sc->initial_aperture == 0) {
421 device_printf(dev, "bad initial aperture size, disabling\n");
422 return ENXIO;
423 }
424
425 gatt = kmalloc( sizeof(struct agp_gatt), M_AGP, M_INTWAIT);
426 sc->gatt = gatt;
427
428 gatt->ag_entries = AGP_GET_APERTURE(dev) >> AGP_PAGE_SHIFT;
429
430 if ( sc->chiptype == CHIP_I810 ) {
431 /* Some i810s have on-chip memory called dcache */
432 if (bus_read_1(sc->sc_res[0], AGP_I810_DRT) &
433 AGP_I810_DRT_POPULATED)
434 sc->dcache_size = 4 * 1024 * 1024;
435 else
436 sc->dcache_size = 0;
437
438 /* According to the specs the gatt on the i810 must be 64k */
439 gatt->ag_virtual = contigmalloc( 64 * 1024, M_AGP, 0,
440 0, ~0, PAGE_SIZE, 0);
441 if (!gatt->ag_virtual) {
442 if (bootverbose)
443 device_printf(dev, "contiguous allocation failed\n");
444 bus_release_resources(dev, sc->sc_res_spec,
445 sc->sc_res);
446 kfree(gatt, M_AGP);
447 agp_generic_detach(dev);
448 return ENOMEM;
449 }
450 bzero(gatt->ag_virtual, gatt->ag_entries * sizeof(u_int32_t));
451
452 gatt->ag_physical = vtophys((vm_offset_t) gatt->ag_virtual);
453 agp_flush_cache();
454 /* Install the GATT. */
455 bus_write_4(sc->sc_res[0], AGP_I810_PGTBL_CTL,
456 gatt->ag_physical | 1);
457 } else if ( sc->chiptype == CHIP_I830 ) {
458 /* The i830 automatically initializes the 128k gatt on boot. */
459 unsigned int gcc1, pgtblctl;
460
461 gcc1 = pci_read_config(sc->bdev, AGP_I830_GCC1, 1);
462 switch (gcc1 & AGP_I830_GCC1_GMS) {
463 case AGP_I830_GCC1_GMS_STOLEN_512:
464 sc->stolen = (512 - 132) * 1024 / 4096;
465 break;
466 case AGP_I830_GCC1_GMS_STOLEN_1024:
467 sc->stolen = (1024 - 132) * 1024 / 4096;
468 break;
469 case AGP_I830_GCC1_GMS_STOLEN_8192:
470 sc->stolen = (8192 - 132) * 1024 / 4096;
471 break;
472 default:
473 sc->stolen = 0;
474 device_printf(dev, "unknown memory configuration, disabling\n");
475 bus_release_resources(dev, sc->sc_res_spec,
476 sc->sc_res);
477 kfree(gatt, M_AGP);
478 agp_generic_detach(dev);
479 return EINVAL;
480 }
481 if (sc->stolen > 0) {
482 device_printf(dev, "detected %dk stolen memory\n",
483 sc->stolen * 4);
484 }
485 device_printf(dev, "aperture size is %dM\n",
486 sc->initial_aperture / 1024 / 1024);
487
488 /* GATT address is already in there, make sure it's enabled */
489 pgtblctl = bus_read_4(sc->sc_res[0], AGP_I810_PGTBL_CTL);
490 pgtblctl |= 1;
491 bus_write_4(sc->sc_res[0], AGP_I810_PGTBL_CTL, pgtblctl);
492
493 gatt->ag_physical = pgtblctl & ~1;
494 } else if (sc->chiptype == CHIP_I855 || sc->chiptype == CHIP_I915 ||
495 sc->chiptype == CHIP_I965 || sc->chiptype == CHIP_G33 ||
496 sc->chiptype == CHIP_G4X) {
497 unsigned int gcc1, pgtblctl, stolen, gtt_size;
498
499 /* Stolen memory is set up at the beginning of the aperture by
500 * the BIOS, consisting of the GATT followed by 4kb for the
501 * BIOS display.
502 */
503 switch (sc->chiptype) {
504 case CHIP_I855:
505 gtt_size = 128;
506 break;
507 case CHIP_I915:
508 gtt_size = 256;
509 break;
510 case CHIP_I965:
511 switch (bus_read_4(sc->sc_res[0], AGP_I810_PGTBL_CTL) &
512 AGP_I810_PGTBL_SIZE_MASK) {
513 case AGP_I810_PGTBL_SIZE_128KB:
514 gtt_size = 128;
515 break;
516 case AGP_I810_PGTBL_SIZE_256KB:
517 gtt_size = 256;
518 break;
519 case AGP_I810_PGTBL_SIZE_512KB:
520 gtt_size = 512;
521 break;
522 case AGP_I965_PGTBL_SIZE_1MB:
523 gtt_size = 1024;
524 break;
525 case AGP_I965_PGTBL_SIZE_2MB:
526 gtt_size = 2048;
527 break;
528 case AGP_I965_PGTBL_SIZE_1_5MB:
529 gtt_size = 1024 + 512;
530 break;
531 default:
532 device_printf(dev, "Bad PGTBL size\n");
533 bus_release_resources(dev, sc->sc_res_spec,
534 sc->sc_res);
535 kfree(gatt, M_AGP);
536 agp_generic_detach(dev);
537 return EINVAL;
538 }
539 break;
540 case CHIP_G33:
541 gcc1 = pci_read_config(sc->bdev, AGP_I855_GCC1, 2);
542 switch (gcc1 & AGP_G33_MGGC_GGMS_MASK) {
543 case AGP_G33_MGGC_GGMS_SIZE_1M:
544 gtt_size = 1024;
545 break;
546 case AGP_G33_MGGC_GGMS_SIZE_2M:
547 gtt_size = 2048;
548 break;
549 default:
550 device_printf(dev, "Bad PGTBL size\n");
551 bus_release_resources(dev, sc->sc_res_spec,
552 sc->sc_res);
553 kfree(gatt, M_AGP);
554 agp_generic_detach(dev);
555 return EINVAL;
556 }
557 break;
558 case CHIP_G4X:
559 gtt_size = 0;
560 break;
561 default:
562 device_printf(dev, "Bad chiptype\n");
563 bus_release_resources(dev, sc->sc_res_spec,
564 sc->sc_res);
565 kfree(gatt, M_AGP);
566 agp_generic_detach(dev);
567 return EINVAL;
568 }
569
570 /* GCC1 is called MGGC on i915+ */
571 gcc1 = pci_read_config(sc->bdev, AGP_I855_GCC1, 1);
572 switch (gcc1 & AGP_I855_GCC1_GMS) {
573 case AGP_I855_GCC1_GMS_STOLEN_1M:
574 stolen = 1024;
575 break;
576 case AGP_I855_GCC1_GMS_STOLEN_4M:
577 stolen = 4 * 1024;
578 break;
579 case AGP_I855_GCC1_GMS_STOLEN_8M:
580 stolen = 8 * 1024;
581 break;
582 case AGP_I855_GCC1_GMS_STOLEN_16M:
583 stolen = 16 * 1024;
584 break;
585 case AGP_I855_GCC1_GMS_STOLEN_32M:
586 stolen = 32 * 1024;
587 break;
588 case AGP_I915_GCC1_GMS_STOLEN_48M:
589 if (sc->chiptype == CHIP_I915 ||
590 sc->chiptype == CHIP_I965 ||
591 sc->chiptype == CHIP_G33 ||
592 sc->chiptype == CHIP_G4X) {
593 stolen = 48 * 1024;
594 } else {
595 stolen = 0;
596 }
597 break;
598 case AGP_I915_GCC1_GMS_STOLEN_64M:
599 if (sc->chiptype == CHIP_I915 ||
600 sc->chiptype == CHIP_I965 ||
601 sc->chiptype == CHIP_G33 ||
602 sc->chiptype == CHIP_G4X) {
603 stolen = 64 * 1024;
604 } else {
605 stolen = 0;
606 }
607 break;
608 case AGP_G33_GCC1_GMS_STOLEN_128M:
609 if (sc->chiptype == CHIP_I965 ||
610 sc->chiptype == CHIP_G33 ||
611 sc->chiptype == CHIP_G4X) {
612 stolen = 128 * 1024;
613 } else {
614 stolen = 0;
615 }
616 break;
617 case AGP_G33_GCC1_GMS_STOLEN_256M:
618 if (sc->chiptype == CHIP_I965 ||
619 sc->chiptype == CHIP_G33 ||
620 sc->chiptype == CHIP_G4X) {
621 stolen = 256 * 1024;
622 } else {
623 stolen = 0;
624 }
625 break;
626 case AGP_G4X_GCC1_GMS_STOLEN_96M:
627 if (sc->chiptype == CHIP_I965 ||
628 sc->chiptype == CHIP_G4X) {
629 stolen = 96 * 1024;
630 } else {
631 stolen = 0;
632 }
633 break;
634 case AGP_G4X_GCC1_GMS_STOLEN_160M:
635 if (sc->chiptype == CHIP_I965 ||
636 sc->chiptype == CHIP_G4X) {
637 stolen = 160 * 1024;
638 } else {
639 stolen = 0;
640 }
641 break;
642 case AGP_G4X_GCC1_GMS_STOLEN_224M:
643 if (sc->chiptype == CHIP_I965 ||
644 sc->chiptype == CHIP_G4X) {
645 stolen = 224 * 1024;
646 } else {
647 stolen = 0;
648 }
649 break;
650 case AGP_G4X_GCC1_GMS_STOLEN_352M:
651 if (sc->chiptype == CHIP_I965 ||
652 sc->chiptype == CHIP_G4X) {
653 stolen = 352 * 1024;
654 } else {
655 stolen = 0;
656 }
657 break;
658 default:
659 device_printf(dev, "unknown memory configuration, "
660 "disabling\n");
661 bus_release_resources(dev, sc->sc_res_spec,
662 sc->sc_res);
663 kfree(gatt, M_AGP);
664 agp_generic_detach(dev);
665 return EINVAL;
666 }
667
668 gtt_size += 4;
669
670 sc->stolen = (stolen - gtt_size) * 1024 / 4096;
671 if (sc->stolen > 0)
672 device_printf(dev, "detected %dk stolen memory\n", sc->stolen * 4);
673 device_printf(dev, "aperture size is %dM\n", sc->initial_aperture / 1024 / 1024);
674
675 /* GATT address is already in there, make sure it's enabled */
676 pgtblctl = bus_read_4(sc->sc_res[0], AGP_I810_PGTBL_CTL);
677 pgtblctl |= 1;
678 bus_write_4(sc->sc_res[0], AGP_I810_PGTBL_CTL, pgtblctl);
679
680 gatt->ag_physical = pgtblctl & ~1;
681 }
682
683 if (0)
684 agp_i810_dump_regs(dev);
685
686 return 0;
687 }
688
689 static int
690 agp_i810_detach(device_t dev)
691 {
692 struct agp_i810_softc *sc = device_get_softc(dev);
693
694 agp_free_cdev(dev);
695
696 /* Clear the GATT base. */
697 if ( sc->chiptype == CHIP_I810 ) {
698 bus_write_4(sc->sc_res[0], AGP_I810_PGTBL_CTL, 0);
699 } else {
700 unsigned int pgtblctl;
701 pgtblctl = bus_read_4(sc->sc_res[0], AGP_I810_PGTBL_CTL);
702 pgtblctl &= ~1;
703 bus_write_4(sc->sc_res[0], AGP_I810_PGTBL_CTL, pgtblctl);
704 }
705
706 /* Put the aperture back the way it started. */
707 AGP_SET_APERTURE(dev, sc->initial_aperture);
708
709 if ( sc->chiptype == CHIP_I810 ) {
710 contigfree(sc->gatt->ag_virtual, 64 * 1024, M_AGP);
711 }
712 kfree(sc->gatt, M_AGP);
713
714 bus_release_resources(dev, sc->sc_res_spec, sc->sc_res);
715 agp_free_res(dev);
716
717 return 0;
718 }
719
720 static int
721 agp_i810_resume(device_t dev)
722 {
723 struct agp_i810_softc *sc;
724 sc = device_get_softc(dev);
725
726 AGP_SET_APERTURE(dev, sc->initial_aperture);
727
728 /* Install the GATT. */
729 bus_write_4(sc->sc_res[0], AGP_I810_PGTBL_CTL,
730 sc->gatt->ag_physical | 1);
731
732 return (bus_generic_resume(dev));
733 }
734
735 /**
736 * Sets the PCI resource size of the aperture on i830-class and below chipsets,
737 * while returning failure on later chipsets when an actual change is
738 * requested.
739 *
740 * This whole function is likely bogus, as the kernel would probably need to
741 * reconfigure the placement of the AGP aperture if a larger size is requested,
742 * which doesn't happen currently.
743 */
744 static int
745 agp_i810_set_aperture(device_t dev, u_int32_t aperture)
746 {
747 struct agp_i810_softc *sc = device_get_softc(dev);
748 u_int16_t miscc, gcc1;
749
750 switch (sc->chiptype) {
751 case CHIP_I810:
752 /*
753 * Double check for sanity.
754 */
755 if (aperture != 32 * 1024 * 1024 && aperture != 64 * 1024 * 1024) {
756 device_printf(dev, "bad aperture size %d\n", aperture);
757 return EINVAL;
758 }
759
760 miscc = pci_read_config(sc->bdev, AGP_I810_MISCC, 2);
761 miscc &= ~AGP_I810_MISCC_WINSIZE;
762 if (aperture == 32 * 1024 * 1024)
763 miscc |= AGP_I810_MISCC_WINSIZE_32;
764 else
765 miscc |= AGP_I810_MISCC_WINSIZE_64;
766
767 pci_write_config(sc->bdev, AGP_I810_MISCC, miscc, 2);
768 break;
769 case CHIP_I830:
770 if (aperture != 64 * 1024 * 1024 &&
771 aperture != 128 * 1024 * 1024) {
772 device_printf(dev, "bad aperture size %d\n", aperture);
773 return EINVAL;
774 }
775 gcc1 = pci_read_config(sc->bdev, AGP_I830_GCC1, 2);
776 gcc1 &= ~AGP_I830_GCC1_GMASIZE;
777 if (aperture == 64 * 1024 * 1024)
778 gcc1 |= AGP_I830_GCC1_GMASIZE_64;
779 else
780 gcc1 |= AGP_I830_GCC1_GMASIZE_128;
781
782 pci_write_config(sc->bdev, AGP_I830_GCC1, gcc1, 2);
783 break;
784 case CHIP_I855:
785 case CHIP_I915:
786 case CHIP_I965:
787 case CHIP_G33:
788 case CHIP_G4X:
789 return agp_generic_set_aperture(dev, aperture);
790 }
791
792 return 0;
793 }
794
795 /**
796 * Writes a GTT entry mapping the page at the given offset from the beginning
797 * of the aperture to the given physical address.
798 */
799 static void
800 agp_i810_write_gtt_entry(device_t dev, int offset, vm_offset_t physical,
801 int enabled)
802 {
803 struct agp_i810_softc *sc = device_get_softc(dev);
804 u_int32_t pte;
805
806 pte = (u_int32_t)physical | 1;
807 if (sc->chiptype == CHIP_I965 || sc->chiptype == CHIP_G33 ||
808 sc->chiptype == CHIP_G4X) {
809 pte |= (physical & 0x0000000f00000000ull) >> 28;
810 } else {
811 /* If we do actually have memory above 4GB on an older system,
812 * crash cleanly rather than scribble on system memory,
813 * so we know we need to fix it.
814 */
815 KASSERT((pte & 0x0000000f00000000ull) == 0,
816 (">4GB physical address in agp"));
817 }
818
819 switch (sc->chiptype) {
820 case CHIP_I810:
821 case CHIP_I830:
822 case CHIP_I855:
823 bus_write_4(sc->sc_res[0],
824 AGP_I810_GTT + (offset >> AGP_PAGE_SHIFT) * 4, pte);
825 break;
826 case CHIP_I915:
827 case CHIP_G33:
828 bus_write_4(sc->sc_res[1],
829 (offset >> AGP_PAGE_SHIFT) * 4, pte);
830 break;
831 case CHIP_I965:
832 bus_write_4(sc->sc_res[0],
833 (offset >> AGP_PAGE_SHIFT) * 4 + (512 * 1024), pte);
834 break;
835 case CHIP_G4X:
836 bus_write_4(sc->sc_res[0],
837 (offset >> AGP_PAGE_SHIFT) * 4 + (2 * 1024 * 1024), pte);
838 break;
839 }
840 }
841
842 static int
843 agp_i810_bind_page(device_t dev, int offset, vm_offset_t physical)
844 {
845 struct agp_i810_softc *sc = device_get_softc(dev);
846
847 if (offset < 0 || offset >= (sc->gatt->ag_entries << AGP_PAGE_SHIFT)) {
848 device_printf(dev, "failed: offset is 0x%08x, shift is %d, entries is %d\n", offset, AGP_PAGE_SHIFT, sc->gatt->ag_entries);
849 return EINVAL;
850 }
851
852 if ( sc->chiptype != CHIP_I810 ) {
853 if ( (offset >> AGP_PAGE_SHIFT) < sc->stolen ) {
854 device_printf(dev, "trying to bind into stolen memory");
855 return EINVAL;
856 }
857 }
858
859 agp_i810_write_gtt_entry(dev, offset, physical, 1);
860
861 return 0;
862 }
863
864 static int
865 agp_i810_unbind_page(device_t dev, int offset)
866 {
867 struct agp_i810_softc *sc = device_get_softc(dev);
868
869 if (offset < 0 || offset >= (sc->gatt->ag_entries << AGP_PAGE_SHIFT))
870 return EINVAL;
871
872 if ( sc->chiptype != CHIP_I810 ) {
873 if ( (offset >> AGP_PAGE_SHIFT) < sc->stolen ) {
874 device_printf(dev, "trying to unbind from stolen memory");
875 return EINVAL;
876 }
877 }
878
879 agp_i810_write_gtt_entry(dev, offset, 0, 0);
880
881 return 0;
882 }
883
884 /*
885 * Writing via memory mapped registers already flushes all TLBs.
886 */
887 static void
888 agp_i810_flush_tlb(device_t dev)
889 {
890 }
891
892 static int
893 agp_i810_enable(device_t dev, u_int32_t mode)
894 {
895
896 return 0;
897 }
898
899 static struct agp_memory *
900 agp_i810_alloc_memory(device_t dev, int type, vm_size_t size)
901 {
902 struct agp_i810_softc *sc = device_get_softc(dev);
903 struct agp_memory *mem;
904
905 if ((size & (AGP_PAGE_SIZE - 1)) != 0)
906 return 0;
907
908 if (sc->agp.as_allocated + size > sc->agp.as_maxmem)
909 return 0;
910
911 if (type == 1) {
912 /*
913 * Mapping local DRAM into GATT.
914 */
915 if ( sc->chiptype != CHIP_I810 )
916 return 0;
917 if (size != sc->dcache_size)
918 return 0;
919 } else if (type == 2) {
920 /*
921 * Type 2 is the contiguous physical memory type, that hands
922 * back a physical address. This is used for cursors on i810.
923 * Hand back as many single pages with physical as the user
924 * wants, but only allow one larger allocation (ARGB cursor)
925 * for simplicity.
926 */
927 if (size != AGP_PAGE_SIZE) {
928 if (sc->argb_cursor != NULL)
929 return 0;
930
931 /* Allocate memory for ARGB cursor, if we can. */
932 sc->argb_cursor = contigmalloc(size, M_AGP,
933 0, 0, ~0, PAGE_SIZE, 0);
934 if (sc->argb_cursor == NULL)
935 return 0;
936 }
937 }
938
939 mem = kmalloc(sizeof *mem, M_AGP, M_INTWAIT);
940 mem->am_id = sc->agp.as_nextid++;
941 mem->am_size = size;
942 mem->am_type = type;
943 if (type != 1 && (type != 2 || size == AGP_PAGE_SIZE))
944 mem->am_obj = vm_object_allocate(OBJT_DEFAULT,
945 atop(round_page(size)));
946 else
947 mem->am_obj = 0;
948
949 if (type == 2) {
950 if (size == AGP_PAGE_SIZE) {
951 /*
952 * Allocate and wire down the page now so that we can
953 * get its physical address.
954 */
955 vm_page_t m;
956
957 m = vm_page_grab(mem->am_obj, 0,
958 VM_ALLOC_NORMAL|VM_ALLOC_ZERO|VM_ALLOC_RETRY);
959 if ((m->flags & PG_ZERO) == 0)
960 vm_page_zero_fill(m);
961 vm_page_wire(m);
962 mem->am_physical = VM_PAGE_TO_PHYS(m);
963 vm_page_wakeup(m);
964 } else {
965 /* Our allocation is already nicely wired down for us.
966 * Just grab the physical address.
967 */
968 mem->am_physical = vtophys(sc->argb_cursor);
969 }
970 } else {
971 mem->am_physical = 0;
972 }
973
974 mem->am_offset = 0;
975 mem->am_is_bound = 0;
976 TAILQ_INSERT_TAIL(&sc->agp.as_memory, mem, am_link);
977 sc->agp.as_allocated += size;
978
979 return mem;
980 }
981
982 static int
983 agp_i810_free_memory(device_t dev, struct agp_memory *mem)
984 {
985 struct agp_i810_softc *sc = device_get_softc(dev);
986
987 if (mem->am_is_bound)
988 return EBUSY;
989
990 if (mem->am_type == 2) {
991 if (mem->am_size == AGP_PAGE_SIZE) {
992 /*
993 * Unwire the page which we wired in alloc_memory.
994 */
995 vm_page_t m = vm_page_lookup(mem->am_obj, 0);
996 vm_page_unwire(m, 0);
997 } else {
998 contigfree(sc->argb_cursor, mem->am_size, M_AGP);
999 sc->argb_cursor = NULL;
1000 }
1001 }
1002
1003 sc->agp.as_allocated -= mem->am_size;
1004 TAILQ_REMOVE(&sc->agp.as_memory, mem, am_link);
1005 if (mem->am_obj)
1006 vm_object_deallocate(mem->am_obj);
1007 kfree(mem, M_AGP);
1008 return 0;
1009 }
1010
1011 static int
1012 agp_i810_bind_memory(device_t dev, struct agp_memory *mem,
1013 vm_offset_t offset)
1014 {
1015 struct agp_i810_softc *sc = device_get_softc(dev);
1016 vm_offset_t i;
1017
1018 /* Do some sanity checks first. */
1019 if (offset < 0 || (offset & (AGP_PAGE_SIZE - 1)) != 0 ||
1020 offset + mem->am_size > AGP_GET_APERTURE(dev)) {
1021 device_printf(dev, "binding memory at bad offset %#x\n",
1022 (int)offset);
1023 return EINVAL;
1024 }
1025
1026 if (mem->am_type == 2 && mem->am_size != AGP_PAGE_SIZE) {
1027 lockmgr(&sc->agp.as_lock, LK_EXCLUSIVE);
1028 if (mem->am_is_bound) {
1029 lockmgr(&sc->agp.as_lock, LK_RELEASE);
1030 return EINVAL;
1031 }
1032 /* The memory's already wired down, just stick it in the GTT. */
1033 for (i = 0; i < mem->am_size; i += AGP_PAGE_SIZE) {
1034 agp_i810_write_gtt_entry(dev, offset + i,
1035 mem->am_physical + i, 1);
1036 }
1037 agp_flush_cache();
1038 mem->am_offset = offset;
1039 mem->am_is_bound = 1;
1040 lockmgr(&sc->agp.as_lock, LK_RELEASE);
1041 return 0;
1042 }
1043
1044 if (mem->am_type != 1)
1045 return agp_generic_bind_memory(dev, mem, offset);
1046
1047 if ( sc->chiptype != CHIP_I810 )
1048 return EINVAL;
1049
1050 for (i = 0; i < mem->am_size; i += AGP_PAGE_SIZE) {
1051 bus_write_4(sc->sc_res[0],
1052 AGP_I810_GTT + (i >> AGP_PAGE_SHIFT) * 4, i | 3);
1053 }
1054
1055 return 0;
1056 }
1057
1058 static int
1059 agp_i810_unbind_memory(device_t dev, struct agp_memory *mem)
1060 {
1061 struct agp_i810_softc *sc = device_get_softc(dev);
1062 vm_offset_t i;
1063
1064 if (mem->am_type == 2 && mem->am_size != AGP_PAGE_SIZE) {
1065 lockmgr(&sc->agp.as_lock, LK_EXCLUSIVE);
1066 if (!mem->am_is_bound) {
1067 lockmgr(&sc->agp.as_lock, LK_RELEASE);
1068 return EINVAL;
1069 }
1070
1071 for (i = 0; i < mem->am_size; i += AGP_PAGE_SIZE) {
1072 agp_i810_write_gtt_entry(dev, mem->am_offset + i,
1073 0, 0);
1074 }
1075 agp_flush_cache();
1076 mem->am_is_bound = 0;
1077 lockmgr(&sc->agp.as_lock, LK_RELEASE);
1078 return 0;
1079 }
1080
1081 if (mem->am_type != 1)
1082 return agp_generic_unbind_memory(dev, mem);
1083
1084 if ( sc->chiptype != CHIP_I810 )
1085 return EINVAL;
1086
1087 for (i = 0; i < mem->am_size; i += AGP_PAGE_SIZE) {
1088 bus_write_4(sc->sc_res[0],
1089 AGP_I810_GTT + (i >> AGP_PAGE_SHIFT) * 4, 0);
1090 }
1091
1092 return 0;
1093 }
1094
1095 static device_method_t agp_i810_methods[] = {
1096 /* Device interface */
1097 DEVMETHOD(device_identify, agp_i810_identify),
1098 DEVMETHOD(device_probe, agp_i810_probe),
1099 DEVMETHOD(device_attach, agp_i810_attach),
1100 DEVMETHOD(device_detach, agp_i810_detach),
1101 DEVMETHOD(device_suspend, bus_generic_suspend),
1102 DEVMETHOD(device_resume, agp_i810_resume),
1103
1104 /* AGP interface */
1105 DEVMETHOD(agp_get_aperture, agp_generic_get_aperture),
1106 DEVMETHOD(agp_set_aperture, agp_i810_set_aperture),
1107 DEVMETHOD(agp_bind_page, agp_i810_bind_page),
1108 DEVMETHOD(agp_unbind_page, agp_i810_unbind_page),
1109 DEVMETHOD(agp_flush_tlb, agp_i810_flush_tlb),
1110 DEVMETHOD(agp_enable, agp_i810_enable),
1111 DEVMETHOD(agp_alloc_memory, agp_i810_alloc_memory),
1112 DEVMETHOD(agp_free_memory, agp_i810_free_memory),
1113 DEVMETHOD(agp_bind_memory, agp_i810_bind_memory),
1114 DEVMETHOD(agp_unbind_memory, agp_i810_unbind_memory),
1115
1116 { 0, 0 }
1117 };
1118
1119 static driver_t agp_i810_driver = {
1120 "agp",
1121 agp_i810_methods,
1122 sizeof(struct agp_i810_softc),
1123 };
1124
1125 static devclass_t agp_devclass;
1126
1127 DRIVER_MODULE(agp_i810, vgapci, agp_i810_driver, agp_devclass, 0, 0);
1128 MODULE_DEPEND(agp_i810, agp, 1, 1, 1);
1129 MODULE_DEPEND(agp_i810, pci, 1, 1, 1);
DragonFly BSD