2 * Copyright 2008 Advanced Micro Devices, Inc.
3 * Copyright 2008 Red Hat Inc.
4 * Copyright 2009 Jerome Glisse.
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10 * and/or sell copies of the Software, and to permit persons to whom the
11 * Software is furnished to do so, subject to the following conditions:
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
22 * OTHER DEALINGS IN THE SOFTWARE.
24 * Authors: Dave Airlie
28 * $FreeBSD: head/sys/dev/drm2/radeon/radeon_device.c 255573 2013-09-14 17:24:41Z dumbbell $
31 #include "drm/drm_legacy.h" /* for drm_dma_handle_t */
32 #include <drm/drm_crtc_helper.h>
33 #include <uapi_drm/radeon_drm.h>
35 #include "radeon_reg.h"
39 static const char radeon_family_name
[][16] = {
105 #define RADEON_PX_QUIRK_DISABLE_PX (1 << 0)
106 #define RADEON_PX_QUIRK_LONG_WAKEUP (1 << 1)
108 struct radeon_px_quirk
{
116 static struct radeon_px_quirk radeon_px_quirk_list
[] = {
117 /* Acer aspire 5560g (CPU: AMD A4-3305M; GPU: AMD Radeon HD 6480g + 7470m)
118 * https://bugzilla.kernel.org/show_bug.cgi?id=74551
120 { PCI_VENDOR_ID_ATI
, 0x6760, 0x1025, 0x0672, RADEON_PX_QUIRK_DISABLE_PX
},
121 /* Asus K73TA laptop with AMD A6-3400M APU and Radeon 6550 GPU
122 * https://bugzilla.kernel.org/show_bug.cgi?id=51381
124 { PCI_VENDOR_ID_ATI
, 0x6741, 0x1043, 0x108c, RADEON_PX_QUIRK_DISABLE_PX
},
125 /* Asus K53TK laptop with AMD A6-3420M APU and Radeon 7670m GPU
126 * https://bugzilla.kernel.org/show_bug.cgi?id=51381
128 { PCI_VENDOR_ID_ATI
, 0x6840, 0x1043, 0x2122, RADEON_PX_QUIRK_DISABLE_PX
},
129 /* macbook pro 8.2 */
130 { PCI_VENDOR_ID_ATI
, 0x6741, PCI_VENDOR_ID_APPLE
, 0x00e2, RADEON_PX_QUIRK_LONG_WAKEUP
},
134 bool radeon_is_px(struct drm_device
*dev
)
136 struct radeon_device
*rdev
= dev
->dev_private
;
138 if (rdev
->flags
& RADEON_IS_PX
)
143 static void radeon_device_handle_px_quirks(struct radeon_device
*rdev
)
145 struct radeon_px_quirk
*p
= radeon_px_quirk_list
;
147 /* Apply PX quirks */
148 while (p
&& p
->chip_device
!= 0) {
149 if (rdev
->pdev
->vendor
== p
->chip_vendor
&&
150 rdev
->pdev
->device
== p
->chip_device
&&
151 rdev
->pdev
->subsystem_vendor
== p
->subsys_vendor
&&
152 rdev
->pdev
->subsystem_device
== p
->subsys_device
) {
153 rdev
->px_quirk_flags
= p
->px_quirk_flags
;
159 if (rdev
->px_quirk_flags
& RADEON_PX_QUIRK_DISABLE_PX
)
160 rdev
->flags
&= ~RADEON_IS_PX
;
164 * radeon_program_register_sequence - program an array of registers.
166 * @rdev: radeon_device pointer
167 * @registers: pointer to the register array
168 * @array_size: size of the register array
170 * Programs an array or registers with and and or masks.
171 * This is a helper for setting golden registers.
173 void radeon_program_register_sequence(struct radeon_device
*rdev
,
174 const u32
*registers
,
175 const u32 array_size
)
177 u32 tmp
, reg
, and_mask
, or_mask
;
183 for (i
= 0; i
< array_size
; i
+=3) {
184 reg
= registers
[i
+ 0];
185 and_mask
= registers
[i
+ 1];
186 or_mask
= registers
[i
+ 2];
188 if (and_mask
== 0xffffffff) {
199 void radeon_pci_config_reset(struct radeon_device
*rdev
)
201 pci_write_config_dword(rdev
->pdev
, 0x7c, RADEON_ASIC_RESET_DATA
);
205 * radeon_surface_init - Clear GPU surface registers.
207 * @rdev: radeon_device pointer
209 * Clear GPU surface registers (r1xx-r5xx).
211 void radeon_surface_init(struct radeon_device
*rdev
)
213 /* FIXME: check this out */
214 if (rdev
->family
< CHIP_R600
) {
217 for (i
= 0; i
< RADEON_GEM_MAX_SURFACES
; i
++) {
218 if (rdev
->surface_regs
[i
].bo
)
219 radeon_bo_get_surface_reg(rdev
->surface_regs
[i
].bo
);
221 radeon_clear_surface_reg(rdev
, i
);
223 /* enable surfaces */
224 WREG32(RADEON_SURFACE_CNTL
, 0);
229 * GPU scratch registers helpers function.
232 * radeon_scratch_init - Init scratch register driver information.
234 * @rdev: radeon_device pointer
236 * Init CP scratch register driver information (r1xx-r5xx)
238 void radeon_scratch_init(struct radeon_device
*rdev
)
242 /* FIXME: check this out */
243 if (rdev
->family
< CHIP_R300
) {
244 rdev
->scratch
.num_reg
= 5;
246 rdev
->scratch
.num_reg
= 7;
248 rdev
->scratch
.reg_base
= RADEON_SCRATCH_REG0
;
249 for (i
= 0; i
< rdev
->scratch
.num_reg
; i
++) {
250 rdev
->scratch
.free
[i
] = true;
251 rdev
->scratch
.reg
[i
] = rdev
->scratch
.reg_base
+ (i
* 4);
256 * radeon_scratch_get - Allocate a scratch register
258 * @rdev: radeon_device pointer
259 * @reg: scratch register mmio offset
261 * Allocate a CP scratch register for use by the driver (all asics).
262 * Returns 0 on success or -EINVAL on failure.
264 int radeon_scratch_get(struct radeon_device
*rdev
, uint32_t *reg
)
268 for (i
= 0; i
< rdev
->scratch
.num_reg
; i
++) {
269 if (rdev
->scratch
.free
[i
]) {
270 rdev
->scratch
.free
[i
] = false;
271 *reg
= rdev
->scratch
.reg
[i
];
279 * radeon_scratch_free - Free a scratch register
281 * @rdev: radeon_device pointer
282 * @reg: scratch register mmio offset
284 * Free a CP scratch register allocated for use by the driver (all asics)
286 void radeon_scratch_free(struct radeon_device
*rdev
, uint32_t reg
)
290 for (i
= 0; i
< rdev
->scratch
.num_reg
; i
++) {
291 if (rdev
->scratch
.reg
[i
] == reg
) {
292 rdev
->scratch
.free
[i
] = true;
299 * GPU doorbell aperture helpers function.
302 * radeon_doorbell_init - Init doorbell driver information.
304 * @rdev: radeon_device pointer
306 * Init doorbell driver information (CIK)
307 * Returns 0 on success, error on failure.
309 static int radeon_doorbell_init(struct radeon_device
*rdev
)
311 /* doorbell bar mapping */
312 rdev
->doorbell
.base
= pci_resource_start(rdev
->pdev
, 2);
313 rdev
->doorbell
.size
= pci_resource_len(rdev
->pdev
, 2);
315 rdev
->doorbell
.num_doorbells
= min_t(u32
, rdev
->doorbell
.size
/ sizeof(u32
), RADEON_MAX_DOORBELLS
);
316 if (rdev
->doorbell
.num_doorbells
== 0)
319 rdev
->doorbell
.ptr
= ioremap(rdev
->doorbell
.base
, rdev
->doorbell
.num_doorbells
* sizeof(u32
));
320 if (rdev
->doorbell
.ptr
== NULL
) {
323 DRM_INFO("doorbell mmio base: 0x%08X\n", (uint32_t)rdev
->doorbell
.base
);
324 DRM_INFO("doorbell mmio size: %u\n", (unsigned)rdev
->doorbell
.size
);
326 memset(&rdev
->doorbell
.used
, 0, sizeof(rdev
->doorbell
.used
));
332 * radeon_doorbell_fini - Tear down doorbell driver information.
334 * @rdev: radeon_device pointer
336 * Tear down doorbell driver information (CIK)
338 static void radeon_doorbell_fini(struct radeon_device
*rdev
)
340 iounmap(rdev
->doorbell
.ptr
);
341 rdev
->doorbell
.ptr
= NULL
;
345 * radeon_doorbell_get - Allocate a doorbell entry
347 * @rdev: radeon_device pointer
348 * @doorbell: doorbell index
350 * Allocate a doorbell for use by the driver (all asics).
351 * Returns 0 on success or -EINVAL on failure.
353 int radeon_doorbell_get(struct radeon_device
*rdev
, u32
*doorbell
)
355 unsigned long offset
= find_first_zero_bit(rdev
->doorbell
.used
, rdev
->doorbell
.num_doorbells
);
356 if (offset
< rdev
->doorbell
.num_doorbells
) {
357 __set_bit(offset
, rdev
->doorbell
.used
);
366 * radeon_doorbell_free - Free a doorbell entry
368 * @rdev: radeon_device pointer
369 * @doorbell: doorbell index
371 * Free a doorbell allocated for use by the driver (all asics)
373 void radeon_doorbell_free(struct radeon_device
*rdev
, u32 doorbell
)
375 if (doorbell
< rdev
->doorbell
.num_doorbells
)
376 __clear_bit(doorbell
, rdev
->doorbell
.used
);
381 * Writeback is the the method by which the the GPU updates special pages
382 * in memory with the status of certain GPU events (fences, ring pointers,
387 * radeon_wb_disable - Disable Writeback
389 * @rdev: radeon_device pointer
391 * Disables Writeback (all asics). Used for suspend.
393 void radeon_wb_disable(struct radeon_device
*rdev
)
395 rdev
->wb
.enabled
= false;
399 * radeon_wb_fini - Disable Writeback and free memory
401 * @rdev: radeon_device pointer
403 * Disables Writeback and frees the Writeback memory (all asics).
404 * Used at driver shutdown.
406 void radeon_wb_fini(struct radeon_device
*rdev
)
408 radeon_wb_disable(rdev
);
409 if (rdev
->wb
.wb_obj
) {
410 if (!radeon_bo_reserve(rdev
->wb
.wb_obj
, false)) {
411 radeon_bo_kunmap(rdev
->wb
.wb_obj
);
412 radeon_bo_unpin(rdev
->wb
.wb_obj
);
413 radeon_bo_unreserve(rdev
->wb
.wb_obj
);
415 radeon_bo_unref(&rdev
->wb
.wb_obj
);
417 rdev
->wb
.wb_obj
= NULL
;
422 * radeon_wb_init- Init Writeback driver info and allocate memory
424 * @rdev: radeon_device pointer
426 * Disables Writeback and frees the Writeback memory (all asics).
427 * Used at driver startup.
428 * Returns 0 on success or an -error on failure.
430 int radeon_wb_init(struct radeon_device
*rdev
)
435 if (rdev
->wb
.wb_obj
== NULL
) {
436 r
= radeon_bo_create(rdev
, RADEON_GPU_PAGE_SIZE
, PAGE_SIZE
, true,
437 RADEON_GEM_DOMAIN_GTT
, 0, NULL
,
440 dev_warn(rdev
->dev
, "(%d) create WB bo failed\n", r
);
443 r
= radeon_bo_reserve(rdev
->wb
.wb_obj
, false);
444 if (unlikely(r
!= 0)) {
445 radeon_wb_fini(rdev
);
448 r
= radeon_bo_pin(rdev
->wb
.wb_obj
, RADEON_GEM_DOMAIN_GTT
,
451 radeon_bo_unreserve(rdev
->wb
.wb_obj
);
452 dev_warn(rdev
->dev
, "(%d) pin WB bo failed\n", r
);
453 radeon_wb_fini(rdev
);
456 wb_ptr
= &rdev
->wb
.wb
;
457 r
= radeon_bo_kmap(rdev
->wb
.wb_obj
, wb_ptr
);
458 radeon_bo_unreserve(rdev
->wb
.wb_obj
);
460 dev_warn(rdev
->dev
, "(%d) map WB bo failed\n", r
);
461 radeon_wb_fini(rdev
);
464 /* clear wb memory */
465 memset(*(void **)wb_ptr
, 0, RADEON_GPU_PAGE_SIZE
);
468 /* disable event_write fences */
469 rdev
->wb
.use_event
= false;
470 /* disabled via module param */
471 if (radeon_no_wb
== 1) {
472 rdev
->wb
.enabled
= false;
474 if (rdev
->flags
& RADEON_IS_AGP
) {
475 /* often unreliable on AGP */
476 rdev
->wb
.enabled
= false;
477 } else if (rdev
->family
< CHIP_R300
) {
478 /* often unreliable on pre-r300 */
479 rdev
->wb
.enabled
= false;
481 rdev
->wb
.enabled
= true;
482 /* event_write fences are only available on r600+ */
483 if (rdev
->family
>= CHIP_R600
) {
484 rdev
->wb
.use_event
= true;
488 /* always use writeback/events on NI, APUs */
489 if (rdev
->family
>= CHIP_PALM
) {
490 rdev
->wb
.enabled
= true;
491 rdev
->wb
.use_event
= true;
494 dev_info(rdev
->dev
, "WB %sabled\n", rdev
->wb
.enabled
? "en" : "dis");
500 * radeon_vram_location - try to find VRAM location
501 * @rdev: radeon device structure holding all necessary informations
502 * @mc: memory controller structure holding memory informations
503 * @base: base address at which to put VRAM
505 * Function will place try to place VRAM at base address provided
506 * as parameter (which is so far either PCI aperture address or
507 * for IGP TOM base address).
509 * If there is not enough space to fit the unvisible VRAM in the 32bits
510 * address space then we limit the VRAM size to the aperture.
512 * If we are using AGP and if the AGP aperture doesn't allow us to have
513 * room for all the VRAM than we restrict the VRAM to the PCI aperture
514 * size and print a warning.
516 * This function will never fails, worst case are limiting VRAM.
518 * Note: GTT start, end, size should be initialized before calling this
519 * function on AGP platform.
521 * Note: We don't explicitly enforce VRAM start to be aligned on VRAM size,
522 * this shouldn't be a problem as we are using the PCI aperture as a reference.
523 * Otherwise this would be needed for rv280, all r3xx, and all r4xx, but
526 * Note: we use mc_vram_size as on some board we need to program the mc to
527 * cover the whole aperture even if VRAM size is inferior to aperture size
528 * Novell bug 204882 + along with lots of ubuntu ones
530 * Note: when limiting vram it's safe to overwritte real_vram_size because
531 * we are not in case where real_vram_size is inferior to mc_vram_size (ie
532 * note afected by bogus hw of Novell bug 204882 + along with lots of ubuntu
535 * Note: IGP TOM addr should be the same as the aperture addr, we don't
536 * explicitly check for that thought.
538 * FIXME: when reducing VRAM size align new size on power of 2.
540 void radeon_vram_location(struct radeon_device
*rdev
, struct radeon_mc
*mc
, u64 base
)
542 uint64_t limit
= (uint64_t)radeon_vram_limit
<< 20;
544 mc
->vram_start
= base
;
545 if (mc
->mc_vram_size
> (rdev
->mc
.mc_mask
- base
+ 1)) {
546 dev_warn(rdev
->dev
, "limiting VRAM to PCI aperture size\n");
547 mc
->real_vram_size
= mc
->aper_size
;
548 mc
->mc_vram_size
= mc
->aper_size
;
550 mc
->vram_end
= mc
->vram_start
+ mc
->mc_vram_size
- 1;
551 if (rdev
->flags
& RADEON_IS_AGP
&& mc
->vram_end
> mc
->gtt_start
&& mc
->vram_start
<= mc
->gtt_end
) {
552 dev_warn(rdev
->dev
, "limiting VRAM to PCI aperture size\n");
553 mc
->real_vram_size
= mc
->aper_size
;
554 mc
->mc_vram_size
= mc
->aper_size
;
556 mc
->vram_end
= mc
->vram_start
+ mc
->mc_vram_size
- 1;
557 if (limit
&& limit
< mc
->real_vram_size
)
558 mc
->real_vram_size
= limit
;
559 dev_info(rdev
->dev
, "VRAM: %juM 0x%016jX - 0x%016jX (%juM used)\n",
560 mc
->mc_vram_size
>> 20, mc
->vram_start
,
561 mc
->vram_end
, mc
->real_vram_size
>> 20);
565 * radeon_gtt_location - try to find GTT location
566 * @rdev: radeon device structure holding all necessary informations
567 * @mc: memory controller structure holding memory informations
569 * Function will place try to place GTT before or after VRAM.
571 * If GTT size is bigger than space left then we ajust GTT size.
572 * Thus function will never fails.
574 * FIXME: when reducing GTT size align new size on power of 2.
576 void radeon_gtt_location(struct radeon_device
*rdev
, struct radeon_mc
*mc
)
578 u64 size_af
, size_bf
;
580 size_af
= ((rdev
->mc
.mc_mask
- mc
->vram_end
) + mc
->gtt_base_align
) & ~mc
->gtt_base_align
;
581 size_bf
= mc
->vram_start
& ~mc
->gtt_base_align
;
582 if (size_bf
> size_af
) {
583 if (mc
->gtt_size
> size_bf
) {
584 dev_warn(rdev
->dev
, "limiting GTT\n");
585 mc
->gtt_size
= size_bf
;
587 mc
->gtt_start
= (mc
->vram_start
& ~mc
->gtt_base_align
) - mc
->gtt_size
;
589 if (mc
->gtt_size
> size_af
) {
590 dev_warn(rdev
->dev
, "limiting GTT\n");
591 mc
->gtt_size
= size_af
;
593 mc
->gtt_start
= (mc
->vram_end
+ 1 + mc
->gtt_base_align
) & ~mc
->gtt_base_align
;
595 mc
->gtt_end
= mc
->gtt_start
+ mc
->gtt_size
- 1;
596 dev_info(rdev
->dev
, "GTT: %juM 0x%016jX - 0x%016jX\n",
597 mc
->gtt_size
>> 20, mc
->gtt_start
, mc
->gtt_end
);
601 * GPU helpers function.
604 * radeon_card_posted - check if the hw has already been initialized
606 * @rdev: radeon_device pointer
608 * Check if the asic has been initialized (all asics).
609 * Used at driver startup.
610 * Returns true if initialized or false if not.
612 bool radeon_card_posted(struct radeon_device
*rdev
)
617 /* required for EFI mode on macbook2,1 which uses an r5xx asic */
618 if (efi_enabled(EFI_BOOT
) &&
619 (rdev
->pdev
->subsystem_vendor
== PCI_VENDOR_ID_APPLE
) &&
620 (rdev
->family
< CHIP_R600
))
622 #endif /* DUMBBELL_WIP */
624 if (ASIC_IS_NODCE(rdev
))
627 /* first check CRTCs */
628 if (ASIC_IS_DCE4(rdev
)) {
629 reg
= RREG32(EVERGREEN_CRTC_CONTROL
+ EVERGREEN_CRTC0_REGISTER_OFFSET
) |
630 RREG32(EVERGREEN_CRTC_CONTROL
+ EVERGREEN_CRTC1_REGISTER_OFFSET
);
631 if (rdev
->num_crtc
>= 4) {
632 reg
|= RREG32(EVERGREEN_CRTC_CONTROL
+ EVERGREEN_CRTC2_REGISTER_OFFSET
) |
633 RREG32(EVERGREEN_CRTC_CONTROL
+ EVERGREEN_CRTC3_REGISTER_OFFSET
);
635 if (rdev
->num_crtc
>= 6) {
636 reg
|= RREG32(EVERGREEN_CRTC_CONTROL
+ EVERGREEN_CRTC4_REGISTER_OFFSET
) |
637 RREG32(EVERGREEN_CRTC_CONTROL
+ EVERGREEN_CRTC5_REGISTER_OFFSET
);
639 if (reg
& EVERGREEN_CRTC_MASTER_EN
)
641 } else if (ASIC_IS_AVIVO(rdev
)) {
642 reg
= RREG32(AVIVO_D1CRTC_CONTROL
) |
643 RREG32(AVIVO_D2CRTC_CONTROL
);
644 if (reg
& AVIVO_CRTC_EN
) {
648 reg
= RREG32(RADEON_CRTC_GEN_CNTL
) |
649 RREG32(RADEON_CRTC2_GEN_CNTL
);
650 if (reg
& RADEON_CRTC_EN
) {
656 /* then check MEM_SIZE, in case the crtcs are off */
657 if (rdev
->family
>= CHIP_R600
)
658 reg
= RREG32(R600_CONFIG_MEMSIZE
);
660 reg
= RREG32(RADEON_CONFIG_MEMSIZE
);
670 * radeon_update_bandwidth_info - update display bandwidth params
672 * @rdev: radeon_device pointer
674 * Used when sclk/mclk are switched or display modes are set.
675 * params are used to calculate display watermarks (all asics)
677 void radeon_update_bandwidth_info(struct radeon_device
*rdev
)
680 u32 sclk
= rdev
->pm
.current_sclk
;
681 u32 mclk
= rdev
->pm
.current_mclk
;
683 /* sclk/mclk in Mhz */
684 a
.full
= dfixed_const(100);
685 rdev
->pm
.sclk
.full
= dfixed_const(sclk
);
686 rdev
->pm
.sclk
.full
= dfixed_div(rdev
->pm
.sclk
, a
);
687 rdev
->pm
.mclk
.full
= dfixed_const(mclk
);
688 rdev
->pm
.mclk
.full
= dfixed_div(rdev
->pm
.mclk
, a
);
690 if (rdev
->flags
& RADEON_IS_IGP
) {
691 a
.full
= dfixed_const(16);
692 /* core_bandwidth = sclk(Mhz) * 16 */
693 rdev
->pm
.core_bandwidth
.full
= dfixed_div(rdev
->pm
.sclk
, a
);
698 * radeon_boot_test_post_card - check and possibly initialize the hw
700 * @rdev: radeon_device pointer
702 * Check if the asic is initialized and if not, attempt to initialize
704 * Returns true if initialized or false if not.
706 bool radeon_boot_test_post_card(struct radeon_device
*rdev
)
708 if (radeon_card_posted(rdev
))
712 DRM_INFO("GPU not posted. posting now...\n");
713 if (rdev
->is_atom_bios
)
714 atom_asic_init(rdev
->mode_info
.atom_context
);
716 radeon_combios_asic_init(rdev
->ddev
);
719 dev_err(rdev
->dev
, "Card not posted and no BIOS - ignoring\n");
725 * radeon_dummy_page_init - init dummy page used by the driver
727 * @rdev: radeon_device pointer
729 * Allocate the dummy page used by the driver (all asics).
730 * This dummy page is used by the driver as a filler for gart entries
731 * when pages are taken out of the GART
732 * Returns 0 on sucess, -ENOMEM on failure.
734 int radeon_dummy_page_init(struct radeon_device
*rdev
)
736 if (rdev
->dummy_page
.dmah
)
738 rdev
->dummy_page
.dmah
= drm_pci_alloc(rdev
->ddev
,
739 PAGE_SIZE
, PAGE_SIZE
);
740 if (rdev
->dummy_page
.dmah
== NULL
)
742 rdev
->dummy_page
.addr
=
743 (dma_addr_t
)rdev
->dummy_page
.dmah
->busaddr
;
748 * radeon_dummy_page_fini - free dummy page used by the driver
750 * @rdev: radeon_device pointer
752 * Frees the dummy page used by the driver (all asics).
754 void radeon_dummy_page_fini(struct radeon_device
*rdev
)
756 if (rdev
->dummy_page
.dmah
== NULL
)
758 drm_pci_free(rdev
->ddev
, rdev
->dummy_page
.dmah
);
759 rdev
->dummy_page
.dmah
= NULL
;
760 rdev
->dummy_page
.addr
= 0;
764 /* ATOM accessor methods */
766 * ATOM is an interpreted byte code stored in tables in the vbios. The
767 * driver registers callbacks to access registers and the interpreter
768 * in the driver parses the tables and executes then to program specific
769 * actions (set display modes, asic init, etc.). See radeon_atombios.c,
770 * atombios.h, and atom.c
774 * cail_pll_read - read PLL register
776 * @info: atom card_info pointer
777 * @reg: PLL register offset
779 * Provides a PLL register accessor for the atom interpreter (r4xx+).
780 * Returns the value of the PLL register.
782 static uint32_t cail_pll_read(struct card_info
*info
, uint32_t reg
)
784 struct radeon_device
*rdev
= info
->dev
->dev_private
;
787 r
= rdev
->pll_rreg(rdev
, reg
);
792 * cail_pll_write - write PLL register
794 * @info: atom card_info pointer
795 * @reg: PLL register offset
796 * @val: value to write to the pll register
798 * Provides a PLL register accessor for the atom interpreter (r4xx+).
800 static void cail_pll_write(struct card_info
*info
, uint32_t reg
, uint32_t val
)
802 struct radeon_device
*rdev
= info
->dev
->dev_private
;
804 rdev
->pll_wreg(rdev
, reg
, val
);
808 * cail_mc_read - read MC (Memory Controller) register
810 * @info: atom card_info pointer
811 * @reg: MC register offset
813 * Provides an MC register accessor for the atom interpreter (r4xx+).
814 * Returns the value of the MC register.
816 static uint32_t cail_mc_read(struct card_info
*info
, uint32_t reg
)
818 struct radeon_device
*rdev
= info
->dev
->dev_private
;
821 r
= rdev
->mc_rreg(rdev
, reg
);
826 * cail_mc_write - write MC (Memory Controller) register
828 * @info: atom card_info pointer
829 * @reg: MC register offset
830 * @val: value to write to the pll register
832 * Provides a MC register accessor for the atom interpreter (r4xx+).
834 static void cail_mc_write(struct card_info
*info
, uint32_t reg
, uint32_t val
)
836 struct radeon_device
*rdev
= info
->dev
->dev_private
;
838 rdev
->mc_wreg(rdev
, reg
, val
);
842 * cail_reg_write - write MMIO register
844 * @info: atom card_info pointer
845 * @reg: MMIO register offset
846 * @val: value to write to the pll register
848 * Provides a MMIO register accessor for the atom interpreter (r4xx+).
850 static void cail_reg_write(struct card_info
*info
, uint32_t reg
, uint32_t val
)
852 struct radeon_device
*rdev
= info
->dev
->dev_private
;
858 * cail_reg_read - read MMIO register
860 * @info: atom card_info pointer
861 * @reg: MMIO register offset
863 * Provides an MMIO register accessor for the atom interpreter (r4xx+).
864 * Returns the value of the MMIO register.
866 static uint32_t cail_reg_read(struct card_info
*info
, uint32_t reg
)
868 struct radeon_device
*rdev
= info
->dev
->dev_private
;
876 * cail_ioreg_write - write IO register
878 * @info: atom card_info pointer
879 * @reg: IO register offset
880 * @val: value to write to the pll register
882 * Provides a IO register accessor for the atom interpreter (r4xx+).
884 static void cail_ioreg_write(struct card_info
*info
, uint32_t reg
, uint32_t val
)
886 struct radeon_device
*rdev
= info
->dev
->dev_private
;
888 WREG32_IO(reg
*4, val
);
892 * cail_ioreg_read - read IO register
894 * @info: atom card_info pointer
895 * @reg: IO register offset
897 * Provides an IO register accessor for the atom interpreter (r4xx+).
898 * Returns the value of the IO register.
900 static uint32_t cail_ioreg_read(struct card_info
*info
, uint32_t reg
)
902 struct radeon_device
*rdev
= info
->dev
->dev_private
;
905 r
= RREG32_IO(reg
*4);
910 * radeon_atombios_init - init the driver info and callbacks for atombios
912 * @rdev: radeon_device pointer
914 * Initializes the driver info and register access callbacks for the
915 * ATOM interpreter (r4xx+).
916 * Returns 0 on sucess, -ENOMEM on failure.
917 * Called at driver startup.
919 int radeon_atombios_init(struct radeon_device
*rdev
)
921 struct card_info
*atom_card_info
=
922 kzalloc(sizeof(struct card_info
), GFP_KERNEL
);
927 rdev
->mode_info
.atom_card_info
= atom_card_info
;
928 atom_card_info
->dev
= rdev
->ddev
;
929 atom_card_info
->reg_read
= cail_reg_read
;
930 atom_card_info
->reg_write
= cail_reg_write
;
931 /* needed for iio ops */
933 atom_card_info
->ioreg_read
= cail_ioreg_read
;
934 atom_card_info
->ioreg_write
= cail_ioreg_write
;
936 DRM_ERROR("Unable to find PCI I/O BAR; using MMIO for ATOM IIO\n");
937 atom_card_info
->ioreg_read
= cail_reg_read
;
938 atom_card_info
->ioreg_write
= cail_reg_write
;
940 atom_card_info
->mc_read
= cail_mc_read
;
941 atom_card_info
->mc_write
= cail_mc_write
;
942 atom_card_info
->pll_read
= cail_pll_read
;
943 atom_card_info
->pll_write
= cail_pll_write
;
945 rdev
->mode_info
.atom_context
= atom_parse(atom_card_info
, rdev
->bios
);
946 if (!rdev
->mode_info
.atom_context
) {
947 radeon_atombios_fini(rdev
);
951 lockinit(&rdev
->mode_info
.atom_context
->mutex
, "rmiacmtx", 0, LK_CANRECURSE
);
952 lockinit(&rdev
->mode_info
.atom_context
->scratch_mutex
, "rmiacsmtx", 0, LK_CANRECURSE
);
953 radeon_atom_initialize_bios_scratch_regs(rdev
->ddev
);
954 atom_allocate_fb_scratch(rdev
->mode_info
.atom_context
);
959 * radeon_atombios_fini - free the driver info and callbacks for atombios
961 * @rdev: radeon_device pointer
963 * Frees the driver info and register access callbacks for the ATOM
964 * interpreter (r4xx+).
965 * Called at driver shutdown.
967 void radeon_atombios_fini(struct radeon_device
*rdev
)
969 if (rdev
->mode_info
.atom_context
) {
970 /* prevents leaking 512 bytes */
971 kfree(rdev
->mode_info
.atom_context
->iio
);
973 kfree(rdev
->mode_info
.atom_context
->scratch
);
975 kfree(rdev
->mode_info
.atom_context
);
976 rdev
->mode_info
.atom_context
= NULL
;
977 kfree(rdev
->mode_info
.atom_card_info
);
978 rdev
->mode_info
.atom_card_info
= NULL
;
983 * COMBIOS is the bios format prior to ATOM. It provides
984 * command tables similar to ATOM, but doesn't have a unified
985 * parser. See radeon_combios.c
989 * radeon_combios_init - init the driver info for combios
991 * @rdev: radeon_device pointer
993 * Initializes the driver info for combios (r1xx-r3xx).
994 * Returns 0 on sucess.
995 * Called at driver startup.
997 int radeon_combios_init(struct radeon_device
*rdev
)
999 radeon_combios_initialize_bios_scratch_regs(rdev
->ddev
);
1004 * radeon_combios_fini - free the driver info for combios
1006 * @rdev: radeon_device pointer
1008 * Frees the driver info for combios (r1xx-r3xx).
1009 * Called at driver shutdown.
1011 void radeon_combios_fini(struct radeon_device
*rdev
)
1016 /* if we get transitioned to only one device, take VGA back */
1018 * radeon_vga_set_decode - enable/disable vga decode
1020 * @cookie: radeon_device pointer
1021 * @state: enable/disable vga decode
1023 * Enable/disable vga decode (all asics).
1024 * Returns VGA resource flags.
1026 static unsigned int radeon_vga_set_decode(void *cookie
, bool state
)
1028 struct radeon_device
*rdev
= cookie
;
1029 radeon_vga_set_state(rdev
, state
);
1031 return VGA_RSRC_LEGACY_IO
| VGA_RSRC_LEGACY_MEM
|
1032 VGA_RSRC_NORMAL_IO
| VGA_RSRC_NORMAL_MEM
;
1034 return VGA_RSRC_NORMAL_IO
| VGA_RSRC_NORMAL_MEM
;
1036 #endif /* DUMBBELL_WIP */
1039 * radeon_check_pot_argument - check that argument is a power of two
1041 * @arg: value to check
1043 * Validates that a certain argument is a power of two (all asics).
1044 * Returns true if argument is valid.
1046 static bool radeon_check_pot_argument(int arg
)
1048 return (arg
& (arg
- 1)) == 0;
1052 * radeon_check_arguments - validate module params
1054 * @rdev: radeon_device pointer
1056 * Validates certain module parameters and updates
1057 * the associated values used by the driver (all asics).
1059 static void radeon_check_arguments(struct radeon_device
*rdev
)
1061 /* vramlimit must be a power of two */
1062 if (!radeon_check_pot_argument(radeon_vram_limit
)) {
1063 dev_warn(rdev
->dev
, "vram limit (%d) must be a power of 2\n",
1065 radeon_vram_limit
= 0;
1068 if (radeon_gart_size
== -1) {
1069 /* default to a larger gart size on newer asics */
1070 if (rdev
->family
>= CHIP_RV770
)
1071 radeon_gart_size
= 1024;
1073 radeon_gart_size
= 512;
1075 /* gtt size must be power of two and greater or equal to 32M */
1076 if (radeon_gart_size
< 32) {
1077 dev_warn(rdev
->dev
, "gart size (%d) too small\n",
1079 if (rdev
->family
>= CHIP_RV770
)
1080 radeon_gart_size
= 1024;
1082 radeon_gart_size
= 512;
1083 } else if (!radeon_check_pot_argument(radeon_gart_size
)) {
1084 dev_warn(rdev
->dev
, "gart size (%d) must be a power of 2\n",
1086 if (rdev
->family
>= CHIP_RV770
)
1087 radeon_gart_size
= 1024;
1089 radeon_gart_size
= 512;
1091 rdev
->mc
.gtt_size
= (uint64_t)radeon_gart_size
<< 20;
1093 /* AGP mode can only be -1, 1, 2, 4, 8 */
1094 switch (radeon_agpmode
) {
1103 dev_warn(rdev
->dev
, "invalid AGP mode %d (valid mode: "
1104 "-1, 0, 1, 2, 4, 8)\n", radeon_agpmode
);
1109 if (!radeon_check_pot_argument(radeon_vm_size
)) {
1110 dev_warn(rdev
->dev
, "VM size (%d) must be a power of 2\n",
1115 if (radeon_vm_size
< 1) {
1116 dev_warn(rdev
->dev
, "VM size (%d) to small, min is 1GB\n",
1122 * Max GPUVM size for Cayman, SI and CI are 40 bits.
1124 if (radeon_vm_size
> 1024) {
1125 dev_warn(rdev
->dev
, "VM size (%d) too large, max is 1TB\n",
1130 /* defines number of bits in page table versus page directory,
1131 * a page is 4KB so we have 12 bits offset, minimum 9 bits in the
1132 * page table and the remaining bits are in the page directory */
1133 if (radeon_vm_block_size
== -1) {
1135 /* Total bits covered by PD + PTs */
1136 unsigned bits
= ilog2(radeon_vm_size
) + 18;
1138 /* Make sure the PD is 4K in size up to 8GB address space.
1139 Above that split equal between PD and PTs */
1140 if (radeon_vm_size
<= 8)
1141 radeon_vm_block_size
= bits
- 9;
1143 radeon_vm_block_size
= (bits
+ 3) / 2;
1145 } else if (radeon_vm_block_size
< 9) {
1146 dev_warn(rdev
->dev
, "VM page table size (%d) too small\n",
1147 radeon_vm_block_size
);
1148 radeon_vm_block_size
= 9;
1151 if (radeon_vm_block_size
> 24 ||
1152 (radeon_vm_size
* 1024) < (1ull << radeon_vm_block_size
)) {
1153 dev_warn(rdev
->dev
, "VM page table size (%d) too large\n",
1154 radeon_vm_block_size
);
1155 radeon_vm_block_size
= 9;
1160 * radeon_switcheroo_set_state - set switcheroo state
1162 * @pdev: pci dev pointer
1163 * @state: vga switcheroo state
1165 * Callback for the switcheroo driver. Suspends or resumes the
1166 * the asics before or after it is powered up using ACPI methods.
1169 static void radeon_switcheroo_set_state(struct pci_dev
*pdev
, enum vga_switcheroo_state state
)
1171 struct drm_device
*dev
= pci_get_drvdata(pdev
);
1172 struct radeon_device
*rdev
= dev
->dev_private
;
1174 if (radeon_is_px(dev
) && state
== VGA_SWITCHEROO_OFF
)
1177 if (state
== VGA_SWITCHEROO_ON
) {
1178 unsigned d3_delay
= dev
->pdev
->d3_delay
;
1180 printk(KERN_INFO
"radeon: switched on\n");
1181 /* don't suspend or resume card normally */
1182 dev
->switch_power_state
= DRM_SWITCH_POWER_CHANGING
;
1184 if (d3_delay
< 20 && (rdev
->px_quirk_flags
& RADEON_PX_QUIRK_LONG_WAKEUP
))
1185 dev
->pdev
->d3_delay
= 20;
1187 radeon_resume_kms(dev
, true, true);
1189 dev
->pdev
->d3_delay
= d3_delay
;
1191 dev
->switch_power_state
= DRM_SWITCH_POWER_ON
;
1192 drm_kms_helper_poll_enable(dev
);
1194 printk(KERN_INFO
"radeon: switched off\n");
1195 drm_kms_helper_poll_disable(dev
);
1196 dev
->switch_power_state
= DRM_SWITCH_POWER_CHANGING
;
1197 radeon_suspend_kms(dev
, true, true);
1198 dev
->switch_power_state
= DRM_SWITCH_POWER_OFF
;
1201 #endif /* DUMBBELL_WIP */
1204 * radeon_switcheroo_can_switch - see if switcheroo state can change
1206 * @pdev: pci dev pointer
1208 * Callback for the switcheroo driver. Check of the switcheroo
1209 * state can be changed.
1210 * Returns true if the state can be changed, false if not.
1213 static bool radeon_switcheroo_can_switch(struct pci_dev
*pdev
)
1215 struct drm_device
*dev
= pci_get_drvdata(pdev
);
1218 * FIXME: open_count is protected by drm_global_mutex but that would lead to
1219 * locking inversion with the driver load path. And the access here is
1220 * completely racy anyway. So don't bother with locking for now.
1222 return dev
->open_count
== 0;
1225 static const struct vga_switcheroo_client_ops radeon_switcheroo_ops
= {
1226 .set_gpu_state
= radeon_switcheroo_set_state
,
1228 .can_switch
= radeon_switcheroo_can_switch
,
1230 #endif /* DUMBBELL_WIP */
1233 * radeon_device_init - initialize the driver
1235 * @rdev: radeon_device pointer
1236 * @pdev: drm dev pointer
1237 * @pdev: pci dev pointer
1238 * @flags: driver flags
1240 * Initializes the driver info and hw (all asics).
1241 * Returns 0 for success or an error on failure.
1242 * Called at driver startup.
1244 int radeon_device_init(struct radeon_device
*rdev
,
1245 struct drm_device
*ddev
,
1246 struct pci_dev
*pdev
,
1252 bool runtime
= false;
1255 rdev
->shutdown
= false;
1256 rdev
->dev
= &pdev
->dev
;
1259 rdev
->flags
= flags
;
1260 rdev
->family
= flags
& RADEON_FAMILY_MASK
;
1261 rdev
->is_atom_bios
= false;
1262 rdev
->usec_timeout
= RADEON_MAX_USEC_TIMEOUT
;
1263 rdev
->mc
.gtt_size
= 512 * 1024 * 1024;
1264 rdev
->accel_working
= false;
1265 rdev
->fictitious_range_registered
= false;
1266 /* set up ring ids */
1267 for (i
= 0; i
< RADEON_NUM_RINGS
; i
++) {
1268 rdev
->ring
[i
].idx
= i
;
1271 DRM_INFO("initializing kernel modesetting (%s 0x%04X:0x%04X 0x%04X:0x%04X).\n",
1272 radeon_family_name
[rdev
->family
], pdev
->vendor
, pdev
->device
,
1273 pdev
->subsystem_vendor
, pdev
->subsystem_device
);
1275 /* mutex initialization are all done here so we
1276 * can recall function without having locking issues */
1277 lockinit(&rdev
->ring_lock
, "drm__radeon_device__ring_lock", 0,
1279 lockinit(&rdev
->dc_hw_i2c_mutex
,
1280 "drm__radeon_device__dc_hw_i2c_mutex", 0, LK_CANRECURSE
);
1281 atomic_set(&rdev
->ih
.lock
, 0);
1282 lockinit(&rdev
->gem
.mutex
, "radeon_gemmtx", 0, LK_CANRECURSE
);
1283 lockinit(&rdev
->pm
.mutex
, "drm__radeon_device__pm__mutex", 0,
1286 lockinit(&rdev
->gpu_clock_mutex
, "radeon_clockmtx", 0, LK_CANRECURSE
);
1287 lockinit(&rdev
->srbm_mutex
, "radeon_srbm_mutex", 0, LK_CANRECURSE
);
1288 lockinit(&rdev
->pm
.mclk_lock
, "drm__radeon_device__pm__mclk_lock", 0,
1290 lockinit(&rdev
->exclusive_lock
, "drm__radeon_device__exclusive_lock",
1292 init_waitqueue_head(&rdev
->irq
.vblank_queue
);
1293 r
= radeon_gem_init(rdev
);
1297 radeon_check_arguments(rdev
);
1298 /* Adjust VM size here.
1299 * Max GPUVM size for cayman+ is 40 bits.
1301 rdev
->vm_manager
.max_pfn
= radeon_vm_size
<< 18;
1303 /* Set asic functions */
1304 r
= radeon_asic_init(rdev
);
1308 /* all of the newer IGP chips have an internal gart
1309 * However some rs4xx report as AGP, so remove that here.
1311 if ((rdev
->family
>= CHIP_RS400
) &&
1312 (rdev
->flags
& RADEON_IS_IGP
)) {
1313 rdev
->flags
&= ~RADEON_IS_AGP
;
1316 if (rdev
->flags
& RADEON_IS_AGP
&& radeon_agpmode
== -1) {
1317 radeon_agp_disable(rdev
);
1320 /* Set the internal MC address mask
1321 * This is the max address of the GPU's
1322 * internal address space.
1324 if (rdev
->family
>= CHIP_CAYMAN
)
1325 rdev
->mc
.mc_mask
= 0xffffffffffULL
; /* 40 bit MC */
1326 else if (rdev
->family
>= CHIP_CEDAR
)
1327 rdev
->mc
.mc_mask
= 0xfffffffffULL
; /* 36 bit MC */
1329 rdev
->mc
.mc_mask
= 0xffffffffULL
; /* 32 bit MC */
1331 /* set DMA mask + need_dma32 flags.
1332 * PCIE - can handle 40-bits.
1333 * IGP - can handle 40-bits
1334 * AGP - generally dma32 is safest
1335 * PCI - dma32 for legacy pci gart, 40 bits on newer asics
1337 rdev
->need_dma32
= false;
1338 if (rdev
->flags
& RADEON_IS_AGP
)
1339 rdev
->need_dma32
= true;
1340 if ((rdev
->flags
& RADEON_IS_PCI
) &&
1341 (rdev
->family
<= CHIP_RS740
))
1342 rdev
->need_dma32
= true;
1344 dma_bits
= rdev
->need_dma32
? 32 : 40;
1346 r
= pci_set_dma_mask(rdev
->pdev
, DMA_BIT_MASK(dma_bits
));
1348 rdev
->need_dma32
= true;
1350 printk(KERN_WARNING
"radeon: No suitable DMA available.\n");
1352 r
= pci_set_consistent_dma_mask(rdev
->pdev
, DMA_BIT_MASK(dma_bits
));
1354 pci_set_consistent_dma_mask(rdev
->pdev
, DMA_BIT_MASK(32));
1355 printk(KERN_WARNING
"radeon: No coherent DMA available.\n");
1357 #endif /* DUMBBELL_WIP */
1359 /* Registers mapping */
1360 /* TODO: block userspace mapping of io register */
1361 spin_init(&rdev
->mmio_idx_lock
, "radeon_mpio");
1362 spin_init(&rdev
->smc_idx_lock
, "radeon_smc");
1363 spin_init(&rdev
->pll_idx_lock
, "radeon_pll");
1364 spin_init(&rdev
->mc_idx_lock
, "radeon_mc");
1365 spin_init(&rdev
->pcie_idx_lock
, "radeon_pcie");
1366 spin_init(&rdev
->pciep_idx_lock
, "radeon_pciep");
1367 spin_init(&rdev
->pif_idx_lock
, "radeon_pif");
1368 spin_init(&rdev
->cg_idx_lock
, "radeon_cg");
1369 spin_init(&rdev
->uvd_idx_lock
, "radeon_uvd");
1370 spin_init(&rdev
->rcu_idx_lock
, "radeon_rcu");
1371 spin_init(&rdev
->didt_idx_lock
, "radeon_didt");
1372 spin_init(&rdev
->end_idx_lock
, "radeon_end");
1373 if (rdev
->family
>= CHIP_BONAIRE
) {
1374 rdev
->rmmio_rid
= PCIR_BAR(5);
1376 rdev
->rmmio_rid
= PCIR_BAR(2);
1378 rdev
->rmmio
= bus_alloc_resource_any(rdev
->dev
->bsddev
, SYS_RES_MEMORY
,
1379 &rdev
->rmmio_rid
, RF_ACTIVE
| RF_SHAREABLE
);
1380 if (rdev
->rmmio
== NULL
) {
1383 rdev
->rmmio_base
= rman_get_start(rdev
->rmmio
);
1384 rdev
->rmmio_size
= rman_get_size(rdev
->rmmio
);
1385 DRM_INFO("register mmio base: 0x%08X\n", (uint32_t)rdev
->rmmio_base
);
1386 DRM_INFO("register mmio size: %u\n", (unsigned)rdev
->rmmio_size
);
1388 /* doorbell bar mapping */
1389 if (rdev
->family
>= CHIP_BONAIRE
)
1390 radeon_doorbell_init(rdev
);
1392 /* io port mapping */
1393 for (i
= 0; i
< DRM_MAX_PCI_RESOURCE
; i
++) {
1396 data
= pci_read_config(rdev
->dev
->bsddev
, PCIR_BAR(i
), 4);
1397 if (PCI_BAR_IO(data
)) {
1398 rdev
->rio_rid
= PCIR_BAR(i
);
1399 rdev
->rio_mem
= bus_alloc_resource_any(rdev
->dev
->bsddev
,
1400 SYS_RES_IOPORT
, &rdev
->rio_rid
,
1401 RF_ACTIVE
| RF_SHAREABLE
);
1405 if (rdev
->rio_mem
== NULL
)
1406 DRM_ERROR("Unable to find PCI I/O BAR\n");
1408 rdev
->tq
= taskqueue_create("radeonkms", M_WAITOK
,
1409 taskqueue_thread_enqueue
, &rdev
->tq
);
1410 taskqueue_start_threads(&rdev
->tq
, 1, TDPRI_KERN_DAEMON
,
1411 -1, "radeon taskq");
1413 if (rdev
->flags
& RADEON_IS_PX
)
1414 radeon_device_handle_px_quirks(rdev
);
1417 /* if we have > 1 VGA cards, then disable the radeon VGA resources */
1418 /* this will fail for cards that aren't VGA class devices, just
1420 vga_client_register(rdev
->pdev
, rdev
, NULL
, radeon_vga_set_decode
);
1423 if (rdev
->flags
& RADEON_IS_PX
)
1425 vga_switcheroo_register_client(rdev
->pdev
, &radeon_switcheroo_ops
, runtime
);
1427 vga_switcheroo_init_domain_pm_ops(rdev
->dev
->bsddev
, &rdev
->vga_pm_domain
);
1429 #endif /* DUMBBELL_WIP */
1431 r
= radeon_init(rdev
);
1435 r
= radeon_gem_debugfs_init(rdev
);
1437 DRM_ERROR("registering gem debugfs failed (%d).\n", r
);
1440 if (rdev
->flags
& RADEON_IS_AGP
&& !rdev
->accel_working
) {
1441 /* Acceleration not working on AGP card try again
1442 * with fallback to PCI or PCIE GART
1444 radeon_asic_reset(rdev
);
1446 radeon_agp_disable(rdev
);
1447 r
= radeon_init(rdev
);
1452 r
= radeon_ib_ring_tests(rdev
);
1454 DRM_ERROR("ib ring test failed (%d).\n", r
);
1456 DRM_INFO("%s: Taking over the fictitious range 0x%jx-0x%jx\n",
1457 __func__
, (uintmax_t)rdev
->mc
.aper_base
,
1458 (uintmax_t)rdev
->mc
.aper_base
+ rdev
->mc
.visible_vram_size
);
1459 r
= vm_phys_fictitious_reg_range(
1461 rdev
->mc
.aper_base
+ rdev
->mc
.visible_vram_size
,
1462 VM_MEMATTR_WRITE_COMBINING
);
1464 DRM_ERROR("Failed to register fictitious range "
1465 "0x%jx-0x%jx (%d).\n", (uintmax_t)rdev
->mc
.aper_base
,
1466 (uintmax_t)rdev
->mc
.aper_base
+ rdev
->mc
.visible_vram_size
, r
);
1469 rdev
->fictitious_range_registered
= true;
1471 if ((radeon_testing
& 1)) {
1472 if (rdev
->accel_working
)
1473 radeon_test_moves(rdev
);
1475 DRM_INFO("radeon: acceleration disabled, skipping move tests\n");
1477 if ((radeon_testing
& 2)) {
1478 if (rdev
->accel_working
)
1479 radeon_test_syncing(rdev
);
1481 DRM_INFO("radeon: acceleration disabled, skipping sync tests\n");
1483 if (radeon_benchmarking
) {
1484 if (rdev
->accel_working
)
1485 radeon_benchmark(rdev
, radeon_benchmarking
);
1487 DRM_INFO("radeon: acceleration disabled, skipping benchmarks\n");
1494 vga_switcheroo_fini_domain_pm_ops(rdev
->dev
);
1500 static void radeon_debugfs_remove_files(struct radeon_device
*rdev
);
1501 #endif /* DUMBBELL_WIP */
1504 * radeon_device_fini - tear down the driver
1506 * @rdev: radeon_device pointer
1508 * Tear down the driver info (all asics).
1509 * Called at driver shutdown.
1511 void radeon_device_fini(struct radeon_device
*rdev
)
1513 DRM_INFO("radeon: finishing device.\n");
1514 rdev
->shutdown
= true;
1515 /* evict vram memory */
1516 radeon_bo_evict_vram(rdev
);
1518 if (rdev
->fictitious_range_registered
) {
1519 vm_phys_fictitious_unreg_range(
1521 rdev
->mc
.aper_base
+ rdev
->mc
.visible_vram_size
);
1526 vga_switcheroo_unregister_client(rdev
->pdev
);
1527 if (rdev
->flags
& RADEON_IS_PX
)
1528 vga_switcheroo_fini_domain_pm_ops(rdev
->dev
);
1529 vga_client_register(rdev
->pdev
, NULL
, NULL
, NULL
);
1530 #endif /* DUMBBELL_WIP */
1532 if (rdev
->tq
!= NULL
) {
1533 taskqueue_free(rdev
->tq
);
1538 bus_release_resource(rdev
->dev
->bsddev
, SYS_RES_IOPORT
, rdev
->rio_rid
,
1540 rdev
->rio_mem
= NULL
;
1541 bus_release_resource(rdev
->dev
->bsddev
, SYS_RES_MEMORY
, rdev
->rmmio_rid
,
1544 if (rdev
->family
>= CHIP_BONAIRE
)
1545 radeon_doorbell_fini(rdev
);
1547 radeon_debugfs_remove_files(rdev
);
1548 #endif /* DUMBBELL_WIP */
1556 * radeon_suspend_kms - initiate device suspend
1558 * @pdev: drm dev pointer
1559 * @state: suspend state
1561 * Puts the hw in the suspend state (all asics).
1562 * Returns 0 for success or an error on failure.
1563 * Called at driver suspend.
1565 int radeon_suspend_kms(struct drm_device
*dev
, bool suspend
, bool fbcon
)
1567 struct radeon_device
*rdev
;
1568 struct drm_crtc
*crtc
;
1569 struct drm_connector
*connector
;
1572 if (dev
== NULL
|| dev
->dev_private
== NULL
) {
1576 rdev
= dev
->dev_private
;
1578 if (dev
->switch_power_state
== DRM_SWITCH_POWER_OFF
)
1581 drm_kms_helper_poll_disable(dev
);
1583 /* turn off display hw */
1584 list_for_each_entry(connector
, &dev
->mode_config
.connector_list
, head
) {
1585 drm_helper_connector_dpms(connector
, DRM_MODE_DPMS_OFF
);
1588 /* unpin the front buffers */
1589 list_for_each_entry(crtc
, &dev
->mode_config
.crtc_list
, head
) {
1590 struct radeon_framebuffer
*rfb
= to_radeon_framebuffer(crtc
->primary
->fb
);
1591 struct radeon_bo
*robj
;
1593 if (rfb
== NULL
|| rfb
->obj
== NULL
) {
1596 robj
= gem_to_radeon_bo(rfb
->obj
);
1597 /* don't unpin kernel fb objects */
1598 if (!radeon_fbdev_robj_is_fb(rdev
, robj
)) {
1599 r
= radeon_bo_reserve(robj
, false);
1601 radeon_bo_unpin(robj
);
1602 radeon_bo_unreserve(robj
);
1606 /* evict vram memory */
1607 radeon_bo_evict_vram(rdev
);
1609 /* wait for gpu to finish processing current batch */
1610 for (i
= 0; i
< RADEON_NUM_RINGS
; i
++) {
1611 r
= radeon_fence_wait_empty(rdev
, i
);
1613 /* delay GPU reset to resume */
1614 radeon_fence_driver_force_completion(rdev
, i
);
1618 radeon_save_bios_scratch_regs(rdev
);
1620 radeon_suspend(rdev
);
1621 radeon_hpd_fini(rdev
);
1622 /* evict remaining vram memory */
1623 radeon_bo_evict_vram(rdev
);
1625 radeon_agp_suspend(rdev
);
1627 pci_save_state(device_get_parent(rdev
->dev
->bsddev
));
1630 /* Shut down the device */
1631 pci_disable_device(dev
->pdev
);
1632 #endif /* DUMBBELL_WIP */
1633 pci_set_powerstate(dev
->dev
->bsddev
, PCI_POWERSTATE_D3
);
1640 #endif /* DUMBBELL_WIP */
1641 radeon_fbdev_set_suspend(rdev
, 1);
1644 #endif /* DUMBBELL_WIP */
1650 * radeon_resume_kms - initiate device resume
1652 * @pdev: drm dev pointer
1654 * Bring the hw back to operating state (all asics).
1655 * Returns 0 for success or an error on failure.
1656 * Called at driver resume.
1658 int radeon_resume_kms(struct drm_device
*dev
, bool resume
, bool fbcon
)
1660 struct drm_connector
*connector
;
1661 struct radeon_device
*rdev
= dev
->dev_private
;
1664 if (dev
->switch_power_state
== DRM_SWITCH_POWER_OFF
)
1671 #endif /* DUMBBELL_WIP */
1673 pci_set_powerstate(dev
->dev
->bsddev
, PCI_POWERSTATE_D0
);
1674 pci_restore_state(device_get_parent(rdev
->dev
->bsddev
));
1676 if (pci_enable_device(dev
->pdev
)) {
1681 #endif /* DUMBBELL_WIP */
1683 /* resume AGP if in use */
1684 radeon_agp_resume(rdev
);
1685 radeon_resume(rdev
);
1687 r
= radeon_ib_ring_tests(rdev
);
1689 DRM_ERROR("ib ring test failed (%d).\n", r
);
1691 if ((rdev
->pm
.pm_method
== PM_METHOD_DPM
) && rdev
->pm
.dpm_enabled
) {
1692 /* do dpm late init */
1693 r
= radeon_pm_late_init(rdev
);
1695 rdev
->pm
.dpm_enabled
= false;
1696 DRM_ERROR("radeon_pm_late_init failed, disabling dpm\n");
1699 /* resume old pm late */
1700 radeon_pm_resume(rdev
);
1703 radeon_restore_bios_scratch_regs(rdev
);
1705 /* init dig PHYs, disp eng pll */
1706 if (rdev
->is_atom_bios
) {
1707 radeon_atom_encoder_init(rdev
);
1708 radeon_atom_disp_eng_pll_init(rdev
);
1709 /* turn on the BL */
1710 if (rdev
->mode_info
.bl_encoder
) {
1711 u8 bl_level
= radeon_get_backlight_level(rdev
,
1712 rdev
->mode_info
.bl_encoder
);
1713 radeon_set_backlight_level(rdev
, rdev
->mode_info
.bl_encoder
,
1717 /* reset hpd state */
1718 radeon_hpd_init(rdev
);
1719 /* blat the mode back in */
1721 drm_helper_resume_force_mode(dev
);
1722 /* turn on display hw */
1723 list_for_each_entry(connector
, &dev
->mode_config
.connector_list
, head
) {
1724 drm_helper_connector_dpms(connector
, DRM_MODE_DPMS_ON
);
1728 drm_kms_helper_poll_enable(dev
);
1730 /* set the power state here in case we are a PX system or headless */
1731 if ((rdev
->pm
.pm_method
== PM_METHOD_DPM
) && rdev
->pm
.dpm_enabled
)
1732 radeon_pm_compute_clocks(rdev
);
1735 radeon_fbdev_set_suspend(rdev
, 0);
1738 #endif /* DUMBBELL_WIP */
1745 * radeon_gpu_reset - reset the asic
1747 * @rdev: radeon device pointer
1749 * Attempt the reset the GPU if it has hung (all asics).
1750 * Returns 0 for success or an error on failure.
1752 int radeon_gpu_reset(struct radeon_device
*rdev
)
1754 unsigned ring_sizes
[RADEON_NUM_RINGS
];
1755 uint32_t *ring_data
[RADEON_NUM_RINGS
];
1762 lockmgr(&rdev
->exclusive_lock
, LK_EXCLUSIVE
);
1764 if (!rdev
->needs_reset
) {
1765 lockmgr(&rdev
->exclusive_lock
, LK_RELEASE
);
1769 radeon_save_bios_scratch_regs(rdev
);
1771 resched
= ttm_bo_lock_delayed_workqueue(&rdev
->mman
.bdev
);
1772 radeon_suspend(rdev
);
1773 radeon_hpd_fini(rdev
);
1775 for (i
= 0; i
< RADEON_NUM_RINGS
; ++i
) {
1776 ring_sizes
[i
] = radeon_ring_backup(rdev
, &rdev
->ring
[i
],
1778 if (ring_sizes
[i
]) {
1780 dev_info(rdev
->dev
, "Saved %d dwords of commands "
1781 "on ring %d.\n", ring_sizes
[i
], i
);
1785 r
= radeon_asic_reset(rdev
);
1787 dev_info(rdev
->dev
, "GPU reset succeeded, trying to resume\n");
1788 radeon_resume(rdev
);
1791 radeon_restore_bios_scratch_regs(rdev
);
1793 for (i
= 0; i
< RADEON_NUM_RINGS
; ++i
) {
1794 if (!r
&& ring_data
[i
]) {
1795 radeon_ring_restore(rdev
, &rdev
->ring
[i
],
1796 ring_sizes
[i
], ring_data
[i
]);
1798 radeon_fence_driver_force_completion(rdev
, i
);
1799 kfree(ring_data
[i
]);
1803 if ((rdev
->pm
.pm_method
== PM_METHOD_DPM
) && rdev
->pm
.dpm_enabled
) {
1804 /* do dpm late init */
1805 r
= radeon_pm_late_init(rdev
);
1807 rdev
->pm
.dpm_enabled
= false;
1808 DRM_ERROR("radeon_pm_late_init failed, disabling dpm\n");
1811 /* resume old pm late */
1812 radeon_pm_resume(rdev
);
1815 /* init dig PHYs, disp eng pll */
1816 if (rdev
->is_atom_bios
) {
1817 radeon_atom_encoder_init(rdev
);
1818 radeon_atom_disp_eng_pll_init(rdev
);
1819 /* turn on the BL */
1820 if (rdev
->mode_info
.bl_encoder
) {
1821 u8 bl_level
= radeon_get_backlight_level(rdev
,
1822 rdev
->mode_info
.bl_encoder
);
1823 radeon_set_backlight_level(rdev
, rdev
->mode_info
.bl_encoder
,
1827 /* reset hpd state */
1828 radeon_hpd_init(rdev
);
1830 ttm_bo_unlock_delayed_workqueue(&rdev
->mman
.bdev
, resched
);
1832 rdev
->in_reset
= true;
1833 rdev
->needs_reset
= false;
1836 downgrade_write(&rdev
->exclusive_lock
);
1839 drm_helper_resume_force_mode(rdev
->ddev
);
1841 /* set the power state here in case we are a PX system or headless */
1842 if ((rdev
->pm
.pm_method
== PM_METHOD_DPM
) && rdev
->pm
.dpm_enabled
)
1843 radeon_pm_compute_clocks(rdev
);
1846 r
= radeon_ib_ring_tests(rdev
);
1850 /* bad news, how to tell it to userspace ? */
1851 dev_info(rdev
->dev
, "GPU reset failed\n");
1854 rdev
->needs_reset
= r
== -EAGAIN
;
1855 rdev
->in_reset
= false;
1857 lockmgr(&rdev
->exclusive_lock
, LK_RELEASE
);
1866 int radeon_debugfs_add_files(struct radeon_device
*rdev
,
1867 struct drm_info_list
*files
,
1872 for (i
= 0; i
< rdev
->debugfs_count
; i
++) {
1873 if (rdev
->debugfs
[i
].files
== files
) {
1874 /* Already registered */
1879 i
= rdev
->debugfs_count
+ 1;
1880 if (i
> RADEON_DEBUGFS_MAX_COMPONENTS
) {
1881 DRM_ERROR("Reached maximum number of debugfs components.\n");
1882 DRM_ERROR("Report so we increase "
1883 "RADEON_DEBUGFS_MAX_COMPONENTS.\n");
1886 rdev
->debugfs
[rdev
->debugfs_count
].files
= files
;
1887 rdev
->debugfs
[rdev
->debugfs_count
].num_files
= nfiles
;
1888 rdev
->debugfs_count
= i
;
1889 #if defined(CONFIG_DEBUG_FS)
1890 drm_debugfs_create_files(files
, nfiles
,
1891 rdev
->ddev
->control
->debugfs_root
,
1892 rdev
->ddev
->control
);
1893 drm_debugfs_create_files(files
, nfiles
,
1894 rdev
->ddev
->primary
->debugfs_root
,
1895 rdev
->ddev
->primary
);
1900 static void radeon_debugfs_remove_files(struct radeon_device
*rdev
)
1902 #if defined(CONFIG_DEBUG_FS)
1905 for (i
= 0; i
< rdev
->debugfs_count
; i
++) {
1906 drm_debugfs_remove_files(rdev
->debugfs
[i
].files
,
1907 rdev
->debugfs
[i
].num_files
,
1908 rdev
->ddev
->control
);
1909 drm_debugfs_remove_files(rdev
->debugfs
[i
].files
,
1910 rdev
->debugfs
[i
].num_files
,
1911 rdev
->ddev
->primary
);
1916 #if defined(CONFIG_DEBUG_FS)
1917 int radeon_debugfs_init(struct drm_minor
*minor
)
1922 void radeon_debugfs_cleanup(struct drm_minor
*minor
)
1926 #endif /* DUMBBELL_WIP */