sys/dev/raid/dpt/dpt_pci.c

   1 /*-
   2  * Copyright (c) 2000 Matthew N. Dodd <winter@jurai.net>
   3  * All rights reserved.
   4  *
   5  * Copyright (c) 1997 Simon Shapiro
   6  * All Rights Reserved
   7  *
   8  * Redistribution and use in source and binary forms, with or without
   9  * modification, are permitted provided that the following conditions
  10  * are met:
  11  * 1. Redistributions of source code must retain the above copyright
  12  *    notice, this list of conditions and the following disclaimer.
  13  * 2. Redistributions in binary form must reproduce the above copyright
  14  *    notice, this list of conditions and the following disclaimer in the
  15  *    documentation and/or other materials provided with the distribution.
  16  *
  17  * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
  18  * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
  19  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
  20  * ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
  21  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
  22  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
  23  * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
  24  * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
  25  * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
  26  * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
  27  * SUCH DAMAGE.
  28  *
  29  *      $FreeBSD: src/sys/dev/dpt/dpt_pci.c,v 1.17.2.2 2000/08/26 22:21:21 peter Exp $
  30  *      $DragonFly: src/sys/dev/raid/dpt/dpt_pci.c,v 1.7 2006/10/25 20:56:01 dillon Exp $
  31  */
  32
  33 #include <sys/param.h>
  34 #include <sys/systm.h>
  35 #include <sys/kernel.h>
  36 #include <sys/module.h>
  37 #include <sys/bus.h>
  38 #include <sys/rman.h>
  39 #include <sys/thread2.h>
  40
  41 #include <bus/pci/pcireg.h>
  42 #include <bus/pci/pcivar.h>
  43
  44 #include <bus/cam/scsi/scsi_all.h>
  45
  46 #include "dpt.h"
  47
  48 #define DPT_VENDOR_ID           0x1044
  49 #define DPT_DEVICE_ID           0xa400
  50
  51 #define DPT_PCI_IOADDR          PCIR_MAPS               /* I/O Address */
  52 #define DPT_PCI_MEMADDR         (PCIR_MAPS + 4)         /* Mem I/O Address */
  53
  54 #define ISA_PRIMARY_WD_ADDRESS  0x1f8
  55
  56 static int      dpt_pci_probe   (device_t);
  57 static int      dpt_pci_attach  (device_t);
  58
  59 static int
  60 dpt_pci_probe (device_t dev)
  61 {
  62         if ((pci_get_vendor(dev) == DPT_VENDOR_ID) &&
  63             (pci_get_device(dev) == DPT_DEVICE_ID)) {
  64                 device_set_desc(dev, "DPT Caching SCSI RAID Controller");
  65                 return (0);
  66         }
  67         return (ENXIO);
  68 }
  69
  70 static int
  71 dpt_pci_attach (device_t dev)
  72 {
  73         dpt_softc_t *   dpt;
  74         struct resource *io = 0;
  75         struct resource *irq = 0;
  76         int             rid;
  77         void *          ih;
  78         int             error = 0;
  79
  80         int             iotype = 0;
  81         u_int32_t       command;
  82
  83         command = pci_read_config(dev, PCIR_COMMAND, /*bytes*/1);
  84
  85 #ifdef DPT_ALLOW_MMIO
  86         if ((command & PCIM_CMD_MEMEN) != 0) {
  87                 rid = DPT_PCI_MEMADDR;
  88                 iotype = SYS_RES_MEMORY;
  89                 io = bus_alloc_resource(dev, iotype, &rid, 0, ~0, 1, RF_ACTIVE);
  90         }
  91 #endif
  92         if (io == NULL && (command &  PCIM_CMD_PORTEN) != 0) {
  93                 rid = DPT_PCI_IOADDR;
  94                 iotype = SYS_RES_IOPORT;
  95                 io = bus_alloc_resource(dev, iotype, &rid, 0, ~0, 1, RF_ACTIVE);
  96         }
  97
  98         if (io == NULL) {
  99                 device_printf(dev, "can't allocate register resources\n");
 100                 error = ENOMEM;
 101                 goto bad;
 102         }
 103
 104         rid = 0;
 105         irq = bus_alloc_resource(dev, SYS_RES_IRQ, &rid, 0, ~0, 1,
 106                                  RF_ACTIVE | RF_SHAREABLE);
 107         if (!irq) {
 108                 device_printf(dev, "No irq?!\n");
 109                 error = ENOMEM;
 110                 goto bad;
 111         }
 112
 113         /* Ensure busmastering is enabled */
 114         command |= PCIM_CMD_BUSMASTEREN;
 115         pci_write_config(dev, PCIR_COMMAND, command, /*bytes*/1);
 116
 117         if (rman_get_start(io) == (ISA_PRIMARY_WD_ADDRESS - 0x10)) {
 118 #ifdef DPT_DEBUG_WARN
 119                 device_printf(dev, "Mapped as an IDE controller.  "
 120                                    "Disabling SCSI setup\n");
 121 #endif
 122                 error = ENXIO;
 123                 goto bad;
 124         }
 125
 126         /* Device registers are offset 0x10 into the register window.  FEH */
 127         dpt = dpt_alloc(dev, rman_get_bustag(io), rman_get_bushandle(io) + 0x10);
 128         if (dpt == NULL) {
 129                 error = ENXIO;
 130                 goto bad;
 131         }
 132
 133         /* Allocate a dmatag representing the capabilities of this attachment */
 134         /* XXX Should be a child of the PCI bus dma tag */
 135         if (bus_dma_tag_create( /* parent    */ NULL,
 136                                 /* alignemnt */ 1,
 137                                 /* boundary  */ 0,
 138                                 /* lowaddr   */ BUS_SPACE_MAXADDR_32BIT,
 139                                 /* highaddr  */ BUS_SPACE_MAXADDR,
 140                                 /* filter    */ NULL,
 141                                 /* filterarg */ NULL,
 142                                 /* maxsize   */ BUS_SPACE_MAXSIZE_32BIT,
 143                                 /* nsegments */ BUS_SPACE_UNRESTRICTED,
 144                                 /* maxsegsz  */ BUS_SPACE_MAXSIZE_32BIT,
 145                                 /* flags     */ 0,
 146                                 &dpt->parent_dmat) != 0) {
 147                 dpt_free(dpt);
 148                 error = ENXIO;
 149                 goto bad;
 150         }
 151
 152         crit_enter();
 153
 154         if (dpt_init(dpt) != 0) {
 155                 dpt_free(dpt);
 156                 error = ENXIO;
 157                 goto bad;
 158         }
 159
 160         /* Register with the XPT */
 161         dpt_attach(dpt);
 162
 163         crit_exit();
 164
 165         error = bus_setup_intr(dev, irq, 0, dpt_intr, dpt,
 166                                &ih, NULL);
 167         if (error) {
 168                 device_printf(dev, "Unable to register interrupt handler\n");
 169                 error = ENXIO;
 170                 goto bad;
 171         }
 172
 173         return (error);
 174
 175 bad:
 176         if (io)
 177                 bus_release_resource(dev, iotype, 0, io);
 178         if (irq)
 179                 bus_release_resource(dev, SYS_RES_IRQ, 0, irq);
 180
 181         return (error);
 182 }
 183
 184 static device_method_t dpt_pci_methods[] = {
 185         /* Device interface */
 186         DEVMETHOD(device_probe,         dpt_pci_probe),
 187         DEVMETHOD(device_attach,        dpt_pci_attach),
 188
 189         { 0, 0 }
 190 };
 191
 192 static driver_t dpt_pci_driver = {
 193         "dpt",
 194         dpt_pci_methods,
 195         sizeof(dpt_softc_t),
 196 };
 197
 198 static devclass_t dpt_devclass;
 199
 200 DRIVER_MODULE(dpt, pci, dpt_pci_driver, dpt_devclass, 0, 0);