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For rt2661 part:
[dragonfly.git] / sys / dev / netif / ral / rt2661.c
blob29777e028bb44ba92e8eefb8370b575c1e980085
1 /*
2 * Copyright (c) 2006
3 * Damien Bergamini <damien.bergamini@free.fr>
4 *
5 * Permission to use, copy, modify, and distribute this software for any
6 * purpose with or without fee is hereby granted, provided that the above
7 * copyright notice and this permission notice appear in all copies.
8 *
9 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
10 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
11 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
12 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
13 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
14 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
15 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
16 *
17 * $FreeBSD: src/sys/dev/ral/rt2661.c,v 1.4 2006/03/21 21:15:43 damien Exp $
18 * $DragonFly: src/sys/dev/netif/ral/rt2661.c,v 1.11 2007/02/06 12:46:09 sephe Exp $
19 */
20
21 /*
22 * Ralink Technology RT2561, RT2561S and RT2661 chipset driver
23 * http://www.ralinktech.com/
24 */
25
26 #include <sys/param.h>
27 #include <sys/bus.h>
28 #include <sys/endian.h>
29 #include <sys/kernel.h>
30 #include <sys/malloc.h>
31 #include <sys/mbuf.h>
32 #include <sys/module.h>
33 #include <sys/queue.h>
34 #include <sys/rman.h>
35 #include <sys/socket.h>
36 #include <sys/sockio.h>
37 #include <sys/sysctl.h>
38 #include <sys/serialize.h>
39
40 #include <net/bpf.h>
41 #include <net/if.h>
42 #include <net/if_arp.h>
43 #include <net/ethernet.h>
44 #include <net/if_dl.h>
45 #include <net/if_media.h>
46 #include <net/ifq_var.h>
47
48 #include <netproto/802_11/ieee80211_var.h>
49 #include <netproto/802_11/ieee80211_radiotap.h>
50
51 #include <dev/netif/ral/if_ralrate.h>
52 #include <dev/netif/ral/rt2661reg.h>
53 #include <dev/netif/ral/rt2661var.h>
54 #include <dev/netif/ral/rt2661_ucode.h>
55
56 #ifdef RAL_DEBUG
57 #define DPRINTF(x) do { if (ral_debug > 0) kprintf x; } while (0)
58 #define DPRINTFN(n, x) do { if (ral_debug >= (n)) kprintf x; } while (0)
59 int ral_debug = 1;
60 SYSCTL_INT(_debug, OID_AUTO, ral, CTLFLAG_RW, &ral_debug, 0, "ral debug level");
61 #else
62 #define DPRINTF(x)
63 #define DPRINTFN(n, x)
64 #endif
65
66 MALLOC_DEFINE(M_RT2661, "rt2661_ratectl", "rt2661 rate control data");
67
68 static void rt2661_dma_map_addr(void *, bus_dma_segment_t *, int,
69 int);
70 static void rt2661_dma_map_mbuf(void *, bus_dma_segment_t *, int,
71 bus_size_t, int);
72 static int rt2661_alloc_tx_ring(struct rt2661_softc *,
73 struct rt2661_tx_ring *, int);
74 static void rt2661_reset_tx_ring(struct rt2661_softc *,
75 struct rt2661_tx_ring *);
76 static void rt2661_free_tx_ring(struct rt2661_softc *,
77 struct rt2661_tx_ring *);
78 static int rt2661_alloc_rx_ring(struct rt2661_softc *,
79 struct rt2661_rx_ring *, int);
80 static void rt2661_reset_rx_ring(struct rt2661_softc *,
81 struct rt2661_rx_ring *);
82 static void rt2661_free_rx_ring(struct rt2661_softc *,
83 struct rt2661_rx_ring *);
84 static struct ieee80211_node *rt2661_node_alloc(
85 struct ieee80211_node_table *);
86 static int rt2661_media_change(struct ifnet *);
87 static void rt2661_next_scan(void *);
88 static int rt2661_newstate(struct ieee80211com *,
89 enum ieee80211_state, int);
90 static uint16_t rt2661_eeprom_read(struct rt2661_softc *, uint8_t);
91 static void rt2661_rx_intr(struct rt2661_softc *);
92 static void rt2661_tx_intr(struct rt2661_softc *);
93 static void rt2661_tx_dma_intr(struct rt2661_softc *,
94 struct rt2661_tx_ring *);
95 static void rt2661_mcu_beacon_expire(struct rt2661_softc *);
96 static void rt2661_mcu_wakeup(struct rt2661_softc *);
97 static void rt2661_mcu_cmd_intr(struct rt2661_softc *);
98 static int rt2661_ack_rate(struct ieee80211com *, int);
99 static uint16_t rt2661_txtime(int, int, uint32_t);
100 static uint8_t rt2661_rxrate(struct rt2661_rx_desc *);
101 static uint8_t rt2661_plcp_signal(int);
102 static void rt2661_setup_tx_desc(struct rt2661_softc *,
103 struct rt2661_tx_desc *, uint32_t, uint16_t, int,
104 int, const bus_dma_segment_t *, int, int, int);
105 static struct mbuf * rt2661_get_rts(struct rt2661_softc *,
106 struct ieee80211_frame *, uint16_t);
107 static int rt2661_tx_data(struct rt2661_softc *, struct mbuf *,
108 struct ieee80211_node *, int);
109 static int rt2661_tx_mgt(struct rt2661_softc *, struct mbuf *,
110 struct ieee80211_node *);
111 static void rt2661_start(struct ifnet *);
112 static void rt2661_watchdog(struct ifnet *);
113 static int rt2661_reset(struct ifnet *);
114 static int rt2661_ioctl(struct ifnet *, u_long, caddr_t,
115 struct ucred *);
116 static void rt2661_bbp_write(struct rt2661_softc *, uint8_t,
117 uint8_t);
118 static uint8_t rt2661_bbp_read(struct rt2661_softc *, uint8_t);
119 static void rt2661_rf_write(struct rt2661_softc *, uint8_t,
120 uint32_t);
121 static int rt2661_tx_cmd(struct rt2661_softc *, uint8_t,
122 uint16_t);
123 static void rt2661_select_antenna(struct rt2661_softc *);
124 static void rt2661_enable_mrr(struct rt2661_softc *);
125 static void rt2661_set_txpreamble(struct rt2661_softc *);
126 static void rt2661_set_basicrates(struct rt2661_softc *,
127 const struct ieee80211_rateset *);
128 static void rt2661_select_band(struct rt2661_softc *,
129 struct ieee80211_channel *);
130 static void rt2661_set_chan(struct rt2661_softc *,
131 struct ieee80211_channel *);
132 static void rt2661_set_bssid(struct rt2661_softc *,
133 const uint8_t *);
134 static void rt2661_set_macaddr(struct rt2661_softc *,
135 const uint8_t *);
136 static void rt2661_update_promisc(struct rt2661_softc *);
137 static int rt2661_wme_update(struct ieee80211com *) __unused;
138 static void rt2661_update_slot(struct ifnet *);
139 static const char *rt2661_get_rf(int);
140 static void rt2661_read_eeprom(struct rt2661_softc *);
141 static int rt2661_bbp_init(struct rt2661_softc *);
142 static void rt2661_init(void *);
143 static void rt2661_stop(void *);
144 static void rt2661_intr(void *);
145 static int rt2661_load_microcode(struct rt2661_softc *,
146 const uint8_t *, int);
147 #ifdef notyet
148 static void rt2661_rx_tune(struct rt2661_softc *);
149 static void rt2661_radar_start(struct rt2661_softc *);
150 static int rt2661_radar_stop(struct rt2661_softc *);
151 #endif
152 static int rt2661_prepare_beacon(struct rt2661_softc *);
153 static void rt2661_enable_tsf_sync(struct rt2661_softc *);
154 static int rt2661_get_rssi(struct rt2661_softc *, uint8_t);
155 static void rt2661_led_newstate(struct rt2661_softc *,
156 enum ieee80211_state);
157
158 /*
159 * Supported rates for 802.11a/b/g modes (in 500Kbps unit).
160 */
161 static const struct ieee80211_rateset rt2661_rateset_11a =
162 { 8, { 12, 18, 24, 36, 48, 72, 96, 108 } };
163
164 static const struct ieee80211_rateset rt2661_rateset_11b =
165 { 4, { 2, 4, 11, 22 } };
166
167 static const struct ieee80211_rateset rt2661_rateset_11g =
168 { 12, { 2, 4, 11, 22, 12, 18, 24, 36, 48, 72, 96, 108 } };
169
170 static const struct {
171 uint32_t reg;
172 uint32_t val;
173 } rt2661_def_mac[] = {
174 RT2661_DEF_MAC
175 };
176
177 static const struct {
178 uint8_t reg;
179 uint8_t val;
180 } rt2661_def_bbp[] = {
181 RT2661_DEF_BBP
182 };
183
184 static const struct rfprog {
185 uint8_t chan;
186 uint32_t r1, r2, r3, r4;
187 } rt2661_rf5225_1[] = {
188 RT2661_RF5225_1
189 }, rt2661_rf5225_2[] = {
190 RT2661_RF5225_2
191 };
192
193 #define LED_EE2MCU(bit) { \
194 .ee_bit = RT2661_EE_LED_##bit, \
195 .mcu_bit = RT2661_MCU_LED_##bit \
196 }
197 static const struct {
198 uint16_t ee_bit;
199 uint16_t mcu_bit;
200 } led_ee2mcu[] = {
201 LED_EE2MCU(RDYG),
202 LED_EE2MCU(RDYA),
203 LED_EE2MCU(ACT),
204 LED_EE2MCU(GPIO0),
205 LED_EE2MCU(GPIO1),
206 LED_EE2MCU(GPIO2),
207 LED_EE2MCU(GPIO3),
208 LED_EE2MCU(GPIO4)
209 };
210 #undef LED_EE2MCU
211
212 struct rt2661_dmamap {
213 bus_dma_segment_t segs[RT2661_MAX_SCATTER];
214 int nseg;
215 };
216
217 int
218 rt2661_attach(device_t dev, int id)
219 {
220 struct rt2661_softc *sc = device_get_softc(dev);
221 struct ieee80211com *ic = &sc->sc_ic;
222 struct ifnet *ifp = &ic->ic_if;
223 uint32_t val;
224 const uint8_t *ucode = NULL;
225 int error, i, ac, ntries, size = 0;
226
227 callout_init(&sc->scan_ch);
228 callout_init(&sc->rssadapt_ch);
229
230 sc->sc_irq_rid = 0;
231 sc->sc_irq = bus_alloc_resource_any(dev, SYS_RES_IRQ, &sc->sc_irq_rid,
232 RF_ACTIVE | RF_SHAREABLE);
233 if (sc->sc_irq == NULL) {
234 device_printf(dev, "could not allocate interrupt resource\n");
235 return ENXIO;
236 }
237
238 /* wait for NIC to initialize */
239 for (ntries = 0; ntries < 1000; ntries++) {
240 if ((val = RAL_READ(sc, RT2661_MAC_CSR0)) != 0)
241 break;
242 DELAY(1000);
243 }
244 if (ntries == 1000) {
245 device_printf(sc->sc_dev,
246 "timeout waiting for NIC to initialize\n");
247 error = EIO;
248 goto fail;
249 }
250
251 /* retrieve RF rev. no and various other things from EEPROM */
252 rt2661_read_eeprom(sc);
253
254 device_printf(dev, "MAC/BBP RT%X, RF %s\n", val,
255 rt2661_get_rf(sc->rf_rev));
256
257 /*
258 * Load 8051 microcode into NIC.
259 */
260 switch (id) {
261 case 0x0301:
262 ucode = rt2561s_ucode;
263 size = sizeof rt2561s_ucode;
264 break;
265 case 0x0302:
266 ucode = rt2561_ucode;
267 size = sizeof rt2561_ucode;
268 break;
269 case 0x0401:
270 ucode = rt2661_ucode;
271 size = sizeof rt2661_ucode;
272 break;
273 }
274
275 error = rt2661_load_microcode(sc, ucode, size);
276 if (error != 0) {
277 device_printf(sc->sc_dev, "could not load 8051 microcode\n");
278 goto fail;
279 }
280
281 /*
282 * Allocate Tx and Rx rings.
283 */
284 for (ac = 0; ac < 4; ac++) {
285 error = rt2661_alloc_tx_ring(sc, &sc->txq[ac],
286 RT2661_TX_RING_COUNT);
287 if (error != 0) {
288 device_printf(sc->sc_dev,
289 "could not allocate Tx ring %d\n", ac);
290 goto fail;
291 }
292 }
293
294 error = rt2661_alloc_tx_ring(sc, &sc->mgtq, RT2661_MGT_RING_COUNT);
295 if (error != 0) {
296 device_printf(sc->sc_dev, "could not allocate Mgt ring\n");
297 goto fail;
298 }
299
300 error = rt2661_alloc_rx_ring(sc, &sc->rxq, RT2661_RX_RING_COUNT);
301 if (error != 0) {
302 device_printf(sc->sc_dev, "could not allocate Rx ring\n");
303 goto fail;
304 }
305
306 STAILQ_INIT(&sc->tx_ratectl);
307
308 sysctl_ctx_init(&sc->sysctl_ctx);
309 sc->sysctl_tree = SYSCTL_ADD_NODE(&sc->sysctl_ctx,
310 SYSCTL_STATIC_CHILDREN(_hw),
311 OID_AUTO,
312 device_get_nameunit(dev),
313 CTLFLAG_RD, 0, "");
314 if (sc->sysctl_tree == NULL) {
315 device_printf(dev, "could not add sysctl node\n");
316 error = ENXIO;
317 goto fail;
318 }
319
320 ifp->if_softc = sc;
321 if_initname(ifp, device_get_name(dev), device_get_unit(dev));
322 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST;
323 ifp->if_init = rt2661_init;
324 ifp->if_ioctl = rt2661_ioctl;
325 ifp->if_start = rt2661_start;
326 ifp->if_watchdog = rt2661_watchdog;
327 ifq_set_maxlen(&ifp->if_snd, IFQ_MAXLEN);
328 ifq_set_ready(&ifp->if_snd);
329
330 ic->ic_phytype = IEEE80211_T_OFDM; /* not only, but not used */
331 ic->ic_opmode = IEEE80211_M_STA; /* default to BSS mode */
332 ic->ic_state = IEEE80211_S_INIT;
333 rt2661_led_newstate(sc, IEEE80211_S_INIT);
334
335 /* set device capabilities */
336 ic->ic_caps =
337 IEEE80211_C_IBSS | /* IBSS mode supported */
338 IEEE80211_C_MONITOR | /* monitor mode supported */
339 IEEE80211_C_HOSTAP | /* HostAp mode supported */
340 IEEE80211_C_TXPMGT | /* tx power management */
341 IEEE80211_C_SHPREAMBLE | /* short preamble supported */
342 IEEE80211_C_SHSLOT | /* short slot time supported */
343 #ifdef notyet
344 IEEE80211_C_WME | /* 802.11e */
345 #endif
346 IEEE80211_C_WEP | /* WEP */
347 IEEE80211_C_WPA; /* 802.11i */
348
349 if (sc->rf_rev == RT2661_RF_5225 || sc->rf_rev == RT2661_RF_5325) {
350 /* set supported .11a rates */
351 ic->ic_sup_rates[IEEE80211_MODE_11A] = rt2661_rateset_11a;
352
353 /* set supported .11a channels */
354 for (i = 36; i <= 64; i += 4) {
355 ic->ic_channels[i].ic_freq =
356 ieee80211_ieee2mhz(i, IEEE80211_CHAN_5GHZ);
357 ic->ic_channels[i].ic_flags = IEEE80211_CHAN_A;
358 }
359 for (i = 100; i <= 140; i += 4) {
360 ic->ic_channels[i].ic_freq =
361 ieee80211_ieee2mhz(i, IEEE80211_CHAN_5GHZ);
362 ic->ic_channels[i].ic_flags = IEEE80211_CHAN_A;
363 }
364 for (i = 149; i <= 165; i += 4) {
365 ic->ic_channels[i].ic_freq =
366 ieee80211_ieee2mhz(i, IEEE80211_CHAN_5GHZ);
367 ic->ic_channels[i].ic_flags = IEEE80211_CHAN_A;
368 }
369 }
370
371 /* set supported .11b and .11g rates */
372 ic->ic_sup_rates[IEEE80211_MODE_11B] = rt2661_rateset_11b;
373 ic->ic_sup_rates[IEEE80211_MODE_11G] = rt2661_rateset_11g;
374
375 /* set supported .11b and .11g channels (1 through 14) */
376 for (i = 1; i <= 14; i++) {
377 ic->ic_channels[i].ic_freq =
378 ieee80211_ieee2mhz(i, IEEE80211_CHAN_2GHZ);
379 ic->ic_channels[i].ic_flags =
380 IEEE80211_CHAN_CCK | IEEE80211_CHAN_OFDM |
381 IEEE80211_CHAN_DYN | IEEE80211_CHAN_2GHZ;
382 }
383
384 ieee80211_ifattach(ic);
385 ic->ic_node_alloc = rt2661_node_alloc;
386 /* ic->ic_wme.wme_update = rt2661_wme_update;*/
387 ic->ic_updateslot = rt2661_update_slot;
388 ic->ic_reset = rt2661_reset;
389 /* enable s/w bmiss handling in sta mode */
390 ic->ic_flags_ext |= IEEE80211_FEXT_SWBMISS;
391
392 /* override state transition machine */
393 sc->sc_newstate = ic->ic_newstate;
394 ic->ic_newstate = rt2661_newstate;
395 ieee80211_media_init(ic, rt2661_media_change, ieee80211_media_status);
396
397 bpfattach_dlt(ifp, DLT_IEEE802_11_RADIO,
398 sizeof (struct ieee80211_frame) + 64, &sc->sc_drvbpf);
399
400 sc->sc_rxtap_len = sizeof sc->sc_rxtapu;
401 sc->sc_rxtap.wr_ihdr.it_len = htole16(sc->sc_rxtap_len);
402 sc->sc_rxtap.wr_ihdr.it_present = htole32(RT2661_RX_RADIOTAP_PRESENT);
403
404 sc->sc_txtap_len = sizeof sc->sc_txtapu;
405 sc->sc_txtap.wt_ihdr.it_len = htole16(sc->sc_txtap_len);
406 sc->sc_txtap.wt_ihdr.it_present = htole32(RT2661_TX_RADIOTAP_PRESENT);
407
408 /*
409 * Add a few sysctl knobs.
410 */
411 sc->dwelltime = 200;
412
413 SYSCTL_ADD_INT(&sc->sysctl_ctx,
414 SYSCTL_CHILDREN(sc->sysctl_tree), OID_AUTO, "dwell",
415 CTLFLAG_RW, &sc->dwelltime, 0,
416 "channel dwell time (ms) for AP/station scanning");
417
418 error = bus_setup_intr(dev, sc->sc_irq, INTR_MPSAFE, rt2661_intr,
419 sc, &sc->sc_ih, ifp->if_serializer);
420 if (error != 0) {
421 device_printf(dev, "could not set up interrupt\n");
422 bpfdetach(ifp);
423 ieee80211_ifdetach(ic);
424 goto fail;
425 }
426
427 if (bootverbose)
428 ieee80211_announce(ic);
429 return 0;
430 fail:
431 rt2661_detach(sc);
432 return error;
433 }
434
435 int
436 rt2661_detach(void *xsc)
437 {
438 struct rt2661_softc *sc = xsc;
439 struct ieee80211com *ic = &sc->sc_ic;
440 struct ifnet *ifp = &ic->ic_if;
441
442 if (device_is_attached(sc->sc_dev)) {
443 lwkt_serialize_enter(ifp->if_serializer);
444
445 callout_stop(&sc->scan_ch);
446 callout_stop(&sc->rssadapt_ch);
447 rt2661_stop(sc);
448 bus_teardown_intr(sc->sc_dev, sc->sc_irq, sc->sc_ih);
449
450 lwkt_serialize_exit(ifp->if_serializer);
451
452 bpfdetach(ifp);
453 ieee80211_ifdetach(ic);
454 }
455
456 rt2661_free_tx_ring(sc, &sc->txq[0]);
457 rt2661_free_tx_ring(sc, &sc->txq[1]);
458 rt2661_free_tx_ring(sc, &sc->txq[2]);
459 rt2661_free_tx_ring(sc, &sc->txq[3]);
460 rt2661_free_tx_ring(sc, &sc->mgtq);
461 rt2661_free_rx_ring(sc, &sc->rxq);
462
463 if (sc->sc_irq != NULL) {
464 bus_release_resource(sc->sc_dev, SYS_RES_IRQ, sc->sc_irq_rid,
465 sc->sc_irq);
466 }
467
468 if (sc->sysctl_tree != NULL)
469 sysctl_ctx_free(&sc->sysctl_ctx);
470
471 return 0;
472 }
473
474 void
475 rt2661_shutdown(void *xsc)
476 {
477 struct rt2661_softc *sc = xsc;
478 struct ifnet *ifp = &sc->sc_ic.ic_if;
479
480 lwkt_serialize_enter(ifp->if_serializer);
481 rt2661_stop(sc);
482 lwkt_serialize_exit(ifp->if_serializer);
483 }
484
485 void
486 rt2661_suspend(void *xsc)
487 {
488 struct rt2661_softc *sc = xsc;
489 struct ifnet *ifp = &sc->sc_ic.ic_if;
490
491 lwkt_serialize_enter(ifp->if_serializer);
492 rt2661_stop(sc);
493 lwkt_serialize_exit(ifp->if_serializer);
494 }
495
496 void
497 rt2661_resume(void *xsc)
498 {
499 struct rt2661_softc *sc = xsc;
500 struct ifnet *ifp = sc->sc_ic.ic_ifp;
501
502 lwkt_serialize_enter(ifp->if_serializer);
503 if (ifp->if_flags & IFF_UP) {
504 ifp->if_init(ifp->if_softc);
505 if (ifp->if_flags & IFF_RUNNING)
506 ifp->if_start(ifp);
507 }
508 lwkt_serialize_exit(ifp->if_serializer);
509 }
510
511 static void
512 rt2661_dma_map_addr(void *arg, bus_dma_segment_t *segs, int nseg, int error)
513 {
514 if (error != 0)
515 return;
516
517 KASSERT(nseg == 1, ("too many DMA segments, %d should be 1", nseg));
518
519 *(bus_addr_t *)arg = segs[0].ds_addr;
520 }
521
522 static int
523 rt2661_alloc_tx_ring(struct rt2661_softc *sc, struct rt2661_tx_ring *ring,
524 int count)
525 {
526 int i, error;
527
528 ring->count = count;
529 ring->queued = 0;
530 ring->cur = ring->next = 0;
531
532 error = bus_dma_tag_create(NULL, 4, 0, BUS_SPACE_MAXADDR_32BIT,
533 BUS_SPACE_MAXADDR, NULL, NULL, count * RT2661_TX_DESC_SIZE, 1,
534 count * RT2661_TX_DESC_SIZE, 0, &ring->desc_dmat);
535 if (error != 0) {
536 device_printf(sc->sc_dev, "could not create desc DMA tag\n");
537 goto fail;
538 }
539
540 error = bus_dmamem_alloc(ring->desc_dmat, (void **)&ring->desc,
541 BUS_DMA_WAITOK | BUS_DMA_ZERO, &ring->desc_map);
542 if (error != 0) {
543 device_printf(sc->sc_dev, "could not allocate DMA memory\n");
544 goto fail;
545 }
546
547 error = bus_dmamap_load(ring->desc_dmat, ring->desc_map, ring->desc,
548 count * RT2661_TX_DESC_SIZE, rt2661_dma_map_addr, &ring->physaddr,
549 0);
550 if (error != 0) {
551 device_printf(sc->sc_dev, "could not load desc DMA map\n");
552
553 bus_dmamem_free(ring->desc_dmat, ring->desc, ring->desc_map);
554 ring->desc = NULL;
555 goto fail;
556 }
557
558 ring->data = kmalloc(count * sizeof (struct rt2661_data), M_DEVBUF,
559 M_WAITOK | M_ZERO);
560
561 error = bus_dma_tag_create(NULL, 1, 0, BUS_SPACE_MAXADDR_32BIT,
562 BUS_SPACE_MAXADDR, NULL, NULL, MCLBYTES * RT2661_MAX_SCATTER,
563 RT2661_MAX_SCATTER, MCLBYTES, 0, &ring->data_dmat);
564 if (error != 0) {
565 device_printf(sc->sc_dev, "could not create data DMA tag\n");
566 goto fail;
567 }
568
569 for (i = 0; i < count; i++) {
570 error = bus_dmamap_create(ring->data_dmat, 0,
571 &ring->data[i].map);
572 if (error != 0) {
573 device_printf(sc->sc_dev, "could not create DMA map\n");
574 goto fail;
575 }
576 }
577 return 0;
578
579 fail: rt2661_free_tx_ring(sc, ring);
580 return error;
581 }
582
583 static void
584 rt2661_reset_tx_ring(struct rt2661_softc *sc, struct rt2661_tx_ring *ring)
585 {
586 struct rt2661_tx_desc *desc;
587 struct rt2661_data *data;
588 int i;
589
590 for (i = 0; i < ring->count; i++) {
591 desc = &ring->desc[i];
592 data = &ring->data[i];
593
594 if (data->m != NULL) {
595 bus_dmamap_sync(ring->data_dmat, data->map,
596 BUS_DMASYNC_POSTWRITE);
597 bus_dmamap_unload(ring->data_dmat, data->map);
598 m_freem(data->m);
599 data->m = NULL;
600 }
601
602 desc->flags = 0;
603 }
604
605 bus_dmamap_sync(ring->desc_dmat, ring->desc_map, BUS_DMASYNC_PREWRITE);
606
607 ring->queued = 0;
608 ring->cur = ring->next = 0;
609 }
610
611 static void
612 rt2661_free_tx_ring(struct rt2661_softc *sc, struct rt2661_tx_ring *ring)
613 {
614 struct rt2661_data *data;
615 int i;
616
617 if (ring->desc != NULL) {
618 bus_dmamap_sync(ring->desc_dmat, ring->desc_map,
619 BUS_DMASYNC_POSTWRITE);
620 bus_dmamap_unload(ring->desc_dmat, ring->desc_map);
621 bus_dmamem_free(ring->desc_dmat, ring->desc, ring->desc_map);
622 ring->desc = NULL;
623 }
624
625 if (ring->desc_dmat != NULL) {
626 bus_dma_tag_destroy(ring->desc_dmat);
627 ring->desc_dmat = NULL;
628 }
629
630 if (ring->data != NULL) {
631 for (i = 0; i < ring->count; i++) {
632 data = &ring->data[i];
633
634 if (data->m != NULL) {
635 bus_dmamap_sync(ring->data_dmat, data->map,
636 BUS_DMASYNC_POSTWRITE);
637 bus_dmamap_unload(ring->data_dmat, data->map);
638 m_freem(data->m);
639 data->m = NULL;
640 }
641
642 if (data->map != NULL) {
643 bus_dmamap_destroy(ring->data_dmat, data->map);
644 data->map = NULL;
645 }
646 }
647
648 kfree(ring->data, M_DEVBUF);
649 ring->data = NULL;
650 }
651
652 if (ring->data_dmat != NULL) {
653 bus_dma_tag_destroy(ring->data_dmat);
654 ring->data_dmat = NULL;
655 }
656 }
657
658 static int
659 rt2661_alloc_rx_ring(struct rt2661_softc *sc, struct rt2661_rx_ring *ring,
660 int count)
661 {
662 struct rt2661_rx_desc *desc;
663 struct rt2661_data *data;
664 bus_addr_t physaddr;
665 int i, error;
666
667 ring->count = count;
668 ring->cur = ring->next = 0;
669
670 error = bus_dma_tag_create(NULL, 4, 0, BUS_SPACE_MAXADDR_32BIT,
671 BUS_SPACE_MAXADDR, NULL, NULL, count * RT2661_RX_DESC_SIZE, 1,
672 count * RT2661_RX_DESC_SIZE, 0, &ring->desc_dmat);
673 if (error != 0) {
674 device_printf(sc->sc_dev, "could not create desc DMA tag\n");
675 goto fail;
676 }
677
678 error = bus_dmamem_alloc(ring->desc_dmat, (void **)&ring->desc,
679 BUS_DMA_WAITOK | BUS_DMA_ZERO, &ring->desc_map);
680 if (error != 0) {
681 device_printf(sc->sc_dev, "could not allocate DMA memory\n");
682 goto fail;
683 }
684
685 error = bus_dmamap_load(ring->desc_dmat, ring->desc_map, ring->desc,
686 count * RT2661_RX_DESC_SIZE, rt2661_dma_map_addr, &ring->physaddr,
687 0);
688 if (error != 0) {
689 device_printf(sc->sc_dev, "could not load desc DMA map\n");
690
691 bus_dmamem_free(ring->desc_dmat, ring->desc, ring->desc_map);
692 ring->desc = NULL;
693 goto fail;
694 }
695
696 ring->data = kmalloc(count * sizeof (struct rt2661_data), M_DEVBUF,
697 M_WAITOK | M_ZERO);
698
699 /*
700 * Pre-allocate Rx buffers and populate Rx ring.
701 */
702 error = bus_dma_tag_create(NULL, 1, 0, BUS_SPACE_MAXADDR_32BIT,
703 BUS_SPACE_MAXADDR, NULL, NULL, MCLBYTES, 1, MCLBYTES, 0,
704 &ring->data_dmat);
705 if (error != 0) {
706 device_printf(sc->sc_dev, "could not create data DMA tag\n");
707 goto fail;
708 }
709
710 for (i = 0; i < count; i++) {
711 desc = &sc->rxq.desc[i];
712 data = &sc->rxq.data[i];
713
714 error = bus_dmamap_create(ring->data_dmat, 0, &data->map);
715 if (error != 0) {
716 device_printf(sc->sc_dev, "could not create DMA map\n");
717 goto fail;
718 }
719
720 data->m = m_getcl(MB_DONTWAIT, MT_DATA, M_PKTHDR);
721 if (data->m == NULL) {
722 device_printf(sc->sc_dev,
723 "could not allocate rx mbuf\n");
724 error = ENOMEM;
725 goto fail;
726 }
727
728 error = bus_dmamap_load(ring->data_dmat, data->map,
729 mtod(data->m, void *), MCLBYTES, rt2661_dma_map_addr,
730 &physaddr, 0);
731 if (error != 0) {
732 device_printf(sc->sc_dev,
733 "could not load rx buf DMA map");
734
735 m_freem(data->m);
736 data->m = NULL;
737 goto fail;
738 }
739
740 desc->flags = htole32(RT2661_RX_BUSY);
741 desc->physaddr = htole32(physaddr);
742 }
743
744 bus_dmamap_sync(ring->desc_dmat, ring->desc_map, BUS_DMASYNC_PREWRITE);
745
746 return 0;
747
748 fail: rt2661_free_rx_ring(sc, ring);
749 return error;
750 }
751
752 static void
753 rt2661_reset_rx_ring(struct rt2661_softc *sc, struct rt2661_rx_ring *ring)
754 {
755 int i;
756
757 for (i = 0; i < ring->count; i++)
758 ring->desc[i].flags = htole32(RT2661_RX_BUSY);
759
760 bus_dmamap_sync(ring->desc_dmat, ring->desc_map, BUS_DMASYNC_PREWRITE);
761
762 ring->cur = ring->next = 0;
763 }
764
765 static void
766 rt2661_free_rx_ring(struct rt2661_softc *sc, struct rt2661_rx_ring *ring)
767 {
768 struct rt2661_data *data;
769 int i;
770
771 if (ring->desc != NULL) {
772 bus_dmamap_sync(ring->desc_dmat, ring->desc_map,
773 BUS_DMASYNC_POSTWRITE);
774 bus_dmamap_unload(ring->desc_dmat, ring->desc_map);
775 bus_dmamem_free(ring->desc_dmat, ring->desc, ring->desc_map);
776 ring->desc = NULL;
777 }
778
779 if (ring->desc_dmat != NULL) {
780 bus_dma_tag_destroy(ring->desc_dmat);
781 ring->desc_dmat = NULL;
782 }
783
784 if (ring->data != NULL) {
785 for (i = 0; i < ring->count; i++) {
786 data = &ring->data[i];
787
788 if (data->m != NULL) {
789 bus_dmamap_sync(ring->data_dmat, data->map,
790 BUS_DMASYNC_POSTREAD);
791 bus_dmamap_unload(ring->data_dmat, data->map);
792 m_freem(data->m);
793 data->m = NULL;
794 }
795
796 if (data->map != NULL) {
797 bus_dmamap_destroy(ring->data_dmat, data->map);
798 data->map = NULL;
799 }
800 }
801
802 kfree(ring->data, M_DEVBUF);
803 ring->data = NULL;
804 }
805
806 if (ring->data_dmat != NULL) {
807 bus_dma_tag_destroy(ring->data_dmat);
808 ring->data_dmat = NULL;
809 }
810 }
811
812 static struct ieee80211_node *
813 rt2661_node_alloc(struct ieee80211_node_table *nt)
814 {
815 struct rt2661_node *rn;
816
817 rn = kmalloc(sizeof (struct rt2661_node), M_80211_NODE,
818 M_NOWAIT | M_ZERO);
819
820 return (rn != NULL) ? &rn->ni : NULL;
821 }
822
823 static int
824 rt2661_media_change(struct ifnet *ifp)
825 {
826 struct rt2661_softc *sc = ifp->if_softc;
827 int error;
828
829 error = ieee80211_media_change(ifp);
830 if (error != ENETRESET)
831 return error;
832
833 if ((ifp->if_flags & (IFF_UP | IFF_RUNNING)) == (IFF_UP | IFF_RUNNING))
834 rt2661_init(sc);
835 return 0;
836 }
837
838 /*
839 * This function is called periodically (every 200ms) during scanning to
840 * switch from one channel to another.
841 */
842 static void
843 rt2661_next_scan(void *arg)
844 {
845 struct rt2661_softc *sc = arg;
846 struct ieee80211com *ic = &sc->sc_ic;
847 struct ifnet *ifp = &ic->ic_if;
848
849 lwkt_serialize_enter(ifp->if_serializer);
850 if (ic->ic_state == IEEE80211_S_SCAN)
851 ieee80211_next_scan(ic);
852 lwkt_serialize_exit(ifp->if_serializer);
853 }
854
855 /*
856 * This function is called for each node present in the node station table.
857 */
858 static void
859 rt2661_iter_func(void *arg, struct ieee80211_node *ni)
860 {
861 struct rt2661_node *rn = (struct rt2661_node *)ni;
862
863 ral_rssadapt_updatestats(&rn->rssadapt);
864 }
865
866 /*
867 * This function is called periodically (every 100ms) in RUN state to update
868 * the rate adaptation statistics.
869 */
870 static void
871 rt2661_update_rssadapt(void *arg)
872 {
873 struct rt2661_softc *sc = arg;
874 struct ieee80211com *ic = &sc->sc_ic;
875 struct ifnet *ifp = &ic->ic_if;
876
877 lwkt_serialize_enter(ifp->if_serializer);
878
879 ieee80211_iterate_nodes(&ic->ic_sta, rt2661_iter_func, arg);
880 callout_reset(&sc->rssadapt_ch, hz / 10, rt2661_update_rssadapt, sc);
881
882 lwkt_serialize_exit(ifp->if_serializer);
883 }
884
885 static int
886 rt2661_newstate(struct ieee80211com *ic, enum ieee80211_state nstate, int arg)
887 {
888 struct rt2661_softc *sc = ic->ic_ifp->if_softc;
889 enum ieee80211_state ostate;
890 struct ieee80211_node *ni;
891 uint32_t tmp;
892 int error = 0;
893
894 ostate = ic->ic_state;
895 callout_stop(&sc->scan_ch);
896
897 if (ostate != nstate)
898 rt2661_led_newstate(sc, nstate);
899
900 switch (nstate) {
901 case IEEE80211_S_INIT:
902 callout_stop(&sc->rssadapt_ch);
903
904 if (ostate == IEEE80211_S_RUN) {
905 /* abort TSF synchronization */
906 tmp = RAL_READ(sc, RT2661_TXRX_CSR9);
907 RAL_WRITE(sc, RT2661_TXRX_CSR9, tmp & ~0x00ffffff);
908 }
909 break;
910
911 case IEEE80211_S_SCAN:
912 rt2661_set_chan(sc, ic->ic_curchan);
913 callout_reset(&sc->scan_ch, (sc->dwelltime * hz) / 1000,
914 rt2661_next_scan, sc);
915 break;
916
917 case IEEE80211_S_AUTH:
918 case IEEE80211_S_ASSOC:
919 rt2661_set_chan(sc, ic->ic_curchan);
920 break;
921
922 case IEEE80211_S_RUN:
923 rt2661_set_chan(sc, ic->ic_curchan);
924
925 ni = ic->ic_bss;
926
927 if (ic->ic_opmode != IEEE80211_M_MONITOR) {
928 rt2661_enable_mrr(sc);
929 rt2661_set_txpreamble(sc);
930 rt2661_set_basicrates(sc, &ni->ni_rates);
931 rt2661_set_bssid(sc, ni->ni_bssid);
932 }
933
934 if (ic->ic_opmode == IEEE80211_M_HOSTAP ||
935 ic->ic_opmode == IEEE80211_M_IBSS) {
936 if ((error = rt2661_prepare_beacon(sc)) != 0)
937 break;
938 }
939
940 if (ic->ic_opmode != IEEE80211_M_MONITOR) {
941 callout_reset(&sc->rssadapt_ch, hz / 10,
942 rt2661_update_rssadapt, sc);
943 rt2661_enable_tsf_sync(sc);
944 }
945 break;
946 }
947
948 return (error != 0) ? error : sc->sc_newstate(ic, nstate, arg);
949 }
950
951 /*
952 * Read 16 bits at address 'addr' from the serial EEPROM (either 93C46 or
953 * 93C66).
954 */
955 static uint16_t
956 rt2661_eeprom_read(struct rt2661_softc *sc, uint8_t addr)
957 {
958 uint32_t tmp;
959 uint16_t val;
960 int n;
961
962 /* clock C once before the first command */
963 RT2661_EEPROM_CTL(sc, 0);
964
965 RT2661_EEPROM_CTL(sc, RT2661_S);
966 RT2661_EEPROM_CTL(sc, RT2661_S | RT2661_C);
967 RT2661_EEPROM_CTL(sc, RT2661_S);
968
969 /* write start bit (1) */
970 RT2661_EEPROM_CTL(sc, RT2661_S | RT2661_D);
971 RT2661_EEPROM_CTL(sc, RT2661_S | RT2661_D | RT2661_C);
972
973 /* write READ opcode (10) */
974 RT2661_EEPROM_CTL(sc, RT2661_S | RT2661_D);
975 RT2661_EEPROM_CTL(sc, RT2661_S | RT2661_D | RT2661_C);
976 RT2661_EEPROM_CTL(sc, RT2661_S);
977 RT2661_EEPROM_CTL(sc, RT2661_S | RT2661_C);
978
979 /* write address (A5-A0 or A7-A0) */
980 n = (RAL_READ(sc, RT2661_E2PROM_CSR) & RT2661_93C46) ? 5 : 7;
981 for (; n >= 0; n--) {
982 RT2661_EEPROM_CTL(sc, RT2661_S |
983 (((addr >> n) & 1) << RT2661_SHIFT_D));
984 RT2661_EEPROM_CTL(sc, RT2661_S |
985 (((addr >> n) & 1) << RT2661_SHIFT_D) | RT2661_C);
986 }
987
988 RT2661_EEPROM_CTL(sc, RT2661_S);
989
990 /* read data Q15-Q0 */
991 val = 0;
992 for (n = 15; n >= 0; n--) {
993 RT2661_EEPROM_CTL(sc, RT2661_S | RT2661_C);
994 tmp = RAL_READ(sc, RT2661_E2PROM_CSR);
995 val |= ((tmp & RT2661_Q) >> RT2661_SHIFT_Q) << n;
996 RT2661_EEPROM_CTL(sc, RT2661_S);
997 }
998
999 RT2661_EEPROM_CTL(sc, 0);
1000
1001 /* clear Chip Select and clock C */
1002 RT2661_EEPROM_CTL(sc, RT2661_S);
1003 RT2661_EEPROM_CTL(sc, 0);
1004 RT2661_EEPROM_CTL(sc, RT2661_C);
1005
1006 return val;
1007 }
1008
1009 static void
1010 rt2661_tx_intr(struct rt2661_softc *sc)
1011 {
1012 struct ieee80211com *ic = &sc->sc_ic;
1013 struct ifnet *ifp = ic->ic_ifp;
1014 struct rt2661_tx_ratectl *rctl;
1015 struct rt2661_node *rn;
1016 uint32_t val, result;
1017 int retrycnt;
1018
1019 for (;;) {
1020 val = RAL_READ(sc, RT2661_STA_CSR4);
1021 if (!(val & RT2661_TX_STAT_VALID))
1022 break;
1023
1024 /* Gather statistics */
1025 result = RT2661_TX_RESULT(val);
1026 if (result == RT2661_TX_SUCCESS)
1027 ifp->if_opackets++;
1028 else
1029 ifp->if_oerrors++;
1030
1031 /* No rate control */
1032 if (RT2661_TX_QID(val) == 0)
1033 continue;
1034
1035 /* retrieve rate control algorithm context */
1036 rctl = STAILQ_FIRST(&sc->tx_ratectl);
1037 if (rctl == NULL) {
1038 /*
1039 * XXX
1040 * This really should not happen. Maybe we should
1041 * use assertion here? But why should we rely on
1042 * hardware to do the correct things? Even the
1043 * reference driver (RT61?) provided by Ralink does
1044 * not provide enough clue that this kind of interrupt
1045 * is promised to be generated for each packet. So
1046 * just print a message and keep going ...
1047 */
1048 if_printf(ifp, "WARNING: no rate control information\n");
1049 continue;
1050 }
1051 STAILQ_REMOVE_HEAD(&sc->tx_ratectl, link);
1052
1053 rn = (struct rt2661_node *)rctl->ni;
1054
1055 switch (result) {
1056 case RT2661_TX_SUCCESS:
1057 retrycnt = RT2661_TX_RETRYCNT(val);
1058
1059 DPRINTFN(10, ("data frame sent successfully after "
1060 "%d retries\n", retrycnt));
1061 if (retrycnt == 0 && rctl->id.id_node != NULL) {
1062 ral_rssadapt_raise_rate(ic, &rn->rssadapt,
1063 &rctl->id);
1064 }
1065 break;
1066
1067 case RT2661_TX_RETRY_FAIL:
1068 DPRINTFN(9, ("sending data frame failed (too much "
1069 "retries)\n"));
1070 if (rctl->id.id_node != NULL) {
1071 ral_rssadapt_lower_rate(ic, rctl->ni,
1072 &rn->rssadapt, &rctl->id);
1073 }
1074 break;
1075
1076 default:
1077 /* other failure */
1078 device_printf(sc->sc_dev,
1079 "sending data frame failed 0x%08x\n", val);
1080 break;
1081 }
1082
1083 ieee80211_free_node(rctl->ni);
1084 rctl->ni = NULL;
1085 kfree(rctl, M_RT2661);
1086 }
1087 }
1088
1089 static void
1090 rt2661_tx_dma_intr(struct rt2661_softc *sc, struct rt2661_tx_ring *txq)
1091 {
1092 struct rt2661_tx_desc *desc;
1093 struct rt2661_data *data;
1094
1095 bus_dmamap_sync(txq->desc_dmat, txq->desc_map, BUS_DMASYNC_POSTREAD);
1096
1097 for (;;) {
1098 desc = &txq->desc[txq->next];
1099 data = &txq->data[txq->next];
1100
1101 if ((le32toh(desc->flags) & RT2661_TX_BUSY) ||
1102 !(le32toh(desc->flags) & RT2661_TX_VALID))
1103 break;
1104
1105 bus_dmamap_sync(txq->data_dmat, data->map,
1106 BUS_DMASYNC_POSTWRITE);
1107 bus_dmamap_unload(txq->data_dmat, data->map);
1108 m_freem(data->m);
1109 data->m = NULL;
1110
1111 /* descriptor is no longer valid */
1112 desc->flags &= ~htole32(RT2661_TX_VALID);
1113
1114 DPRINTFN(15, ("tx dma done q=%p idx=%u\n", txq, txq->next));
1115
1116 txq->queued--;
1117 if (++txq->next >= txq->count) /* faster than % count */
1118 txq->next = 0;
1119 }
1120
1121 bus_dmamap_sync(txq->desc_dmat, txq->desc_map, BUS_DMASYNC_PREWRITE);
1122
1123 if (txq->queued < txq->count) {
1124 struct ifnet *ifp = &sc->sc_ic.ic_if;
1125
1126 sc->sc_tx_timer = 0;
1127 ifp->if_flags &= ~IFF_OACTIVE;
1128 rt2661_start(ifp);
1129 }
1130 }
1131
1132 static void
1133 rt2661_rx_intr(struct rt2661_softc *sc)
1134 {
1135 struct ieee80211com *ic = &sc->sc_ic;
1136 struct ifnet *ifp = ic->ic_ifp;
1137 struct rt2661_rx_desc *desc;
1138 struct rt2661_data *data;
1139 bus_addr_t physaddr;
1140 struct ieee80211_frame *wh;
1141 struct ieee80211_node *ni;
1142 struct rt2661_node *rn;
1143 struct mbuf *mnew, *m;
1144 int error;
1145
1146 bus_dmamap_sync(sc->rxq.desc_dmat, sc->rxq.desc_map,
1147 BUS_DMASYNC_POSTREAD);
1148
1149 for (;;) {
1150 int rssi;
1151
1152 desc = &sc->rxq.desc[sc->rxq.cur];
1153 data = &sc->rxq.data[sc->rxq.cur];
1154
1155 if (le32toh(desc->flags) & RT2661_RX_BUSY)
1156 break;
1157
1158 if ((le32toh(desc->flags) & RT2661_RX_PHY_ERROR) ||
1159 (le32toh(desc->flags) & RT2661_RX_CRC_ERROR)) {
1160 /*
1161 * This should not happen since we did not request
1162 * to receive those frames when we filled TXRX_CSR0.
1163 */
1164 DPRINTFN(5, ("PHY or CRC error flags 0x%08x\n",
1165 le32toh(desc->flags)));
1166 ifp->if_ierrors++;
1167 goto skip;
1168 }
1169
1170 if ((le32toh(desc->flags) & RT2661_RX_CIPHER_MASK) != 0) {
1171 ifp->if_ierrors++;
1172 goto skip;
1173 }
1174
1175 /*
1176 * Try to allocate a new mbuf for this ring element and load it
1177 * before processing the current mbuf. If the ring element
1178 * cannot be loaded, drop the received packet and reuse the old
1179 * mbuf. In the unlikely case that the old mbuf can't be
1180 * reloaded either, explicitly panic.
1181 */
1182 mnew = m_getcl(MB_DONTWAIT, MT_DATA, M_PKTHDR);
1183 if (mnew == NULL) {
1184 ifp->if_ierrors++;
1185 goto skip;
1186 }
1187
1188 bus_dmamap_sync(sc->rxq.data_dmat, data->map,
1189 BUS_DMASYNC_POSTREAD);
1190 bus_dmamap_unload(sc->rxq.data_dmat, data->map);
1191
1192 error = bus_dmamap_load(sc->rxq.data_dmat, data->map,
1193 mtod(mnew, void *), MCLBYTES, rt2661_dma_map_addr,
1194 &physaddr, 0);
1195 if (error != 0) {
1196 m_freem(mnew);
1197
1198 /* try to reload the old mbuf */
1199 error = bus_dmamap_load(sc->rxq.data_dmat, data->map,
1200 mtod(data->m, void *), MCLBYTES,
1201 rt2661_dma_map_addr, &physaddr, 0);
1202 if (error != 0) {
1203 /* very unlikely that it will fail... */
1204 panic("%s: could not load old rx mbuf",
1205 device_get_name(sc->sc_dev));
1206 }
1207 ifp->if_ierrors++;
1208 goto skip;
1209 }
1210
1211 /*
1212 * New mbuf successfully loaded, update Rx ring and continue
1213 * processing.
1214 */
1215 m = data->m;
1216 data->m = mnew;
1217 desc->physaddr = htole32(physaddr);
1218
1219 /* finalize mbuf */
1220 m->m_pkthdr.rcvif = ifp;
1221 m->m_pkthdr.len = m->m_len =
1222 (le32toh(desc->flags) >> 16) & 0xfff;
1223
1224 rssi = rt2661_get_rssi(sc, desc->rssi);
1225
1226 if (sc->sc_drvbpf != NULL) {
1227 struct rt2661_rx_radiotap_header *tap = &sc->sc_rxtap;
1228 uint32_t tsf_lo, tsf_hi;
1229
1230 /* get timestamp (low and high 32 bits) */
1231 tsf_hi = RAL_READ(sc, RT2661_TXRX_CSR13);
1232 tsf_lo = RAL_READ(sc, RT2661_TXRX_CSR12);
1233
1234 tap->wr_tsf =
1235 htole64(((uint64_t)tsf_hi << 32) | tsf_lo);
1236 tap->wr_flags = 0;
1237 tap->wr_rate = rt2661_rxrate(desc);
1238 tap->wr_chan_freq = htole16(ic->ic_curchan->ic_freq);
1239 tap->wr_chan_flags = htole16(ic->ic_curchan->ic_flags);
1240 tap->wr_antsignal = rssi;
1241
1242 bpf_ptap(sc->sc_drvbpf, m, tap, sc->sc_rxtap_len);
1243 }
1244
1245 wh = mtod(m, struct ieee80211_frame *);
1246 ni = ieee80211_find_rxnode(ic,
1247 (struct ieee80211_frame_min *)wh);
1248
1249 /* send the frame to the 802.11 layer */
1250 ieee80211_input(ic, m, ni, rssi, 0);
1251
1252 /* give rssi to the rate adatation algorithm */
1253 rn = (struct rt2661_node *)ni;
1254 ral_rssadapt_input(ic, ni, &rn->rssadapt, rssi);
1255
1256 /* node is no longer needed */
1257 ieee80211_free_node(ni);
1258
1259 skip: desc->flags |= htole32(RT2661_RX_BUSY);
1260
1261 DPRINTFN(15, ("rx intr idx=%u\n", sc->rxq.cur));
1262
1263 sc->rxq.cur = (sc->rxq.cur + 1) % RT2661_RX_RING_COUNT;
1264 }
1265
1266 bus_dmamap_sync(sc->rxq.desc_dmat, sc->rxq.desc_map,
1267 BUS_DMASYNC_PREWRITE);
1268 }
1269
1270 /* ARGSUSED */
1271 static void
1272 rt2661_mcu_beacon_expire(struct rt2661_softc *sc)
1273 {
1274 /* do nothing */
1275 }
1276
1277 static void
1278 rt2661_mcu_wakeup(struct rt2661_softc *sc)
1279 {
1280 RAL_WRITE(sc, RT2661_MAC_CSR11, 5 << 16);
1281
1282 RAL_WRITE(sc, RT2661_SOFT_RESET_CSR, 0x7);
1283 RAL_WRITE(sc, RT2661_IO_CNTL_CSR, 0x18);
1284 RAL_WRITE(sc, RT2661_PCI_USEC_CSR, 0x20);
1285
1286 /* send wakeup command to MCU */
1287 rt2661_tx_cmd(sc, RT2661_MCU_CMD_WAKEUP, 0);
1288 }
1289
1290 static void
1291 rt2661_mcu_cmd_intr(struct rt2661_softc *sc)
1292 {
1293 RAL_READ(sc, RT2661_M2H_CMD_DONE_CSR);
1294 RAL_WRITE(sc, RT2661_M2H_CMD_DONE_CSR, 0xffffffff);
1295 }
1296
1297 static void
1298 rt2661_intr(void *arg)
1299 {
1300 struct rt2661_softc *sc = arg;
1301 struct ifnet *ifp = &sc->sc_ic.ic_if;
1302 uint32_t r1, r2;
1303
1304 /* disable MAC and MCU interrupts */
1305 RAL_WRITE(sc, RT2661_INT_MASK_CSR, 0xffffff7f);
1306 RAL_WRITE(sc, RT2661_MCU_INT_MASK_CSR, 0xffffffff);
1307
1308 /* don't re-enable interrupts if we're shutting down */
1309 if (!(ifp->if_flags & IFF_RUNNING))
1310 return;
1311
1312 r1 = RAL_READ(sc, RT2661_INT_SOURCE_CSR);
1313 RAL_WRITE(sc, RT2661_INT_SOURCE_CSR, r1);
1314
1315 r2 = RAL_READ(sc, RT2661_MCU_INT_SOURCE_CSR);
1316 RAL_WRITE(sc, RT2661_MCU_INT_SOURCE_CSR, r2);
1317
1318 if (r1 & RT2661_MGT_DONE)
1319 rt2661_tx_dma_intr(sc, &sc->mgtq);
1320
1321 if (r1 & RT2661_RX_DONE)
1322 rt2661_rx_intr(sc);
1323
1324 if (r1 & RT2661_TX0_DMA_DONE)
1325 rt2661_tx_dma_intr(sc, &sc->txq[0]);
1326
1327 if (r1 & RT2661_TX1_DMA_DONE)
1328 rt2661_tx_dma_intr(sc, &sc->txq[1]);
1329
1330 if (r1 & RT2661_TX2_DMA_DONE)
1331 rt2661_tx_dma_intr(sc, &sc->txq[2]);
1332
1333 if (r1 & RT2661_TX3_DMA_DONE)
1334 rt2661_tx_dma_intr(sc, &sc->txq[3]);
1335
1336 if (r1 & RT2661_TX_DONE)
1337 rt2661_tx_intr(sc);
1338
1339 if (r2 & RT2661_MCU_CMD_DONE)
1340 rt2661_mcu_cmd_intr(sc);
1341
1342 if (r2 & RT2661_MCU_BEACON_EXPIRE)
1343 rt2661_mcu_beacon_expire(sc);
1344
1345 if (r2 & RT2661_MCU_WAKEUP)
1346 rt2661_mcu_wakeup(sc);
1347
1348 /* re-enable MAC and MCU interrupts */
1349 RAL_WRITE(sc, RT2661_INT_MASK_CSR, 0x0000ff10);
1350 RAL_WRITE(sc, RT2661_MCU_INT_MASK_CSR, 0);
1351 }
1352
1353 /* quickly determine if a given rate is CCK or OFDM */
1354 #define RAL_RATE_IS_OFDM(rate) ((rate) >= 12 && (rate) != 22)
1355
1356 #define RAL_ACK_SIZE 14 /* 10 + 4(FCS) */
1357 #define RAL_CTS_SIZE 14 /* 10 + 4(FCS) */
1358
1359 #define RAL_SIFS 10 /* us */
1360
1361 /*
1362 * This function is only used by the Rx radiotap code. It returns the rate at
1363 * which a given frame was received.
1364 */
1365 static uint8_t
1366 rt2661_rxrate(struct rt2661_rx_desc *desc)
1367 {
1368 if (le32toh(desc->flags) & RT2661_RX_OFDM) {
1369 /* reverse function of rt2661_plcp_signal */
1370 switch (desc->rate & 0xf) {
1371 case 0xb: return 12;
1372 case 0xf: return 18;
1373 case 0xa: return 24;
1374 case 0xe: return 36;
1375 case 0x9: return 48;
1376 case 0xd: return 72;
1377 case 0x8: return 96;
1378 case 0xc: return 108;
1379 }
1380 } else {
1381 if (desc->rate == 10)
1382 return 2;
1383 if (desc->rate == 20)
1384 return 4;
1385 if (desc->rate == 55)
1386 return 11;
1387 if (desc->rate == 110)
1388 return 22;
1389 }
1390 return 2; /* should not get there */
1391 }
1392
1393 /*
1394 * Return the expected ack rate for a frame transmitted at rate `rate'.
1395 * XXX: this should depend on the destination node basic rate set.
1396 */
1397 static int
1398 rt2661_ack_rate(struct ieee80211com *ic, int rate)
1399 {
1400 switch (rate) {
1401 /* CCK rates */
1402 case 2:
1403 return 2;
1404 case 4:
1405 case 11:
1406 case 22:
1407 return (ic->ic_curmode == IEEE80211_MODE_11B) ? 4 : rate;
1408
1409 /* OFDM rates */
1410 case 12:
1411 case 18:
1412 return 12;
1413 case 24:
1414 case 36:
1415 return 24;
1416 case 48:
1417 case 72:
1418 case 96:
1419 case 108:
1420 return 48;
1421 }
1422
1423 /* default to 1Mbps */
1424 return 2;
1425 }
1426
1427 /*
1428 * Compute the duration (in us) needed to transmit `len' bytes at rate `rate'.
1429 * The function automatically determines the operating mode depending on the
1430 * given rate. `flags' indicates whether short preamble is in use or not.
1431 */
1432 static uint16_t
1433 rt2661_txtime(int len, int rate, uint32_t flags)
1434 {
1435 uint16_t txtime;
1436
1437 if (RAL_RATE_IS_OFDM(rate)) {
1438 /* IEEE Std 802.11a-1999, pp. 37 */
1439 txtime = (8 + 4 * len + 3 + rate - 1) / rate;
1440 txtime = 16 + 4 + 4 * txtime + 6;
1441 } else {
1442 /* IEEE Std 802.11b-1999, pp. 28 */
1443 txtime = (16 * len + rate - 1) / rate;
1444 if (rate != 2 && (flags & IEEE80211_F_SHPREAMBLE))
1445 txtime += 72 + 24;
1446 else
1447 txtime += 144 + 48;
1448 }
1449
1450 return txtime;
1451 }
1452
1453 static uint8_t
1454 rt2661_plcp_signal(int rate)
1455 {
1456 switch (rate) {
1457 /* CCK rates (returned values are device-dependent) */
1458 case 2: return 0x0;
1459 case 4: return 0x1;
1460 case 11: return 0x2;
1461 case 22: return 0x3;
1462
1463 /* OFDM rates (cf IEEE Std 802.11a-1999, pp. 14 Table 80) */
1464 case 12: return 0xb;
1465 case 18: return 0xf;
1466 case 24: return 0xa;
1467 case 36: return 0xe;
1468 case 48: return 0x9;
1469 case 72: return 0xd;
1470 case 96: return 0x8;
1471 case 108: return 0xc;
1472
1473 /* unsupported rates (should not get there) */
1474 default: return 0xff;
1475 }
1476 }
1477
1478 static void
1479 rt2661_setup_tx_desc(struct rt2661_softc *sc, struct rt2661_tx_desc *desc,
1480 uint32_t flags, uint16_t xflags, int len, int rate,
1481 const bus_dma_segment_t *segs, int nsegs, int ac, int ratectl)
1482 {
1483 struct ieee80211com *ic = &sc->sc_ic;
1484 uint16_t plcp_length;
1485 int i, remainder;
1486
1487 desc->flags = htole32(flags);
1488 desc->flags |= htole32(len << 16);
1489 desc->flags |= htole32(RT2661_TX_VALID);
1490
1491 desc->xflags = htole16(xflags);
1492 desc->xflags |= htole16(nsegs << 13);
1493
1494 desc->wme = htole16(
1495 RT2661_QID(ac) |
1496 RT2661_AIFSN(2) |
1497 RT2661_LOGCWMIN(4) |
1498 RT2661_LOGCWMAX(10));
1499
1500 /*
1501 * Remember whether TX rate control information should be gathered.
1502 * This field is driver private data only. It will be made available
1503 * by the NIC in STA_CSR4 on Tx done interrupts.
1504 */
1505 desc->qid = ratectl;
1506
1507 /* setup PLCP fields */
1508 desc->plcp_signal = rt2661_plcp_signal(rate);
1509 desc->plcp_service = 4;
1510
1511 len += IEEE80211_CRC_LEN;
1512 if (RAL_RATE_IS_OFDM(rate)) {
1513 desc->flags |= htole32(RT2661_TX_OFDM);
1514
1515 plcp_length = len & 0xfff;
1516 desc->plcp_length_hi = plcp_length >> 6;
1517 desc->plcp_length_lo = plcp_length & 0x3f;
1518 } else {
1519 plcp_length = (16 * len + rate - 1) / rate;
1520 if (rate == 22) {
1521 remainder = (16 * len) % 22;
1522 if (remainder != 0 && remainder < 7)
1523 desc->plcp_service |= RT2661_PLCP_LENGEXT;
1524 }
1525 desc->plcp_length_hi = plcp_length >> 8;
1526 desc->plcp_length_lo = plcp_length & 0xff;
1527
1528 if (rate != 2 && (ic->ic_flags & IEEE80211_F_SHPREAMBLE))
1529 desc->plcp_signal |= 0x08;
1530 }
1531
1532 /* RT2x61 supports scatter with up to 5 segments */
1533 for (i = 0; i < nsegs; i++) {
1534 desc->addr[i] = htole32(segs[i].ds_addr);
1535 desc->len [i] = htole16(segs[i].ds_len);
1536 }
1537
1538 desc->flags |= htole32(RT2661_TX_BUSY);
1539 }
1540
1541 static int
1542 rt2661_tx_mgt(struct rt2661_softc *sc, struct mbuf *m0,
1543 struct ieee80211_node *ni)
1544 {
1545 struct ieee80211com *ic = &sc->sc_ic;
1546 struct rt2661_tx_desc *desc;
1547 struct rt2661_data *data;
1548 struct ieee80211_frame *wh;
1549 struct rt2661_dmamap map;
1550 uint16_t dur;
1551 uint32_t flags = 0; /* XXX HWSEQ */
1552 int rate, error;
1553
1554 desc = &sc->mgtq.desc[sc->mgtq.cur];
1555 data = &sc->mgtq.data[sc->mgtq.cur];
1556
1557 /* send mgt frames at the lowest available rate */
1558 rate = IEEE80211_IS_CHAN_5GHZ(ic->ic_curchan) ? 12 : 2;
1559
1560 error = bus_dmamap_load_mbuf(sc->mgtq.data_dmat, data->map, m0,
1561 rt2661_dma_map_mbuf, &map, 0);
1562 if (error != 0) {
1563 device_printf(sc->sc_dev, "could not map mbuf (error %d)\n",
1564 error);
1565 m_freem(m0);
1566 return error;
1567 }
1568
1569 if (sc->sc_drvbpf != NULL) {
1570 struct rt2661_tx_radiotap_header *tap = &sc->sc_txtap;
1571
1572 tap->wt_flags = 0;
1573 tap->wt_rate = rate;
1574 tap->wt_chan_freq = htole16(ic->ic_curchan->ic_freq);
1575 tap->wt_chan_flags = htole16(ic->ic_curchan->ic_flags);
1576
1577 bpf_ptap(sc->sc_drvbpf, m0, tap, sc->sc_txtap_len);
1578 }
1579
1580 data->m = m0;
1581
1582 wh = mtod(m0, struct ieee80211_frame *);
1583
1584 if (!IEEE80211_IS_MULTICAST(wh->i_addr1)) {
1585 flags |= RT2661_TX_NEED_ACK;
1586
1587 dur = rt2661_txtime(RAL_ACK_SIZE, rate, ic->ic_flags) +
1588 RAL_SIFS;
1589 *(uint16_t *)wh->i_dur = htole16(dur);
1590
1591 /* tell hardware to add timestamp in probe responses */
1592 if ((wh->i_fc[0] &
1593 (IEEE80211_FC0_TYPE_MASK | IEEE80211_FC0_SUBTYPE_MASK)) ==
1594 (IEEE80211_FC0_TYPE_MGT | IEEE80211_FC0_SUBTYPE_PROBE_RESP))
1595 flags |= RT2661_TX_TIMESTAMP;
1596 }
1597
1598 rt2661_setup_tx_desc(sc, desc, flags, 0 /* XXX HWSEQ */,
1599 m0->m_pkthdr.len, rate, map.segs, map.nseg, RT2661_QID_MGT, 0);
1600
1601 bus_dmamap_sync(sc->mgtq.data_dmat, data->map, BUS_DMASYNC_PREWRITE);
1602 bus_dmamap_sync(sc->mgtq.desc_dmat, sc->mgtq.desc_map,
1603 BUS_DMASYNC_PREWRITE);
1604
1605 DPRINTFN(10, ("sending mgt frame len=%u idx=%u rate=%u\n",
1606 m0->m_pkthdr.len, sc->mgtq.cur, rate));
1607
1608 /* kick mgt */
1609 sc->mgtq.queued++;
1610 sc->mgtq.cur = (sc->mgtq.cur + 1) % RT2661_MGT_RING_COUNT;
1611 RAL_WRITE(sc, RT2661_TX_CNTL_CSR, RT2661_KICK_MGT);
1612
1613 ieee80211_free_node(ni);
1614
1615 return 0;
1616 }
1617
1618 /*
1619 * Build a RTS control frame.
1620 */
1621 static struct mbuf *
1622 rt2661_get_rts(struct rt2661_softc *sc, struct ieee80211_frame *wh,
1623 uint16_t dur)
1624 {
1625 struct ieee80211_frame_rts *rts;
1626 struct mbuf *m;
1627
1628 MGETHDR(m, MB_DONTWAIT, MT_DATA);
1629 if (m == NULL) {
1630 sc->sc_ic.ic_stats.is_tx_nobuf++;
1631 device_printf(sc->sc_dev, "could not allocate RTS frame\n");
1632 return NULL;
1633 }
1634
1635 rts = mtod(m, struct ieee80211_frame_rts *);
1636
1637 rts->i_fc[0] = IEEE80211_FC0_VERSION_0 | IEEE80211_FC0_TYPE_CTL |
1638 IEEE80211_FC0_SUBTYPE_RTS;
1639 rts->i_fc[1] = IEEE80211_FC1_DIR_NODS;
1640 *(uint16_t *)rts->i_dur = htole16(dur);
1641 IEEE80211_ADDR_COPY(rts->i_ra, wh->i_addr1);
1642 IEEE80211_ADDR_COPY(rts->i_ta, wh->i_addr2);
1643
1644 m->m_pkthdr.len = m->m_len = sizeof (struct ieee80211_frame_rts);
1645
1646 return m;
1647 }
1648
1649 static int
1650 rt2661_tx_data(struct rt2661_softc *sc, struct mbuf *m0,
1651 struct ieee80211_node *ni, int ac)
1652 {
1653 struct ieee80211com *ic = &sc->sc_ic;
1654 struct rt2661_tx_ring *txq = &sc->txq[ac];
1655 struct rt2661_tx_desc *desc;
1656 struct rt2661_data *data;
1657 struct rt2661_tx_ratectl *rctl;
1658 struct rt2661_node *rn;
1659 struct ieee80211_rateset *rs;
1660 struct ieee80211_frame *wh;
1661 struct ieee80211_key *k;
1662 const struct chanAccParams *cap;
1663 struct mbuf *mnew;
1664 struct rt2661_dmamap map;
1665 uint16_t dur;
1666 uint32_t flags = 0;
1667 int error, rate, noack = 0;
1668
1669 wh = mtod(m0, struct ieee80211_frame *);
1670
1671 if (ic->ic_fixed_rate != IEEE80211_FIXED_RATE_NONE) {
1672 rs = &ic->ic_sup_rates[ic->ic_curmode];
1673 rate = rs->rs_rates[ic->ic_fixed_rate];
1674 } else {
1675 rs = &ni->ni_rates;
1676 rn = (struct rt2661_node *)ni;
1677 ni->ni_txrate = ral_rssadapt_choose(&rn->rssadapt, rs,
1678 wh, m0->m_pkthdr.len, NULL, 0);
1679 rate = rs->rs_rates[ni->ni_txrate];
1680 }
1681 rate &= IEEE80211_RATE_VAL;
1682
1683 if (wh->i_fc[0] & IEEE80211_FC0_SUBTYPE_QOS) {
1684 cap = &ic->ic_wme.wme_chanParams;
1685 noack = cap->cap_wmeParams[ac].wmep_noackPolicy;
1686 }
1687
1688 if (wh->i_fc[1] & IEEE80211_FC1_WEP) {
1689 k = ieee80211_crypto_encap(ic, ni, m0);
1690 if (k == NULL) {
1691 m_freem(m0);
1692 return ENOBUFS;
1693 }
1694
1695 /* packet header may have moved, reset our local pointer */
1696 wh = mtod(m0, struct ieee80211_frame *);
1697 }
1698
1699 /*
1700 * IEEE Std 802.11-1999, pp 82: "A STA shall use an RTS/CTS exchange
1701 * for directed frames only when the length of the MPDU is greater
1702 * than the length threshold indicated by [...]" ic_rtsthreshold.
1703 */
1704 if (!IEEE80211_IS_MULTICAST(wh->i_addr1) &&
1705 m0->m_pkthdr.len > ic->ic_rtsthreshold) {
1706 struct mbuf *m;
1707 uint16_t dur;
1708 int rtsrate, ackrate;
1709
1710 rtsrate = IEEE80211_IS_CHAN_5GHZ(ic->ic_curchan) ? 12 : 2;
1711 ackrate = rt2661_ack_rate(ic, rate);
1712
1713 dur = rt2661_txtime(m0->m_pkthdr.len + 4, rate, ic->ic_flags) +
1714 rt2661_txtime(RAL_CTS_SIZE, rtsrate, ic->ic_flags) +
1715 /* XXX: noack (QoS)? */
1716 rt2661_txtime(RAL_ACK_SIZE, ackrate, ic->ic_flags) +
1717 3 * RAL_SIFS;
1718
1719 m = rt2661_get_rts(sc, wh, dur);
1720
1721 desc = &txq->desc[txq->cur];
1722 data = &txq->data[txq->cur];
1723
1724 error = bus_dmamap_load_mbuf(txq->data_dmat, data->map, m,
1725 rt2661_dma_map_mbuf, &map, 0);
1726 if (error != 0) {
1727 device_printf(sc->sc_dev,
1728 "could not map mbuf (error %d)\n", error);
1729 m_freem(m);
1730 m_freem(m0);
1731 return error;
1732 }
1733
1734 data->m = m;
1735
1736 rt2661_setup_tx_desc(sc, desc, RT2661_TX_NEED_ACK |
1737 RT2661_TX_MORE_FRAG, 0, m->m_pkthdr.len,
1738 rtsrate, map.segs, map.nseg, ac, 0);
1739
1740 bus_dmamap_sync(txq->data_dmat, data->map,
1741 BUS_DMASYNC_PREWRITE);
1742
1743 txq->queued++;
1744 txq->cur = (txq->cur + 1) % RT2661_TX_RING_COUNT;
1745
1746 /*
1747 * IEEE Std 802.11-1999: when an RTS/CTS exchange is used, the
1748 * asynchronous data frame shall be transmitted after the CTS
1749 * frame and a SIFS period.
1750 */
1751 flags |= RT2661_TX_LONG_RETRY | RT2661_TX_IFS;
1752 }
1753
1754 data = &txq->data[txq->cur];
1755 desc = &txq->desc[txq->cur];
1756
1757 error = bus_dmamap_load_mbuf(txq->data_dmat, data->map, m0,
1758 rt2661_dma_map_mbuf, &map, 0);
1759 if (error != 0 && error != EFBIG) {
1760 device_printf(sc->sc_dev, "could not map mbuf (error %d)\n",
1761 error);
1762 m_freem(m0);
1763 return error;
1764 }
1765 if (error != 0) {
1766 mnew = m_defrag(m0, MB_DONTWAIT);
1767 if (mnew == NULL) {
1768 device_printf(sc->sc_dev,
1769 "could not defragment mbuf\n");
1770 m_freem(m0);
1771 return ENOBUFS;
1772 }
1773 m0 = mnew;
1774
1775 error = bus_dmamap_load_mbuf(txq->data_dmat, data->map, m0,
1776 rt2661_dma_map_mbuf, &map, 0);
1777 if (error != 0) {
1778 device_printf(sc->sc_dev,
1779 "could not map mbuf (error %d)\n", error);
1780 m_freem(m0);
1781 return error;
1782 }
1783
1784 /* packet header have moved, reset our local pointer */
1785 wh = mtod(m0, struct ieee80211_frame *);
1786 }
1787
1788 if (sc->sc_drvbpf != NULL) {
1789 struct rt2661_tx_radiotap_header *tap = &sc->sc_txtap;
1790
1791 tap->wt_flags = 0;
1792 tap->wt_rate = rate;
1793 tap->wt_chan_freq = htole16(ic->ic_curchan->ic_freq);
1794 tap->wt_chan_flags = htole16(ic->ic_curchan->ic_flags);
1795
1796 bpf_ptap(sc->sc_drvbpf, m0, tap, sc->sc_txtap_len);
1797 }
1798
1799 data->m = m0;
1800
1801 rctl = kmalloc(sizeof(*rctl), M_RT2661, M_NOWAIT);
1802 if (rctl != NULL) {
1803 rctl->ni = ni;
1804
1805 /* remember link conditions for rate adaptation algorithm */
1806 if (ic->ic_fixed_rate == IEEE80211_FIXED_RATE_NONE) {
1807 rctl->id.id_len = m0->m_pkthdr.len;
1808 rctl->id.id_rateidx = ni->ni_txrate;
1809 rctl->id.id_node = ni;
1810 rctl->id.id_rssi = ni->ni_rssi;
1811 } else {
1812 rctl->id.id_node = NULL;
1813 }
1814 STAILQ_INSERT_TAIL(&sc->tx_ratectl, rctl, link);
1815 }
1816
1817 if (!noack && !IEEE80211_IS_MULTICAST(wh->i_addr1)) {
1818 flags |= RT2661_TX_NEED_ACK;
1819
1820 dur = rt2661_txtime(RAL_ACK_SIZE, rt2661_ack_rate(ic, rate),
1821 ic->ic_flags) + RAL_SIFS;
1822 *(uint16_t *)wh->i_dur = htole16(dur);
1823 }
1824
1825 rt2661_setup_tx_desc(sc, desc, flags, 0, m0->m_pkthdr.len, rate,
1826 map.segs, map.nseg, ac, rctl != NULL);
1827
1828 bus_dmamap_sync(txq->data_dmat, data->map, BUS_DMASYNC_PREWRITE);
1829 bus_dmamap_sync(txq->desc_dmat, txq->desc_map, BUS_DMASYNC_PREWRITE);
1830
1831 DPRINTFN(10, ("sending data frame len=%u idx=%u rate=%u\n",
1832 m0->m_pkthdr.len, txq->cur, rate));
1833
1834 /* kick Tx */
1835 txq->queued++;
1836 txq->cur = (txq->cur + 1) % RT2661_TX_RING_COUNT;
1837 RAL_WRITE(sc, RT2661_TX_CNTL_CSR, 1 << ac);
1838
1839 if (rctl == NULL)
1840 ieee80211_free_node(ni);
1841
1842 return 0;
1843 }
1844
1845 static void
1846 rt2661_start(struct ifnet *ifp)
1847 {
1848 struct rt2661_softc *sc = ifp->if_softc;
1849 struct ieee80211com *ic = &sc->sc_ic;
1850 struct mbuf *m0;
1851 struct ether_header *eh;
1852 struct ieee80211_node *ni;
1853 int ac;
1854
1855 /* prevent management frames from being sent if we're not ready */
1856 if (!(ifp->if_flags & IFF_RUNNING))
1857 return;
1858
1859 for (;;) {
1860 IF_POLL(&ic->ic_mgtq, m0);
1861 if (m0 != NULL) {
1862 if (sc->mgtq.queued >= RT2661_MGT_RING_COUNT) {
1863 ifp->if_flags |= IFF_OACTIVE;
1864 break;
1865 }
1866 IF_DEQUEUE(&ic->ic_mgtq, m0);
1867
1868 ni = (struct ieee80211_node *)m0->m_pkthdr.rcvif;
1869 m0->m_pkthdr.rcvif = NULL;
1870
1871 if (ic->ic_rawbpf != NULL)
1872 bpf_mtap(ic->ic_rawbpf, m0);
1873
1874 if (rt2661_tx_mgt(sc, m0, ni) != 0)
1875 break;
1876
1877 } else {
1878 if (ic->ic_state != IEEE80211_S_RUN)
1879 break;
1880
1881 m0 = ifq_dequeue(&ifp->if_snd, NULL);
1882 if (m0 == NULL)
1883 break;
1884
1885 if (m0->m_len < sizeof (struct ether_header) &&
1886 !(m0 = m_pullup(m0, sizeof (struct ether_header))))
1887 continue;
1888
1889 eh = mtod(m0, struct ether_header *);
1890 ni = ieee80211_find_txnode(ic, eh->ether_dhost);
1891 if (ni == NULL) {
1892 m_freem(m0);
1893 ifp->if_oerrors++;
1894 continue;
1895 }
1896
1897 /* classify mbuf so we can find which tx ring to use */
1898 if (ieee80211_classify(ic, m0, ni) != 0) {
1899 m_freem(m0);
1900 ieee80211_free_node(ni);
1901 ifp->if_oerrors++;
1902 continue;
1903 }
1904
1905 /* no QoS encapsulation for EAPOL frames */
1906 ac = (eh->ether_type != htons(ETHERTYPE_PAE)) ?
1907 M_WME_GETAC(m0) : WME_AC_BE;
1908
1909 if (sc->txq[ac].queued >= RT2661_TX_RING_COUNT - 1) {
1910 /* there is no place left in this ring */
1911 ifp->if_flags |= IFF_OACTIVE;
1912 m_freem(m0);
1913 ieee80211_free_node(ni);
1914 break;
1915 }
1916
1917 BPF_MTAP(ifp, m0);
1918
1919 m0 = ieee80211_encap(ic, m0, ni);
1920 if (m0 == NULL) {
1921 ieee80211_free_node(ni);
1922 ifp->if_oerrors++;
1923 continue;
1924 }
1925
1926 if (ic->ic_rawbpf != NULL)
1927 bpf_mtap(ic->ic_rawbpf, m0);
1928
1929 if (rt2661_tx_data(sc, m0, ni, ac) != 0) {
1930 ieee80211_free_node(ni);
1931 ifp->if_oerrors++;
1932 break;
1933 }
1934 }
1935
1936 sc->sc_tx_timer = 5;
1937 ifp->if_timer = 1;
1938 }
1939 }
1940
1941 static void
1942 rt2661_watchdog(struct ifnet *ifp)
1943 {
1944 struct rt2661_softc *sc = ifp->if_softc;
1945 struct ieee80211com *ic = &sc->sc_ic;
1946
1947 ifp->if_timer = 0;
1948
1949 if (sc->sc_tx_timer > 0) {
1950 if (--sc->sc_tx_timer == 0) {
1951 device_printf(sc->sc_dev, "device timeout\n");
1952 rt2661_init(sc);
1953 ifp->if_oerrors++;
1954 return;
1955 }
1956 ifp->if_timer = 1;
1957 }
1958
1959 ieee80211_watchdog(ic);
1960 }
1961
1962 /*
1963 * This function allows for fast channel switching in monitor mode (used by
1964 * net-mgmt/kismet). In IBSS mode, we must explicitly reset the interface to
1965 * generate a new beacon frame.
1966 */
1967 static int
1968 rt2661_reset(struct ifnet *ifp)
1969 {
1970 struct rt2661_softc *sc = ifp->if_softc;
1971 struct ieee80211com *ic = &sc->sc_ic;
1972
1973 if (ic->ic_opmode != IEEE80211_M_MONITOR)
1974 return ENETRESET;
1975
1976 rt2661_set_chan(sc, ic->ic_curchan);
1977
1978 return 0;
1979 }
1980
1981 static int
1982 rt2661_ioctl(struct ifnet *ifp, u_long cmd, caddr_t data, struct ucred *cr)
1983 {
1984 struct rt2661_softc *sc = ifp->if_softc;
1985 struct ieee80211com *ic = &sc->sc_ic;
1986 int error = 0;
1987
1988 switch (cmd) {
1989 case SIOCSIFFLAGS:
1990 if (ifp->if_flags & IFF_UP) {
1991 if (ifp->if_flags & IFF_RUNNING)
1992 rt2661_update_promisc(sc);
1993 else
1994 rt2661_init(sc);
1995 } else {
1996 if (ifp->if_flags & IFF_RUNNING)
1997 rt2661_stop(sc);
1998 }
1999 break;
2000
2001 default:
2002 error = ieee80211_ioctl(ic, cmd, data, cr);
2003 }
2004
2005 if (error == ENETRESET) {
2006 if ((ifp->if_flags & (IFF_UP | IFF_RUNNING)) ==
2007 (IFF_UP | IFF_RUNNING) &&
2008 (ic->ic_roaming != IEEE80211_ROAMING_MANUAL))
2009 rt2661_init(sc);
2010 error = 0;
2011 }
2012 return error;
2013 }
2014
2015 static void
2016 rt2661_bbp_write(struct rt2661_softc *sc, uint8_t reg, uint8_t val)
2017 {
2018 uint32_t tmp;
2019 int ntries;
2020
2021 for (ntries = 0; ntries < 100; ntries++) {
2022 if (!(RAL_READ(sc, RT2661_PHY_CSR3) & RT2661_BBP_BUSY))
2023 break;
2024 DELAY(1);
2025 }
2026 if (ntries == 100) {
2027 device_printf(sc->sc_dev, "could not write to BBP\n");
2028 return;
2029 }
2030
2031 tmp = RT2661_BBP_BUSY | (reg & 0x7f) << 8 | val;
2032 RAL_WRITE(sc, RT2661_PHY_CSR3, tmp);
2033
2034 DPRINTFN(15, ("BBP R%u <- 0x%02x\n", reg, val));
2035 }
2036
2037 static uint8_t
2038 rt2661_bbp_read(struct rt2661_softc *sc, uint8_t reg)
2039 {
2040 uint32_t val;
2041 int ntries;
2042
2043 for (ntries = 0; ntries < 100; ntries++) {
2044 if (!(RAL_READ(sc, RT2661_PHY_CSR3) & RT2661_BBP_BUSY))
2045 break;
2046 DELAY(1);
2047 }
2048 if (ntries == 100) {
2049 device_printf(sc->sc_dev, "could not read from BBP\n");
2050 return 0;
2051 }
2052
2053 val = RT2661_BBP_BUSY | RT2661_BBP_READ | reg << 8;
2054 RAL_WRITE(sc, RT2661_PHY_CSR3, val);
2055
2056 for (ntries = 0; ntries < 100; ntries++) {
2057 val = RAL_READ(sc, RT2661_PHY_CSR3);
2058 if (!(val & RT2661_BBP_BUSY))
2059 return val & 0xff;
2060 DELAY(1);
2061 }
2062
2063 device_printf(sc->sc_dev, "could not read from BBP\n");
2064 return 0;
2065 }
2066
2067 static void
2068 rt2661_rf_write(struct rt2661_softc *sc, uint8_t reg, uint32_t val)
2069 {
2070 uint32_t tmp;
2071 int ntries;
2072
2073 for (ntries = 0; ntries < 100; ntries++) {
2074 if (!(RAL_READ(sc, RT2661_PHY_CSR4) & RT2661_RF_BUSY))
2075 break;
2076 DELAY(1);
2077 }
2078 if (ntries == 100) {
2079 device_printf(sc->sc_dev, "could not write to RF\n");
2080 return;
2081 }
2082
2083 tmp = RT2661_RF_BUSY | RT2661_RF_21BIT | (val & 0x1fffff) << 2 |
2084 (reg & 3);
2085 RAL_WRITE(sc, RT2661_PHY_CSR4, tmp);
2086
2087 /* remember last written value in sc */
2088 sc->rf_regs[reg] = val;
2089
2090 DPRINTFN(15, ("RF R[%u] <- 0x%05x\n", reg & 3, val & 0x1fffff));
2091 }
2092
2093 static int
2094 rt2661_tx_cmd(struct rt2661_softc *sc, uint8_t cmd, uint16_t arg)
2095 {
2096 if (RAL_READ(sc, RT2661_H2M_MAILBOX_CSR) & RT2661_H2M_BUSY)
2097 return EIO; /* there is already a command pending */
2098
2099 RAL_WRITE(sc, RT2661_H2M_MAILBOX_CSR,
2100 RT2661_H2M_BUSY | RT2661_TOKEN_NO_INTR << 16 | arg);
2101
2102 RAL_WRITE(sc, RT2661_HOST_CMD_CSR, RT2661_KICK_CMD | cmd);
2103
2104 return 0;
2105 }
2106
2107 static void
2108 rt2661_select_antenna(struct rt2661_softc *sc)
2109 {
2110 uint8_t bbp4, bbp77;
2111 uint32_t tmp;
2112
2113 bbp4 = rt2661_bbp_read(sc, 4);
2114 bbp77 = rt2661_bbp_read(sc, 77);
2115
2116 /* TBD */
2117
2118 /* make sure Rx is disabled before switching antenna */
2119 tmp = RAL_READ(sc, RT2661_TXRX_CSR0);
2120 RAL_WRITE(sc, RT2661_TXRX_CSR0, tmp | RT2661_DISABLE_RX);
2121
2122 rt2661_bbp_write(sc, 4, bbp4);
2123 rt2661_bbp_write(sc, 77, bbp77);
2124
2125 /* restore Rx filter */
2126 RAL_WRITE(sc, RT2661_TXRX_CSR0, tmp);
2127 }
2128
2129 /*
2130 * Enable multi-rate retries for frames sent at OFDM rates.
2131 * In 802.11b/g mode, allow fallback to CCK rates.
2132 */
2133 static void
2134 rt2661_enable_mrr(struct rt2661_softc *sc)
2135 {
2136 struct ieee80211com *ic = &sc->sc_ic;
2137 uint32_t tmp;
2138
2139 tmp = RAL_READ(sc, RT2661_TXRX_CSR4);
2140
2141 tmp &= ~RT2661_MRR_CCK_FALLBACK;
2142 if (!IEEE80211_IS_CHAN_5GHZ(ic->ic_bss->ni_chan))
2143 tmp |= RT2661_MRR_CCK_FALLBACK;
2144 tmp |= RT2661_MRR_ENABLED;
2145
2146 RAL_WRITE(sc, RT2661_TXRX_CSR4, tmp);
2147 }
2148
2149 static void
2150 rt2661_set_txpreamble(struct rt2661_softc *sc)
2151 {
2152 uint32_t tmp;
2153
2154 tmp = RAL_READ(sc, RT2661_TXRX_CSR4);
2155
2156 tmp &= ~RT2661_SHORT_PREAMBLE;
2157 if (sc->sc_ic.ic_flags & IEEE80211_F_SHPREAMBLE)
2158 tmp |= RT2661_SHORT_PREAMBLE;
2159
2160 RAL_WRITE(sc, RT2661_TXRX_CSR4, tmp);
2161 }
2162
2163 static void
2164 rt2661_set_basicrates(struct rt2661_softc *sc,
2165 const struct ieee80211_rateset *rs)
2166 {
2167 #define RV(r) ((r) & IEEE80211_RATE_VAL)
2168 uint32_t mask = 0;
2169 uint8_t rate;
2170 int i, j;
2171
2172 for (i = 0; i < rs->rs_nrates; i++) {
2173 rate = rs->rs_rates[i];
2174
2175 if (!(rate & IEEE80211_RATE_BASIC))
2176 continue;
2177
2178 /*
2179 * Find h/w rate index. We know it exists because the rate
2180 * set has already been negotiated.
2181 */
2182 for (j = 0; rt2661_rateset_11g.rs_rates[j] != RV(rate); j++);
2183
2184 mask |= 1 << j;
2185 }
2186
2187 RAL_WRITE(sc, RT2661_TXRX_CSR5, mask);
2188
2189 DPRINTF(("Setting basic rate mask to 0x%x\n", mask));
2190 #undef RV
2191 }
2192
2193 /*
2194 * Reprogram MAC/BBP to switch to a new band. Values taken from the reference
2195 * driver.
2196 */
2197 static void
2198 rt2661_select_band(struct rt2661_softc *sc, struct ieee80211_channel *c)
2199 {
2200 uint8_t bbp17, bbp35, bbp96, bbp97, bbp98, bbp104;
2201 uint32_t tmp;
2202
2203 /* update all BBP registers that depend on the band */
2204 bbp17 = 0x20; bbp96 = 0x48; bbp104 = 0x2c;
2205 bbp35 = 0x50; bbp97 = 0x48; bbp98 = 0x48;
2206 if (IEEE80211_IS_CHAN_5GHZ(c)) {
2207 bbp17 += 0x08; bbp96 += 0x10; bbp104 += 0x0c;
2208 bbp35 += 0x10; bbp97 += 0x10; bbp98 += 0x10;
2209 }
2210 if ((IEEE80211_IS_CHAN_2GHZ(c) && sc->ext_2ghz_lna) ||
2211 (IEEE80211_IS_CHAN_5GHZ(c) && sc->ext_5ghz_lna)) {
2212 bbp17 += 0x10; bbp96 += 0x10; bbp104 += 0x10;
2213 }
2214
2215 rt2661_bbp_write(sc, 17, bbp17);
2216 rt2661_bbp_write(sc, 96, bbp96);
2217 rt2661_bbp_write(sc, 104, bbp104);
2218
2219 if ((IEEE80211_IS_CHAN_2GHZ(c) && sc->ext_2ghz_lna) ||
2220 (IEEE80211_IS_CHAN_5GHZ(c) && sc->ext_5ghz_lna)) {
2221 rt2661_bbp_write(sc, 75, 0x80);
2222 rt2661_bbp_write(sc, 86, 0x80);
2223 rt2661_bbp_write(sc, 88, 0x80);
2224 }
2225
2226 rt2661_bbp_write(sc, 35, bbp35);
2227 rt2661_bbp_write(sc, 97, bbp97);
2228 rt2661_bbp_write(sc, 98, bbp98);
2229
2230 tmp = RAL_READ(sc, RT2661_PHY_CSR0);
2231 tmp &= ~(RT2661_PA_PE_2GHZ | RT2661_PA_PE_5GHZ);
2232 if (IEEE80211_IS_CHAN_2GHZ(c))
2233 tmp |= RT2661_PA_PE_2GHZ;
2234 else
2235 tmp |= RT2661_PA_PE_5GHZ;
2236 RAL_WRITE(sc, RT2661_PHY_CSR0, tmp);
2237 }
2238
2239 static void
2240 rt2661_set_chan(struct rt2661_softc *sc, struct ieee80211_channel *c)
2241 {
2242 struct ieee80211com *ic = &sc->sc_ic;
2243 const struct rfprog *rfprog;
2244 uint8_t bbp3, bbp94 = RT2661_BBPR94_DEFAULT;
2245 int8_t power;
2246 u_int i, chan;
2247
2248 chan = ieee80211_chan2ieee(ic, c);
2249 if (chan == 0 || chan == IEEE80211_CHAN_ANY)
2250 return;
2251
2252 /* select the appropriate RF settings based on what EEPROM says */
2253 rfprog = (sc->rfprog == 0) ? rt2661_rf5225_1 : rt2661_rf5225_2;
2254
2255 /* find the settings for this channel (we know it exists) */
2256 for (i = 0; rfprog[i].chan != chan; i++);
2257
2258 power = sc->txpow[i];
2259 if (power < 0) {
2260 bbp94 += power;
2261 power = 0;
2262 } else if (power > 31) {
2263 bbp94 += power - 31;
2264 power = 31;
2265 }
2266
2267 /*
2268 * If we are switching from the 2GHz band to the 5GHz band or
2269 * vice-versa, BBP registers need to be reprogrammed.
2270 */
2271 if (c->ic_flags != sc->sc_curchan->ic_flags) {
2272 rt2661_select_band(sc, c);
2273 rt2661_select_antenna(sc);
2274 }
2275 sc->sc_curchan = c;
2276
2277 rt2661_rf_write(sc, RAL_RF1, rfprog[i].r1);
2278 rt2661_rf_write(sc, RAL_RF2, rfprog[i].r2);
2279 rt2661_rf_write(sc, RAL_RF3, rfprog[i].r3 | power << 7);
2280 rt2661_rf_write(sc, RAL_RF4, rfprog[i].r4 | sc->rffreq << 10);
2281
2282 DELAY(200);
2283
2284 rt2661_rf_write(sc, RAL_RF1, rfprog[i].r1);
2285 rt2661_rf_write(sc, RAL_RF2, rfprog[i].r2);
2286 rt2661_rf_write(sc, RAL_RF3, rfprog[i].r3 | power << 7 | 1);
2287 rt2661_rf_write(sc, RAL_RF4, rfprog[i].r4 | sc->rffreq << 10);
2288
2289 DELAY(200);
2290
2291 rt2661_rf_write(sc, RAL_RF1, rfprog[i].r1);
2292 rt2661_rf_write(sc, RAL_RF2, rfprog[i].r2);
2293 rt2661_rf_write(sc, RAL_RF3, rfprog[i].r3 | power << 7);
2294 rt2661_rf_write(sc, RAL_RF4, rfprog[i].r4 | sc->rffreq << 10);
2295
2296 /* enable smart mode for MIMO-capable RFs */
2297 bbp3 = rt2661_bbp_read(sc, 3);
2298
2299 bbp3 &= ~RT2661_SMART_MODE;
2300 if (sc->rf_rev == RT2661_RF_5325 || sc->rf_rev == RT2661_RF_2529)
2301 bbp3 |= RT2661_SMART_MODE;
2302
2303 rt2661_bbp_write(sc, 3, bbp3);
2304
2305 if (bbp94 != RT2661_BBPR94_DEFAULT)
2306 rt2661_bbp_write(sc, 94, bbp94);
2307
2308 /* 5GHz radio needs a 1ms delay here */
2309 if (IEEE80211_IS_CHAN_5GHZ(c))
2310 DELAY(1000);
2311 }
2312
2313 static void
2314 rt2661_set_bssid(struct rt2661_softc *sc, const uint8_t *bssid)
2315 {
2316 uint32_t tmp;
2317
2318 tmp = bssid[0] | bssid[1] << 8 | bssid[2] << 16 | bssid[3] << 24;
2319 RAL_WRITE(sc, RT2661_MAC_CSR4, tmp);
2320
2321 tmp = bssid[4] | bssid[5] << 8 | RT2661_ONE_BSSID << 16;
2322 RAL_WRITE(sc, RT2661_MAC_CSR5, tmp);
2323 }
2324
2325 static void
2326 rt2661_set_macaddr(struct rt2661_softc *sc, const uint8_t *addr)
2327 {
2328 uint32_t tmp;
2329
2330 tmp = addr[0] | addr[1] << 8 | addr[2] << 16 | addr[3] << 24;
2331 RAL_WRITE(sc, RT2661_MAC_CSR2, tmp);
2332
2333 tmp = addr[4] | addr[5] << 8;
2334 RAL_WRITE(sc, RT2661_MAC_CSR3, tmp);
2335 }
2336
2337 static void
2338 rt2661_update_promisc(struct rt2661_softc *sc)
2339 {
2340 struct ifnet *ifp = sc->sc_ic.ic_ifp;
2341 uint32_t tmp;
2342
2343 tmp = RAL_READ(sc, RT2661_TXRX_CSR0);
2344
2345 tmp &= ~RT2661_DROP_NOT_TO_ME;
2346 if (!(ifp->if_flags & IFF_PROMISC))
2347 tmp |= RT2661_DROP_NOT_TO_ME;
2348
2349 RAL_WRITE(sc, RT2661_TXRX_CSR0, tmp);
2350
2351 DPRINTF(("%s promiscuous mode\n", (ifp->if_flags & IFF_PROMISC) ?
2352 "entering" : "leaving"));
2353 }
2354
2355 /*
2356 * Update QoS (802.11e) settings for each h/w Tx ring.
2357 */
2358 static int
2359 rt2661_wme_update(struct ieee80211com *ic)
2360 {
2361 struct rt2661_softc *sc = ic->ic_ifp->if_softc;
2362 const struct wmeParams *wmep;
2363
2364 wmep = ic->ic_wme.wme_chanParams.cap_wmeParams;
2365
2366 /* XXX: not sure about shifts. */
2367 /* XXX: the reference driver plays with AC_VI settings too. */
2368
2369 /* update TxOp */
2370 RAL_WRITE(sc, RT2661_AC_TXOP_CSR0,
2371 wmep[WME_AC_BE].wmep_txopLimit << 16 |
2372 wmep[WME_AC_BK].wmep_txopLimit);
2373 RAL_WRITE(sc, RT2661_AC_TXOP_CSR1,
2374 wmep[WME_AC_VI].wmep_txopLimit << 16 |
2375 wmep[WME_AC_VO].wmep_txopLimit);
2376
2377 /* update CWmin */
2378 RAL_WRITE(sc, RT2661_CWMIN_CSR,
2379 wmep[WME_AC_BE].wmep_logcwmin << 12 |
2380 wmep[WME_AC_BK].wmep_logcwmin << 8 |
2381 wmep[WME_AC_VI].wmep_logcwmin << 4 |
2382 wmep[WME_AC_VO].wmep_logcwmin);
2383
2384 /* update CWmax */
2385 RAL_WRITE(sc, RT2661_CWMAX_CSR,
2386 wmep[WME_AC_BE].wmep_logcwmax << 12 |
2387 wmep[WME_AC_BK].wmep_logcwmax << 8 |
2388 wmep[WME_AC_VI].wmep_logcwmax << 4 |
2389 wmep[WME_AC_VO].wmep_logcwmax);
2390
2391 /* update Aifsn */
2392 RAL_WRITE(sc, RT2661_AIFSN_CSR,
2393 wmep[WME_AC_BE].wmep_aifsn << 12 |
2394 wmep[WME_AC_BK].wmep_aifsn << 8 |
2395 wmep[WME_AC_VI].wmep_aifsn << 4 |
2396 wmep[WME_AC_VO].wmep_aifsn);
2397
2398 return 0;
2399 }
2400
2401 static void
2402 rt2661_update_slot(struct ifnet *ifp)
2403 {
2404 struct rt2661_softc *sc = ifp->if_softc;
2405 struct ieee80211com *ic = &sc->sc_ic;
2406 uint8_t slottime;
2407 uint32_t tmp;
2408
2409 slottime = (ic->ic_flags & IEEE80211_F_SHSLOT) ? 9 : 20;
2410
2411 tmp = RAL_READ(sc, RT2661_MAC_CSR9);
2412 tmp = (tmp & ~0xff) | slottime;
2413 RAL_WRITE(sc, RT2661_MAC_CSR9, tmp);
2414 }
2415
2416 static const char *
2417 rt2661_get_rf(int rev)
2418 {
2419 switch (rev) {
2420 case RT2661_RF_5225: return "RT5225";
2421 case RT2661_RF_5325: return "RT5325 (MIMO XR)";
2422 case RT2661_RF_2527: return "RT2527";
2423 case RT2661_RF_2529: return "RT2529 (MIMO XR)";
2424 default: return "unknown";
2425 }
2426 }
2427
2428 static void
2429 rt2661_read_eeprom(struct rt2661_softc *sc)
2430 {
2431 struct ieee80211com *ic = &sc->sc_ic;
2432 uint16_t val;
2433 int i;
2434
2435 /* read MAC address */
2436 val = rt2661_eeprom_read(sc, RT2661_EEPROM_MAC01);
2437 ic->ic_myaddr[0] = val & 0xff;
2438 ic->ic_myaddr[1] = val >> 8;
2439
2440 val = rt2661_eeprom_read(sc, RT2661_EEPROM_MAC23);
2441 ic->ic_myaddr[2] = val & 0xff;
2442 ic->ic_myaddr[3] = val >> 8;
2443
2444 val = rt2661_eeprom_read(sc, RT2661_EEPROM_MAC45);
2445 ic->ic_myaddr[4] = val & 0xff;
2446 ic->ic_myaddr[5] = val >> 8;
2447
2448 val = rt2661_eeprom_read(sc, RT2661_EEPROM_ANTENNA);
2449 /* XXX: test if different from 0xffff? */
2450 sc->rf_rev = (val >> 11) & 0x1f;
2451 sc->hw_radio = (val >> 10) & 0x1;
2452 sc->rx_ant = (val >> 4) & 0x3;
2453 sc->tx_ant = (val >> 2) & 0x3;
2454 sc->nb_ant = val & 0x3;
2455
2456 DPRINTF(("RF revision=%d\n", sc->rf_rev));
2457
2458 val = rt2661_eeprom_read(sc, RT2661_EEPROM_CONFIG2);
2459 sc->ext_5ghz_lna = (val >> 6) & 0x1;
2460 sc->ext_2ghz_lna = (val >> 4) & 0x1;
2461
2462 DPRINTF(("External 2GHz LNA=%d\nExternal 5GHz LNA=%d\n",
2463 sc->ext_2ghz_lna, sc->ext_5ghz_lna));
2464
2465 val = rt2661_eeprom_read(sc, RT2661_EEPROM_RSSI_2GHZ_OFFSET);
2466 if ((val & 0xff) != 0xff)
2467 sc->rssi_2ghz_corr = (int8_t)(val & 0xff); /* signed */
2468
2469 val = rt2661_eeprom_read(sc, RT2661_EEPROM_RSSI_5GHZ_OFFSET);
2470 if ((val & 0xff) != 0xff)
2471 sc->rssi_5ghz_corr = (int8_t)(val & 0xff); /* signed */
2472
2473 /* adjust RSSI correction for external low-noise amplifier */
2474 if (sc->ext_2ghz_lna)
2475 sc->rssi_2ghz_corr -= 14;
2476 if (sc->ext_5ghz_lna)
2477 sc->rssi_5ghz_corr -= 14;
2478
2479 DPRINTF(("RSSI 2GHz corr=%d\nRSSI 5GHz corr=%d\n",
2480 sc->rssi_2ghz_corr, sc->rssi_5ghz_corr));
2481
2482 val = rt2661_eeprom_read(sc, RT2661_EEPROM_FREQ_OFFSET);
2483 if ((val >> 8) != 0xff)
2484 sc->rfprog = (val >> 8) & 0x3;
2485 if ((val & 0xff) != 0xff)
2486 sc->rffreq = val & 0xff;
2487
2488 DPRINTF(("RF prog=%d\nRF freq=%d\n", sc->rfprog, sc->rffreq));
2489
2490 /* read Tx power for all a/b/g channels */
2491 for (i = 0; i < 19; i++) {
2492 val = rt2661_eeprom_read(sc, RT2661_EEPROM_TXPOWER + i);
2493 sc->txpow[i * 2] = (int8_t)(val >> 8); /* signed */
2494 DPRINTF(("Channel=%d Tx power=%d\n",
2495 rt2661_rf5225_1[i * 2].chan, sc->txpow[i * 2]));
2496 sc->txpow[i * 2 + 1] = (int8_t)(val & 0xff); /* signed */
2497 DPRINTF(("Channel=%d Tx power=%d\n",
2498 rt2661_rf5225_1[i * 2 + 1].chan, sc->txpow[i * 2 + 1]));
2499 }
2500
2501 /* read vendor-specific BBP values */
2502 for (i = 0; i < 16; i++) {
2503 val = rt2661_eeprom_read(sc, RT2661_EEPROM_BBP_BASE + i);
2504 if (val == 0 || val == 0xffff)
2505 continue; /* skip invalid entries */
2506 sc->bbp_prom[i].reg = val >> 8;
2507 sc->bbp_prom[i].val = val & 0xff;
2508 DPRINTF(("BBP R%d=%02x\n", sc->bbp_prom[i].reg,
2509 sc->bbp_prom[i].val));
2510 }
2511
2512 val = rt2661_eeprom_read(sc, RT2661_EEPROM_LED_OFFSET);
2513 DPRINTF(("LED %02x\n", val));
2514 if (val == 0xffff) {
2515 sc->mcu_led = RT2661_MCU_LED_DEFAULT;
2516 } else {
2517 #define N(arr) (int)(sizeof(arr) / sizeof(arr[0]))
2518
2519 for (i = 0; i < N(led_ee2mcu); ++i) {
2520 if (val & led_ee2mcu[i].ee_bit)
2521 sc->mcu_led |= led_ee2mcu[i].mcu_bit;
2522 }
2523
2524 #undef N
2525
2526 sc->mcu_led |= ((val >> RT2661_EE_LED_MODE_SHIFT) &
2527 RT2661_EE_LED_MODE_MASK);
2528 }
2529 }
2530
2531 static int
2532 rt2661_bbp_init(struct rt2661_softc *sc)
2533 {
2534 #define N(a) (sizeof (a) / sizeof ((a)[0]))
2535 int i, ntries;
2536 uint8_t val;
2537
2538 /* wait for BBP to be ready */
2539 for (ntries = 0; ntries < 100; ntries++) {
2540 val = rt2661_bbp_read(sc, 0);
2541 if (val != 0 && val != 0xff)
2542 break;
2543 DELAY(100);
2544 }
2545 if (ntries == 100) {
2546 device_printf(sc->sc_dev, "timeout waiting for BBP\n");
2547 return EIO;
2548 }
2549
2550 /* initialize BBP registers to default values */
2551 for (i = 0; i < N(rt2661_def_bbp); i++) {
2552 rt2661_bbp_write(sc, rt2661_def_bbp[i].reg,
2553 rt2661_def_bbp[i].val);
2554 }
2555
2556 /* write vendor-specific BBP values (from EEPROM) */
2557 for (i = 0; i < 16; i++) {
2558 if (sc->bbp_prom[i].reg == 0)
2559 continue;
2560 rt2661_bbp_write(sc, sc->bbp_prom[i].reg, sc->bbp_prom[i].val);
2561 }
2562
2563 return 0;
2564 #undef N
2565 }
2566
2567 static void
2568 rt2661_init(void *priv)
2569 {
2570 #define N(a) (sizeof (a) / sizeof ((a)[0]))
2571 struct rt2661_softc *sc = priv;
2572 struct ieee80211com *ic = &sc->sc_ic;
2573 struct ifnet *ifp = ic->ic_ifp;
2574 uint32_t tmp, sta[3];
2575 int i, ntries;
2576
2577 rt2661_stop(sc);
2578
2579 /* initialize Tx rings */
2580 RAL_WRITE(sc, RT2661_AC1_BASE_CSR, sc->txq[1].physaddr);
2581 RAL_WRITE(sc, RT2661_AC0_BASE_CSR, sc->txq[0].physaddr);
2582 RAL_WRITE(sc, RT2661_AC2_BASE_CSR, sc->txq[2].physaddr);
2583 RAL_WRITE(sc, RT2661_AC3_BASE_CSR, sc->txq[3].physaddr);
2584
2585 /* initialize Mgt ring */
2586 RAL_WRITE(sc, RT2661_MGT_BASE_CSR, sc->mgtq.physaddr);
2587
2588 /* initialize Rx ring */
2589 RAL_WRITE(sc, RT2661_RX_BASE_CSR, sc->rxq.physaddr);
2590
2591 /* initialize Tx rings sizes */
2592 RAL_WRITE(sc, RT2661_TX_RING_CSR0,
2593 RT2661_TX_RING_COUNT << 24 |
2594 RT2661_TX_RING_COUNT << 16 |
2595 RT2661_TX_RING_COUNT << 8 |
2596 RT2661_TX_RING_COUNT);
2597
2598 RAL_WRITE(sc, RT2661_TX_RING_CSR1,
2599 RT2661_TX_DESC_WSIZE << 16 |
2600 RT2661_TX_RING_COUNT << 8 | /* XXX: HCCA ring unused */
2601 RT2661_MGT_RING_COUNT);
2602
2603 /* initialize Rx rings */
2604 RAL_WRITE(sc, RT2661_RX_RING_CSR,
2605 RT2661_RX_DESC_BACK << 16 |
2606 RT2661_RX_DESC_WSIZE << 8 |
2607 RT2661_RX_RING_COUNT);
2608
2609 /* XXX: some magic here */
2610 RAL_WRITE(sc, RT2661_TX_DMA_DST_CSR, 0xaa);
2611
2612 /* load base addresses of all 5 Tx rings (4 data + 1 mgt) */
2613 RAL_WRITE(sc, RT2661_LOAD_TX_RING_CSR, 0x1f);
2614
2615 /* load base address of Rx ring */
2616 RAL_WRITE(sc, RT2661_RX_CNTL_CSR, 2);
2617
2618 /* initialize MAC registers to default values */
2619 for (i = 0; i < N(rt2661_def_mac); i++)
2620 RAL_WRITE(sc, rt2661_def_mac[i].reg, rt2661_def_mac[i].val);
2621
2622 IEEE80211_ADDR_COPY(ic->ic_myaddr, IF_LLADDR(ifp));
2623 rt2661_set_macaddr(sc, ic->ic_myaddr);
2624
2625 /* set host ready */
2626 RAL_WRITE(sc, RT2661_MAC_CSR1, 3);
2627 RAL_WRITE(sc, RT2661_MAC_CSR1, 0);
2628
2629 /* wait for BBP/RF to wakeup */
2630 for (ntries = 0; ntries < 1000; ntries++) {
2631 if (RAL_READ(sc, RT2661_MAC_CSR12) & 8)
2632 break;
2633 DELAY(1000);
2634 }
2635 if (ntries == 1000) {
2636 kprintf("timeout waiting for BBP/RF to wakeup\n");
2637 rt2661_stop(sc);
2638 return;
2639 }
2640
2641 if (rt2661_bbp_init(sc) != 0) {
2642 rt2661_stop(sc);
2643 return;
2644 }
2645
2646 /* select default channel */
2647 sc->sc_curchan = ic->ic_curchan;
2648 rt2661_select_band(sc, sc->sc_curchan);
2649 rt2661_select_antenna(sc);
2650 rt2661_set_chan(sc, sc->sc_curchan);
2651
2652 /* update Rx filter */
2653 tmp = RAL_READ(sc, RT2661_TXRX_CSR0) & 0xffff;
2654
2655 tmp |= RT2661_DROP_PHY_ERROR | RT2661_DROP_CRC_ERROR;
2656 if (ic->ic_opmode != IEEE80211_M_MONITOR) {
2657 tmp |= RT2661_DROP_CTL | RT2661_DROP_VER_ERROR |
2658 RT2661_DROP_ACKCTS;
2659 if (ic->ic_opmode != IEEE80211_M_HOSTAP)
2660 tmp |= RT2661_DROP_TODS;
2661 if (!(ifp->if_flags & IFF_PROMISC))
2662 tmp |= RT2661_DROP_NOT_TO_ME;
2663 }
2664
2665 RAL_WRITE(sc, RT2661_TXRX_CSR0, tmp);
2666
2667 /* clear STA registers */
2668 RAL_READ_REGION_4(sc, RT2661_STA_CSR0, sta, N(sta));
2669
2670 /* initialize ASIC */
2671 RAL_WRITE(sc, RT2661_MAC_CSR1, 4);
2672
2673 /* clear any pending interrupt */
2674 RAL_WRITE(sc, RT2661_INT_SOURCE_CSR, 0xffffffff);
2675
2676 /* enable interrupts */
2677 RAL_WRITE(sc, RT2661_INT_MASK_CSR, 0x0000ff10);
2678 RAL_WRITE(sc, RT2661_MCU_INT_MASK_CSR, 0);
2679
2680 /* kick Rx */
2681 RAL_WRITE(sc, RT2661_RX_CNTL_CSR, 1);
2682
2683 ifp->if_flags &= ~IFF_OACTIVE;
2684 ifp->if_flags |= IFF_RUNNING;
2685
2686 if (ic->ic_opmode != IEEE80211_M_MONITOR) {
2687 if (ic->ic_roaming != IEEE80211_ROAMING_MANUAL)
2688 ieee80211_new_state(ic, IEEE80211_S_SCAN, -1);
2689 } else
2690 ieee80211_new_state(ic, IEEE80211_S_RUN, -1);
2691 #undef N
2692 }
2693
2694 void
2695 rt2661_stop(void *priv)
2696 {
2697 struct rt2661_softc *sc = priv;
2698 struct ieee80211com *ic = &sc->sc_ic;
2699 struct ifnet *ifp = ic->ic_ifp;
2700 struct rt2661_tx_ratectl *rctl;
2701 uint32_t tmp;
2702
2703 ieee80211_new_state(ic, IEEE80211_S_INIT, -1);
2704
2705 sc->sc_tx_timer = 0;
2706 ifp->if_timer = 0;
2707 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE);
2708
2709 /* abort Tx (for all 5 Tx rings) */
2710 RAL_WRITE(sc, RT2661_TX_CNTL_CSR, 0x1f << 16);
2711
2712 /* disable Rx (value remains after reset!) */
2713 tmp = RAL_READ(sc, RT2661_TXRX_CSR0);
2714 RAL_WRITE(sc, RT2661_TXRX_CSR0, tmp | RT2661_DISABLE_RX);
2715
2716 /* reset ASIC */
2717 RAL_WRITE(sc, RT2661_MAC_CSR1, 3);
2718 RAL_WRITE(sc, RT2661_MAC_CSR1, 0);
2719
2720 /* disable interrupts */
2721 RAL_WRITE(sc, RT2661_INT_MASK_CSR, 0xffffffff);
2722 RAL_WRITE(sc, RT2661_MCU_INT_MASK_CSR, 0xffffffff);
2723
2724 /* clear any pending interrupt */
2725 RAL_WRITE(sc, RT2661_INT_SOURCE_CSR, 0xffffffff);
2726 RAL_WRITE(sc, RT2661_MCU_INT_SOURCE_CSR, 0xffffffff);
2727
2728 while ((rctl = STAILQ_FIRST(&sc->tx_ratectl)) != NULL) {
2729 STAILQ_REMOVE_HEAD(&sc->tx_ratectl, link);
2730 ieee80211_free_node(rctl->ni);
2731 rctl->ni = NULL;
2732 kfree(rctl, M_RT2661);
2733 }
2734
2735 /* reset Tx and Rx rings */
2736 rt2661_reset_tx_ring(sc, &sc->txq[0]);
2737 rt2661_reset_tx_ring(sc, &sc->txq[1]);
2738 rt2661_reset_tx_ring(sc, &sc->txq[2]);
2739 rt2661_reset_tx_ring(sc, &sc->txq[3]);
2740 rt2661_reset_tx_ring(sc, &sc->mgtq);
2741 rt2661_reset_rx_ring(sc, &sc->rxq);
2742 }
2743
2744 static int
2745 rt2661_load_microcode(struct rt2661_softc *sc, const uint8_t *ucode, int size)
2746 {
2747 int ntries;
2748
2749 /* reset 8051 */
2750 RAL_WRITE(sc, RT2661_MCU_CNTL_CSR, RT2661_MCU_RESET);
2751
2752 /* cancel any pending Host to MCU command */
2753 RAL_WRITE(sc, RT2661_H2M_MAILBOX_CSR, 0);
2754 RAL_WRITE(sc, RT2661_M2H_CMD_DONE_CSR, 0xffffffff);
2755 RAL_WRITE(sc, RT2661_HOST_CMD_CSR, 0);
2756
2757 /* write 8051's microcode */
2758 RAL_WRITE(sc, RT2661_MCU_CNTL_CSR, RT2661_MCU_RESET | RT2661_MCU_SEL);
2759 RAL_WRITE_REGION_1(sc, RT2661_MCU_CODE_BASE, ucode, size);
2760 RAL_WRITE(sc, RT2661_MCU_CNTL_CSR, RT2661_MCU_RESET);
2761
2762 /* kick 8051's ass */
2763 RAL_WRITE(sc, RT2661_MCU_CNTL_CSR, 0);
2764
2765 /* wait for 8051 to initialize */
2766 for (ntries = 0; ntries < 500; ntries++) {
2767 if (RAL_READ(sc, RT2661_MCU_CNTL_CSR) & RT2661_MCU_READY)
2768 break;
2769 DELAY(100);
2770 }
2771 if (ntries == 500) {
2772 kprintf("timeout waiting for MCU to initialize\n");
2773 return EIO;
2774 }
2775 return 0;
2776 }
2777
2778 #ifdef notyet
2779 /*
2780 * Dynamically tune Rx sensitivity (BBP register 17) based on average RSSI and
2781 * false CCA count. This function is called periodically (every seconds) when
2782 * in the RUN state. Values taken from the reference driver.
2783 */
2784 static void
2785 rt2661_rx_tune(struct rt2661_softc *sc)
2786 {
2787 uint8_t bbp17;
2788 uint16_t cca;
2789 int lo, hi, dbm;
2790
2791 /*
2792 * Tuning range depends on operating band and on the presence of an
2793 * external low-noise amplifier.
2794 */
2795 lo = 0x20;
2796 if (IEEE80211_IS_CHAN_5GHZ(sc->sc_curchan))
2797 lo += 0x08;
2798 if ((IEEE80211_IS_CHAN_2GHZ(sc->sc_curchan) && sc->ext_2ghz_lna) ||
2799 (IEEE80211_IS_CHAN_5GHZ(sc->sc_curchan) && sc->ext_5ghz_lna))
2800 lo += 0x10;
2801 hi = lo + 0x20;
2802
2803 /* retrieve false CCA count since last call (clear on read) */
2804 cca = RAL_READ(sc, RT2661_STA_CSR1) & 0xffff;
2805
2806 if (dbm >= -35) {
2807 bbp17 = 0x60;
2808 } else if (dbm >= -58) {
2809 bbp17 = hi;
2810 } else if (dbm >= -66) {
2811 bbp17 = lo + 0x10;
2812 } else if (dbm >= -74) {
2813 bbp17 = lo + 0x08;
2814 } else {
2815 /* RSSI < -74dBm, tune using false CCA count */
2816
2817 bbp17 = sc->bbp17; /* current value */
2818
2819 hi -= 2 * (-74 - dbm);
2820 if (hi < lo)
2821 hi = lo;
2822
2823 if (bbp17 > hi) {
2824 bbp17 = hi;
2825
2826 } else if (cca > 512) {
2827 if (++bbp17 > hi)
2828 bbp17 = hi;
2829 } else if (cca < 100) {
2830 if (--bbp17 < lo)
2831 bbp17 = lo;
2832 }
2833 }
2834
2835 if (bbp17 != sc->bbp17) {
2836 rt2661_bbp_write(sc, 17, bbp17);
2837 sc->bbp17 = bbp17;
2838 }
2839 }
2840
2841 /*
2842 * Enter/Leave radar detection mode.
2843 * This is for 802.11h additional regulatory domains.
2844 */
2845 static void
2846 rt2661_radar_start(struct rt2661_softc *sc)
2847 {
2848 uint32_t tmp;
2849
2850 /* disable Rx */
2851 tmp = RAL_READ(sc, RT2661_TXRX_CSR0);
2852 RAL_WRITE(sc, RT2661_TXRX_CSR0, tmp | RT2661_DISABLE_RX);
2853
2854 rt2661_bbp_write(sc, 82, 0x20);
2855 rt2661_bbp_write(sc, 83, 0x00);
2856 rt2661_bbp_write(sc, 84, 0x40);
2857
2858 /* save current BBP registers values */
2859 sc->bbp18 = rt2661_bbp_read(sc, 18);
2860 sc->bbp21 = rt2661_bbp_read(sc, 21);
2861 sc->bbp22 = rt2661_bbp_read(sc, 22);
2862 sc->bbp16 = rt2661_bbp_read(sc, 16);
2863 sc->bbp17 = rt2661_bbp_read(sc, 17);
2864 sc->bbp64 = rt2661_bbp_read(sc, 64);
2865
2866 rt2661_bbp_write(sc, 18, 0xff);
2867 rt2661_bbp_write(sc, 21, 0x3f);
2868 rt2661_bbp_write(sc, 22, 0x3f);
2869 rt2661_bbp_write(sc, 16, 0xbd);
2870 rt2661_bbp_write(sc, 17, sc->ext_5ghz_lna ? 0x44 : 0x34);
2871 rt2661_bbp_write(sc, 64, 0x21);
2872
2873 /* restore Rx filter */
2874 RAL_WRITE(sc, RT2661_TXRX_CSR0, tmp);
2875 }
2876
2877 static int
2878 rt2661_radar_stop(struct rt2661_softc *sc)
2879 {
2880 uint8_t bbp66;
2881
2882 /* read radar detection result */
2883 bbp66 = rt2661_bbp_read(sc, 66);
2884
2885 /* restore BBP registers values */
2886 rt2661_bbp_write(sc, 16, sc->bbp16);
2887 rt2661_bbp_write(sc, 17, sc->bbp17);
2888 rt2661_bbp_write(sc, 18, sc->bbp18);
2889 rt2661_bbp_write(sc, 21, sc->bbp21);
2890 rt2661_bbp_write(sc, 22, sc->bbp22);
2891 rt2661_bbp_write(sc, 64, sc->bbp64);
2892
2893 return bbp66 == 1;
2894 }
2895 #endif
2896
2897 static int
2898 rt2661_prepare_beacon(struct rt2661_softc *sc)
2899 {
2900 struct ieee80211com *ic = &sc->sc_ic;
2901 struct ieee80211_beacon_offsets bo;
2902 struct rt2661_tx_desc desc;
2903 struct mbuf *m0;
2904 int rate;
2905
2906 m0 = ieee80211_beacon_alloc(ic, ic->ic_bss, &bo);
2907 if (m0 == NULL) {
2908 device_printf(sc->sc_dev, "could not allocate beacon frame\n");
2909 return ENOBUFS;
2910 }
2911
2912 /* send beacons at the lowest available rate */
2913 rate = IEEE80211_IS_CHAN_5GHZ(ic->ic_bss->ni_chan) ? 12 : 2;
2914
2915 rt2661_setup_tx_desc(sc, &desc, RT2661_TX_TIMESTAMP, RT2661_TX_HWSEQ,
2916 m0->m_pkthdr.len, rate, NULL, 0, RT2661_QID_MGT, 0);
2917
2918 /* copy the first 24 bytes of Tx descriptor into NIC memory */
2919 RAL_WRITE_REGION_1(sc, RT2661_HW_BEACON_BASE0, (uint8_t *)&desc, 24);
2920
2921 /* copy beacon header and payload into NIC memory */
2922 RAL_WRITE_REGION_1(sc, RT2661_HW_BEACON_BASE0 + 24,
2923 mtod(m0, uint8_t *), m0->m_pkthdr.len);
2924
2925 m_freem(m0);
2926 return 0;
2927 }
2928
2929 /*
2930 * Enable TSF synchronization and tell h/w to start sending beacons for IBSS
2931 * and HostAP operating modes.
2932 */
2933 static void
2934 rt2661_enable_tsf_sync(struct rt2661_softc *sc)
2935 {
2936 struct ieee80211com *ic = &sc->sc_ic;
2937 uint32_t tmp;
2938
2939 if (ic->ic_opmode != IEEE80211_M_STA) {
2940 /*
2941 * Change default 16ms TBTT adjustment to 8ms.
2942 * Must be done before enabling beacon generation.
2943 */
2944 RAL_WRITE(sc, RT2661_TXRX_CSR10, 1 << 12 | 8);
2945 }
2946
2947 tmp = RAL_READ(sc, RT2661_TXRX_CSR9) & 0xff000000;
2948
2949 /* set beacon interval (in 1/16ms unit) */
2950 tmp |= ic->ic_bss->ni_intval * 16;
2951
2952 tmp |= RT2661_TSF_TICKING | RT2661_ENABLE_TBTT;
2953 if (ic->ic_opmode == IEEE80211_M_STA)
2954 tmp |= RT2661_TSF_MODE(1);
2955 else
2956 tmp |= RT2661_TSF_MODE(2) | RT2661_GENERATE_BEACON;
2957
2958 RAL_WRITE(sc, RT2661_TXRX_CSR9, tmp);
2959 }
2960
2961 /*
2962 * Retrieve the "Received Signal Strength Indicator" from the raw values
2963 * contained in Rx descriptors. The computation depends on which band the
2964 * frame was received. Correction values taken from the reference driver.
2965 */
2966 static int
2967 rt2661_get_rssi(struct rt2661_softc *sc, uint8_t raw)
2968 {
2969 int lna, agc, rssi;
2970
2971 lna = (raw >> 5) & 0x3;
2972 agc = raw & 0x1f;
2973
2974 rssi = (2 * agc) - RT2661_NOISE_FLOOR;
2975
2976 if (IEEE80211_IS_CHAN_2GHZ(sc->sc_curchan)) {
2977 rssi += sc->rssi_2ghz_corr;
2978
2979 if (lna == 1)
2980 rssi -= 64;
2981 else if (lna == 2)
2982 rssi -= 74;
2983 else if (lna == 3)
2984 rssi -= 90;
2985 } else {
2986 rssi += sc->rssi_5ghz_corr;
2987
2988 if (lna == 1)
2989 rssi -= 64;
2990 else if (lna == 2)
2991 rssi -= 86;
2992 else if (lna == 3)
2993 rssi -= 100;
2994 }
2995 return rssi;
2996 }
2997
2998 static void
2999 rt2661_dma_map_mbuf(void *arg, bus_dma_segment_t *seg, int nseg,
3000 bus_size_t map_size __unused, int error)
3001 {
3002 struct rt2661_dmamap *map = arg;
3003
3004 if (error)
3005 return;
3006
3007 KASSERT(nseg <= RT2661_MAX_SCATTER, ("too many DMA segments"));
3008
3009 bcopy(seg, map->segs, nseg * sizeof(bus_dma_segment_t));
3010 map->nseg = nseg;
3011 }
3012
3013 static void
3014 rt2661_led_newstate(struct rt2661_softc *sc, enum ieee80211_state nstate)
3015 {
3016 struct ieee80211com *ic = &sc->sc_ic;
3017 uint32_t off, on;
3018 uint32_t mail = sc->mcu_led;
3019
3020 if (RAL_READ(sc, RT2661_H2M_MAILBOX_CSR) & RT2661_H2M_BUSY) {
3021 DPRINTF(("%s failed\n", __func__));
3022 return;
3023 }
3024
3025 switch (nstate) {
3026 case IEEE80211_S_INIT:
3027 mail &= ~(RT2661_MCU_LED_LINKA | RT2661_MCU_LED_LINKG |
3028 RT2661_MCU_LED_RF);
3029 break;
3030 default:
3031 if (ic->ic_curchan == NULL)
3032 return;
3033
3034 on = RT2661_MCU_LED_LINKG;
3035 off = RT2661_MCU_LED_LINKA;
3036 if (IEEE80211_IS_CHAN_5GHZ(ic->ic_curchan)) {
3037 on = RT2661_MCU_LED_LINKA;
3038 off = RT2661_MCU_LED_LINKG;
3039 }
3040
3041 mail |= RT2661_MCU_LED_RF | on;
3042 mail &= ~off;
3043 break;
3044 }
3045
3046 RAL_WRITE(sc, RT2661_H2M_MAILBOX_CSR,
3047 RT2661_H2M_BUSY | RT2661_TOKEN_NO_INTR << 16 | mail);
3048 RAL_WRITE(sc, RT2661_HOST_CMD_CSR, RT2661_KICK_CMD | RT2661_MCU_SET_LED);
3049 }
DragonFly BSD