2 * Copyright (c) 2001 Alcove - Nicolas Souchu
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
8 * 1. Redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer.
10 * 2. Redistributions in binary form must reproduce the above copyright
11 * notice, this list of conditions and the following disclaimer in the
12 * documentation and/or other materials provided with the distribution.
14 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
15 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
16 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
17 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
18 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
19 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
20 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
21 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
22 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
23 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
26 * $FreeBSD: src/sys/isa/ppc.c,v 1.26.2.5 2001/10/02 05:21:45 nsouch Exp $
27 * $DragonFly: src/sys/dev/misc/ppc/ppc.c,v 1.15 2007/10/23 03:04:49 y0netan1 Exp $
33 #include <sys/param.h>
34 #include <sys/systm.h>
35 #include <sys/kernel.h>
37 #include <sys/malloc.h>
39 #include <sys/thread2.h>
43 #include <machine/clock.h>
44 #include <machine/vmparam.h>
46 #include <bus/isa/isareg.h>
47 #include <bus/isa/isavar.h>
49 #include <bus/ppbus/ppbconf.h>
50 #include <bus/ppbus/ppb_msq.h>
56 #define LOG_PPC(function, ppc, string) \
57 if (bootverbose) kprintf("%s: %s\n", function, string)
60 #define DEVTOSOFTC(dev) ((struct ppc_data *)device_get_softc(dev))
62 devclass_t ppc_devclass
;
64 static int ppc_probe(device_t dev
);
65 static int ppc_attach(device_t dev
);
66 static int ppc_read_ivar(device_t bus
, device_t dev
, int index
, uintptr_t *val
);
68 static void ppc_reset_epp(device_t
);
69 static void ppc_ecp_sync(device_t
);
70 static void ppcintr(void *arg
);
72 static int ppc_exec_microseq(device_t
, struct ppb_microseq
**);
73 static int ppc_setmode(device_t
, int);
75 static int ppc_read(device_t
, char *, int, int);
76 static int ppc_write(device_t
, char *, int, int);
78 static u_char
ppc_io(device_t
, int, u_char
*, int, u_char
);
80 static int ppc_setup_intr(device_t
, device_t
, struct resource
*, int,
81 void (*)(void *), void *, void **, lwkt_serialize_t
);
82 static int ppc_teardown_intr(device_t
, device_t
, struct resource
*, void *);
84 static device_method_t ppc_methods
[] = {
85 /* device interface */
86 DEVMETHOD(device_probe
, ppc_probe
),
87 DEVMETHOD(device_attach
, ppc_attach
),
90 DEVMETHOD(bus_read_ivar
, ppc_read_ivar
),
91 DEVMETHOD(bus_setup_intr
, ppc_setup_intr
),
92 DEVMETHOD(bus_teardown_intr
, ppc_teardown_intr
),
93 DEVMETHOD(bus_alloc_resource
, bus_generic_alloc_resource
),
96 DEVMETHOD(ppbus_io
, ppc_io
),
97 DEVMETHOD(ppbus_exec_microseq
, ppc_exec_microseq
),
98 DEVMETHOD(ppbus_reset_epp
, ppc_reset_epp
),
99 DEVMETHOD(ppbus_setmode
, ppc_setmode
),
100 DEVMETHOD(ppbus_ecp_sync
, ppc_ecp_sync
),
101 DEVMETHOD(ppbus_read
, ppc_read
),
102 DEVMETHOD(ppbus_write
, ppc_write
),
107 static driver_t ppc_driver
= {
110 sizeof(struct ppc_data
),
113 static char *ppc_models
[] = {
114 "SMC-like", "SMC FDC37C665GT", "SMC FDC37C666GT", "PC87332", "PC87306",
115 "82091AA", "Generic", "W83877F", "W83877AF", "Winbond", "PC87334",
116 "SMC FDC37C935", "PC87303", 0
119 /* list of available modes */
120 static char *ppc_avms
[] = {
121 "COMPATIBLE", "NIBBLE-only", "PS2-only", "PS2/NIBBLE", "EPP-only",
122 "EPP/NIBBLE", "EPP/PS2", "EPP/PS2/NIBBLE", "ECP-only",
123 "ECP/NIBBLE", "ECP/PS2", "ECP/PS2/NIBBLE", "ECP/EPP",
124 "ECP/EPP/NIBBLE", "ECP/EPP/PS2", "ECP/EPP/PS2/NIBBLE", 0
127 /* list of current executing modes
128 * Note that few modes do not actually exist.
130 static char *ppc_modes
[] = {
131 "COMPATIBLE", "NIBBLE", "PS/2", "PS/2", "EPP",
132 "EPP", "EPP", "EPP", "ECP",
133 "ECP", "ECP+PS2", "ECP+PS2", "ECP+EPP",
134 "ECP+EPP", "ECP+EPP", "ECP+EPP", 0
137 static char *ppc_epp_protocol
[] = { " (EPP 1.9)", " (EPP 1.7)", 0 };
141 * BIOS printer list - used by BIOS probe.
143 #define BIOS_PPC_PORTS 0x408
144 #define BIOS_PORTS (short *)(KERNBASE+BIOS_PPC_PORTS)
145 #define BIOS_MAX_PPC 4
152 ppc_ecp_sync(device_t dev
)
155 struct ppc_data
*ppc
= DEVTOSOFTC(dev
);
157 if (!(ppc
->ppc_avm
& PPB_ECP
) && !(ppc
->ppc_dtm
& PPB_ECP
))
161 if ((r
& 0xe0) != PPC_ECR_EPP
)
164 for (i
= 0; i
< 100; i
++) {
171 kprintf("ppc%d: ECP sync failed as data still " \
172 "present in FIFO.\n", ppc
->ppc_unit
);
180 * Detect parallel port FIFO
183 ppc_detect_fifo(struct ppc_data
*ppc
)
186 char ctr_sav
, ctr
, cc
;
190 ecr_sav
= r_ecr(ppc
);
191 ctr_sav
= r_ctr(ppc
);
193 /* enter ECP configuration mode, no interrupt, no DMA */
196 /* read PWord size - transfers in FIFO mode must be PWord aligned */
197 ppc
->ppc_pword
= (r_cnfgA(ppc
) & PPC_PWORD_MASK
);
199 /* XXX 16 and 32 bits implementations not supported */
200 if (ppc
->ppc_pword
!= PPC_PWORD_8
) {
201 LOG_PPC(__func__
, ppc
, "PWord not supported");
205 w_ecr(ppc
, 0x34); /* byte mode, no interrupt, no DMA */
207 w_ctr(ppc
, ctr
| PCD
); /* set direction to 1 */
209 /* enter ECP test mode, no interrupt, no DMA */
213 for (i
=0; i
<1024; i
++) {
214 if (r_ecr(ppc
) & PPC_FIFO_EMPTY
)
220 LOG_PPC(__func__
, ppc
, "can't flush FIFO");
224 /* enable interrupts, no DMA */
227 /* determine readIntrThreshold
228 * fill the FIFO until serviceIntr is set
230 for (i
=0; i
<1024; i
++) {
231 w_fifo(ppc
, (char)i
);
232 if (!ppc
->ppc_rthr
&& (r_ecr(ppc
) & PPC_SERVICE_INTR
)) {
233 /* readThreshold reached */
236 if (r_ecr(ppc
) & PPC_FIFO_FULL
) {
243 LOG_PPC(__func__
, ppc
, "can't fill FIFO");
247 w_ecr(ppc
, 0xd4); /* test mode, no interrupt, no DMA */
248 w_ctr(ppc
, ctr
& ~PCD
); /* set direction to 0 */
249 w_ecr(ppc
, 0xd0); /* enable interrupts */
251 /* determine writeIntrThreshold
252 * empty the FIFO until serviceIntr is set
254 for (i
=ppc
->ppc_fifo
; i
>0; i
--) {
255 if (r_fifo(ppc
) != (char)(ppc
->ppc_fifo
-i
)) {
256 LOG_PPC(__func__
, ppc
, "invalid data in FIFO");
259 if (r_ecr(ppc
) & PPC_SERVICE_INTR
) {
260 /* writeIntrThreshold reached */
261 ppc
->ppc_wthr
= ppc
->ppc_fifo
- i
+1;
263 /* if FIFO empty before the last byte, error */
264 if (i
>1 && (r_ecr(ppc
) & PPC_FIFO_EMPTY
)) {
265 LOG_PPC(__func__
, ppc
, "data lost in FIFO");
270 /* FIFO must be empty after the last byte */
271 if (!(r_ecr(ppc
) & PPC_FIFO_EMPTY
)) {
272 LOG_PPC(__func__
, ppc
, "can't empty the FIFO");
289 ppc_detect_port(struct ppc_data
*ppc
)
292 w_ctr(ppc
, 0x0c); /* To avoid missing PS2 ports */
294 if (r_dtr(ppc
) != 0xaa)
301 * EPP timeout, according to the PC87332 manual
302 * Semantics of clearing EPP timeout bit.
303 * PC87332 - reading SPP_STR does it...
304 * SMC - write 1 to EPP timeout bit XXX
305 * Others - (?) write 0 to EPP timeout bit
308 ppc_reset_epp_timeout(struct ppc_data
*ppc
)
314 w_str(ppc
, r
& 0xfe);
320 ppc_check_epp_timeout(struct ppc_data
*ppc
)
322 ppc_reset_epp_timeout(ppc
);
324 return (!(r_str(ppc
) & TIMEOUT
));
328 * Configure current operating mode
331 ppc_generic_setmode(struct ppc_data
*ppc
, int mode
)
335 /* check if mode is available */
336 if (mode
&& !(ppc
->ppc_avm
& mode
))
339 /* if ECP mode, configure ecr register */
340 if ((ppc
->ppc_avm
& PPB_ECP
) || (ppc
->ppc_dtm
& PPB_ECP
)) {
341 /* return to byte mode (keeping direction bit),
342 * no interrupt, no DMA to be able to change to
345 w_ecr(ppc
, PPC_ECR_RESET
);
346 ecr
= PPC_DISABLE_INTR
;
350 else if (mode
& PPB_ECP
)
351 /* select ECP mode */
353 else if (mode
& PPB_PS2
)
354 /* select PS2 mode with ECP */
357 /* select COMPATIBLE/NIBBLE mode */
363 ppc
->ppc_mode
= mode
;
369 * The ppc driver is free to choose options like FIFO or DMA
370 * if ECP mode is available.
372 * The 'RAW' option allows the upper drivers to force the ppc mode
373 * even with FIFO, DMA available.
376 ppc_smclike_setmode(struct ppc_data
*ppc
, int mode
)
380 /* check if mode is available */
381 if (mode
&& !(ppc
->ppc_avm
& mode
))
384 /* if ECP mode, configure ecr register */
385 if ((ppc
->ppc_avm
& PPB_ECP
) || (ppc
->ppc_dtm
& PPB_ECP
)) {
386 /* return to byte mode (keeping direction bit),
387 * no interrupt, no DMA to be able to change to
390 w_ecr(ppc
, PPC_ECR_RESET
);
391 ecr
= PPC_DISABLE_INTR
;
394 /* select EPP mode */
396 else if (mode
& PPB_ECP
)
397 /* select ECP mode */
399 else if (mode
& PPB_PS2
)
400 /* select PS2 mode with ECP */
403 /* select COMPATIBLE/NIBBLE mode */
409 ppc
->ppc_mode
= mode
;
414 #ifdef PPC_PROBE_CHIPSET
418 * Probe for a Natsemi PC873xx-family part.
420 * References in this function are to the National Semiconductor
421 * PC87332 datasheet TL/C/11930, May 1995 revision.
423 static int pc873xx_basetab
[] = {0x0398, 0x026e, 0x015c, 0x002e, 0};
424 static int pc873xx_porttab
[] = {0x0378, 0x03bc, 0x0278, 0};
425 static int pc873xx_irqtab
[] = {5, 7, 5, 0};
427 static int pc873xx_regstab
[] = {
428 PC873_FER
, PC873_FAR
, PC873_PTR
,
429 PC873_FCR
, PC873_PCR
, PC873_PMC
,
430 PC873_TUP
, PC873_SID
, PC873_PNP0
,
431 PC873_PNP1
, PC873_LPTBA
, -1
434 static char *pc873xx_rnametab
[] = {
435 "FER", "FAR", "PTR", "FCR", "PCR",
436 "PMC", "TUP", "SID", "PNP0", "PNP1",
441 ppc_pc873xx_detect(struct ppc_data
*ppc
, int chipset_mode
) /* XXX mode never forced */
443 static int index
= 0;
445 int ptr
, pcr
, val
, i
;
447 while ((idport
= pc873xx_basetab
[index
++])) {
449 /* XXX should check first to see if this location is already claimed */
452 * Pull the 873xx through the power-on ID cycle (2.2,1.).
453 * We can't use this to locate the chip as it may already have
454 * been used by the BIOS.
456 (void)inb(idport
); (void)inb(idport
);
457 (void)inb(idport
); (void)inb(idport
);
460 * Read the SID byte. Possible values are :
467 outb(idport
, PC873_SID
);
468 val
= inb(idport
+ 1);
469 if ((val
& 0xf0) == 0x10) {
470 ppc
->ppc_model
= NS_PC87332
;
471 } else if ((val
& 0xf8) == 0x70) {
472 ppc
->ppc_model
= NS_PC87306
;
473 } else if ((val
& 0xf8) == 0x50) {
474 ppc
->ppc_model
= NS_PC87334
;
475 } else if ((val
& 0xf8) == 0x40) { /* Should be 0x30 by the
476 documentation, but probing
478 ppc
->ppc_model
= NS_PC87303
;
480 if (bootverbose
&& (val
!= 0xff))
481 kprintf("PC873xx probe at 0x%x got unknown ID 0x%x\n", idport
, val
);
482 continue ; /* not recognised */
485 /* print registers */
488 for (i
=0; pc873xx_regstab
[i
] != -1; i
++) {
489 outb(idport
, pc873xx_regstab
[i
]);
490 kprintf(" %s=0x%x", pc873xx_rnametab
[i
],
491 inb(idport
+ 1) & 0xff);
497 * We think we have one. Is it enabled and where we want it to be?
499 outb(idport
, PC873_FER
);
500 val
= inb(idport
+ 1);
501 if (!(val
& PC873_PPENABLE
)) {
503 kprintf("PC873xx parallel port disabled\n");
506 outb(idport
, PC873_FAR
);
507 val
= inb(idport
+ 1);
508 /* XXX we should create a driver instance for every port found */
509 if (pc873xx_porttab
[val
& 0x3] != ppc
->ppc_base
) {
511 /* First try to change the port address to that requested... */
513 switch(ppc
->ppc_base
) {
531 outb(idport
, PC873_FAR
);
532 outb(idport
+ 1, val
);
533 outb(idport
+ 1, val
);
535 /* Check for success by reading back the value we supposedly
536 wrote and comparing...*/
538 outb(idport
, PC873_FAR
);
539 val
= inb(idport
+ 1) & 0x3;
541 /* If we fail, report the failure... */
543 if (pc873xx_porttab
[val
] != ppc
->ppc_base
) {
545 kprintf("PC873xx at 0x%x not for driver at port 0x%x\n",
546 pc873xx_porttab
[val
], ppc
->ppc_base
);
551 outb(idport
, PC873_PTR
);
552 ptr
= inb(idport
+ 1);
554 /* get irq settings */
555 if (ppc
->ppc_base
== 0x378)
556 irq
= (ptr
& PC873_LPTBIRQ7
) ? 7 : 5;
558 irq
= pc873xx_irqtab
[val
];
561 kprintf("PC873xx irq %d at 0x%x\n", irq
, ppc
->ppc_base
);
564 * Check if irq settings are correct
566 if (irq
!= ppc
->ppc_irq
) {
568 * If the chipset is not locked and base address is 0x378,
569 * we have another chance
571 if (ppc
->ppc_base
== 0x378 && !(ptr
& PC873_CFGLOCK
)) {
572 if (ppc
->ppc_irq
== 7) {
573 outb(idport
+ 1, (ptr
| PC873_LPTBIRQ7
));
574 outb(idport
+ 1, (ptr
| PC873_LPTBIRQ7
));
576 outb(idport
+ 1, (ptr
& ~PC873_LPTBIRQ7
));
577 outb(idport
+ 1, (ptr
& ~PC873_LPTBIRQ7
));
580 kprintf("PC873xx irq set to %d\n", ppc
->ppc_irq
);
583 kprintf("PC873xx sorry, can't change irq setting\n");
587 kprintf("PC873xx irq settings are correct\n");
590 outb(idport
, PC873_PCR
);
591 pcr
= inb(idport
+ 1);
593 if ((ptr
& PC873_CFGLOCK
) || !chipset_mode
) {
595 kprintf("PC873xx %s", (ptr
& PC873_CFGLOCK
)?"locked":"unlocked");
597 ppc
->ppc_avm
|= PPB_NIBBLE
;
601 if (pcr
& PC873_EPPEN
) {
602 ppc
->ppc_avm
|= PPB_EPP
;
607 if (pcr
& PC873_EPP19
)
608 ppc
->ppc_epp
= EPP_1_9
;
610 ppc
->ppc_epp
= EPP_1_7
;
612 if ((ppc
->ppc_model
== NS_PC87332
) && bootverbose
) {
613 outb(idport
, PC873_PTR
);
614 ptr
= inb(idport
+ 1);
615 if (ptr
& PC873_EPPRDIR
)
616 kprintf(", Regular mode");
618 kprintf(", Automatic mode");
620 } else if (pcr
& PC873_ECPEN
) {
621 ppc
->ppc_avm
|= PPB_ECP
;
625 if (pcr
& PC873_ECPCLK
) { /* XXX */
626 ppc
->ppc_avm
|= PPB_PS2
;
631 outb(idport
, PC873_PTR
);
632 ptr
= inb(idport
+ 1);
633 if (ptr
& PC873_EXTENDED
) {
634 ppc
->ppc_avm
|= PPB_SPP
;
641 kprintf("PC873xx unlocked");
643 if (chipset_mode
& PPB_ECP
) {
644 if ((chipset_mode
& PPB_EPP
) && bootverbose
)
645 kprintf(", ECP+EPP not supported");
648 pcr
|= (PC873_ECPEN
| PC873_ECPCLK
); /* XXX */
649 outb(idport
+ 1, pcr
);
650 outb(idport
+ 1, pcr
);
655 } else if (chipset_mode
& PPB_EPP
) {
656 pcr
&= ~(PC873_ECPEN
| PC873_ECPCLK
);
657 pcr
|= (PC873_EPPEN
| PC873_EPP19
);
658 outb(idport
+ 1, pcr
);
659 outb(idport
+ 1, pcr
);
661 ppc
->ppc_epp
= EPP_1_9
; /* XXX */
666 /* enable automatic direction turnover */
667 if (ppc
->ppc_model
== NS_PC87332
) {
668 outb(idport
, PC873_PTR
);
669 ptr
= inb(idport
+ 1);
670 ptr
&= ~PC873_EPPRDIR
;
671 outb(idport
+ 1, ptr
);
672 outb(idport
+ 1, ptr
);
675 kprintf(", Automatic mode");
678 pcr
&= ~(PC873_ECPEN
| PC873_ECPCLK
| PC873_EPPEN
);
679 outb(idport
+ 1, pcr
);
680 outb(idport
+ 1, pcr
);
682 /* configure extended bit in PTR */
683 outb(idport
, PC873_PTR
);
684 ptr
= inb(idport
+ 1);
686 if (chipset_mode
& PPB_PS2
) {
687 ptr
|= PC873_EXTENDED
;
693 /* default to NIBBLE mode */
694 ptr
&= ~PC873_EXTENDED
;
699 outb(idport
+ 1, ptr
);
700 outb(idport
+ 1, ptr
);
703 ppc
->ppc_avm
= chipset_mode
;
709 ppc
->ppc_type
= PPC_TYPE_GENERIC
;
710 ppc_generic_setmode(ppc
, chipset_mode
);
712 return(chipset_mode
);
718 * ppc_smc37c66xgt_detect
720 * SMC FDC37C66xGT configuration.
723 ppc_smc37c66xgt_detect(struct ppc_data
*ppc
, int chipset_mode
)
728 int csr
= SMC66x_CSR
; /* initial value is 0x3F0 */
730 int port_address
[] = { -1 /* disabled */ , 0x3bc, 0x378, 0x278 };
733 #define cio csr+1 /* config IO port is either 0x3F1 or 0x371 */
736 * Detection: enter configuration mode and read CRD register.
740 outb(csr
, SMC665_iCODE
);
741 outb(csr
, SMC665_iCODE
);
745 if (inb(cio
) == 0x65) {
750 for (i
= 0; i
< 2; i
++) {
752 outb(csr
, SMC666_iCODE
);
753 outb(csr
, SMC666_iCODE
);
757 if (inb(cio
) == 0x66) {
762 /* Another chance, CSR may be hard-configured to be at 0x370 */
768 * If chipset not found, do not continue.
776 /* read the port's address: bits 0 and 1 of CR1 */
777 r
= inb(cio
) & SMC_CR1_ADDR
;
778 if (port_address
[(int)r
] != ppc
->ppc_base
)
781 ppc
->ppc_model
= type
;
784 * CR1 and CR4 registers bits 3 and 0/1 for mode configuration
785 * If SPP mode is detected, try to set ECP+EPP mode
790 kprintf("ppc%d: SMC registers CR1=0x%x", ppc
->ppc_unit
,
794 kprintf(" CR4=0x%x", inb(cio
) & 0xff);
801 /* autodetect mode */
803 /* 666GT is ~certainly~ hardwired to an extended ECP+EPP mode */
804 if (type
== SMC_37C666GT
) {
805 ppc
->ppc_avm
|= PPB_ECP
| PPB_EPP
| PPB_SPP
;
807 kprintf(" configuration hardwired, supposing " \
811 if ((inb(cio
) & SMC_CR1_MODE
) == 0) {
812 /* already in extended parallel port mode, read CR4 */
814 r
= (inb(cio
) & SMC_CR4_EMODE
);
818 ppc
->ppc_avm
|= PPB_SPP
;
824 ppc
->ppc_avm
|= PPB_EPP
| PPB_SPP
;
830 ppc
->ppc_avm
|= PPB_ECP
| PPB_SPP
;
836 ppc
->ppc_avm
|= PPB_ECP
| PPB_EPP
| PPB_SPP
;
838 kprintf(" ECP+EPP SPP");
842 /* not an extended port mode */
843 ppc
->ppc_avm
|= PPB_SPP
;
850 ppc
->ppc_avm
= chipset_mode
;
852 /* 666GT is ~certainly~ hardwired to an extended ECP+EPP mode */
853 if (type
== SMC_37C666GT
)
857 if ((chipset_mode
& (PPB_ECP
| PPB_EPP
)) == 0) {
858 /* do not use ECP when the mode is not forced to */
859 outb(cio
, r
| SMC_CR1_MODE
);
863 /* an extended mode is selected */
864 outb(cio
, r
& ~SMC_CR1_MODE
);
866 /* read CR4 register and reset mode field */
868 r
= inb(cio
) & ~SMC_CR4_EMODE
;
870 if (chipset_mode
& PPB_ECP
) {
871 if (chipset_mode
& PPB_EPP
) {
872 outb(cio
, r
| SMC_ECPEPP
);
876 outb(cio
, r
| SMC_ECP
);
882 outb(cio
, r
| SMC_EPPSPP
);
887 ppc
->ppc_avm
= chipset_mode
;
890 /* set FIFO threshold to 16 */
891 if (ppc
->ppc_avm
& PPB_ECP
) {
902 if (ppc
->ppc_avm
& PPB_EPP
) {
908 * Set the EPP protocol...
909 * Low=EPP 1.9 (1284 standard) and High=EPP 1.7
911 if (ppc
->ppc_epp
== EPP_1_9
)
912 outb(cio
, (r
& ~SMC_CR4_EPPTYPE
));
914 outb(cio
, (r
| SMC_CR4_EPPTYPE
));
917 /* end config mode */
920 ppc
->ppc_type
= PPC_TYPE_SMCLIKE
;
921 ppc_smclike_setmode(ppc
, chipset_mode
);
923 return (chipset_mode
);
927 * SMC FDC37C935 configuration
928 * Found on many Alpha machines
931 ppc_smc37c935_detect(struct ppc_data
*ppc
, int chipset_mode
)
936 outb(SMC935_CFG
, 0x55); /* enter config mode */
937 outb(SMC935_CFG
, 0x55);
940 outb(SMC935_IND
, SMC935_ID
); /* check device id */
941 if (inb(SMC935_DAT
) == 0x2)
945 outb(SMC935_CFG
, 0xaa); /* exit config mode */
949 ppc
->ppc_model
= type
;
951 outb(SMC935_IND
, SMC935_LOGDEV
); /* select parallel port, */
952 outb(SMC935_DAT
, 3); /* which is logical device 3 */
954 /* set io port base */
955 outb(SMC935_IND
, SMC935_PORTHI
);
956 outb(SMC935_DAT
, (u_char
)((ppc
->ppc_base
& 0xff00) >> 8));
957 outb(SMC935_IND
, SMC935_PORTLO
);
958 outb(SMC935_DAT
, (u_char
)(ppc
->ppc_base
& 0xff));
961 ppc
->ppc_avm
= PPB_COMPATIBLE
; /* default mode */
963 ppc
->ppc_avm
= chipset_mode
;
964 outb(SMC935_IND
, SMC935_PPMODE
);
965 outb(SMC935_DAT
, SMC935_CENT
); /* start in compatible mode */
967 /* SPP + EPP or just plain SPP */
968 if (chipset_mode
& (PPB_SPP
)) {
969 if (chipset_mode
& PPB_EPP
) {
970 if (ppc
->ppc_epp
== EPP_1_9
) {
971 outb(SMC935_IND
, SMC935_PPMODE
);
972 outb(SMC935_DAT
, SMC935_EPP19SPP
);
974 if (ppc
->ppc_epp
== EPP_1_7
) {
975 outb(SMC935_IND
, SMC935_PPMODE
);
976 outb(SMC935_DAT
, SMC935_EPP17SPP
);
979 outb(SMC935_IND
, SMC935_PPMODE
);
980 outb(SMC935_DAT
, SMC935_SPP
);
984 /* ECP + EPP or just plain ECP */
985 if (chipset_mode
& PPB_ECP
) {
986 if (chipset_mode
& PPB_EPP
) {
987 if (ppc
->ppc_epp
== EPP_1_9
) {
988 outb(SMC935_IND
, SMC935_PPMODE
);
989 outb(SMC935_DAT
, SMC935_ECPEPP19
);
991 if (ppc
->ppc_epp
== EPP_1_7
) {
992 outb(SMC935_IND
, SMC935_PPMODE
);
993 outb(SMC935_DAT
, SMC935_ECPEPP17
);
996 outb(SMC935_IND
, SMC935_PPMODE
);
997 outb(SMC935_DAT
, SMC935_ECP
);
1002 outb(SMC935_CFG
, 0xaa); /* exit config mode */
1004 ppc
->ppc_type
= PPC_TYPE_SMCLIKE
;
1005 ppc_smclike_setmode(ppc
, chipset_mode
);
1007 return (chipset_mode
);
1011 * Winbond W83877F stuff
1013 * EFER: extended function enable register
1014 * EFIR: extended function index register
1015 * EFDR: extended function data register
1017 #define efir ((efer == 0x250) ? 0x251 : 0x3f0)
1018 #define efdr ((efer == 0x250) ? 0x252 : 0x3f1)
1020 static int w83877f_efers
[] = { 0x250, 0x3f0, 0x3f0, 0x250 };
1021 static int w83877f_keys
[] = { 0x89, 0x86, 0x87, 0x88 };
1022 static int w83877f_keyiter
[] = { 1, 2, 2, 1 };
1023 static int w83877f_hefs
[] = { WINB_HEFERE
, WINB_HEFRAS
, WINB_HEFERE
| WINB_HEFRAS
, 0 };
1026 ppc_w83877f_detect(struct ppc_data
*ppc
, int chipset_mode
)
1029 unsigned char r
, hefere
, hefras
;
1031 for (i
= 0; i
< 4; i
++) {
1032 /* first try to enable configuration registers */
1033 efer
= w83877f_efers
[i
];
1035 /* write the key to the EFER */
1036 for (j
= 0; j
< w83877f_keyiter
[i
]; j
++)
1037 outb (efer
, w83877f_keys
[i
]);
1039 /* then check HEFERE and HEFRAS bits */
1041 hefere
= inb(efdr
) & WINB_HEFERE
;
1044 hefras
= inb(efdr
) & WINB_HEFRAS
;
1048 * 0 1 write 89h to 250h (power-on default)
1049 * 1 0 write 86h twice to 3f0h
1050 * 1 1 write 87h twice to 3f0h
1051 * 0 0 write 88h to 250h
1053 if ((hefere
| hefras
) == w83877f_hefs
[i
])
1057 return (-1); /* failed */
1060 /* check base port address - read from CR23 */
1062 if (ppc
->ppc_base
!= inb(efdr
) * 4) /* 4 bytes boundaries */
1065 /* read CHIP ID from CR9/bits0-3 */
1068 switch (inb(efdr
) & WINB_CHIPID
) {
1069 case WINB_W83877F_ID
:
1070 ppc
->ppc_model
= WINB_W83877F
;
1073 case WINB_W83877AF_ID
:
1074 ppc
->ppc_model
= WINB_W83877AF
;
1078 ppc
->ppc_model
= WINB_UNKNOWN
;
1082 /* dump of registers */
1083 kprintf("ppc%d: 0x%x - ", ppc
->ppc_unit
, w83877f_keys
[i
]);
1084 for (i
= 0; i
<= 0xd; i
++) {
1086 kprintf("0x%x ", inb(efdr
));
1088 for (i
= 0x10; i
<= 0x17; i
++) {
1090 kprintf("0x%x ", inb(efdr
));
1093 kprintf("0x%x ", inb(efdr
));
1094 for (i
= 0x20; i
<= 0x29; i
++) {
1096 kprintf("0x%x ", inb(efdr
));
1099 kprintf("ppc%d:", ppc
->ppc_unit
);
1102 ppc
->ppc_type
= PPC_TYPE_GENERIC
;
1104 if (!chipset_mode
) {
1105 /* autodetect mode */
1109 r
= inb(efdr
) & (WINB_PRTMODS0
| WINB_PRTMODS1
);
1113 r
|= (inb(efdr
) & WINB_PRTMODS2
);
1118 kprintf("ppc%d: W83757 compatible mode\n",
1120 return (-1); /* generic or SMC-like */
1127 kprintf(" not in parallel port mode\n");
1130 case (WINB_PARALLEL
| WINB_EPP_SPP
):
1131 ppc
->ppc_avm
|= PPB_EPP
| PPB_SPP
;
1133 kprintf(" EPP SPP");
1136 case (WINB_PARALLEL
| WINB_ECP
):
1137 ppc
->ppc_avm
|= PPB_ECP
| PPB_SPP
;
1139 kprintf(" ECP SPP");
1142 case (WINB_PARALLEL
| WINB_ECP_EPP
):
1143 ppc
->ppc_avm
|= PPB_ECP
| PPB_EPP
| PPB_SPP
;
1144 ppc
->ppc_type
= PPC_TYPE_SMCLIKE
;
1147 kprintf(" ECP+EPP SPP");
1150 kprintf("%s: unknown case (0x%x)!\n", __func__
, r
);
1156 /* select CR9 and set PRTMODS2 bit */
1158 outb(efdr
, inb(efdr
) & ~WINB_PRTMODS2
);
1160 /* select CR0 and reset PRTMODSx bits */
1162 outb(efdr
, inb(efdr
) & ~(WINB_PRTMODS0
| WINB_PRTMODS1
));
1164 if (chipset_mode
& PPB_ECP
) {
1165 if (chipset_mode
& PPB_EPP
) {
1166 outb(efdr
, inb(efdr
) | WINB_ECP_EPP
);
1168 kprintf(" ECP+EPP");
1170 ppc
->ppc_type
= PPC_TYPE_SMCLIKE
;
1173 outb(efdr
, inb(efdr
) | WINB_ECP
);
1178 /* select EPP_SPP otherwise */
1179 outb(efdr
, inb(efdr
) | WINB_EPP_SPP
);
1181 kprintf(" EPP SPP");
1183 ppc
->ppc_avm
= chipset_mode
;
1189 /* exit configuration mode */
1192 switch (ppc
->ppc_type
) {
1193 case PPC_TYPE_SMCLIKE
:
1194 ppc_smclike_setmode(ppc
, chipset_mode
);
1197 ppc_generic_setmode(ppc
, chipset_mode
);
1201 return (chipset_mode
);
1206 * ppc_generic_detect
1209 ppc_generic_detect(struct ppc_data
*ppc
, int chipset_mode
)
1211 /* default to generic */
1212 ppc
->ppc_type
= PPC_TYPE_GENERIC
;
1215 kprintf("ppc%d:", ppc
->ppc_unit
);
1217 /* first, check for ECP */
1218 w_ecr(ppc
, PPC_ECR_PS2
);
1219 if ((r_ecr(ppc
) & 0xe0) == PPC_ECR_PS2
) {
1220 ppc
->ppc_dtm
|= PPB_ECP
| PPB_SPP
;
1222 kprintf(" ECP SPP");
1224 /* search for SMC style ECP+EPP mode */
1225 w_ecr(ppc
, PPC_ECR_EPP
);
1228 /* try to reset EPP timeout bit */
1229 if (ppc_check_epp_timeout(ppc
)) {
1230 ppc
->ppc_dtm
|= PPB_EPP
;
1232 if (ppc
->ppc_dtm
& PPB_ECP
) {
1233 /* SMC like chipset found */
1234 ppc
->ppc_model
= SMC_LIKE
;
1235 ppc
->ppc_type
= PPC_TYPE_SMCLIKE
;
1238 kprintf(" ECP+EPP");
1244 /* restore to standard mode */
1245 w_ecr(ppc
, PPC_ECR_STD
);
1248 /* XXX try to detect NIBBLE and PS2 modes */
1249 ppc
->ppc_dtm
|= PPB_NIBBLE
;
1255 ppc
->ppc_avm
= chipset_mode
;
1257 ppc
->ppc_avm
= ppc
->ppc_dtm
;
1262 switch (ppc
->ppc_type
) {
1263 case PPC_TYPE_SMCLIKE
:
1264 ppc_smclike_setmode(ppc
, chipset_mode
);
1267 ppc_generic_setmode(ppc
, chipset_mode
);
1271 return (chipset_mode
);
1277 * mode is the mode suggested at boot
1280 ppc_detect(struct ppc_data
*ppc
, int chipset_mode
)
1282 #ifdef PPC_PROBE_CHIPSET
1285 /* list of supported chipsets */
1286 int (*chipset_detect
[])(struct ppc_data
*, int) = {
1288 ppc_smc37c66xgt_detect
,
1290 ppc_smc37c935_detect
,
1296 /* if can't find the port and mode not forced return error */
1297 if (!ppc_detect_port(ppc
) && chipset_mode
== 0)
1298 return (EIO
); /* failed, port not present */
1300 /* assume centronics compatible mode is supported */
1301 ppc
->ppc_avm
= PPB_COMPATIBLE
;
1303 #ifdef PPC_PROBE_CHIPSET
1304 /* we have to differenciate available chipset modes,
1305 * chipset running modes and IEEE-1284 operating modes
1307 * after detection, the port must support running in compatible mode
1309 if (ppc
->ppc_flags
& 0x40) {
1311 kprintf("ppc: chipset forced to generic\n");
1314 ppc
->ppc_mode
= ppc_generic_detect(ppc
, chipset_mode
);
1316 #ifdef PPC_PROBE_CHIPSET
1318 for (i
=0; chipset_detect
[i
] != NULL
; i
++) {
1319 if ((mode
= chipset_detect
[i
](ppc
, chipset_mode
)) != -1) {
1320 ppc
->ppc_mode
= mode
;
1327 /* configure/detect ECP FIFO */
1328 if ((ppc
->ppc_avm
& PPB_ECP
) && !(ppc
->ppc_flags
& 0x80))
1329 ppc_detect_fifo(ppc
);
1335 * ppc_exec_microseq()
1337 * Execute a microsequence.
1338 * Microsequence mechanism is supposed to handle fast I/O operations.
1341 ppc_exec_microseq(device_t dev
, struct ppb_microseq
**p_msq
)
1343 struct ppc_data
*ppc
= DEVTOSOFTC(dev
);
1344 struct ppb_microseq
*mi
;
1354 struct ppb_microseq
*stack
= 0;
1356 /* microsequence registers are equivalent to PC-like port registers */
1358 #define r_reg(register,ppc) (bus_space_read_1((ppc)->bst, (ppc)->bsh, register))
1359 #define w_reg(register, ppc, byte) (bus_space_write_1((ppc)->bst, (ppc)->bsh, register, byte))
1361 #define INCR_PC (mi ++) /* increment program counter */
1365 switch (mi
->opcode
) {
1367 cc
= r_reg(mi
->arg
[0].i
, ppc
);
1368 cc
&= (char)mi
->arg
[2].i
; /* clear mask */
1369 cc
|= (char)mi
->arg
[1].i
; /* assert mask */
1370 w_reg(mi
->arg
[0].i
, ppc
, cc
);
1374 case MS_OP_RASSERT_P
:
1378 if ((len
= mi
->arg
[0].i
) == MS_ACCUM
) {
1379 accum
= ppc
->ppc_accum
;
1380 for (; accum
; accum
--)
1381 w_reg(reg
, ppc
, *ptr
++);
1382 ppc
->ppc_accum
= accum
;
1384 for (i
=0; i
<len
; i
++)
1385 w_reg(reg
, ppc
, *ptr
++);
1391 case MS_OP_RFETCH_P
:
1393 mask
= (char)mi
->arg
[2].i
;
1396 if ((len
= mi
->arg
[0].i
) == MS_ACCUM
) {
1397 accum
= ppc
->ppc_accum
;
1398 for (; accum
; accum
--)
1399 *ptr
++ = r_reg(reg
, ppc
) & mask
;
1400 ppc
->ppc_accum
= accum
;
1402 for (i
=0; i
<len
; i
++)
1403 *ptr
++ = r_reg(reg
, ppc
) & mask
;
1410 *((char *) mi
->arg
[2].p
) = r_reg(mi
->arg
[0].i
, ppc
) &
1418 /* let's suppose the next instr. is the same */
1420 for (;mi
->opcode
== MS_OP_RASSERT
; INCR_PC
)
1421 w_reg(mi
->arg
[0].i
, ppc
, (char)mi
->arg
[1].i
);
1423 if (mi
->opcode
== MS_OP_DELAY
) {
1424 DELAY(mi
->arg
[0].i
);
1432 tsleep(NULL
, 0, "ppbdelay",
1433 mi
->arg
[0].i
* (hz
/1000));
1439 iter
= mi
->arg
[1].i
;
1440 p
= (char *)mi
->arg
[2].p
;
1442 /* XXX delay limited to 255 us */
1443 for (i
=0; i
<iter
; i
++) {
1444 w_reg(reg
, ppc
, *p
++);
1445 DELAY((unsigned char)*p
++);
1451 ppc
->ppc_accum
= mi
->arg
[0].i
;
1456 if (--ppc
->ppc_accum
> 0)
1463 if ((cc
& (char)mi
->arg
[0].i
) == (char)mi
->arg
[0].i
)
1470 if ((cc
& (char)mi
->arg
[0].i
) == 0)
1477 if ((cc
& ((char)mi
->arg
[0].i
| (char)mi
->arg
[1].i
)) ==
1485 * If the C call returns !0 then end the microseq.
1486 * The current state of ptr is passed to the C function
1488 if ((error
= mi
->arg
[0].f(mi
->arg
[1].p
, ppc
->ppc_ptr
)))
1495 ppc
->ppc_ptr
= (char *)mi
->arg
[0].p
;
1501 panic("%s: too much calls", __func__
);
1504 /* store the state of the actual
1509 /* jump to the new microsequence */
1510 mi
= (struct ppb_microseq
*)mi
->arg
[0].p
;
1517 /* retrieve microseq and pc state before the call */
1520 /* reset the stack */
1523 /* XXX return code */
1531 /* can't return to ppb level during the execution
1532 * of a submicrosequence */
1534 panic("%s: can't return to ppb level",
1537 /* update pc for ppb level of execution */
1540 /* return to ppb level of execution */
1544 panic("%s: unknown microsequence opcode 0x%x",
1545 __func__
, mi
->opcode
);
1555 device_t dev
= (device_t
)arg
;
1556 struct ppc_data
*ppc
= (struct ppc_data
*)device_get_softc(dev
);
1557 u_char ctr
, ecr
, str
;
1564 kprintf("![%x/%x/%x]", ctr
, ecr
, str
);
1567 /* don't use ecp mode with IRQENABLE set */
1568 if (ctr
& IRQENABLE
) {
1572 /* interrupts are generated by nFault signal
1573 * only in ECP mode */
1574 if ((str
& nFAULT
) && (ppc
->ppc_mode
& PPB_ECP
)) {
1575 /* check if ppc driver has programmed the
1576 * nFault interrupt */
1577 if (ppc
->ppc_irqstat
& PPC_IRQ_nFAULT
) {
1579 w_ecr(ppc
, ecr
| PPC_nFAULT_INTR
);
1580 ppc
->ppc_irqstat
&= ~PPC_IRQ_nFAULT
;
1582 /* shall be handled by underlying layers XXX */
1587 if (ppc
->ppc_irqstat
& PPC_IRQ_DMA
) {
1588 /* disable interrupts (should be done by hardware though) */
1589 w_ecr(ppc
, ecr
| PPC_SERVICE_INTR
);
1590 ppc
->ppc_irqstat
&= ~PPC_IRQ_DMA
;
1593 /* check if DMA completed */
1594 if ((ppc
->ppc_avm
& PPB_ECP
) && (ecr
& PPC_ENABLE_DMA
)) {
1599 w_ecr(ppc
, ecr
& ~PPC_ENABLE_DMA
);
1602 if (ppc
->ppc_dmastat
== PPC_DMA_STARTED
) {
1612 ppc
->ppc_dmastat
= PPC_DMA_COMPLETE
;
1614 /* wakeup the waiting process */
1615 wakeup((caddr_t
)ppc
);
1618 } else if (ppc
->ppc_irqstat
& PPC_IRQ_FIFO
) {
1620 /* classic interrupt I/O */
1621 ppc
->ppc_irqstat
&= ~PPC_IRQ_FIFO
;
1628 ppc_read(device_t dev
, char *buf
, int len
, int mode
)
1634 * Call this function if you want to send data in any advanced mode
1635 * of your parallel port: FIFO, DMA
1637 * If what you want is not possible (no ECP, no DMA...),
1638 * EINVAL is returned
1641 ppc_write(device_t dev
, char *buf
, int len
, int how
)
1643 struct ppc_data
*ppc
= DEVTOSOFTC(dev
);
1644 char ecr
, ecr_sav
, ctr
, ctr_sav
;
1652 ecr_sav
= r_ecr(ppc
);
1653 ctr_sav
= r_ctr(ppc
);
1656 * Send buffer with DMA, FIFO and interrupts
1658 if ((ppc
->ppc_avm
& PPB_ECP
) && (ppc
->ppc_registered
)) {
1660 if (ppc
->ppc_dmachan
> 0) {
1662 /* byte mode, no intr, no DMA, dir=0, flush fifo
1664 ecr
= PPC_ECR_STD
| PPC_DISABLE_INTR
;
1667 /* disable nAck interrupts */
1672 ppc
->ppc_dmaflags
= ISADMA_WRITE
;
1673 ppc
->ppc_dmaddr
= (caddr_t
)buf
;
1674 ppc
->ppc_dmacnt
= (u_int
)len
;
1676 switch (ppc
->ppc_mode
) {
1677 case PPB_COMPATIBLE
:
1678 /* compatible mode with FIFO, no intr, DMA, dir=0 */
1679 ecr
= PPC_ECR_FIFO
| PPC_DISABLE_INTR
| PPC_ENABLE_DMA
;
1682 ecr
= PPC_ECR_ECP
| PPC_DISABLE_INTR
| PPC_ENABLE_DMA
;
1692 /* enter splhigh() not to be preempted
1693 * by the dma interrupt, we may miss
1694 * the wakeup otherwise
1698 ppc
->ppc_dmastat
= PPC_DMA_INIT
;
1700 /* enable interrupts */
1701 ecr
&= ~PPC_SERVICE_INTR
;
1702 ppc
->ppc_irqstat
= PPC_IRQ_DMA
;
1711 kprintf("s%d", ppc
->ppc_dmacnt
);
1713 ppc
->ppc_dmastat
= PPC_DMA_STARTED
;
1715 /* Wait for the DMA completed interrupt. We hope we won't
1716 * miss it, otherwise a signal will be necessary to unlock the
1721 error
= tsleep((caddr_t
)ppc
, PCATCH
, "ppcdma", 0);
1723 } while (error
== EWOULDBLOCK
);
1734 ppc
->ppc_dmaddr
, ppc
->ppc_dmacnt
,
1737 /* no dma, no interrupt, flush the fifo */
1738 w_ecr(ppc
, PPC_ECR_RESET
);
1740 ppc
->ppc_dmastat
= PPC_DMA_INTERRUPTED
;
1744 /* wait for an empty fifo */
1745 while (!(r_ecr(ppc
) & PPC_FIFO_EMPTY
)) {
1747 for (spin
=100; spin
; spin
--)
1748 if (r_ecr(ppc
) & PPC_FIFO_EMPTY
)
1753 error
= tsleep((caddr_t
)ppc
, PCATCH
, "ppcfifo", hz
/100);
1754 if (error
!= EWOULDBLOCK
) {
1758 /* no dma, no interrupt, flush the fifo */
1759 w_ecr(ppc
, PPC_ECR_RESET
);
1761 ppc
->ppc_dmastat
= PPC_DMA_INTERRUPTED
;
1768 /* no dma, no interrupt, flush the fifo */
1769 w_ecr(ppc
, PPC_ECR_RESET
);
1772 error
= EINVAL
; /* XXX we should FIFO and
1779 /* PDRQ must be kept unasserted until nPDACK is
1780 * deasserted for a minimum of 350ns (SMC datasheet)
1782 * Consequence may be a FIFO that never empty
1786 w_ecr(ppc
, ecr_sav
);
1787 w_ctr(ppc
, ctr_sav
);
1793 ppc_reset_epp(device_t dev
)
1795 struct ppc_data
*ppc
= DEVTOSOFTC(dev
);
1797 ppc_reset_epp_timeout(ppc
);
1803 ppc_setmode(device_t dev
, int mode
)
1805 struct ppc_data
*ppc
= DEVTOSOFTC(dev
);
1807 switch (ppc
->ppc_type
) {
1808 case PPC_TYPE_SMCLIKE
:
1809 return (ppc_smclike_setmode(ppc
, mode
));
1812 case PPC_TYPE_GENERIC
:
1814 return (ppc_generic_setmode(ppc
, mode
));
1822 static struct isa_pnp_id lpc_ids
[] = {
1823 { 0x0004d041, "Standard parallel printer port" }, /* PNP0400 */
1824 { 0x0104d041, "ECP parallel printer port" }, /* PNP0401 */
1829 ppc_probe(device_t dev
)
1832 static short next_bios_ppc
= 0;
1834 struct ppc_data
*ppc
;
1839 parent
= device_get_parent(dev
);
1841 error
= ISA_PNP_PROBE(parent
, dev
, lpc_ids
);
1844 else if (error
!= 0) /* XXX shall be set after detection */
1845 device_set_desc(dev
, "Parallel port");
1848 * Allocate the ppc_data structure.
1850 ppc
= DEVTOSOFTC(dev
);
1851 bzero(ppc
, sizeof(struct ppc_data
));
1853 ppc
->rid_irq
= ppc
->rid_drq
= ppc
->rid_ioport
= 0;
1854 ppc
->res_irq
= ppc
->res_drq
= ppc
->res_ioport
= 0;
1856 /* retrieve ISA parameters */
1857 error
= bus_get_resource(dev
, SYS_RES_IOPORT
, 0, &port
, NULL
);
1861 * If port not specified, use bios list.
1864 if((next_bios_ppc
< BIOS_MAX_PPC
) &&
1865 (*(BIOS_PORTS
+next_bios_ppc
) != 0) ) {
1866 port
= *(BIOS_PORTS
+next_bios_ppc
++);
1868 device_printf(dev
, "parallel port found at 0x%x\n",
1871 device_printf(dev
, "parallel port not found.\n");
1874 bus_set_resource(dev
, SYS_RES_IOPORT
, 0, port
,
1875 IO_LPTSIZE_EXTENDED
);
1879 /* IO port is mandatory */
1881 /* Try "extended" IO port range...*/
1882 ppc
->res_ioport
= bus_alloc_resource(dev
, SYS_RES_IOPORT
,
1883 &ppc
->rid_ioport
, 0, ~0,
1884 IO_LPTSIZE_EXTENDED
, RF_ACTIVE
);
1886 if (ppc
->res_ioport
!= 0) {
1888 device_printf(dev
, "using extended I/O port range\n");
1890 /* Failed? If so, then try the "normal" IO port range... */
1891 ppc
->res_ioport
= bus_alloc_resource(dev
, SYS_RES_IOPORT
,
1892 &ppc
->rid_ioport
, 0, ~0,
1895 if (ppc
->res_ioport
!= 0) {
1897 device_printf(dev
, "using normal I/O port range\n");
1899 device_printf(dev
, "cannot reserve I/O port range\n");
1904 ppc
->ppc_base
= rman_get_start(ppc
->res_ioport
);
1906 ppc
->bsh
= rman_get_bushandle(ppc
->res_ioport
);
1907 ppc
->bst
= rman_get_bustag(ppc
->res_ioport
);
1909 ppc
->ppc_flags
= device_get_flags(dev
);
1911 if (!(ppc
->ppc_flags
& 0x20)) {
1912 ppc
->res_irq
= bus_alloc_resource(dev
, SYS_RES_IRQ
, &ppc
->rid_irq
,
1913 0ul, ~0ul, 1, RF_SHAREABLE
);
1914 ppc
->res_drq
= bus_alloc_resource(dev
, SYS_RES_DRQ
, &ppc
->rid_drq
,
1915 0ul, ~0ul, 1, RF_ACTIVE
);
1919 ppc
->ppc_irq
= rman_get_start(ppc
->res_irq
);
1921 ppc
->ppc_dmachan
= rman_get_start(ppc
->res_drq
);
1923 ppc
->ppc_unit
= device_get_unit(dev
);
1924 ppc
->ppc_model
= GENERIC
;
1926 ppc
->ppc_mode
= PPB_COMPATIBLE
;
1927 ppc
->ppc_epp
= (ppc
->ppc_flags
& 0x10) >> 4;
1929 ppc
->ppc_type
= PPC_TYPE_GENERIC
;
1932 * Try to detect the chipset and its mode.
1934 if (ppc_detect(ppc
, ppc
->ppc_flags
& 0xf))
1940 if (ppc
->res_irq
!= 0) {
1941 bus_release_resource(dev
, SYS_RES_IRQ
, ppc
->rid_irq
,
1944 if (ppc
->res_ioport
!= 0) {
1945 bus_deactivate_resource(dev
, SYS_RES_IOPORT
, ppc
->rid_ioport
,
1947 bus_release_resource(dev
, SYS_RES_IOPORT
, ppc
->rid_ioport
,
1950 if (ppc
->res_drq
!= 0) {
1951 bus_deactivate_resource(dev
, SYS_RES_DRQ
, ppc
->rid_drq
,
1953 bus_release_resource(dev
, SYS_RES_DRQ
, ppc
->rid_drq
,
1960 ppc_attach(device_t dev
)
1962 struct ppc_data
*ppc
= DEVTOSOFTC(dev
);
1965 device_t parent
= device_get_parent(dev
);
1967 device_printf(dev
, "%s chipset (%s) in %s mode%s\n",
1968 ppc_models
[ppc
->ppc_model
], ppc_avms
[ppc
->ppc_avm
],
1969 ppc_modes
[ppc
->ppc_mode
], (PPB_IS_EPP(ppc
->ppc_mode
)) ?
1970 ppc_epp_protocol
[ppc
->ppc_epp
] : "");
1973 device_printf(dev
, "FIFO with %d/%d/%d bytes threshold\n",
1974 ppc
->ppc_fifo
, ppc
->ppc_wthr
, ppc
->ppc_rthr
);
1976 if ((ppc
->ppc_avm
& PPB_ECP
) && (ppc
->ppc_dmachan
> 0)) {
1977 /* acquire the DMA channel forever */ /* XXX */
1978 isa_dma_acquire(ppc
->ppc_dmachan
);
1979 isa_dmainit(ppc
->ppc_dmachan
, 1024); /* nlpt.BUFSIZE */
1982 /* add ppbus as a child of this isa to parallel bridge */
1983 ppbus
= device_add_child(dev
, "ppbus", -1);
1986 * Probe the ppbus and attach devices found.
1988 device_probe_and_attach(ppbus
);
1990 /* register the ppc interrupt handler as default */
1992 /* default to the tty mask for registration */ /* XXX */
1993 if (BUS_SETUP_INTR(parent
, dev
, ppc
->res_irq
, 0,
1995 &ppc
->intr_cookie
, NULL
) == 0) {
1996 /* remember the ppcintr is registered */
1997 ppc
->ppc_registered
= 1;
2005 ppc_io(device_t ppcdev
, int iop
, u_char
*addr
, int cnt
, u_char byte
)
2007 struct ppc_data
*ppc
= DEVTOSOFTC(ppcdev
);
2010 bus_space_write_multi_1(ppc
->bst
, ppc
->bsh
, PPC_EPP_DATA
, addr
, cnt
);
2013 bus_space_write_multi_2(ppc
->bst
, ppc
->bsh
, PPC_EPP_DATA
, (u_int16_t
*)addr
, cnt
);
2016 bus_space_write_multi_4(ppc
->bst
, ppc
->bsh
, PPC_EPP_DATA
, (u_int32_t
*)addr
, cnt
);
2019 bus_space_read_multi_1(ppc
->bst
, ppc
->bsh
, PPC_EPP_DATA
, addr
, cnt
);
2022 bus_space_read_multi_2(ppc
->bst
, ppc
->bsh
, PPC_EPP_DATA
, (u_int16_t
*)addr
, cnt
);
2025 bus_space_read_multi_4(ppc
->bst
, ppc
->bsh
, PPC_EPP_DATA
, (u_int32_t
*)addr
, cnt
);
2028 return (r_dtr(ppc
));
2031 return (r_str(ppc
));
2034 return (r_ctr(ppc
));
2037 return (r_epp_A(ppc
));
2040 return (r_epp_D(ppc
));
2043 return (r_ecr(ppc
));
2046 return (r_fifo(ppc
));
2070 panic("%s: unknown I/O operation", __func__
);
2074 return (0); /* not significative */
2078 ppc_read_ivar(device_t bus
, device_t dev
, int index
, uintptr_t *val
)
2080 struct ppc_data
*ppc
= (struct ppc_data
*)device_get_softc(bus
);
2083 case PPC_IVAR_EPP_PROTO
:
2084 *val
= (u_long
)ppc
->ppc_epp
;
2087 *val
= (u_long
)ppc
->ppc_irq
;
2097 * Resource is useless here since ppbus devices' interrupt handlers are
2098 * multiplexed to the same resource initially allocated by ppc
2101 ppc_setup_intr(device_t bus
, device_t child
, struct resource
*r
, int flags
,
2102 void (*ihand
)(void *), void *arg
,
2103 void **cookiep
, lwkt_serialize_t serializer
)
2106 struct ppc_data
*ppc
= DEVTOSOFTC(bus
);
2108 if (ppc
->ppc_registered
) {
2109 /* XXX refuse registration if DMA is in progress */
2111 /* first, unregister the default interrupt handler */
2112 if ((error
= BUS_TEARDOWN_INTR(device_get_parent(bus
),
2113 bus
, ppc
->res_irq
, ppc
->intr_cookie
)))
2116 /* bus_deactivate_resource(bus, SYS_RES_IRQ, ppc->rid_irq, */
2117 /* ppc->res_irq); */
2119 /* DMA/FIFO operation won't be possible anymore */
2120 ppc
->ppc_registered
= 0;
2123 /* pass registration to the upper layer, ignore the incoming resource */
2124 return (BUS_SETUP_INTR(device_get_parent(bus
), child
,
2125 r
, flags
, ihand
, arg
, cookiep
, serializer
));
2129 * When no underlying device has a registered interrupt, register the ppc
2133 ppc_teardown_intr(device_t bus
, device_t child
, struct resource
*r
, void *ih
)
2136 struct ppc_data
*ppc
= DEVTOSOFTC(bus
);
2137 device_t parent
= device_get_parent(bus
);
2139 /* pass unregistration to the upper layer */
2140 if ((error
= BUS_TEARDOWN_INTR(parent
, child
, r
, ih
)))
2143 /* default to the tty mask for registration */ /* XXX */
2145 !(error
= BUS_SETUP_INTR(parent
, bus
, ppc
->res_irq
,
2147 &ppc
->intr_cookie
, NULL
))
2149 /* remember the ppcintr is registered */
2150 ppc
->ppc_registered
= 1;
2156 DRIVER_MODULE(ppc
, isa
, ppc_driver
, ppc_devclass
, 0, 0);
2157 DRIVER_MODULE(ppc
, acpi
, ppc_driver
, ppc_devclass
, 0, 0);