sys/platform/pc32/isa/timerreg.h

   1 /*-
   2  * Copyright (c) 1993 The Regents of the University of California.
   3  * All rights reserved.
   4  *
   5  * Redistribution and use in source and binary forms, with or without
   6  * modification, are permitted provided that the following conditions
   7  * are met:
   8  * 1. Redistributions of source code must retain the above copyright
   9  *    notice, this list of conditions and the following disclaimer.
  10  * 2. Redistributions in binary form must reproduce the above copyright
  11  *    notice, this list of conditions and the following disclaimer in the
  12  *    documentation and/or other materials provided with the distribution.
  13  * 3. All advertising materials mentioning features or use of this software
  14  *    must display the following acknowledgement:
  15  *      This product includes software developed by the University of
  16  *      California, Berkeley and its contributors.
  17  * 4. Neither the name of the University nor the names of its contributors
  18  *    may be used to endorse or promote products derived from this software
  19  *    without specific prior written permission.
  20  *
  21  * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND
  22  * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
  23  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
  24  * ARE DISCLAIMED.  IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE
  25  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
  26  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
  27  * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
  28  * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
  29  * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
  30  * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
  31  * SUCH DAMAGE.
  32  *
  33  *      from: Header: timerreg.h,v 1.2 93/02/28 15:08:58 mccanne Exp
  34  * $FreeBSD: src/sys/i386/isa/timerreg.h,v 1.6 1999/08/28 00:45:04 peter Exp $
  35  * $DragonFly: src/sys/platform/pc32/isa/timerreg.h,v 1.4 2005/02/27 12:44:43 asmodai Exp $
  36  */
  37
  38 /*
  39  *
  40  * Register definitions for the Intel 8253 Programmable Interval Timer.
  41  *
  42  * This chip has three independent 16-bit down counters that can be
  43  * read on the fly.  There are three mode registers and three countdown
  44  * registers.  The countdown registers are addressed directly, via the
  45  * first three I/O ports.  The three mode registers are accessed via
  46  * the fourth I/O port, with two bits in the mode byte indicating the
  47  * register.  (Why are hardware interfaces always so braindead?).
  48  *
  49  * To write a value into the countdown register, the mode register
  50  * is first programmed with a command indicating the which byte of
  51  * the two byte register is to be modified.  The three possibilities
  52  * are load msb (TMR_MR_MSB), load lsb (TMR_MR_LSB), or load lsb then
  53  * msb (TMR_MR_BOTH).
  54  *
  55  * To read the current value ("on the fly") from the countdown register,
  56  * you write a "latch" command into the mode register, then read the stable
  57  * value from the corresponding I/O port.  For example, you write
  58  * TMR_MR_LATCH into the corresponding mode register.  Presumably,
  59  * after doing this, a write operation to the I/O port would result
  60  * in undefined behavior (but hopefully not fry the chip).
  61  * Reading in this manner has no side effects.
  62  *
  63  * [IBM-PC]
  64  * The outputs of the three timers are connected as follows:
  65  *
  66  *       timer 0 -> irq 0
  67  *       timer 1 -> dma chan 0 (for dram refresh)
  68  *       timer 2 -> speaker (via keyboard controller)
  69  *
  70  * Timer 0 is used to call hardclock.
  71  * Timer 2 is used to generate console beeps.
  72  *
  73  * [PC-9801]
  74  * The outputs of the three timers are connected as follows:
  75  *
  76  *       timer 0 -> irq 0
  77  *       timer 1 -> speaker (via keyboard controller)
  78  *       timer 2 -> RS232C
  79  *
  80  * Timer 0 is used to call hardclock.
  81  * Timer 1 is used to generate console beeps.
  82  *
  83  * TIMER_INTTC:         Interrupt on Terminal Count.  OUT initially low,
  84  *                              goes high on terminal count and remains
  85  *                              high until a new count or a mode 0 control
  86  *                              word is written.
  87  *
  88  * TIMER_ONESHOT:       Hardware Retriggerable One Shot.  Out initially high,
  89  *                      out goes low following the trigger and remains low
  90  *                      until terminal count, then goes high and remains
  91  *                      high until the next trigger.
  92  *
  93  * TIMER_RATEGEN:       Rate Generator.  OUT is initially high.  When the
  94  *                      count has decremented to 1 OUT goes low for one CLK
  95  *                      pulse, then goes high again.  Counter reloads and
  96  *                      the sequence is repeated.
  97  *
  98  * TIMER_SQWAVE:        Square Wave Generator.  OUT is initially high.  When
  99  *                      half the count is expired, OUT goes low.  Counter
 100  *                      reloads, OUT goes high, and the sequence repepats.
 101  *
 102  * TIMER_SWSTROBE:      S/W Triggered Strobe.  OUT initially high.  On
 103  *                      terminal count OUT goes low for one CLK pulse
 104  *                      and then goes high again.  Counting stops.
 105  *                      The counting sequence is 'triggered' by writing
 106  *                      the initial count.  Writing a control word and
 107  *                      initial count resets and reloads the counter.
 108  *
 109  * TIMER_HWSTROBE:      H/W Triggered Strobe.  OUT initially high.  A rising
 110  *                      edge on GATE loads the counter and counting begins.
 111  *                      On terminal count OUT goes low for one CLK and then
 112  *                      high again.
 113  *
 114  * NOTE: the largest possible initial count is 0x0000.  This is equivalent
 115  * to 2^16 binary and 10^4 BCD counts.  The counter does not stop when it
 116  * reaches zero.  In Modes INTTC, ONESHOT, SWSTROBE, and HWSTROBE the
 117  * counter wraps aroudn to the highest count (0xFFFF or 9999bcd) and
 118  * continues counting.  In MODES RATEGEN and SQWAVE (which are periodic)
 119  * the counter reloads itself with the initial count and continues counting
 120  * from there.
 121  */
 122
 123 /*
 124  * Macros for specifying values to be written into a mode register.
 125  */
 126 #define TIMER_CNTR0     (IO_TIMER1 + 0) /* timer 0 counter port */
 127 #define TIMER_CNTR1     (IO_TIMER1 + 1) /* timer 1 counter port */
 128 #define TIMER_CNTR2     (IO_TIMER1 + 2) /* timer 2 counter port */
 129 #define TIMER_MODE      (IO_TIMER1 + 3) /* timer mode port */
 130 #define         TIMER_SEL0      0x00    /* select counter 0 */
 131 #define         TIMER_SEL1      0x40    /* select counter 1 */
 132 #define         TIMER_SEL2      0x80    /* select counter 2 */
 133 #define         TIMER_INTTC     0x00    /* mode 0, intr on terminal cnt */
 134 #define         TIMER_ONESHOT   0x02    /* mode 1, one shot */
 135 #define         TIMER_RATEGEN   0x04    /* mode 2, rate generator */
 136 #define         TIMER_SQWAVE    0x06    /* mode 3, square wave */
 137 #define         TIMER_SWSTROBE  0x08    /* mode 4, s/w triggered strobe */
 138 #define         TIMER_HWSTROBE  0x0a    /* mode 5, h/w triggered strobe */
 139 #define         TIMER_LATCH     0x00    /* latch counter for reading */
 140 #define         TIMER_LSB       0x10    /* r/w counter LSB */
 141 #define         TIMER_MSB       0x20    /* r/w counter MSB */
 142 #define         TIMER_16BIT     0x30    /* r/w counter 16 bits, LSB first */
 143 #define         TIMER_BCD       0x01    /* count in BCD */
 144