sys/platform/pc32/isa/intr_machdep.h

   1 /*-
   2  * Copyright (c) 1991 The Regents of the University of California.
   3  * All rights reserved.
   4  *
   5  * Redistribution and use in source and binary forms, with or without
   6  * modification, are permitted provided that the following conditions
   7  * are met:
   8  * 1. Redistributions of source code must retain the above copyright
   9  *    notice, this list of conditions and the following disclaimer.
  10  * 2. Redistributions in binary form must reproduce the above copyright
  11  *    notice, this list of conditions and the following disclaimer in the
  12  *    documentation and/or other materials provided with the distribution.
  13  * 3. All advertising materials mentioning features or use of this software
  14  *    must display the following acknowledgement:
  15  *      This product includes software developed by the University of
  16  *      California, Berkeley and its contributors.
  17  * 4. Neither the name of the University nor the names of its contributors
  18  *    may be used to endorse or promote products derived from this software
  19  *    without specific prior written permission.
  20  *
  21  * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND
  22  * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
  23  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
  24  * ARE DISCLAIMED.  IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE
  25  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
  26  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
  27  * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
  28  * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
  29  * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
  30  * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
  31  * SUCH DAMAGE.
  32  *
  33  * $FreeBSD: src/sys/i386/isa/intr_machdep.h,v 1.19.2.2 2001/10/14 20:05:50 luigi Exp $
  34  * $DragonFly: src/sys/platform/pc32/isa/intr_machdep.h,v 1.25 2006/10/23 21:50:31 dillon Exp $
  35  */
  36
  37 #ifndef _ARCH_ISA_INTR_MACHDEP_H_
  38 #define _ARCH_ISA_INTR_MACHDEP_H_
  39
  40 #ifndef LOCORE
  41 #ifndef _SYS_INTERRUPT_H_
  42 #include <sys/interrupt.h>
  43 #endif
  44 #ifndef _SYS_SERIALIZE_H_
  45 #include <sys/serialize.h>
  46 #endif
  47 #endif
  48
  49 /*
  50  * Low level interrupt code.
  51  */
  52
  53 #ifdef _KERNEL
  54
  55 #define IDT_OFFSET      32
  56
  57 #if defined(SMP)
  58 /*
  59  * XXX FIXME: rethink location for all IPI vectors.
  60  */
  61
  62 /*
  63     APIC TPR priority vector levels:
  64
  65         0xff (255) +-------------+
  66                    |             | 15 (IPIs: Xcpustop, Xspuriousint)
  67         0xf0 (240) +-------------+
  68                    |             | 14 (IPIs: Xinvltlb, Xipiq, Xtimer)
  69         0xe0 (224) +-------------+
  70                    |             | 13
  71         0xd0 (208) +-------------+
  72                    |             | 12
  73         0xc0 (192) +-------------+
  74                    |             | 11
  75         0xb0 (176) +-------------+
  76                    |             | 10
  77         0xa0 (160) +-------------+
  78                    |             |  9
  79         0x90 (144) +-------------+
  80                    |             |  8 (linux/BSD syscall, IGNORE FAST HW INTS)
  81         0x80 (128) +-------------+
  82                    |             |  7 (FAST_INTR 16-23)
  83         0x70 (112) +-------------+
  84                    |             |  6 (FAST_INTR 0-15)
  85         0x60 (96)  +-------------+
  86                    |             |  5 (IGNORE HW INTS)
  87         0x50 (80)  +-------------+
  88                    |             |  4 (2nd IO APIC)
  89         0x40 (64)  +------+------+
  90                    |      |      |  3 (upper APIC hardware INTs: PCI)
  91         0x30 (48)  +------+------+
  92                    |             |  2 (start of hardware INTs: ISA)
  93         0x20 (32)  +-------------+
  94                    |             |  1 (exceptions, traps, etc.)
  95         0x10 (16)  +-------------+
  96                    |             |  0 (exceptions, traps, etc.)
  97         0x00 (0)   +-------------+
  98  */
  99
 100 /* blocking values for local APIC Task Priority Register */
 101 #define TPR_BLOCK_HWI           0x4f            /* hardware INTs */
 102 #define TPR_IGNORE_HWI          0x5f            /* ignore INTs */
 103 #define TPR_BLOCK_FHWI          0x7f            /* hardware FAST INTs */
 104 #define TPR_IGNORE_FHWI         0x8f            /* ignore FAST INTs */
 105 #define TPR_IPI_ONLY            0xdf            /* ignore FAST INTs */
 106 #define TPR_BLOCK_XINVLTLB      0xef            /* block most IPIs */
 107 #define TPR_BLOCK_XCPUSTOP      0xf0            /* block Xcpustop */
 108 #define TPR_BLOCK_ALL           0xff            /* all INTs */
 109
 110 /* TLB shootdowns */
 111 #define XINVLTLB_OFFSET         (IDT_OFFSET + 192)
 112
 113 /* unused/open (was inter-cpu clock handling) */
 114 #define XUNUSED113_OFFSET       (IDT_OFFSET + 193)
 115
 116 /* unused/open (was inter-cpu rendezvous) */
 117 #define XUNUSED114_OFFSET       (IDT_OFFSET + 194)
 118
 119 /* IPIQ */
 120 #define XIPIQ_OFFSET            (IDT_OFFSET + 195)
 121
 122 /* Local APIC TIMER */
 123 #define XTIMER_OFFSET           (IDT_OFFSET + 196)
 124
 125 /* IPI to signal CPUs to stop and wait for another CPU to restart them */
 126 #define XCPUSTOP_OFFSET         (IDT_OFFSET + 208)
 127
 128 /*
 129  * Note: this vector MUST be xxxx1111, 32 + 223 = 255 = 0xff:
 130  */
 131 #define XSPURIOUSINT_OFFSET     (IDT_OFFSET + 223)
 132
 133 #endif /* SMP */
 134
 135 #ifndef LOCORE
 136
 137 /*
 138  * Type of the first (asm) part of an interrupt handler.
 139  */
 140 typedef void inthand_t(u_int cs, u_int ef, u_int esp, u_int ss);
 141 typedef void unpendhand_t(void);
 142
 143 #define IDTVEC(name)    __CONCAT(X,name)
 144
 145 #if defined(SMP)
 146 inthand_t
 147         Xinvltlb,       /* TLB shootdowns */
 148         Xcpuast,        /* Additional software trap on other cpu */
 149         Xforward_irq,   /* Forward irq to cpu holding ISR lock */
 150         Xcpustop,       /* CPU stops & waits for another CPU to restart it */
 151         Xspuriousint,   /* handle APIC "spurious INTs" */
 152         Xtimer,         /* handle LAPIC timer INT */
 153         Xipiq;          /* handle lwkt_send_ipiq() requests */
 154 #endif /* SMP */
 155
 156 void    call_fast_unpend(int irq);
 157 void    isa_defaultirq (void);
 158 int     isa_nmi (int cd);
 159 void    icu_reinit (void);
 160
 161 #endif /* LOCORE */
 162
 163 #endif /* _KERNEL */
 164
 165 #endif /* !_ARCH_ISA_INTR_MACHDEP_H_ */