sys/platform/pc32/isa/ic/scd1400.h

   1 /*****************************************************************************/
   2
   3 /*
   4  *      cd1400.h  -- cd1400 UART hardware info.
   5  *
   6  * Copyright (c) 1995 Greg Ungerer (gerg@stallion.oz.au).
   7  * All rights reserved.
   8  *
   9  * Redistribution and use in source and binary forms, with or without
  10  * modification, are permitted provided that the following conditions
  11  * are met:
  12  * 1. Redistributions of source code must retain the above copyright
  13  *    notice, this list of conditions and the following disclaimer.
  14  * 2. Redistributions in binary form must reproduce the above copyright
  15  *    notice, this list of conditions and the following disclaimer in the
  16  *    documentation and/or other materials provided with the distribution.
  17  * 3. All advertising materials mentioning features or use of this software
  18  *    must display the following acknowledgement:
  19  *      This product includes software developed by Greg Ungerer.
  20  * 4. Neither the name of the author nor the names of any co-contributors
  21  *    may be used to endorse or promote products derived from this software
  22  *    without specific prior written permission.
  23  *
  24  * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
  25  * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
  26  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
  27  * ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
  28  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
  29  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
  30  * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
  31  * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
  32  * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
  33  * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
  34  * SUCH DAMAGE.
  35  *
  36  * $FreeBSD: src/sys/i386/isa/ic/scd1400.h,v 1.5 1999/08/28 00:45:15 peter Exp $
  37  * $DragonFly: src/sys/platform/pc32/isa/ic/scd1400.h,v 1.2 2003/06/17 04:28:37 dillon Exp $
  38  */
  39
  40 /*****************************************************************************/
  41 #ifndef _CD1400_H
  42 #define _CD1400_H
  43 /*****************************************************************************/
  44
  45 /*
  46  *      Define the number of async ports per cd1400 uart chip.
  47  */
  48 #define CD1400_PORTS            4
  49
  50 /*
  51  *      Define the cd1400 uarts internal FIFO sizes.
  52  */
  53 #define CD1400_TXFIFOSIZE       12
  54 #define CD1400_RXFIFOSIZE       12
  55
  56 /*
  57  *      Local RX FIFO thresh hold level. Also define the RTS thresh hold
  58  *      based on the RX thresh hold.
  59  */
  60 #define FIFO_RXTHRESHOLD        6
  61 #define FIFO_RTSTHRESHOLD       7
  62
  63 /*****************************************************************************/
  64
  65 /*
  66  *      Define the cd1400 register addresses. These are all the valid
  67  *      registers with the cd1400. Some are global, some virtual, some
  68  *      per port.
  69  */
  70 #define GFRCR           0x40
  71 #define CAR             0x68
  72 #define GCR             0x4b
  73 #define SVRR            0x67
  74 #define RICR            0x44
  75 #define TICR            0x45
  76 #define MICR            0x46
  77 #define RIR             0x6b
  78 #define TIR             0x6a
  79 #define MIR             0x69
  80 #define PPR             0x7e
  81
  82 #define RIVR            0x43
  83 #define TIVR            0x42
  84 #define MIVR            0x41
  85 #define TDR             0x63
  86 #define RDSR            0x62
  87 #define MISR            0x4c
  88 #define EOSRR           0x60
  89
  90 #define LIVR            0x18
  91 #define CCR             0x05
  92 #define SRER            0x06
  93 #define COR1            0x08
  94 #define COR2            0x09
  95 #define COR3            0x0a
  96 #define COR4            0x1e
  97 #define COR5            0x1f
  98 #define CCSR            0x0b
  99 #define RDCR            0x0e
 100 #define SCHR1           0x1a
 101 #define SCHR2           0x1b
 102 #define SCHR3           0x1c
 103 #define SCHR4           0x1d
 104 #define SCRL            0x22
 105 #define SCRH            0x23
 106 #define LNC             0x24
 107 #define MCOR1           0x15
 108 #define MCOR2           0x16
 109 #define RTPR            0x21
 110 #define MSVR1           0x6c
 111 #define MSVR2           0x6d
 112 #define PSVR            0x6f
 113 #define RBPR            0x78
 114 #define RCOR            0x7c
 115 #define TBPR            0x72
 116 #define TCOR            0x76
 117
 118 /*****************************************************************************/
 119
 120 /*
 121  *      Define the set of baud rate clock divisors.
 122  */
 123 #define CD1400_CLK0     8
 124 #define CD1400_CLK1     32
 125 #define CD1400_CLK2     128
 126 #define CD1400_CLK3     512
 127 #define CD1400_CLK4     2048
 128
 129 #define CD1400_NUMCLKS  5
 130
 131 /*****************************************************************************/
 132
 133 /*
 134  *      Define the clock pre-scalar value to be a 5 ms clock. This should be
 135  *      OK for now. It would probably be better to make it 10 ms, but we
 136  *      can't fit that divisor into 8 bits!
 137  */
 138 #define PPR_SCALAR      244
 139
 140 /*****************************************************************************/
 141
 142 /*
 143  *      Define values used to set character size options.
 144  */
 145 #define COR1_CHL5       0x00
 146 #define COR1_CHL6       0x01
 147 #define COR1_CHL7       0x02
 148 #define COR1_CHL8       0x03
 149
 150 /*
 151  *      Define values used to set the number of stop bits.
 152  */
 153 #define COR1_STOP1      0x00
 154 #define COR1_STOP15     0x04
 155 #define COR1_STOP2      0x08
 156
 157 /*
 158  *      Define values used to set the parity scheme in use.
 159  */
 160 #define COR1_PARNONE    0x00
 161 #define COR1_PARFORCE   0x20
 162 #define COR1_PARENB     0x40
 163 #define COR1_PARIGNORE  0x10
 164
 165 #define COR1_PARODD     0x80
 166 #define COR1_PAREVEN    0x00
 167
 168 #define COR2_IXM        0x80
 169 #define COR2_TXIBE      0x40
 170 #define COR2_ETC        0x20
 171 #define COR2_LLM        0x10
 172 #define COR2_RLM        0x08
 173 #define COR2_RTSAO      0x04
 174 #define COR2_CTSAE      0x02
 175
 176 #define COR3_SCDRNG     0x80
 177 #define COR3_SCD34      0x40
 178 #define COR3_FCT        0x20
 179 #define COR3_SCD12      0x10
 180
 181 /*
 182  *      Define the bit values of COR4.
 183  */
 184 #define COR4_BRKINT     0x08
 185 #define COR4_IGNBRK     0x18
 186
 187 /*
 188  *      Define the bit values of COR5.
 189  */
 190 #define COR5_ISTRIP     0x80
 191
 192 /*****************************************************************************/
 193
 194 /*
 195  *      Define the modem control register values.
 196  *      Note that the actual hardware is a little different to the conventional
 197  *      pin names on the cd1400.
 198  */
 199 #define MSVR1_DTR       0x01
 200 #define MSVR1_DSR       0x10
 201 #define MSVR1_RI        0x20
 202 #define MSVR1_CTS       0x40
 203 #define MSVR1_DCD       0x80
 204
 205 #define MSVR2_RTS       0x02
 206 #define MSVR2_DSR       0x10
 207 #define MSVR2_RI        0x20
 208 #define MSVR2_CTS       0x40
 209 #define MSVR2_DCD       0x80
 210
 211 #define MCOR1_DCD       0x80
 212 #define MCOR1_CTS       0x40
 213 #define MCOR1_RI        0x20
 214 #define MCOR1_DSR       0x10
 215
 216 #define MCOR2_DCD       0x80
 217 #define MCOR2_CTS       0x40
 218 #define MCOR2_RI        0x20
 219 #define MCOR2_DSR       0x10
 220
 221 /*****************************************************************************/
 222
 223 /*
 224  *      Define the bits used with the service (interrupt) enable register.
 225  */
 226 #define SRER_NNDT       0x01
 227 #define SRER_TXEMPTY    0x02
 228 #define SRER_TXDATA     0x04
 229 #define SRER_RXDATA     0x10
 230 #define SRER_MODEM      0x80
 231
 232 /*****************************************************************************/
 233
 234 /*
 235  *      Define operational commands for the command register.
 236  */
 237 #define CCR_RESET       0x80
 238 #define CCR_CORCHANGE   0x4e
 239 #define CCR_SENDCH      0x20
 240 #define CCR_CHANCTRL    0x10
 241
 242 #define CCR_TXENABLE    (CCR_CHANCTRL | 0x08)
 243 #define CCR_TXDISABLE   (CCR_CHANCTRL | 0x04)
 244 #define CCR_RXENABLE    (CCR_CHANCTRL | 0x02)
 245 #define CCR_RXDISABLE   (CCR_CHANCTRL | 0x01)
 246
 247 #define CCR_SENDSCHR1   (CCR_SENDCH | 0x01)
 248 #define CCR_SENDSCHR2   (CCR_SENDCH | 0x02)
 249 #define CCR_SENDSCHR3   (CCR_SENDCH | 0x03)
 250 #define CCR_SENDSCHR4   (CCR_SENDCH | 0x04)
 251
 252 #define CCR_RESETCHAN   (CCR_RESET | 0x00)
 253 #define CCR_RESETFULL   (CCR_RESET | 0x01)
 254 #define CCR_TXFLUSHFIFO (CCR_RESET | 0x02)
 255
 256 #define CCR_MAXWAIT     10000
 257
 258 /*****************************************************************************/
 259
 260 /*
 261  *      Define the valid acknowledgement types (for hw ack cycle).
 262  */
 263 #define ACK_TYPMASK     0x07
 264 #define ACK_TYPTX       0x02
 265 #define ACK_TYPMDM      0x01
 266 #define ACK_TYPRXGOOD   0x03
 267 #define ACK_TYPRXBAD    0x07
 268
 269 #define SVRR_RX         0x01
 270 #define SVRR_TX         0x02
 271 #define SVRR_MDM        0x04
 272
 273 #define ST_OVERRUN      0x01
 274 #define ST_FRAMING      0x02
 275 #define ST_PARITY       0x04
 276 #define ST_BREAK        0x08
 277 #define ST_SCHAR1       0x10
 278 #define ST_SCHAR2       0x20
 279 #define ST_SCHAR3       0x30
 280 #define ST_SCHAR4       0x40
 281 #define ST_RANGE        0x70
 282 #define ST_SCHARMASK    0x70
 283 #define ST_TIMEOUT      0x80
 284
 285 #define MISR_DCD        0x80
 286 #define MISR_CTS        0x40
 287 #define MISR_RI         0x20
 288 #define MISR_DSR        0x10
 289
 290 /*****************************************************************************/
 291
 292 /*
 293  *      Defines for the CCSR status register.
 294  */
 295 #define CCSR_RXENABLED  0x80
 296 #define CCSR_RXFLOWON   0x40
 297 #define CCSR_RXFLOWOFF  0x20
 298 #define CCSR_TXENABLED  0x08
 299 #define CCSR_TXFLOWON   0x04
 300 #define CCSR_TXFLOWOFF  0x02
 301
 302 /*****************************************************************************/
 303
 304 /*
 305  *      Define the embedded commands.
 306  */
 307 #define ETC_CMD         0x00
 308 #define ETC_STARTBREAK  0x81
 309 #define ETC_DELAY       0x82
 310 #define ETC_STOPBREAK   0x83
 311
 312 /*****************************************************************************/
 313 #endif