2 * Copyright (C) 1995 by Pavel Antonov, Moscow, Russia.
3 * Copyright (C) 1995 by Andrey A. Chernov, Moscow, Russia.
6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions
9 * 1. Redistributions of source code must retain the above copyright
10 * notice, this list of conditions and the following disclaimer.
11 * 2. Redistributions in binary form must reproduce the above copyright
12 * notice, this list of conditions and the following disclaimer in the
13 * documentation and/or other materials provided with the distribution.
15 * THIS SOFTWARE IS PROVIDED BY THE AUTHORS ``AS IS'' AND
16 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
17 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
18 * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE
19 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
20 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
21 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
22 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
23 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
24 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
27 * $FreeBSD: src/sys/i386/isa/ic/cd180.h,v 1.2.12.1 2000/08/03 01:01:25 peter Exp $
28 * $DragonFly: src/sys/platform/pc32/isa/ic/cd180.h,v 1.2 2003/06/17 04:28:37 dillon Exp $
32 * Cirrus Logic CD180 registers
35 /* Global registers */
36 #define CD180_GIVR 0x40 /* Global Interrupt Verctor Register */
37 #define CD180_GICR 0x41 /* Global Interrupting Channel Register */
38 #define CD180_PILR1 0x61 /* Priority Interrupt Level Register 1 */
39 #define CD180_PILR2 0x62 /* Priority Interrupt Level Register 2 */
40 #define CD180_PILR3 0x63 /* Priority Interrupt Level Register 3 */
41 #define CD180_CAR 0x64 /* Channel Access Register */
42 #define CD180_GFRCR 0x6B /* Global Firmware Revision Code Register */
43 #define CD180_PPRH 0x70 /* Prescaler Period Register MSB */
44 #define CD180_PPRL 0x71 /* Prescaler Period Register LSB */
45 #define CD180_RDR 0x78 /* Receiver Data Register */
46 #define CD180_RCSR 0x7A /* Receiver Character Status Register */
47 #define CD180_TDR 0x7B /* Transmit Data Register */
48 #define CD180_EOIR 0x7F /* End of Interrupt Register */
50 /* Channel Registers */
51 #define CD180_CCR 0x01 /* Channel Command Register */
52 #define CD180_IER 0x02 /* Interrupt Enable Register */
53 #define CD180_COR1 0x03 /* Channel Option Register 1 */
54 #define CD180_COR2 0x04 /* Channel Option Register 1 */
55 #define CD180_COR3 0x05 /* Channel Option Register 1 */
56 #define CD180_CCSR 0x06 /* Channel Control STatus Register */
57 #define CD180_RDCR 0x07 /* Receive Data Count Register */
58 #define CD180_SCHR1 0x09 /* Special Character Register 1 */
59 #define CD180_SCHR2 0x0A /* Special Character Register 2 */
60 #define CD180_SCHR3 0x0B /* Special Character Register 3 */
61 #define CD180_SCHR4 0x0C /* Special Character Register 4 */
62 #define CD180_MCOR1 0x10 /* Modem Change Option 1 Register */
63 #define CD180_MCOR2 0x11 /* Modem Change Option 2 Register */
64 #define CD180_MCR 0x12 /* Modem Change Register */
65 #define CD180_RTPR 0x18 /* Receive Timeout Period Register */
66 #define CD180_MSVR 0x28 /* Modem Signal Value Register */
67 #define CD180_RBPRH 0x31 /* Receive Baud Rate Period Register MSB */
68 #define CD180_RBPRL 0x32 /* Receive Baud Rate Period Register LSB */
69 #define CD180_TBPRH 0x39 /* Transmit Baud Rate Period Register MSB */
70 #define CD180_TBPRL 0x3A /* Transmit Baud Rate Period Register LSB */
72 /** Register descritpions **/
74 /* Global Interrupt Vector Register */
75 #define GIVR_IT_MSCI 0x01 /* Modem Signal Change Interrupt */
76 #define GIVR_IT_TDI 0x02 /* Transmit Data Interrupt */
77 #define GIVR_IT_RGDI 0x03 /* Receive Good Data Interrupt */
78 #define GIVR_IT_REI 0x07 /* Receive Exception Interrupt */
80 /* Global Interrupt Channel Register */
81 #define GICR_CHAN 0x1C /* Channel Number Mask */
82 #define GICR_LSH 2 /* Channel Number Shift */
84 /* Channel Address Register */
85 #define CAR_CHAN 0x07 /* Channel Number Mask */
86 #define CAR_A7 0x08 /* Addres bit 7 (unused) */
88 /* Receive Character Status Register */
89 #define RCSR_OE 0x01 /* Overrun Error */
90 #define RCSR_FE 0x02 /* Frame Error */
91 #define RCSR_PE 0x04 /* Parity Error */
92 #define RCSR_Break 0x08 /* Break detected */
93 #define RCSR_Timeout 0x80 /* Rx Timeout */
94 #define RCSR_SCMASK 0x70 /* Special Character Detected Mask */
95 #define RCSR_SC1 0x10 /* Special Char 1 (or 1 & 3 seq matched) */
96 #define RCSR_SC2 0x20 /* Special Char 2 (or 2 & 4 seq matched) */
97 #define RCSR_SC3 0x30 /* Special Char 3 */
98 #define RCSR_SC4 0x40 /* Special Char 4 */
100 /* Channel Command Register */
101 #define CCR_ResetChan 0x80 /* Reset Channel */
102 #define CCR_HWRESET 0x81 /* Hardware Reset (all channels) */
103 #define CCR_CORCHG1 0x42 /* Channel Option Register 1 Changed */
104 #define CCR_CORCHG2 0x44 /* Channel Option Register 2 Changed */
105 #define CCR_CORCHG3 0x48 /* Channel Option Register 3 Changed */
106 #define CCR_SENDSPCH1 0x21 /* Send Special Character 1 */
107 #define CCR_SENDSPCH2 0x22 /* Send Special Character 2 */
108 #define CCR_SENDSPCH3 0x23 /* Send Special Character 3 */
109 #define CCR_SENDSPCH4 0x24 /* Send Special Character 4 */
110 #define CCR_RCVRDIS 0x11 /* Receiver Disable */
111 #define CCR_RCVREN 0x12 /* Receiver Enable */
112 #define CCR_XMTRDIS 0x14 /* Transmitter Disable */
113 #define CCR_XMTREN 0x18 /* Transmitter Enable */
115 /* Interrupt Enable Register */
116 #define IER_DSR 0x80 /* Enable interrupt on DSR change */
117 #define IER_CD 0x40 /* Enable interrupt on CD change */
118 #define IER_CTS 0x20 /* Enable interrupt on CTS change */
119 #define IER_RxData 0x10 /* Enable interrupt on Receive Data */
120 #define IER_RxSC 0x08 /* Enable interrupt on Receive Spec. Char */
121 #define IER_TxRdy 0x04 /* Enable interrupt on TX FIFO empty */
122 #define IER_TxMpty 0x02 /* Enable interrupt on TX completely empty*/
123 #define IER_RET 0x01 /* Enable interrupt on RX Except. Timeout */
125 /* Channel Option Register 1 */
126 #define COR1_ODDP 0x80 /* Odd Parity */
127 #define COR1_ParMMASK 0x60 /* Parity Mode mask */
128 #define COR1_NOPAR 0x02 /* No Parity */
129 #define COR1_FORCEPAR 0x20 /* Force Parity */
130 #define COR1_NORMPAR 0x40 /* Normal Parity */
131 #define COR1_Ignore 0x10 /* Ignore Parity on RX */
132 #define COR1_StopMASK 0x0C /* Stop Bits mode mask */
133 #define COR1_1SB 0x00 /* 1 Stop Bit */
134 #define COR1_15SB 0x04 /* 1.5 Stop Bits */
135 #define COR1_2SB 0x08 /* 2 Stop Bits */
136 #define COR1_CHLMASK 0x03 /* Character Length mask */
137 #define COR1_5BITS 0x00 /* 5 bits */
138 #define COR1_6BITS 0x01 /* 6 bits */
139 #define COR1_7BITS 0x02 /* 7 bits */
140 #define COR1_8BITS 0x03 /* 8 bits */
142 /* Channel Option Register 2 */
143 #define COR2_IXM 0x80 /* Implied XON mode */
144 #define COR2_TxIBE 0x40 /* Enable In-Band XON/XOFF Flow Control */
145 #define COR2_ETC 0x20 /* Embedded Tx Commands Enable */
146 #define COR2_LLM 0x10 /* Local Loopback Mode */
147 #define COR2_RLM 0x08 /* Remote Loopback Mode */
148 #define COR2_RtsAO 0x04 /* RTS Automatic Output Enable */
149 #define COR2_CtsAE 0x02 /* CTS Automatic Enable */
150 #define COR2_DsrAE 0x01 /* DSR Automatic Enable */
152 /* Channel Option Register 3 */
153 #define COR3_XonCH 0x80 /* XON is a double seq (1 & 3) */
154 #define COR3_XoffCH 0x40 /* XOFF is a double seq (1 & 3) */
155 #define COR3_FCT 0x20 /* Flow-Control Transparency Mode */
156 #define COR3_SCDE 0x10 /* Special Character Detection Enable */
157 #define COR3_RxTHMASK 0x0F /* RX FIFO Threshold value (1-8) */
159 /* Channel Control Status Register */
160 #define CCSR_RxEn 0x80 /* Revceiver Enabled */
161 #define CCSR_RxFloff 0x40 /* Receive Flow Off (XOFF sent) */
162 #define CCSR_RxFlon 0x20 /* Receive Flow On (XON sent) */
163 #define CCSR_TxEn 0x08 /* Transmitter Enabled */
164 #define CCSR_TxFloff 0x04 /* Transmit Flow Off (got XOFF) */
165 #define CCSR_TxFlon 0x02 /* Transmit Flow On (got XON) */
167 /* Modem Change Option Register 1 */
168 #define MCOR1_DSRzd 0x80 /* Detect 0->1 transition of DSR */
169 #define MCOR1_CDzd 0x40 /* Detect 0->1 transition of CD */
170 #define MCOR1_CTSzd 0x20 /* Detect 0->1 transition of CTS */
171 #define MCOR1_DTRthMASK 0x0F /* Automatic DTR FC Threshold (1-8) chars */
173 /* Modem Change Option Register 2 */
174 #define MCOR2_DSRod 0x80 /* Detect 1->0 transition of DSR */
175 #define MCOR2_CDod 0x40 /* Detect 1->0 transition of CD */
176 #define MCOR2_CTSod 0x20 /* Detect 1->0 transition of CTS */
178 /* Modem Change Register */
179 #define MCR_DSRchg 0x80 /* DSR Changed */
180 #define MCR_CDchg 0x40 /* CD Changed */
181 #define MCR_CTSchg 0x20 /* CTS Changed */
183 /* Modem Signal Value Register */
184 #define MSVR_DSR 0x80 /* Current state of DSR input */
185 #define MSVR_CD 0x40 /* Current state of DSR input */
186 #define MSVR_CTS 0x20 /* Current state of CTS input */
187 #define MSVR_DTR 0x02 /* Current state of DTR output */
188 #define MSVR_RTS 0x01 /* Current state of RTS output */
190 /* Escape characters */
191 #define CD180_C_ESC 0x00 /* Escape character */
192 #define CD180_C_SBRK 0x81 /* Start sending BREAK */
193 #define CD180_C_DELAY 0x82 /* Delay output */
194 #define CD180_C_EBRK 0x83 /* Stop sending BREAK */
197 #define CD180_NCHAN 8 /* 8 channels per chip */
198 #define CD180_CTICKS 16 /* 16 ticks for character processing */
199 #define CD180_NFIFO 8 /* 8 bytes in FIFO */
