sys/dev/netif/mii_layer/nsphyreg.h

   1 /*      $NetBSD: nsphyreg.h,v 1.1 1998/08/10 23:58:39 thorpej Exp $     */
   2
   3 /*-
   4  * Copyright (c) 1998 The NetBSD Foundation, Inc.
   5  * All rights reserved.
   6  *
   7  * This code is derived from software contributed to The NetBSD Foundation
   8  * by Jason R. Thorpe of the Numerical Aerospace Simulation Facility,
   9  * NASA Ames Research Center.
  10  *
  11  * Redistribution and use in source and binary forms, with or without
  12  * modification, are permitted provided that the following conditions
  13  * are met:
  14  * 1. Redistributions of source code must retain the above copyright
  15  *    notice, this list of conditions and the following disclaimer.
  16  * 2. Redistributions in binary form must reproduce the above copyright
  17  *    notice, this list of conditions and the following disclaimer in the
  18  *    documentation and/or other materials provided with the distribution.
  19  * 3. All advertising materials mentioning features or use of this software
  20  *    must display the following acknowledgement:
  21  *      This product includes software developed by the NetBSD
  22  *      Foundation, Inc. and its contributors.
  23  * 4. Neither the name of The NetBSD Foundation nor the names of its
  24  *    contributors may be used to endorse or promote products derived
  25  *    from this software without specific prior written permission.
  26  *
  27  * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
  28  * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
  29  * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
  30  * PURPOSE ARE DISCLAIMED.  IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
  31  * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
  32  * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
  33  * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
  34  * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
  35  * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
  36  * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
  37  * POSSIBILITY OF SUCH DAMAGE.
  38  *
  39  * $FreeBSD: src/sys/dev/mii/nsphyreg.h,v 1.2 1999/08/28 00:42:16 peter Exp $
  40  * $DragonFly: src/sys/dev/netif/mii_layer/nsphyreg.h,v 1.3 2006/08/06 10:32:23 sephe Exp $
  41  */
  42
  43 #ifndef _DEV_MII_NSPHYREG_H_
  44 #define _DEV_MII_NSPHYREG_H_
  45
  46 /*
  47  * DP83840 registers.
  48  */
  49
  50 #define MII_NSPHY_DCR           0x12    /* Disconnect counter */
  51
  52 #define MII_NSPHY_FCSCR         0x13    /* False carrier sense counter */
  53
  54 #define MII_NSPHY_RECR          0x15    /* Receive error counter */
  55
  56 #define MII_NSPHY_SRR           0x16    /* Silicon revision */
  57
  58 #define MII_NSPHY_PCR           0x17    /* PCS sub-layer configuration */
  59 #define PCR_NRZI                0x8000  /* NRZI encoding enabled for 100TX */
  60 #define PCR_DESCRTOSEL          0x4000  /* descrambler t/o select (2ms) */
  61 #define PCR_DESCRTODIS          0x2000  /* descrambler t/o disable */
  62 #define PCR_REPEATER            0x1000  /* repeater mode */
  63 #define PCR_ENCSEL              0x0800  /* encoder mode select */
  64 #define PCR_TXREADYSEL          0x0400  /* use internal txrdy signal */
  65 #define PCR_CONGCTRL            0x0100  /* congestion control */
  66 #define PCR_CLK25MDIS           0x0080  /* CLK25M disable */
  67 #define PCR_FLINK100            0x0040  /* force good link in 100mbps */
  68 #define PCR_CIMDIS              0x0020  /* carrier integrity monitor disable */
  69 #define PCR_TXOFF               0x0010  /* force transmit off */
  70 #define PCR_LED1MODE            0x0004  /* LED1 mode: see below */
  71 #define PCR_LED4MODE            0x0002  /* LED4 mode: see below */
  72
  73 /*
  74  * LED1 Mode:
  75  *
  76  *      1       LED1 output configured to PAR's CON_STATUS, useful for
  77  *              network management in 100baseTX mode.
  78  *
  79  *      0       Normal LED1 operation - 10baseTX and 100baseTX transmission
  80  *              activity.
  81  *
  82  * LED4 Mode:
  83  *
  84  *      1       LED4 output configured to indicate full-duplex in both
  85  *              10baseT and 100baseTX modes.
  86  *
  87  *      0       LED4 output configured to indicate polarity in 10baseT
  88  *              mode and full-duplex in 100baseTX mode.
  89  */
  90
  91 #define MII_NSPHY_LBREMR        0x18    /* Loopback, bypass, error mask */
  92 #define LBREMR_BADSSDEN         0x8000  /* enable bad SSD detection */
  93 #define LBREMR_BP4B5B           0x4000  /* bypass 4b/5b encoding */
  94 #define LBREMR_BPSCR            0x2000  /* bypass scrambler */
  95 #define LBREMR_BPALIGN          0x1000  /* bypass alignment function */
  96 #define LBREMR_10LOOP           0x0800  /* 10baseT loopback */
  97 #define LBREMR_LB1              0x0200  /* loopback ctl 1 */
  98 #define LBREMR_LB0              0x0100  /* loopback ctl 0 */
  99 #define LBREMR_ALTCRS           0x0040  /* alt crs operation */
 100 #define LBREMR_LOOPXMTDIS       0x0020  /* disable transmit in 100TX loopbk */
 101 #define LBREMR_CODEERR          0x0010  /* code errors */
 102 #define LBREMR_PEERR            0x0008  /* premature end errors */
 103 #define LBREMR_LINKERR          0x0004  /* link errors */
 104 #define LBREMR_PKTERR           0x0002  /* packet errors */
 105
 106 #define MII_NSPHY_PAR           0x19    /* Physical address and status */
 107 #define PAR_DISCRSJAB           0x0800  /* disable car sense during jab */
 108 #define PAR_ANENSTAT            0x0400  /* autoneg mode status */
 109 #define PAR_FEFIEN              0x0100  /* far end fault enable */
 110 #define PAR_FDX                 0x0080  /* full duplex status */
 111 #define PAR_10                  0x0040  /* 10mbps mode */
 112 #define PAR_CON                 0x0020  /* connect status */
 113 #define PAR_AMASK               0x001f  /* PHY address bits */
 114
 115 #define MII_NSPHY_10BTSR        0x1b    /* 10baseT status */
 116 #define MII_NSPHY_10BTCR        0x1c    /* 10baseT configuration */
 117
 118 #endif /* _DEV_MII_NSPHYREG_H_ */