sys/dev/netif/et/if_etvar.h

   1 /*
   2  * Copyright (c) 2007 The DragonFly Project.  All rights reserved.
   3  *
   4  * This code is derived from software contributed to The DragonFly Project
   5  * by Sepherosa Ziehau <sepherosa@gmail.com>
   6  *
   7  * Redistribution and use in source and binary forms, with or without
   8  * modification, are permitted provided that the following conditions
   9  * are met:
  10  *
  11  * 1. Redistributions of source code must retain the above copyright
  12  *    notice, this list of conditions and the following disclaimer.
  13  * 2. Redistributions in binary form must reproduce the above copyright
  14  *    notice, this list of conditions and the following disclaimer in
  15  *    the documentation and/or other materials provided with the
  16  *    distribution.
  17  * 3. Neither the name of The DragonFly Project nor the names of its
  18  *    contributors may be used to endorse or promote products derived
  19  *    from this software without specific, prior written permission.
  20  *
  21  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  22  * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  23  * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
  24  * FOR A PARTICULAR PURPOSE ARE DISCLAIMED.  IN NO EVENT SHALL THE
  25  * COPYRIGHT HOLDERS OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
  26  * INCIDENTAL, SPECIAL, EXEMPLARY OR CONSEQUENTIAL DAMAGES (INCLUDING,
  27  * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
  28  * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
  29  * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
  30  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT
  31  * OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
  32  * SUCH DAMAGE.
  33  *
  34  * $DragonFly: src/sys/dev/netif/et/if_etvar.h,v 1.4 2007/10/23 14:28:42 sephe Exp $
  35  */
  36
  37 #ifndef _IF_ETVAR_H
  38 #define _IF_ETVAR_H
  39
  40 #define ET_ALIGN                0x1000  /* XXX safest guess */
  41 #define ET_NSEG_MAX             32      /* XXX no limit actually */
  42 #define ET_NSEG_SPARE           8
  43
  44 #define ET_TX_NDESC             512
  45 #define ET_RX_NDESC             512
  46 #define ET_RX_NRING             2
  47 #define ET_RX_NSTAT             (ET_RX_NRING * ET_RX_NDESC)
  48
  49 #define ET_TX_RING_SIZE         (ET_TX_NDESC * sizeof(struct et_txdesc))
  50 #define ET_RX_RING_SIZE         (ET_RX_NDESC * sizeof(struct et_rxdesc))
  51 #define ET_RXSTAT_RING_SIZE     (ET_RX_NSTAT * sizeof(struct et_rxstat))
  52
  53 #define ET_JUMBO_ALIGN          8
  54 #define ET_JUMBO_FRAMELEN       (ET_MEM_SIZE - ET_MEM_RXSIZE_MIN -      \
  55                                  ET_MEM_TXSIZE_EX)
  56 #define ET_JUMBO_MTU            (ET_JUMBO_FRAMELEN - ETHER_HDR_LEN -    \
  57                                  EVL_ENCAPLEN - ETHER_CRC_LEN)
  58
  59 #define ET_FRAMELEN(mtu)        (ETHER_HDR_LEN + EVL_ENCAPLEN + (mtu) + \
  60                                  ETHER_CRC_LEN)
  61
  62 #define ET_JSLOTS               (ET_RX_NDESC + 128)
  63 #define ET_JLEN                 roundup2(ET_JUMBO_FRAMELEN, ET_JUMBO_ALIGN)
  64 #define ET_JUMBO_MEM_SIZE       (ET_JSLOTS * ET_JLEN)
  65
  66 #define CSR_WRITE_4(sc, reg, val)       \
  67         bus_space_write_4((sc)->sc_mem_bt, (sc)->sc_mem_bh, (reg), (val))
  68 #define CSR_READ_4(sc, reg)             \
  69         bus_space_read_4((sc)->sc_mem_bt, (sc)->sc_mem_bh, (reg))
  70
  71 #define ET_ADDR_HI(addr)        ((uint64_t) (addr) >> 32)
  72 #define ET_ADDR_LO(addr)        ((uint64_t) (addr) & 0xffffffff)
  73
  74 struct et_txdesc {
  75         uint32_t        td_addr_hi;
  76         uint32_t        td_addr_lo;
  77         uint32_t        td_ctrl1;       /* ET_TDCTRL1_ */
  78         uint32_t        td_ctrl2;       /* ET_TDCTRL2_ */
  79 } __packed;
  80
  81 #define ET_TDCTRL1_LEN          __BITS(15, 0)
  82
  83 #define ET_TDCTRL2_LAST_FRAG    __BIT(0)
  84 #define ET_TDCTRL2_FIRST_FRAG   __BIT(1)
  85 #define ET_TDCTRL2_INTR         __BIT(2)
  86
  87 struct et_rxdesc {
  88         uint32_t        rd_addr_lo;
  89         uint32_t        rd_addr_hi;
  90         uint32_t        rd_ctrl;        /* ET_RDCTRL_ */
  91 } __packed;
  92
  93 #define ET_RDCTRL_BUFIDX        __BITS(9, 0)
  94
  95 struct et_rxstat {
  96         uint32_t        rxst_info1;
  97         uint32_t        rxst_info2;     /* ET_RXST_INFO2_ */
  98 } __packed;
  99
 100 #define ET_RXST_INFO2_LEN       __BITS(15, 0)
 101 #define ET_RXST_INFO2_BUFIDX    __BITS(25, 16)
 102 #define ET_RXST_INFO2_RINGIDX   __BITS(27, 26)
 103
 104 struct et_rxstatus {
 105         uint32_t        rxs_ring;
 106         uint32_t        rxs_stat_ring;  /* ET_RXS_STATRING_ */
 107 } __packed;
 108
 109 #define ET_RXS_STATRING_INDEX   __BITS(27, 16)
 110 #define ET_RXS_STATRING_WRAP    __BIT(28)
 111
 112 struct et_txbuf {
 113         struct mbuf             *tb_mbuf;
 114         bus_dmamap_t            tb_dmap;
 115 };
 116
 117 struct et_rxbuf {
 118         struct mbuf             *rb_mbuf;
 119         bus_dmamap_t            rb_dmap;
 120         bus_addr_t              rb_paddr;
 121 };
 122
 123 struct et_txstatus_data {
 124         uint32_t                *txsd_status;
 125         bus_addr_t              txsd_paddr;
 126         bus_dma_tag_t           txsd_dtag;
 127         bus_dmamap_t            txsd_dmap;
 128 };
 129
 130 struct et_rxstatus_data {
 131         struct et_rxstatus      *rxsd_status;
 132         bus_addr_t              rxsd_paddr;
 133         bus_dma_tag_t           rxsd_dtag;
 134         bus_dmamap_t            rxsd_dmap;
 135 };
 136
 137 struct et_rxstat_ring {
 138         struct et_rxstat        *rsr_stat;
 139         bus_addr_t              rsr_paddr;
 140         bus_dma_tag_t           rsr_dtag;
 141         bus_dmamap_t            rsr_dmap;
 142
 143         int                     rsr_index;
 144         int                     rsr_wrap;
 145 };
 146
 147 struct et_txdesc_ring {
 148         struct et_txdesc        *tr_desc;
 149         bus_addr_t              tr_paddr;
 150         bus_dma_tag_t           tr_dtag;
 151         bus_dmamap_t            tr_dmap;
 152
 153         int                     tr_ready_index;
 154         int                     tr_ready_wrap;
 155 };
 156
 157 struct et_rxdesc_ring {
 158         struct et_rxdesc        *rr_desc;
 159         bus_addr_t              rr_paddr;
 160         bus_dma_tag_t           rr_dtag;
 161         bus_dmamap_t            rr_dmap;
 162
 163         uint32_t                rr_posreg;
 164         int                     rr_index;
 165         int                     rr_wrap;
 166 };
 167
 168 struct et_txbuf_data {
 169         struct et_txbuf         tbd_buf[ET_TX_NDESC];
 170
 171         int                     tbd_start_index;
 172         int                     tbd_start_wrap;
 173         int                     tbd_used;
 174 };
 175
 176 struct et_softc;
 177 struct et_rxbuf_data;
 178 typedef int     (*et_newbuf_t)(struct et_rxbuf_data *, int, int);
 179
 180 struct et_rxbuf_data {
 181         struct et_rxbuf         rbd_buf[ET_RX_NDESC];
 182
 183         struct et_softc         *rbd_softc;
 184         struct et_rxdesc_ring   *rbd_ring;
 185
 186         int                     rbd_jumbo;
 187         int                     rbd_bufsize;
 188         et_newbuf_t             rbd_newbuf;
 189 };
 190
 191 struct et_jslot;
 192
 193 struct et_jumbo_data {
 194         bus_dma_tag_t           jd_dtag;
 195         bus_dmamap_t            jd_dmap;
 196         void                    *jd_buf;
 197
 198         struct lwkt_serialize   jd_serializer;
 199         struct et_jslot         *jd_slots;
 200         SLIST_HEAD(, et_jslot)  jd_free_slots;
 201 };
 202
 203 struct et_jslot {
 204         struct et_jumbo_data    *jslot_data;
 205         void                    *jslot_buf;
 206         bus_addr_t              jslot_paddr;
 207         int                     jslot_inuse;
 208         int                     jslot_index;
 209         SLIST_ENTRY(et_jslot)   jslot_link;
 210 };
 211
 212 struct et_softc {
 213         struct arpcom           arpcom;
 214         int                     sc_if_flags;
 215         uint32_t                sc_flags;       /* ET_FLAG_ */
 216
 217         int                     sc_mem_rid;
 218         struct resource         *sc_mem_res;
 219         bus_space_tag_t         sc_mem_bt;
 220         bus_space_handle_t      sc_mem_bh;
 221
 222         int                     sc_irq_rid;
 223         struct resource         *sc_irq_res;
 224         void                    *sc_irq_handle;
 225
 226         device_t                sc_miibus;
 227         struct callout          sc_tick;
 228
 229         bus_dma_tag_t           sc_dtag;
 230
 231         struct et_rxdesc_ring   sc_rx_ring[ET_RX_NRING];
 232         struct et_rxstat_ring   sc_rxstat_ring;
 233         struct et_rxstatus_data sc_rx_status;
 234
 235         struct et_txdesc_ring   sc_tx_ring;
 236         struct et_txstatus_data sc_tx_status;
 237
 238         bus_dma_tag_t           sc_rxbuf_dtag;
 239         bus_dmamap_t            sc_rxbuf_tmp_dmap;
 240         struct et_rxbuf_data    sc_rx_data[ET_RX_NRING];
 241
 242         bus_dma_tag_t           sc_txbuf_dtag;
 243         struct et_txbuf_data    sc_tx_data;
 244
 245         struct et_jumbo_data    sc_jumbo_data;
 246
 247         uint32_t                sc_tx;
 248         uint32_t                sc_tx_intr;
 249
 250         struct sysctl_ctx_list  sc_sysctl_ctx;
 251         struct sysctl_oid       *sc_sysctl_tree;
 252
 253         /*
 254          * Sysctl variables
 255          */
 256         int                     sc_rx_intr_npkts;
 257         int                     sc_rx_intr_delay;
 258         int                     sc_tx_intr_nsegs;
 259         uint32_t                sc_timer;
 260 };
 261
 262 #define ET_FLAG_TXRX_ENABLED    0x1
 263 #define ET_FLAG_JUMBO           0x2
 264
 265 #endif  /* !_IF_ETVAR_H */